Molded direct bond and interconnected stack

Abstract

The invention relates to a molded direct bonded and interconnected stack. The dies and / or wafers are stacked and bonded in various arrangements, including stacks, and may be covered by moldings to facilitate processing, packaging, and the like. In various examples, the molded member may more or less cover the stack to facilitate connection with devices in the stack, enhance thermal management, and the like.

Description

[0001] This application is a divisional application of the application patent application with the application date of July 2, 2019, the application number of 201980045338.X, and the invention name of “Molded Direct Bond and Interconnected Stack”. Priority and Cross Reference to Related Applications

[0002] This application claims the benefit under 35 U.S.C. § 119(e)(1) of U.S. Nonprovisional Application No. 16 / 460,068, filed July 2, 2019, and U.S. Provisional Application No. 62 / 694,845, filed July 6, 2018, which are hereby incorporated by reference in their entirety. TECHNICAL FIELD

[0003] The following description relates to processing of integrated circuits (“ICs”). More specifically, the following description relates to techniques for packaging dies or wafers and other microelectronic assemblies. BACKGROUND

[0004] Microelectronic elements typically include thin sheets of a semiconductor material, such as silicon or gallium arsenide, commonly referred to as semiconductor wafers. The wafers can be formed to include multiple integrated chips or dies on a surface of the wafer and / or partially embedded within the wafer. Dies that are separate from the wafer are typically provided as individual pre-packaged units. In some packaging designs, the dies are mounted to a substrate or chip carrier, which in turn is mounted on a circuit board, such as a printed circuit board (PCB). For example, many dies are provided in the form of a package suitable for surface mounting.

[0005] Packaged semiconductor dies can also be provided in a “stacked” arrangement, in which one package is provided on, for example, a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements can allow multiple different dies or devices to be mounted in a single footprint on a circuit board, and can further facilitate high speed operation by providing short interconnects between the packages. Typically, this interconnect distance can only be slightly greater than the thickness of the dies themselves. To enable interconnects within a stack of die packages, interconnect structures for mechanical and electrical connections can be provided on both sides (e.g., faces) of each die package, except for the topmost package.

[0006] Additionally, as part of a variety of microelectronic packaging schemes, dies or wafers can be stacked in three-dimensional arrangements. This can include stacking one or more dies, device layers, and / or wafers on a larger base die, device, wafer, substrate, etc., stacking multiple dies or wafers in a vertical or horizontal arrangement, and various combinations of these two operations.

[0007] The dies or wafers can be bonded in a stacked arrangement using various bonding techniques, including direct dielectric bonding, non-adhesive techniques such as ZiBond® or hybrid bonding techniques such as DBI®, both of which are available from Invensas Bonding Technologies Inc. (formerly Ziptronix, Inc.), a Xperi company. Direct dielectric bonding techniques include a spontaneous covalent bonding process that occurs when two prepared dielectric surfaces are brought together under ambient conditions without an adhesive or intervening material, and hybrid bonding techniques likewise incorporate direct metal-to-metal bonding of respective metal bonding pads at the bonding surfaces of the respective dies or wafers without an intervening material to form a unified conductive structure (see, e.g., U.S. Patent Nos. 6,864,585 and 7,485,968, the entire contents of which are incorporated herein). Annealing of the metal bonding pads can be used to enhance the metal-to-metal bonding.

[0008] The respective mating surfaces of the bonded dies or wafers typically include embedded conductive interconnect structures (which can be metal) or the like. In some examples, the bonding surfaces are arranged and aligned such that the conductive interconnect structures from the respective surfaces are joined during bonding. The joined interconnect structures form a continuous conductive interconnect between the stacked dies or wafers (for signals, power, etc.).

[0009] There can be many challenges in implementing stacked die and wafer arrangements. When using direct bonding or hybrid bonding techniques to bond stacked dies or wafers, it is typically desirable that the surfaces of the dies or wafers to be bonded be extremely flat, smooth and clean. For example, typically, the surfaces should have very low variation in surface topography (i.e., nanometer scale variation) so that the surfaces can be brought into close mating to form a durable bond.

[0010] Double-sided dies or wafers can be formed and prepared for stacking and bonding, where both sides of the die or wafer will be bonded to other substrates, wafers or dies, such as with multiple die-to-die or die-to-wafer applications. Preparing both sides of the die or wafer includes trimming both surfaces to meet dielectric roughness specifications and metal layer (e.g., copper, etc.) recess specifications. The hybrid surfaces for bonding with another die, wafer or other substrate can be prepared using chemical mechanical polishing (CMP) processes, plasma processes, wet and dry cleaning methods, etc.

[0011] For various connectivity, performance optimization and enhanced thermal management purposes, it can be desirable to package stacked and bonded dies and wafers in various configurations. BRIEF DESCRIPTION OF DRAWINGS

[0012] A detailed description is provided with reference to the accompanying drawings. In the drawings, the leftmost numeral of the reference numeral indicates the drawing in which that reference numeral first appears. The same reference numerals are used in different drawings to indicate similar or identical items.

[0013] For the purposes of discussion, the devices and systems shown in the figures are illustrated as having multiple components. Various implementations of the devices and / or systems as described herein may include fewer components and remain within the scope of this disclosure. Alternatively, other implementations of the devices and / or systems may include more components or various combinations of the described components and remain within the scope of this disclosure.

[0014] Figure 1 It is a cross-sectional profile view of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment.

[0015] Figure 2 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment, wherein the top of the stack is not covered.

[0016] Figure 3 It is a cross-sectional profile view of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment, wherein the top of the stack is covered.

[0017] Figure 4 It is a cross-sectional profile view of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment, wherein the top of the stack is uncovered and the molding extends to the bottom of the stack.

[0018] Figure 5 It is a cross-sectional profile view of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment, wherein the top of the stack is covered and the molding extends to the bottom of the stack.

[0019] Figure 6 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment, wherein the dies are not of equal size and the top of the stack is covered.

[0020] Figure 7 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment, wherein the dies are not of equal size, wherein the top of the stack is covered and the molding extends to the bottom of the stack.

[0021] Figure 8 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment, wherein the top dies of the stack have no interconnects on one side.

[0022] Figure 9 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment, wherein the top dies of the stack have no interconnects on one side and the molding extends to the bottom of the stack.

[0023] Figure 10 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack and molding comprising dies arranged in a lateral manner at the same level, according to one embodiment.

[0024] Figure 11 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack and molding comprising, according to one embodiment, a die and a wafer in a certain lateral arrangement at the same level.

[0025] Figure 12 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack, including some kind of etching of the die edges, according to one embodiment.

[0026] Figure 13 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die stack and molded part, including some kind of etching of the die edge, according to one embodiment.

[0027] Figure 14 It is a cross-sectional profile of an example die-to-wafer and / or die-to-die hybrid bonding stack, including some kind of etching of the die edges according to another embodiment.

[0028] Figure 15 This is a cross-sectional profile view of an example die-to-wafer and / or die-to-die memory stack according to one embodiment.

[0029] Figure 16 This is a cross-sectional profile of an example die-to-wafer and / or die-to-die hybrid bonding stack including flip-chip terminations according to one embodiment.

[0030] Figures 17-20 Cross-sectional profiles of example die-to-wafer and / or die-to-die hybrid bonding stacks, including various combinations on a substrate, are shown according to multiple embodiments.

[0031] Figure 21 This is a flowchart illustrating an example process for forming a stacked and bonded structure according to one embodiment. Detailed Implementation Overview

[0032] Representative technologies and devices are disclosed, including process steps for stacking and bonding dies and / or wafers, including hybrid bonding of die-to-die, die-to-wafer, and wafer-to-wafer without adhesive. In various embodiments, dies and / or wafers are stacked and bonded in various arrangements, including stacks, and may be covered by molding parts for ease of handling, packaging, etc. In various examples, the molding parts may more or less cover the stack to facilitate connection to devices in the stack, enhance thermal management, etc.

[0033] Various implementations and arrangements are discussed with reference to electrical and electronic components and various carriers. Although specific components (i.e., dies, wafers, integrated circuit (IC) chip dies, substrates, etc.) are mentioned, this is not intended to be restrictive, but rather for ease of discussion and illustration. The techniques and devices discussed with reference to wafers, dies, substrates, etc. are applicable to any type or number of electronic components, circuits (e.g., integrated circuits (ICs), hybrid circuits, ASICs, memory devices, processors, etc.), groups of components, passive components, MEMS (microelectromechanical systems) components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.) that can be integrated and coupled to interface with each other, with external circuits, systems, carriers, etc. Each of these different components, circuits, groups, packages, structures, etc., may be collectively referred to as a “microelectronic component.” For simplicity, unless otherwise stated, a component bonded to another component is referred to herein as a “die.” Example Implementation

[0034] Figure 1 This is a cross-sectional profile view of an example die-to-wafer and / or die-to-die stack and molding according to one embodiment. In the example shown, stack 100 (or microelectronic component 100) is formed by stacking and bonding (e.g., hybrid bonding without adhesive) a plurality of dies 102 (e.g., any desired number of dies 102). In an alternative embodiment, stack 100 is monolithized after stacking and bonding (e.g., hybrid bonding without adhesive). Figure 1 The die 102 shown is formed from multiple wafers. In one implementation, such as Figure 1 As shown, the die 102 may not be perfectly aligned in the stack 100. In other words, the edges of the die 102 are not precisely aligned, and there is some error or misalignment “e” from one die 102 to another in the stack 100. In different examples, the misalignment “e” may be caused by the precision tolerance of pick-and-place tools, etc.

[0035] The die 102 (or wafer) can be formed using various techniques to include a substrate 104 and one or more insulating or dielectric layers 106. For example, Figure 1The die 102 shown may represent a double-sided die 102, which has insulating layers 106 on both surfaces of the substrate layer 104. It may also include a die 102', such as... Figure 1 As shown, die 102' can be a single-sided or double-sided die or wafer. In cases where direct bonding to both sides of die 102 is not required, single-sided die 102 or 102' can be positioned in stack 100 as a top die 102, bottom die 102, or any other die 102. Unless otherwise stated, the term "die 102" as used herein includes both single-sided and double-sided dies and wafers.

[0036] The substrate 104 may include silicon, germanium, glass, quartz, a dielectric surface, a direct or indirect gap semiconductor material or layer, or another suitable material. An insulating layer 106 is deposited or formed on the substrate 104 and may be composed of an inorganic dielectric material layer, such as oxides, nitrides, oxynitrides, carbon oxides, carbides, carbonitrides, diamond, diamond-like materials, glass, ceramics, glass ceramics, etc.

[0037] The bonding surface 108 of die 102 may include conductive features 110, such as TSVs, traces, pads, and interconnect structures. For example, the conductive features 110 are embedded in the insulating layer 106 and arranged such that the conductive features 110 of the corresponding bonding surfaces 108 of opposing devices can be matched and joined as needed during the bonding process. The joined conductive features 110 can form continuous conductive interconnects (for signals, power, ground, etc.) between stacked devices.

[0038] An damascene (damascus) process (or similar process) can be used to form embedded conductive features 110 in insulating layer 106. Conductive features 110 can be made of a metal (e.g., copper) or other conductive materials or combinations thereof, and include structures, traces, pads, patterns, etc. In some examples, a barrier layer can be deposited in a chamber for conductive features 110 before depositing the material for conductive features 110, such that the barrier layer is disposed between conductive features 110 and insulating layer 106. The barrier layer can be made of tantalum, titanium, tungsten layers, or combinations thereof with various corresponding compounds or alloys thereof (e.g., or another conductive material) to prevent or reduce the diffusion of material of conductive features 110 into insulating layer 106. After forming conductive features 110, the exposed surfaces of device wafer 102 including insulating layer 106 and conductive features 110 can be planarized (e.g., via CMP) to form a flat bonding surface 108.

[0039] Forming the bonding surface 108 involves trimming the surface 108 to meet dielectric roughness specifications and metal layer (e.g., copper, etc.) recess specifications (if specified) to prepare the surface 108 for hybrid bonding. In other words, the bonding surface 108 is formed to be as flat and smooth as possible, with very small (nanometer-scale) surface topological changes. Low surface roughness can be achieved using various conventional processes such as chemical mechanical polishing (CMP), dry etching, or wet etching. This process provides a flat and smooth surface 108 for generating reliable bonds.

[0040] Embedded conductive traces 112, partially extending into the dielectric substrate 106 beneath the prepared surface 108, can be used to electrically couple conductive features 110 to desired components throughout the die 102. For example, conductive features 110 can be coupled to conductive (e.g., copper) through-silicon vias (TSVs) 114, etc., extending through part or all of the die 102 to achieve electrical connectivity through the thickness of the die 102. For example, in some cases, TSV 114 can extend to about 50 micrometers, depending on the thickness of the die 102. The accompanying drawings illustrate examples of various arrangements of the die 102 with conductive features 110, traces 112, and TSV 114, which are not intended to be limiting. In various embodiments, some of the conductive features 110, traces 112, and TSV 114 may not be present in the die 102 (or wafer), while in other embodiments, additional conductive features 110, traces 112, and TSV 114, or other circuit components, etc., may be present.

[0041] For example, dies 102 can be co-bonded to other dies 102 having metal pads 110, traces 112, and / or TSVs 114 without adhesive to achieve the desired electrical connections through the dies 102 while forming a stack 100. Co-bonding includes direct dielectric-to-dielectric bonding of the respective insulating layers 106 of each die 102 without adhesive or other intermediate materials (e.g., ZIBOND®) and direct metal-to-metal bonding of the respective conductive features 110 of each die 102 without intermediate materials (e.g., DBI®). Dielectric-to-dielectric bonding occurs naturally when the respective bonding surfaces 108 are brought together at ambient temperature. Metal-to-metal bonding (which may include diffusion between the metals of the conductive features 10) can occur with or without pressure using heat.

[0042] like Figure 1As shown, an electrical connection can be established from the top surface of the top die 102 of the stack 100 (e.g., via conductive feature 110) through the dies 102 of the stack 100 (any number of dies 102) (e.g., via conductive elements 110, traces 112, and TSV 114) and to the bottom surface of the bottom die 102 of the stack 100 (e.g., via TSV 114). Figure 1 In the example, conductive feature 110 provides a connection to the top surface of stack 100, and TSV 114 having at least one electrically coupled pad 116 provides a connection to the bottom surface of bottom die 102 of stack 100 (in some cases, a titanium layer (not shown) or the like can couple TSV 114 to pad 116). In alternative embodiments, one or both of the top and bottom surfaces of stack 100 may not have connections, or components different from those shown may provide connections to either the top or bottom surface of stack 100. For example, in some embodiments, stack 100 may not include conductive feature 110 at the top surface of stack 100, or TSV 114 in top die 102, or TSV 114 and pad 116 in bottom die 102.

[0043] In some implementations, one or more TSVs 114 provide thermal connectivity between dies 102. For example, the TSV can help dissipate heat from some dies 102 or transfer it to other dies 102 and / or the external environment. In this implementation, the TSV 114 is made of a thermally conductive material and may include a thermally conductive barrier layer (not shown). In some examples, the TSV 114 may be sized based on the function of the associated die 102 (e.g., heat generation) to achieve optimal heat dissipation.

[0044] Figure 2 This is a cross-sectional profile view of a microelectronic assembly 200 comprising multiple stacks 100 of dies 102. In some embodiments, each stack 100 includes the same number of dies 102. In other embodiments, some stacks 100 may include a different number of dies 102 compared to other stacks 100 of the assembly 200. In one implementation, such as Figure 2 As shown, die 102 is not perfectly aligned within stack 100. In other words, the edges of die 102 are not precisely aligned within stack 100, and there are some edge errors or misalignments from die 102 to die 102. In some embodiments, stack 100 is monolithized from multiple wafers, which, as described above, have been stacked and bonded.

[0045] In one implementation, the bottom die 102' group includes a main wafer 202 for stacking 100. In this implementation, the die 102 can be stacked on the main wafer 202, which is then monolithically mounted at the boundary of the stack 100 as needed. In other implementations, the main wafer 202 can be monolithically mounted at different stages of the process, if any.

[0046] like Figure 2 As shown, one or more stacks 100 of component 200 may be covered in a molding compound 204 including a sealant, etc. In various embodiments, the molding compound 204 may include a high-strength, high-thermal-stress (high-heat-resistant) sealant material, which may also have high heat dissipation properties. Furthermore, it may be desirable for the molding compound 204 to have a coefficient of thermal expansion (CTE) of less than 20 to aid in warpage control. For example, HITACHI® offers such a sealant or "epoxy molding compound" called "CEL". Other similar products are also commercially available. In one embodiment, component 200 is covered by molding compound 204, and then component 200 is sliced ​​into multiple stacks 100. Individual stacks 100 may be covered with additional sealant 204 as needed. In other embodiments, the stacks 100 are molded after the stacks 100 are formed, including stacking and bonding individual dies 102 to the stacks 100 or monolithizing wafers to form dies 102 and stacks 100. For example, the molding compound 204 may be deposited before or after the monolithization of dies 102. In both cases, the molding 204 may cover the entire stack 100 of dies 102 or selected dies 102. For example, in one embodiment, the main wafer 202 (and die 102') may not be covered by the molding 204. This may be due to manufacturing process or design.

[0047] For all implementations disclosed herein, molding part 204 may comprise a single layer of sealant covering some or all of the dies 102 of the stack 100, or molding part 204 may comprise multiple layers of sealant of the same or different materials (e.g., a laminate). Furthermore, in one implementation, molding part 204 includes particles within the sealant, and molding part 204 has a variation in particle density: from a low-particle or particle-free state at the top or bottom of the stack 100 to a higher-density particle state at another location at the top or bottom of the stack 100. In one example, particles may exist at different densities in the multilayer sealant, when present. In various embodiments, molding part 204 includes an inorganic shell, etc.

[0048] In some examples, adding molding 204 to the stack 100 of die 102 and / or component 200 can provide final encapsulation for the stack 100 or component 200. The stacking solution makes it easy to handle during fabrication and assembly, as well as deploy in applications. Molded 204 provides protection for die 102 and stack 100, as well as component 200 and any discrete components that can be encapsulated with die 102.

[0049] In one implementation, such as Figure 2 As shown, the top surface of one or more stacks 100 (or all stacks 100) may not have molding 204. The exposed top surface of the top die 102 may be used to further interconnect the top die 102 of the stack 100 to other circuitry, devices (e.g., optical, radio frequency (RF), analog, digital, logic, memory, or other devices), etc. (e.g., when conductive feature 110 is present at the top surface of die 102), such as including additional dies 102 or components 200. Alternatively or additionally, the top surface of the top die 102 may not be covered to enhance heat dissipation. For example, without sealant 204 at the top surface of the top die 102 of component 200, heat can be dissipated more easily and efficiently from the die 102. In this case, conductive feature 110 (and trace 112) may not be present at the top surface of the top die 102. For example, TSV 114 may be present if it is used to aid in heat dissipation through the top surface.

[0050] In one implementation, component 200 includes one or more electrical contacts or terminals 206 on a surface (e.g., a bottom surface) of component 200. Terminals 206 can be used to electrically couple the component to another circuit, device, printed circuit board (PCB), etc. Figure 2 As shown, terminal 206 can be electrically coupled via pad 116 to TSV 114 (or other interconnects) of die 102 (such as the bottom die 102) of stack 100 of component 200. For example, component 200 may include an electrical connection from one or more top dies 102 of stack 100 (e.g., in some cases, the top surface of the top die 102) through die 102 of stack 100 to terminal 206.

[0051] In some embodiments, additional layers, circuit components, vias, etc., may also be incorporated into stack 100 and / or component 200 as needed. In alternative implementations, TSV 114 may be optional in some dies 102 and / or some stacks 100.

[0052] In one implementation, such as Figure 3As shown, the top surface of one or more stacks 100 (or all stacks 100) may include a molding 204. In this implementation, the molding 204 at the top surface of the stacks 100 and the component 200 protects the stacks 100 and the component 200 during handling, assembly, deployment, etc. In one embodiment, each stack 100 is individually covered by the molding 204, including the top and sides of the stack 100. In one embodiment, the main wafer 202 (and die 102') may not be covered by the molding 204. Figure 3 As illustrated in the examples, in some embodiments, the top die 102 of component 200 may not include conductive features 110 (or traces 112 and / or TSV 114) when no electrical connection is intended at the top surface of die 102 and component 200. These components may be optional, for example, when they are used for other purposes (e.g., when circuit components are disposed on or within the upper insulating layer 106, etc.).

[0053] Similarly, as Figure 3 As shown in the examples, die 102 can have various component configurations and arrangements in certain applications. For example, as Figure 3 As shown, die 102'' may include a TSV 114, which is directly coupled to a conductive pad 110 on an adjacent die 102 to provide connectivity to the adjacent bonded die 102. For example, the end face of the TSV 114 may be exposed at the bonding surface 108 of die 102'' to form a contact surface for bonding to the conductive pad 110 on the adjacent die 102. In other embodiments, such as Figure 3 As shown, die 102'' may include conductive pads 110 at the bonding surface, wherein TSV 114 is directly coupled to conductive pads 110. These conductive pads 110 may be bonded to conductive pads 110 (or other conductive structures) on adjacent dies 102.

[0054] In one implementation, such as Figure 4 and 5 As shown, the entire stack 100 can be covered by molding compound 204, including the main wafer 202 and the die 102'. In this implementation, the main wafer 202 can be monolithized into dies 102' prior to the packaging step so that they can be covered by molding compound 204. Multiple dies 102 (in groups or one at a time) can be stacked onto the main die 102' to form stack 100, which can then be covered by molding compound 204. Alternatively, molding compound 204 can be applied to component 200 after all dies 102 are stacked and bonded to stack 100. In any case, molding compound 204 can be present on the side of stack 100. Furthermore, in an alternative embodiment, the stack 100 of component 200 can be separated from each other after the molding step.

[0055] As shown in the figure Figure 4 An example component 200 is shown, wherein the top surface (i.e., the back side) of component 200 and stack 100 does not have the molding 204. In one embodiment, the molding 204 may be deposited on component 200 and then removed from the top surface of stack 100. In various examples, the molding 204 may be removed from the top surface of stack 100 to provide interconnection to top die 102, improved heat dissipation, etc. Figure 5 This illustrates a case where the top surface (i.e., the back surface) is covered by the molded part 204.

[0056] like Figure 6 and 7 As shown, the sizes (e.g., dimensions, area, coverage area, thickness, etc.) of the dies 102 of the stack 100 can be inconsistent. For example, dies 102 with different coverage areas or thicknesses can be stacked and bonded to form the stack 100. Without the molding part 204, the stack 100 of inconsistent dies 102 presents uneven side edges and / or stacks 100 with different heights. Covering the stack 100 with the molding part 204 can provide the same package as the stack 100 and / or component 200 (in terms of side edges / surface and height).

[0057] Figure 6 The example shown illustrates an embodiment in which die 102 is covered by molding 204 but the main wafer (main die 102') is not covered by molding 204. In some embodiments, the thickness of the molding layer 204 on the side edge of the top die 102 is greater than the thickness of the molding layer 204 disposed on the side edge of the lower second die 102. Figure 7 The example shows an embodiment in which both the die 102 and the main die 102' are covered by the molding 204, as described above.

[0058] like Figure 8 and 9 As shown, in some implementations, stack 100 may include dies 102, which have interconnects on one side instead of the other. For example, as shown, the top die 102 may not have interconnects to its top surface. In this case, interconnects may not be needed on the top surface (e.g., the back side) of stack 100 or component 200. In alternative embodiments, other dies 102 may include interconnects only on one side. In some embodiments, a TSV 114 for the top die 102 is also optional; however, the TSV 114 can be used for heat dissipation.

[0059] In some examples, such as Figure 8 and 9As shown, a heat sink 802 or other component 902 (e.g., a sensor, optical component, etc.) may be included in the stack 100. For example, the heat sink 802 may be located at the top of the stack 100 to assist in dissipating heat from one or more dies 102 of the stack 100 into the environment. In some cases, a thermally conductive TSV 114 may help transfer excess heat from some dies 102 to other dies 102 and the heat sink 802. In alternative embodiments, depending on the application and performance requirements, the heat sink 802 or other component 902 may be located at a location within the stack 100 or at the bottom of the stack 100.

[0060] like Figure 8 and 9 As shown, when the heatsink 802 or other component 902 is located on top of the stack 100, the top of the stack 100 (e.g., the top surface or "back side" of the die 102) may not have the molding 204. In some cases, some stacks 100 of the assembly 200 may include the molding 204 surrounding the stack 100 and included at the top surface of the stack 100, while other stacks 100 (e.g., stacks 100 including the heatsink 802 or other component 902) may not have the molding 204 at the top surface, but have the molding 204 on the sides of the stack 100.

[0061] like Figure 10 and 11 As shown, in some embodiments, consistent and / or inconsistent dies 102 can be stacked and bonded to form a stack 100, wherein a plurality of dies 102 are laterally positioned on the same level within the component 200 package. For example, as Figure 10 As shown, the main die 202 does not need to be monolithized at each stack 100. Therefore, more than one stack 100 can be bonded to a single main die 102'. For example, in Figure 10 In the example, the second and third stacks 100 are bonded to a single master core 102', and the fourth and fifth stacks 100 are bonded to another master core 102'.

[0062] like Figure 10As shown, the stacks 100 bonded to the main master chip 102' can be collectively covered within the molding compound 204. For example, in this example, the second and third stacks 100 can be collectively covered (e.g., co-packaged) within the molding compound 204, while the fourth and fifth stacks 100 can be collectively covered (e.g., co-packaged) within the molding compound 204. Alternatively or in combination, the molding compound 204 for some of the stacks 100 bonded to the common main master chip 102' can be separated, with the separated molding compound 204 individually surrounding each stack 100. As shown in the example, the main master chip 102' (or wafer) can be exempted from molding. Alternatively, the main master chip 102' (or wafer) can be covered with the molding compound 204.

[0063] like Figure 11 As shown, in some embodiments, additional dies 102 may be stacked laterally on the same level as component 200 to form one or more common stacks or partial common stacks 1100. For example, Figure 11 An example of a partial common stack 1100 is shown. In this example, the first row of dies 102 bonded to the main master die 102' may not be monolithized at each stack 100. Therefore, more than one stack 100 can be bonded to a single main master die 102' and the same "first row" die 102.

[0064] For example, in Figure 11 In the example, the second and third stacks 100 include the same first row of dies 102 bonded to the same master die 102'. Subsequent multiple rows of dies 102 of the second and third stacks 100 are bonded to the same first row of dies 102. Therefore, the second and third stacks 100 share a common master die 102' and a common first row of dies 102. When some dies 102 are common to multiple stacks 100, this results in a partially common stack 1100. In other embodiments, additional rows of dies 102 for the second and third stacks 100 may be common. For example, if dies 102 in all rows of multiple stacks 100 are common to multiple stacks 100, this results in a common stack 1100.

[0065] like Figure 11 As shown, the fourth and fifth stacks 100 also include the same first row of dies 102 bonded to the same master die 102'. Subsequent multiple rows of dies 102 of the fourth and fifth stacks 100 are bonded to the same first row of dies 102. Therefore, the fourth and fifth stacks 100 share the common master die 102' and the common first row of dies 102, thereby creating a partially common stack 1100.

[0066] like Figure 10 and 11As shown, the first stack 100 is covered by molding 204 (except for the main core 102'), and each portion of the common stack 1100 is also covered by molding 204 (except for the main core 102'). However, as Figure 10 and 11 As shown, one or more partial common stacks 1100 may include a molding 204 on the top surface of the die 102 of the partial common stack 1100, and one or more partial common stacks 1100 may not have a molding 204 on the top surface of the die 102 of the partial common stack 1100. As described above, removing the molding 204 (or not depositing the molding 204) on the top surface of the top die 102 may allow interconnection with the top die 102, may improve heat dissipation from the top die 102, etc. Additional Examples

[0067] Figure 12 and 13 An example embodiment of component 200 is shown, wherein one or more stacks 100 of bonding dies 102 are bonded to a host wafer 202. In some examples, the host wafer 202 may be monolithically converted into a main die 102' (not shown). In the various embodiments shown, die 102 may be a double-sided die having conductive features 110 embedded within an insulating layer 106 on either side of a substrate layer 104. In some embodiments, details such as traces 112 and TSVs 114 may be assumed to exist, but are not shown for clarity of the drawings.

[0068] In one implementation, such as Figure 12 and 13 As shown, one or more insulating layers 106 may be etched at the peripheral edge of die 102 (see 1202) to remove some of the insulating layer 106 at the periphery. The peripheral etching 1202 may be intentional depending on device, package, processing, etc. In this implementation, etching 1202 may be present on one or more sides or edges of die 102. In some cases, etching 1202 includes removing a portion of the insulating layer 106 at the periphery and exposing the underlying substrate layer 104. In other cases, etching 1202 may not expose the substrate layer 104, or etching 1202 may also remove some of the substrate layer 104.

[0069] Figure 14 This is another illustration of a die 102 having etched peripheral edges (recesses 1202) according to one embodiment. In the example embodiment, Figure 14 The illustration more closely shows the relative proportions of the recess 1202 with respect to the base layer 104 and the insulating layer 106. In other embodiments, other proportions may exist.

[0070] In some cases, as described above, the molding compound 204 may be filled with particles. For example, particles may be added to the molding compound 204 to change its coefficient of thermal expansion (CTE). This can help reduce package warpage, for example, by balancing the CTE across the entire package (e.g., component 200). However, in some cases, the particles in the molding compound 204 may be too large to be contained within the smaller recesses 1202 formed by peripheral etching. Any voids left after the molding compound 204 is applied to the stack 100 can cause “popcorn” failures in the packaged components (e.g., component 200).

[0071] In various implementations, the alternative is to exclude particles from the molded part 204 (and not accept the benefits of doing so), such as Figure 13 As shown, a multilayer molding 204 can be used to mitigate potential failures. For example, a first low-viscosity compound 1302 can be applied around the stack 100 to form a compound layer 1302 around the stack 100 and penetrate the etched recess 1202. Then, a layer of molding 204 can be applied after the layer 1302.

[0072] In this implementation, the first layer of compound 1302 may not include fillers or particles. For example, having a low viscosity, the primary purpose of compound 1302 may be to fill the etched recesses 1302 in die 102. However, compound 1302 may also form a layer on the vertical walls of die 102 of stack 100. After applying the first layer of compound 1302, stack 100 and / or component 200 may be covered by molding 204. In alternative embodiments, additional layers may also be used to cover stack 100 and / or component 200.

[0073] In other implementations, the first layer (low viscosity) compound 1302 (or resin) may comprise submicron particles or even nanoparticles small enough to be incorporated into the recess 1202. The submicron or nanoparticles may comprise silica, silicon, silica / silicon compounds, etc. The size (e.g., diameter) of the nanoparticles may average 20 nm in some cases, while in others they may be smaller or larger.

[0074] In one embodiment, a first layer compound 1302 (having submicron or nano-sized filler particles) is formed over the vertical walls of the die 102 and the recess 1202. In some embodiments, preferably, the submicron or nanoparticle content of the first layer compound 1302 is greater than 5%. The molding layer 204 typically comprises reinforcing particles with a particle content typically greater than 50%, and preferably, the particle content of the molding layer 204 is higher than the particle content of the first layer compound 1302 within the recess 1202. Similarly, in some applications, it is preferable that the nominal size of the particles in the molding layer 204 is larger than the nominal size of the particles in the first layer compound 1302.

[0075] refer to Figure 15 and 16 In typical practice, ball grid arrays (BGAs) and other similar techniques are used to couple memory dies to other memory dies. In these cases, the die-to-die pitch is typically around 45 micrometers. Using similar techniques, the logic die-to-intercalation pitch is approximately 90-100 micrometers. However, in some embodiments, it is possible and practical to assemble memory die stacks (such as stack 100) separately with a finer pitch and then stack them on top of the logic dies. Note that in some cases, the logic die may not be larger than the memory die.

[0076] Figure 15 and 16 An example of a "high-bandwidth memory" component 200 is shown, which includes a stack 100 of memory dies 102 (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, etc.) coupled to logic dies 1502. As described above, in various implementations, dies 102 are hybrid bonded (DBI®) to form the stack 100. Figure 15 As shown, stack 100 (or bottom die 102) can be hybrid-bonded to logic die 1502. Logic die 1502 may include terminals 206 for coupling component 200 to circuitry, PCBs, devices, etc., as described above. Using direct or hybrid bonding techniques, the distance between dies 102 and between die 102 and logic die 1502 can be significantly reduced (this distance is the die thickness plus the height of the copper pillars and solder balls, due to die thickness and current technology). In one embodiment, circuit elements (such as conductive features 110, etc.) at a bonding surface of one or more bonded dies 102 are less than 20 micrometers, and in other applications less than 5 micrometers or even less than 1 micrometer.

[0077] like Figure 16As shown, alternatively, flip-chip technology or similar techniques can be used to couple the stack 100 to the logic die 1502. For example, a flip-chip terminal 1602 can be coupled to the bottom side of the bottom die 102, which engages with a terminal 1602 at the top surface of the logic die 1502. Therefore, a combination of hybrid bonding and flip-chip technology can be used with component 200. In alternative embodiments, other coupling techniques can also be used, if desired, to couple the hybrid bonding stack 100 to the logic die 1502, inserts, etc.

[0078] exist Figure 16 The image also shows a molding 1604 that covers the flip chip terminals 1602 and fills the gap between the stack 100 and the logic die 1502. In some embodiments, the component 200 may also be covered by the molding 204 as needed for processing, packaging, etc.

[0079] Figures 17-20 Additional implementations using stack 100 and / or component 200 are shown in various applications. For example, in Figure 17 The diagram illustrates component 1700, which includes multiple dies 102, including a stack 100 of dies 102 mixed and bonded to the insert 1702. In one embodiment, the insert 1702 is made of a semiconductor, such as silicon. The drawings have been simplified for clarity.

[0080] In various embodiments, such as Figure 17 As shown, some dies 102 may be molded, while others may not be molded. A heatsink or other cooling device 1704 (e.g., a fan, etc.) is coupled to the unmolded dies 102 to cool them (which may include high-power components such as processors, etc.). The insert 1702 includes a hybrid bonding pad 110 and at least one wire bonding pad 1706.

[0081] like Figure 18 As shown, wire bonding pad 1706 can be used to couple remote components (e.g., components coupled to (or through) laminate 1802 or integral with laminate 1802) to pad 1706 via wire 1804. In the illustrated embodiment, laminate 1802 is co-bonded to insert 1702. Alternatively, laminate 1802 can be coupled to insert 1702 via another bonding technique.

[0082] For example, such as Figure 19 As shown, the laminate 1802 can be coupled to the insert 1702 using BGA technology, another surface mount technology, etc. In one implementation, such as Figure 19As shown, the laminate 1802 may include one or more wire bonding pads 1902, which may be used with wires 1804 to couple to wire bonding pads 1706, etc.

[0083] In one embodiment, such as Figure 19 As shown, component 200 or stack 100 can be packaged together with another component 1904, which can be co-bonded to insert 1702. Component 1904 and component 200 or stack 100 can be covered within a molded part 1906 including a sealant (or other encapsulation) as needed. Package or stack 100 and component 1904 can be co-bonded to insert 1702. Cooling device 1704 can be coupled to component 1904 and / or stack 100, as... Figure 19 As shown. Additionally, filler 1604 can be used to cover terminal 206 and fill the gap between insert 1702 and laminate 1802. Alternatively, insert 1702 can be packaged together with other components or separately.

[0084] like Figure 20 As shown, stack 100 may be covered by molding 204, while other dies 102 and / or components may be uncovered. Heat sinks or other cooling devices 1704 (e.g., fans, etc.) are coupled to the unmolded dies 102 to cool them (which may include high-power components such as processors, etc.). Additional cooling devices may also be coupled to stack 100, which may not have molding 204 at its top surface. Insert 1702 includes hybrid bonding pads 110 and at least one wire bonding pad 1706. As shown, insert 1702 may be coupled to laminate 1802 via BGA arrangement or other coupling techniques. Example process

[0085] Figure 21 This is a flowchart illustrating an example process 2100 for forming a microelectronic assembly (such as microelectronic assembly 200) comprising a stack of dies (e.g., a stack 100 of dies 102) and bonding. In some embodiments, the stack of dies may be covered by a molding (e.g., molding 204) for handling, processing, application, etc. Process 2100 references... Figures 1 to 20 .

[0086] The order in which the processes are described is not intended to be limiting, and any number of the described process blocks can be combined in any order to implement the process or alternative processes. Furthermore, individual blocks may be removed from the process without departing from the spirit and scope of the subject matter described herein. Moreover, the process can be implemented in any suitable hardware, software, firmware, or combination thereof without departing from the scope of the subject matter described herein. In alternative implementations, other techniques may be included in the process in various combinations and remain within the scope of this disclosure.

[0087] At block 2102, the process includes forming a microelectronic stack (e.g., a stack 100 of die 102). In an alternative embodiment, the process includes forming multiple microelectronic stacks. In one implementation, forming a microelectronic stack includes the following blocks:

[0088] At block 2104, the process includes providing a first substrate (e.g., a first die 102) having a front side and a back side. The back side has a bonding surface including a non-conductive bonding layer and exposed conductive first circuit elements. The first substrate has first circuit elements electrically coupled to the first substrate and extending at least partially through a first conductive via through the first substrate.

[0089] In block 2106, the process includes providing a second substrate having a front side and a back side. The front side includes a non-conductive bonding layer and exposed conductive first circuit elements.

[0090] At block 2108, the process includes coupling the front side of the second substrate to the back side of the first substrate by contacting a non-conductive bonding layer between the first and second substrates. In one embodiment, the side edges of the first substrate are not aligned with the side edges of the second substrate. Coupling includes contacting a first circuit element of the first substrate with a first circuit element of the second substrate (e.g., hybrid bonding).

[0091] At block 2110, the process includes covering the side edges of the first and second substrates with a molding compound (e.g., molding compound 204). In one implementation, the process includes covering the back side of the second substrate with the molding compound. In various embodiments, the molding compound comprises more than one layer or more than one material or compound. In some embodiments, at least one of the multiple layers of the molding compound comprises particles to help balance the CTE of the component, thereby preventing component warpage.

[0092] In one embodiment, the back side of the second substrate includes a second non-conductive bonding layer and exposed conductive second circuit elements. In this embodiment, the second substrate has a second conductive via that electrically couples the first circuit elements of the second substrate to the second circuit elements.

[0093] In one implementation, the process includes providing a third substrate having a front side and a back side, the front side including a non-conductive bonding layer and exposed conductive first circuit elements. The process includes coupling the front side of the third substrate to the back side of the second substrate by contacting the non-conductive bonding layer of the third substrate with a non-conductive bonding layer of the second substrate. In one embodiment, the side edges of the third substrate are not aligned relative to the side edges of the second substrate and / or the first substrate. Coupling includes contacting the first circuit elements of the third substrate with second circuit elements of the second substrate (e.g., hybrid bonding).

[0094] In this implementation, the process includes forming a recess at the bonding layer of the first and / or second substrates at the periphery of the first and / or second substrates before covering the side edges of the first and second substrates with a molding member, and filling at least the recess with a low-viscosity compound.

[0095] In another implementation, the process includes covering the side edges of the third substrate with a molding compound. In yet another implementation, the process includes covering the back side of the third substrate with a molding compound.

[0096] In one implementation, the process includes co-bonding a stack of microelectronics to a semiconductor insert having at least one wire bonding contact pad. In another implementation, the process includes coupling the insert to a laminate having a second wire bonding contact pad, and bonding at least one wire bonding contact pad of the insert to the second wire bonding contact pad of the laminate using wires. For example, the insert may be co-bonded to the laminate.

[0097] In other implementations, parts of the microelectronic component are covered by one or more molding layers, while other parts are not covered.

[0098] Although various implementations and examples are discussed herein, other implementations and examples are possible by combining features and elements of the various implementations and examples. In various embodiments, some process steps may be modified or eliminated compared to the process steps described herein.

[0099] The technologies, components, and devices described herein are not limited to Figures 1 to 21 The illustrations herein, without departing from the scope of this disclosure, can be applied to other designs, types, arrangements, and constructions, including other electrical components. In some cases, additional or alternative components, techniques, sequences, or processes may be used to implement the techniques described herein. Furthermore, these components and / or techniques may be arranged and / or combined in various combinations, producing similar or nearly identical results. in conclusion

[0100] Although implementations of this disclosure have been described in language specific to structural features and / or method actions, it should be understood that the implementation is not necessarily limited to the specific features or actions described. Rather, the specific features and actions disclosed are representative forms of the implementation example devices and technologies.

[0101] Each claim in this document constitutes a separate embodiment, and embodiments combining different claims and / or different embodiments are within the scope of this disclosure and will be clear to those skilled in the art upon review of this disclosure.

Claims

1. A microelectronic component, comprising: Substrate; A first die and a first bonding layer on the first die, wherein the first bonding layer is directly bonded to the substrate without adhesive; The second die has microelectronic circuit elements formed therein, and the second die is disposed on top of the first die, wherein the first die is directly bonded to a second bonding layer on the second die without adhesive. The first encapsulation layer is configured to be adjacent to the sidewall of the second die; as well as A second encapsulation layer is deposited on and laterally adjacent to the first encapsulation layer, the second encapsulation layer comprising an inorganic material.

2. The microelectronic component according to claim 1, wherein the first encapsulation layer and the second encapsulation layer have different material compositions.

3. The microelectronic assembly according to claim 1, wherein the side edge of the second die is laterally offset from the side edge of the first die.

4. The microelectronic component according to claim 1, wherein the first encapsulation layer and the second encapsulation layer have different coefficients of thermal expansion (CTE).

5. The microelectronic component according to claim 1, wherein the first encapsulation layer comprises silicon dioxide.

6. The microelectronic component of claim 1, further comprising a conductive feature on the surface of the second die opposite to the second bonding layer, the conductive feature being configured to be electrically connected to another component.

7. The microelectronic component of claim 6, wherein the surface of the second die is free of the first encapsulation material.

8. The microelectronic component of claim 6, further comprising a plurality of through-substrate vias (TSVs) in the second die.

9. The microelectronic component of claim 8, wherein the first die includes a first plurality of pads, wherein the plurality of TSVs in the second die are connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

10. The microelectronic component of claim 1, wherein the substrate has a first lateral coverage area larger than the second lateral coverage area of ​​the first die, and wherein the second lateral coverage area of ​​the first die is smaller than the third lateral coverage area of ​​the second die.

11. The microelectronic component of claim 10, wherein the first lateral coverage area of ​​the substrate is larger than the third lateral coverage area of ​​the second die.

12. The microelectronic component of claim 1, wherein the first die area of ​​the first die is smaller than the second die area of ​​the second die.

13. The microelectronic component of claim 1, wherein the second bonding layer on the first die and the second die is directly bonded using dielectric-to-dielectric and metal-to-metal direct bonding.

14. The microelectronic component of claim 1, wherein the first die comprises a memory die.

15. The microelectronic component of claim 1, wherein the first encapsulation layer comprises a plurality of layers.

16. The microelectronic component of claim 1, wherein the first encapsulation layer comprises molding compound.

17. The microelectronic component of claim 1, wherein a portion of the first encapsulation layer is disposed on a portion of the first die.

18. A microelectronic component, comprising: Substrate; A first die and a first bonding layer on the first die, the first bonding layer being directly bonded to the substrate without adhesive, the first die comprising a memory die; The second die has microelectronic circuit elements formed therein, and the second die is disposed on top of the first die, wherein the first die is mixed and bonded to a second bonding layer on the second die; The first encapsulation layer is configured to be adjacent to the sidewall of the second die; as well as A second encapsulation layer is deposited on and laterally adjacent to the first encapsulation layer, and the second encapsulation layer comprises an inorganic material. The surface of the second die opposite to the second bonding layer includes a conductive feature configured to be electrically connected to another component, and the surface of the second die does not have the first encapsulation layer.

19. The microelectronic component of claim 18, wherein the first encapsulation layer and the second encapsulation layer have different material compositions.

20. The microelectronic component of claim 18, wherein the first encapsulation layer comprises a plurality of layers.

21. The microelectronic component of claim 18, wherein the first encapsulation layer comprises silicon dioxide.

22. The microelectronic component of claim 18, wherein the first encapsulation layer comprises an inorganic material.

23. The microelectronic component of claim 18, wherein the first encapsulation layer comprises molding compound.

24. The microelectronic component of claim 18, further comprising a plurality of through-substrate vias (TSVs) in the second die.

25. The microelectronic component of claim 24, wherein the first die includes a first plurality of pads, wherein the plurality of TSVs in the second die are connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

26. The microelectronic component of claim 18, wherein the substrate has a first lateral coverage area larger than the second lateral coverage area of ​​the first die, and wherein the second lateral coverage area of ​​the first die is smaller than the third lateral coverage area of ​​the second die.

27. The microelectronic component of claim 26, wherein the first lateral coverage area of ​​the substrate is larger than the third lateral coverage area of ​​the second die.

28. A microelectronic component, comprising: Substrate having a first lateral coverage area; A first die and a first bonding layer on the first die, the first bonding layer being directly bonded to the substrate without adhesive, the first die comprising a memory die, the first die having a second lateral coverage area smaller than the first lateral coverage area; The second die has microelectronic circuit elements formed therein and is disposed on top of the first die, the first die is mixed and bonded to a second bonding layer on the second die, and the second die has a third lateral coverage area that is smaller than the first lateral coverage area and larger than the second lateral coverage area. as well as The first encapsulation layer is configured to be adjacent to the sidewall of the second die.

29. The microelectronic component of claim 28 further includes a second encapsulation layer, the second encapsulation layer being deposited on the first encapsulation layer and configured to be laterally adjacent to the first encapsulation layer.

30. The microelectronic component of claim 29, wherein the first encapsulation layer and the second encapsulation layer comprise at least two different materials.

31. The microelectronic component of claim 28, wherein the first encapsulation layer comprises an inorganic material.

32. The microelectronic component of claim 28, further comprising a plurality of through-substrate vias (TSVs) in the second die, wherein the first die includes a first plurality of pads, wherein the plurality of TSVs in the second die are connected to a second plurality of pads in the second bonding layer, the second plurality of pads being directly bonded to the first plurality of pads.

33. The microelectronic assembly of claim 28, wherein at least two side edges of the first die are disposed within the third lateral coverage area of ​​the second die.

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