Software and hardware hybrid calibration method and system for navigation anti-interference system

Abstract

The invention provides a software and hardware mixed calibration method and system for a navigation anti-interference system, the calibration method comprises hardware calibration and software calibration, the hardware calibration adopts power-on one-time calibration, and the software calibration is dynamically adjusted according to the real-time state of a navigation signal in the operation process of the navigation anti-interference system; the hardware calibration comprises the steps that the radio frequency switch is switched to the second switching end to enter a calibration mode; the calibration signals are respectively sent to the FPGA chip calibration module; the first path is designated as a reference path, and the other paths are to-be-calibrated paths; optionally selecting one to-be-calibrated path to be compared with the reference path, and calculating a time-varying consistency response; the software calibration comprises the following steps: the radio frequency switch is switched to the first switching end to enter a normal working mode; normal signals are respectively sent to the FPGA chip calibration module; consistency calibration is carried out on the reference path and all the to-be-calibrated paths at the same time, all the to-be-calibrated paths are compared with the reference path, and time-varying consistency response is calculated. By adopting the calibration method provided by the invention, null offset is effectively avoided, and the anti-interference capability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of navigation anti-jamming, and particularly relates to a software and hardware hybrid calibration method and system for a navigation anti-jamming system. BACKGROUND

[0002] With the wide application of wireless communication technology, the electromagnetic environment presents a complex situation of "multiple interference types, high intensity, and intelligence", and navigation systems are facing severe threats. Among them, radio interference covers useful signals through narrowband / wideband suppression signals, electromagnetic pulse interference damages radio frequency front ends with transient strong energy, and artificial deception interference misleads the receiving end by disguising as navigation signals. These interferences may cause missile guidance deviation to exceed 100 meters, and in the civil aviation scene, the positioning accuracy is reduced from meters to hundreds of meters, threatening the safe operation of the fields of transportation, aerospace, etc.

[0003] To cope with the above threats, anti-jamming antennas have become the core equipment to improve the anti-jamming capability of navigation receivers. According to the difference in the incident direction of useful signals and interference signals, it adjusts the weighting coefficients of each channel through the "spatial filtering" principle, and forms a directional diagram of "main lobe pointing to useful signals and null suppressing interference signals". However, this process highly depends on the amplitude and phase consistency of each radio frequency channel: if the channel amplitude deviation exceeds 0.5 dB or the phase deviation exceeds 5°, the null depth will drop from 30 dB to below 15 dB, and the anti-jamming effect will be significantly weakened; if the deviation is further expanded, the null may even shift, completely losing the ability to suppress interference.

[0004] However, each channel of the anti-jamming antenna contains analog devices such as low-noise amplifiers, mixers, intermediate frequency amplifiers, etc., which are affected by factors such as manufacturing tolerance, temperature difference, environmental fluctuations, etc., and channel mismatch problems are difficult to avoid. Manufacturing tolerance leads to a gain deviation of ±1 dB for low-noise amplifiers in the same batch and a phase shift of ±3° for mixers; temperature difference (such as an array temperature difference of 10℃) causes a crystal oscillator frequency drift of ±5ppm, which translates to a phase deviation of ±1.8°; humidity and vibration cause filter insertion loss fluctuations of ±0.3 dB. These deviations will make the output signals of each array element incoherent, and the back-end algorithm cannot accurately estimate the signal direction, which in turn leads to a decrease in the main lobe gain of the directional diagram and an increase in the side lobe, ultimately causing a decrease in anti-jamming performance, thus reducing the signal-to-noise ratio of the navigation receiver and the positioning accuracy, and even causing the receiver to lose lock. Therefore, how to solve the channel mismatch problem has become a key technical bottleneck to improve the performance of the navigation anti-jamming system.

[0005] Existing calibration methods for navigation anti-jamming systems employ either pure hardware or pure software calibration. Hardware calibration suffers from "step limitations" in its physical adjustments, failing to achieve continuous accuracy compensation. Furthermore, the adjustable range of hardware is limited; calibration becomes completely ineffective when channel errors exceed the hardware's adjustment limit. Pure software calibration can only compensate for "modelable systematic errors" (such as fixed offsets and linear gain deviations), and cannot address the inherent physical defects of the hardware. For example, in navigation anti-jamming systems, nonlinear distortion in the RF amplifier represents a physical deviation that exceeds the algorithm's correction capabilities.

[0006] Therefore, a hybrid hardware and software calibration method and system for navigation anti-interference systems is needed to at least partially solve the above-mentioned technical problems. Summary of the Invention

[0007] In view of this, embodiments of this application provide a hardware and software hybrid calibration method and system for a navigation anti-interference system, in order to at least solve one of the problems in the prior art.

[0008] In a first aspect, embodiments of this application provide a hardware-software hybrid calibration system for a navigation anti-interference system, the calibration system comprising: An antenna array composed of 100 oscillators is used to receive navigation signals; Each RF switch has a common terminal, a control terminal, a first switching terminal, and a second switching terminal. The first switching terminal signal of each RF switch is connected to the corresponding element of the antenna array. Each RF unit includes a low-noise amplifier, a digitally controlled attenuator, a shared RF chip, an intermediate frequency filter, and a shared up-converter connected in sequence. The input signal of the low-noise amplifier of each RF unit is connected to the common terminal of the RF switch of the corresponding channel. Intermediate frequency (IF) unit, wherein the input terminal of the IF unit is connected to the IF filter of each radio frequency (RF) unit, and the output terminal is connected to... The upconverter shared by the radio frequency units is used for analog-to-digital / digital-to-analog conversion, calibration signal generation, anti-interference beamforming, protocol conversion, hardware calibration control, and software calibration processing. A power divider is used to generate one channel of radio frequency signal. The power divider's calibration signal Each output terminal is connected to the second switching terminal of the corresponding RF switch, and the input terminal is connected to the upconverter; The intermediate frequency unit is also connected to the radio frequency chip, the control terminal of each radio frequency switch, and each digitally controlled attenuator.

[0009] Optionally, the intermediate frequency unit includes an FPGA chip and components respectively connected to the input terminals of the FPGA chip. The FPGA chip includes a digital-to-analog converter (DAC) and a digital-to-analog converter (DAC) connected to the output of the FPGA chip. The input of each DAC is connected to the intermediate frequency (IF) filter of the corresponding RF unit. The upconverter shared by the radio frequency units; The output of the FPGA chip is also connected to the radio frequency chip, the control terminal of each radio frequency switch, and each digitally controlled attenuator.

[0010] Secondly, this application also provides a hardware and software hybrid calibration method for a navigation anti-interference system. The calibration method includes hardware calibration and software calibration. The hardware calibration is a one-time calibration upon power-on, while the software calibration is dynamically adjusted according to the real-time status of the navigation signal during the operation of the navigation anti-interference system. Hardware calibration includes the following steps: The FPGA sends a high-level control signal to the RF switch via a general purpose input / output port, causing the RF switch to switch to the second switching terminal and enter the calibration mode; The FPGA generates an intermediate frequency (IF) single-carrier signal, which is then converted into an analog signal by a digital-to-analog converter (DAC) and fed into an upconverter to convert the IF signal to radio frequency (RF). The output signal of the upconverter is then divided by a power divider. The calibration signals are respectively connected to the path calibration signal. The second switching terminal of the RF switch; The path calibration signals are respectively connected to After the RF unit, the signal is sent to the FPGA chip calibration module via the corresponding analog-to-digital converter. Designate the first path as the reference path, and the remaining paths as paths to be calibrated; Choose any path to be calibrated and compare it with the reference path, calculate the time-varying consistency response, and adjust the gain of the RF chip and digitally controlled attenuator and the phase of the RF chip of the path to be calibrated by configuring the register. Then repeat the process for the remaining paths to be calibrated. Software calibration includes the following steps: The FPGA sends a low-level control signal to the RF switch via a general purpose input / output port, causing the RF switch to switch to the first switching terminal and enter the normal operation mode. Antenna array Each oscillator receives a normal signal and sends it to... RF unit, The normal signal is sent to the FPGA chip calibration module via an analog-to-digital converter; Designate the first path as the reference path, and the remaining paths as paths to be calibrated; The reference path and all paths to be calibrated are simultaneously subjected to consistency calibration. All paths to be calibrated are compared with the reference path, and the time-varying consistency response is calculated. Amplitude compensation and phase compensation are performed on all paths to be calibrated in the FPGA.

[0011] Optionally, the FPGA calibration module calculates the time-varying consistency response, specifically including: Perform calibration on the reference path and the path to be calibrated separately. Each independent sample is [number] times, with a sample length of [length]. Points were obtained to acquire two time-domain sequences; Perform on each time-domain sequence Point Fast Fourier Transform generates two paths Group of complex sequences in the frequency domain; The target frequency point corresponding to the carrier frequency of the positioning calibration signal is located from... Extracting the complex number of the target frequency point from a group of complex number sequences in the frequency domain; Amplitude and phase errors are calculated based on frequency domain ratios.

[0012] Optionally, the FPGA calibration module calculates the time-varying consistency response, specifically including: The reference path and all paths to be calibrated are sampled synchronously and independently, with each sample length being [length missing]. Points, obtain Path time-domain sequence; right Execution of time-domain sequences Point Fast Fourier Transform, generating Path frequency domain complex sequence; In the frequency domain complex sequence of the corresponding reference path, the frequency point with the largest positioning amplitude is the target frequency point. The reference path and all paths to be calibrated extract the complex number of the target frequency point from their respective frequency domain complex sequences. Calculate the frequency domain ratio of each path to be calibrated to the reference path at the target frequency, and determine the amplitude deviation and phase deviation of each path to be calibrated relative to the reference path.

[0013] According to the calibration method of this application embodiment, hardware calibration generates a single-carrier calibration signal through an FPGA chip, and controls the gain and phase of the radio frequency according to the calibration algorithm to complete the static deviation compensation at the hardware level; software calibration is performed in real time during system operation. For normally received navigation signals, the frequency domain ratio of the path to be calibrated to the reference path is calculated as a compensation coefficient, and dynamic amplitude and phase deviation correction is realized in the digital domain of the FPGA chip. Through hardware and software collaboration, it covers all types of channel mismatch scenarios such as manufacturing tolerances and temperature drift, controls the channel amplitude deviation and phase deviation within a limited range, and maintains the null depth stably. This significantly improves the positioning accuracy and stability of the navigation anti-interference system in complex electromagnetic environments, and requires no additional hardware resources, making it highly feasible in engineering.

[0014] Additional advantages, objectives, and features of this application will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon review of the following description, or may be learned by practice of the application. The objectives and other advantages of this application can be realized and obtained by means of the structures specifically pointed out in the specification and drawings.

[0015] Those skilled in the art will understand that the purposes and advantages that can be achieved with this application are not limited to those specifically described above, and that the above and other purposes that this application can achieve will be more clearly understood from the following detailed description. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, do not constitute a limitation thereof. The components in the drawings are not drawn to scale but are merely for illustrating the principles of this application. For ease of illustration and description of certain parts of this application, corresponding portions in the drawings may be enlarged, i.e., may appear larger relative to other components in an exemplary device actually manufactured according to this application. In the drawings: Figure 1 This is a structural block diagram of a calibration system according to an embodiment of this application; Figure 2 This is a flowchart of a calibration method according to an embodiment of this application; Figure 3 This is a hardware calibration flowchart of a calibration method according to an embodiment of this application; Figure 4 This is a flowchart of the software calibration process in a calibration method according to an embodiment of this application.

[0017] Explanation of reference numerals in the attached figures: 100. Calibration system; 110. Antenna array; 111. Vibrator; 120. Radio frequency switch; 130. RF unit; 131. Low-noise amplifier; 132. Digitally controlled attenuator; 133. RF chip; 134. Intermediate frequency filter; 135. Upconverter; 140. Intermediate frequency unit; 141. Analog-to-digital converter; 142. FPGA chip; 143. Digital-to-analog converter; 150. Power divider. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the embodiments and accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain this application, but are not intended to limit it.

[0019] It should also be noted that, in order to avoid obscuring this application with unnecessary details, only the structures and / or processing steps closely related to the solution according to this application are shown in the accompanying drawings, while other details that are not closely related to this application are omitted.

[0020] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, element, step, or component, but does not exclude the presence or addition of one or more other features, elements, steps, or components.

[0021] It should also be noted that, unless otherwise specified, the term "connection" in this article can refer not only to a direct connection, but also to an indirect connection involving an intermediary.

[0022] In the following description, embodiments of the present application will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar parts, or the same or similar steps.

[0023] First, refer to Figure 1 This application describes a hardware / software hybrid calibration system 100 for a navigation anti-interference system according to an embodiment of the present application. For example... Figure 1 As shown, the calibration system 100 includes an antenna array 110, RF switch 120 The circuit includes a radio frequency unit 130, an intermediate frequency unit 140, and a power divider 150. Among these, It is a positive integer.

[0024] Specifically, by An antenna array 110, consisting of 111 oscillators, is used to receive navigation signals.

[0025] in, The oscillators 111 can be arranged in a uniform square or circular array. The spacing between the oscillators 111 can be... . The wavelength is the navigation signal wavelength. The arrangement direction of each oscillator 111 can be consistent with the direction of the incoming navigation signal wave, thereby improving the signal reception gain.

[0026] Each of the RF switches 120 has a common terminal, a control terminal, a first switching terminal, and a second switching terminal. The first switching terminal signal of each RF switch 120 is connected to the corresponding element 111 of the antenna array 110. The RF switches can be single-pole double-throw (SPDT) type RF switches. When the first switching terminal signal is connected to the corresponding element of the antenna array, it is in normal operating mode. When the second switching terminal signal is connected to the output of the power divider, it is in hardware calibration mode.

[0027] Each of the RF units 130 includes, in sequence, a low-noise amplifier 131 (LNA), a digitally controlled attenuator 132, a shared RF chip 133, an intermediate frequency filter 134, and a shared up-converter 135. The input signal of the LNA 131 of each RF unit is connected to the common terminal of the corresponding RF switch 120. Each RF unit can achieve high-quality processing and frequency conversion of weak RF signals. The aforementioned radio frequency units with the same path operate in parallel. These radio frequency units can simultaneously receive radio frequency signals of the same frequency and then perform independent processing and frequency conversion.

[0028] Furthermore, the RF chip 133 can be a CA-RF1947 RF chip. The CA-RF1947 RF chip integrates a four-channel independent downconversion receiver link, a low-noise fractional frequency synthesizer, and a system clock circuit. It also incorporates functional modules such as a low-noise amplifier, mixer, local oscillator phase-shifting network, intermediate frequency amplifier / attenuator, and output buffer. It supports individual configuration of the gain and phase parameters of each channel via the SPI interface, providing core support for hardware calibration.

[0029] Intermediate frequency unit 140, the input of which is connected to the intermediate frequency filter 134 of each radio frequency unit, and the output of which is connected to... The upconverter 135, shared by the radio frequency units, is used for analog-to-digital / digital-to-analog conversion, calibration signal generation, anti-interference beamforming, protocol conversion, hardware calibration control, and software calibration processing.

[0030] Specifically, the intermediate frequency unit 140 may include an FPGA chip 142, and components respectively connected to the input terminals of the FPGA chip. The system includes one analog-to-digital converter (ADC) 141 and one digital-to-analog converter (DAC) 143 connected to the output of the FPGA chip. The input of each ADC 141 is connected to the intermediate frequency filter of the corresponding RF unit. The DAC is connected to... The upconverter is shared by all RF units. The ADC performs analog-to-digital signal conversion. The DAC performs digital-to-analog signal conversion. The FPGA, based on a digital synthesis module (DDS), processes calibration signal generation, anti-interference beamforming (calculating weighting coefficients based on calibrated data), protocol conversion (debugging protocol, client protocol, etc.), hardware calibration control (SPI driver, error calculation, register configuration), and software calibration processing (real-time sampling, fast Fourier transform, compensation coefficient calculation, time-domain compensation).

[0031] A power divider 150 is used to generate one channel of radio frequency signal. Circuit calibration signal. Power divider. Each output terminal is connected to the second switching terminal of the corresponding RF switch, and the input terminal is connected to the upconverter.

[0032] The intermediate frequency unit 140 is also connected to the radio frequency chip 133, the control terminal of each radio frequency switch 120, and each digitally controlled attenuator 132. When the intermediate frequency unit adopts an ADC-FPGA-DAC combination, the output terminal of the FPGA chip is also connected to the radio frequency chip, the control terminal of each radio frequency switch, and each digitally controlled attenuator.

[0033] The calibration system according to the embodiments of this application can solve the technical problems of limited accuracy of existing pure hardware calibration and inability of pure software calibration to correct physical defects, thereby improving the amplitude and phase consistency and anti-interference performance of multi-channel navigation anti-interference system.

[0034] The following will combine Figure 2 , Figure 3 and Figure 4 A calibration method 200 according to an embodiment of this application is described. The radio frequency chip used in calibration method 200 is exemplified by the CA-RF1947 radio frequency chip, but this is not intended to be limiting.

[0035] Calibration method 200 may include hardware calibration 210 and software calibration 220. Hardware calibration is a one-time power-on calibration that utilizes the configurable gain and phase of the RF chip and a digitally controlled attenuator to perform hardware compensation without increasing hardware resources. Software calibration, as a supplement to hardware calibration, dynamically adjusts the system based on the real-time signal status during operation. It can track channel characteristic drift caused by environmental changes (such as temperature and electromagnetic interference), further optimize channel consistency, and perform calibration in the digital domain.

[0036] Specifically, see Figure 3 Hardware calibration 210 may include the following steps: In step S211, the FPGA sends a high-level control signal to the RF switch via a general purpose input / output port (GPIO) to switch the RF switch to the second switching terminal and enter the calibration mode.

[0037] In step S212, the FPGA's DDS module generates an intermediate frequency (IF) single-carrier signal (power and frequency are configurable). This signal is converted to an analog signal by a digital-to-analog converter and then sent to an upconverter to convert the IF signal to radio frequency (RF). For example, the GPS IF is 45.42MHz, and the RF is 1575.42MHz. The upconverter output signal is then divided by 1 minute... Power dividers (isolation ≥20dB) are divided into The calibration signals are respectively connected to the path calibration signal. The second switching terminal of the RF switch.

[0038] In step S213, The path calibration signals are respectively connected to After the RF unit, the signal is sent to the FPGA chip calibration module via the corresponding analog-to-digital converter.

[0039] In step S214, the first path is designated as the reference path, and the remaining paths... The path is to be calibrated. .

[0040] In step S215, one path to be calibrated is selected and compared with the reference path to calculate the time-varying consistency response (amplitude / phase error). The gain of the RF chip and digitally controlled attenuator of the path to be calibrated is adjusted through the configuration register (to compensate for amplitude error) and the phase of the RF chip is adjusted (to compensate for phase error). Then, the process is repeated for the remaining paths to be calibrated.

[0041] In step S215, the FPGA calibration module calculates the time-varying consistency response, which may include: Dual-channel time-domain sampling: for the reference channel and the path to be calibrated Perform separately Each sampling is independent. The length of each sampling is... Points are used to obtain two time-domain sequences.

[0042] Suggested route: .

[0043] Path to be calibrated: .

[0044] in, .

[0045] Frequency domain transformation: Performed on each time domain sequence. Point Fast Fourier Transform (FFT) generates two paths Group of complex sequences in the frequency domain.

[0046] Suggested route: .

[0047] Path to be calibrated: .

[0048] in, ; Corresponding frequency points. Frequency domain conversion uses existing frequency domain conversion methods.

[0049] Target frequency extraction: Locate the target frequency corresponding to the carrier frequency of the calibration signal, from... Extract the complex number of the target frequency point from the group frequency domain complex number sequence.

[0050] Extracted target frequency points The complex form of is , Suggested route: .

[0051] Path to be calibrated: .

[0052] Calculate the frequency domain ratio .

[0053] in .

[0054] Amplitude and phase errors are calculated based on frequency domain ratios.

[0055] Calculate amplitude error After converting to dB value, take Group average.

[0056] Calculate phase error ,Pick Group average.

[0057] Finally, based on the amplitude error, the GPIO controls the digitally controlled attenuator and the SPI configures the RF chip's gain register. Based on the phase error, the RF chip's phase register is configured via SPI. The above steps are repeated to complete the calibration of the other paths and the reference path in sequence.

[0058] See Figure 4 Software calibration 220 may include the following steps: In step S221, the FPGA sends a low-level control signal to the RF switch via a general purpose input / output port, causing the RF switch to switch to the first switching terminal and enter normal operation mode.

[0059] In step S222, the antenna array's Each oscillator receives a normal signal and sends it to... RF unit, Normal signals are sent to the FPGA chip calibration module via an analog-to-digital converter.

[0060] In step S223, the first path is designated as the reference path, and the remaining paths are paths to be calibrated.

[0061] In step S224, the reference path and all paths to be calibrated are simultaneously subjected to consistency calibration. All paths to be calibrated are compared with the reference path, and the time-varying consistency response is calculated. Amplitude compensation and phase compensation are performed on all paths to be calibrated in the FPGA.

[0062] In step S224, the FPGA calibration module calculates the time-varying consistency response, which may include: Reference route and all paths to be calibrated Perform synchronous independent sampling. Each sampling length is [length missing]. Points, obtain Road time-domain sequence.

[0063] in, The time-domain sequence of the path is expressed as follows: Suggested route: .

[0064] Path to be calibrated: .

[0065] right Execution of time-domain sequences Point Fast Fourier Transform, generating Road frequency domain complex sequence.

[0066] in, The complex sequence of the frequency domain is expressed as follows: Suggested route: .

[0067] Path to be calibrated: .

[0068] In the frequency domain complex sequence corresponding to the reference path, the frequency point with the largest positioning amplitude is the target frequency point. The reference path and all paths to be calibrated extract the complex number of the target frequency point from their respective frequency domain complex sequences.

[0069] Among them, the extracted target frequency points The complex form of is , Suggested route: .

[0070] Path to be calibrated: .

[0071] Calculate the frequency domain ratio (i.e., compensation coefficient) between each path to be calibrated and the reference path at the target frequency, and determine the amplitude deviation and phase deviation of each path to be calibrated relative to the reference path.

[0072] Specifically, calculate the frequency domain ratio. This frequency domain ratio includes the amplitude compensation factor. and phase compensation factor It directly reflects the amplitude / phase deviation of the path to be calibrated relative to the reference path.

[0073] The FPGA chip calibration module performs time-domain data calibration on each channel to be calibrated. Apply compensation coefficient Calibration complete: . For the calibrated data, compared with the reference path Maintain amplitude and phase consistency.

[0074] The calibration method in this application embodiment utilizes the gain / phase configurable characteristics and digitally controlled attenuator of the CA-RF1947 RF chip for hardware calibration, and is implemented based on the existing ADC-FPGA-DAC architecture for software calibration. This eliminates the need for additional dedicated calibration chips, extra sensors, and other hardware resources, reducing system design and manufacturing costs. It offers the following advantages: The calibration process is highly automated: hardware calibration is automatically triggered upon power-up, and software calibration runs in the background in real time without manual intervention; the FPGA chip integrates calibration algorithms, and the calculation latency is controlled at the millisecond level, which does not affect the real-time processing efficiency of navigation signals.

[0075] Hardware calibration addresses "static errors" such as manufacturing tolerances and inherent device defects, while software calibration addresses "dynamic errors" such as nonlinear distortion and environmental fluctuations. The two complement each other, covering all types of channel mismatch scenarios. This solves the technical problems of limited adjustability in pure hardware calibration and the inability of pure software calibration to correct physical defects. It features parallel channels, with hardware calibration supporting precise compensation for each channel and software calibration enabling parallel calibration of multiple channels. It is compatible with anti-interference antenna arrays with different numbers of channels.

[0076] Hardware calibration passed Second-rate The statistical average calculation error of point FFT eliminates single-sample noise interference. The software calibration is based on real-time signal dynamic tracking deviation. It addresses dynamic amplitude and phase shifts caused by environmental changes such as temperature drift and electromagnetic interference through FPGA chip digital domain compensation, making the overall channel consistency better than pure software calibration or pure hardware calibration schemes.

[0077] After hardware and software co-calibration, the system zero-depression depth can be stably maintained above 30dB, effectively avoiding zero-depression offset. The anti-interference capability can be improved by more than 20% compared with traditional methods, ensuring the positioning accuracy (meter level) and locking stability of the navigation receiver in complex electromagnetic environments.

[0078] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0079] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0080] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0081] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0082] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0083] The above description is merely a specific embodiment or illustration of the embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.

Claims

1. A hardware and software hybrid calibration system for a navigation anti-interference system, characterized in that, The calibration system includes: An antenna array composed of 100 oscillators is used to receive navigation signals; Each RF switch has a common terminal, a control terminal, a first switching terminal, and a second switching terminal. The first switching terminal signal of each RF switch is connected to the corresponding element of the antenna array. Each RF unit includes a low-noise amplifier, a digitally controlled attenuator, a shared RF chip, an intermediate frequency filter, and a shared up-converter connected in sequence. The input signal of the low-noise amplifier of each RF unit is connected to the common terminal of the RF switch of the corresponding channel. Intermediate frequency (IF) unit, wherein the input terminal of the IF unit is connected to the IF filter of each radio frequency (RF) unit, and the output terminal is connected to... The upconverter shared by the radio frequency units is used for analog-to-digital / digital-to-analog conversion, calibration signal generation, anti-interference beamforming, protocol conversion, hardware calibration control, and software calibration processing. A power divider is used to generate one channel of radio frequency signal. The power divider's calibration signal. Each output terminal is connected to the second switching terminal of the corresponding RF switch, and the input terminal is connected to the upconverter; The intermediate frequency unit is also connected to the radio frequency chip, the control terminal of each radio frequency switch, and each digitally controlled attenuator.

2. The calibration system according to claim 1, characterized in that, The intermediate frequency unit includes an FPGA chip and components respectively connected to the input terminals of the FPGA chip. The FPGA chip includes a digital-to-analog converter (DAC) and a digital-to-analog converter (DAC), with the input of each DAC connected to the intermediate frequency (IF) filter of the corresponding RF unit. The upconverter shared by the radio frequency units; The output of the FPGA chip is also connected to the radio frequency chip, the control terminal of each radio frequency switch, and each digitally controlled attenuator.

3. The calibration system according to claim 1, characterized in that, The oscillators form a uniform square or circular array, with a spacing between the oscillators of _____. , The orientation of each oscillator is consistent with the direction of the incoming navigation signal wave. The wavelength is the navigation signal wavelength.

4. The calibration system according to claim 1, characterized in that, The radio frequency chip is a CA-RF1947 chip.

5. The calibration system according to claim 1, characterized in that, The radio frequency switch is a single-pole double-throw radio frequency switch.

6. A calibration method based on the calibration system as described in any one of claims 1 to 5, characterized in that, The calibration method includes hardware calibration and software calibration. Hardware calibration is a one-time calibration upon power-on, while software calibration is dynamically adjusted according to the real-time status of the navigation signal during the operation of the navigation anti-interference system. Hardware calibration includes the following steps: The FPGA sends a high-level control signal to the RF switch via a general-purpose input / output port, causing the RF switch to switch to the second switching terminal and enter the calibration mode. The FPGA generates an intermediate frequency (IF) single-carrier signal, which is then converted into an analog signal by a digital-to-analog converter (DAC) and fed into an upconverter to convert the IF signal to radio frequency (RF). The output signal of the upconverter is then divided by a power divider. The calibration signals are respectively connected to the path calibration signal. The second switching terminal of the RF switch; The path calibration signals are respectively connected to After the RF unit, the signal is sent to the FPGA chip calibration module via the corresponding analog-to-digital converter. Designate the first path as the reference path, and the remaining paths as paths to be calibrated; Choose any path to be calibrated and compare it with the reference path, calculate the time-varying consistency response, and adjust the gain of the RF chip and digitally controlled attenuator and the phase of the RF chip of the path to be calibrated by configuring the register. Then repeat the process for the remaining paths to be calibrated. Software calibration includes the following steps: The FPGA sends a low-level control signal to the RF switch via a general purpose input / output port, causing the RF switch to switch to the first switching terminal and enter normal operation mode; Antenna array Each oscillator receives a normal signal and sends it to... RF unit, The normal signal is sent to the FPGA chip calibration module via an analog-to-digital converter; Designate the first path as the reference path, and the remaining paths as paths to be calibrated; The reference path and all paths to be calibrated are simultaneously subjected to consistency calibration. All paths to be calibrated are compared with the reference path, and the time-varying consistency response is calculated. Amplitude compensation and phase compensation are performed on all paths to be calibrated in the FPGA.

7. The calibration method according to claim 6, characterized in that, In hardware calibration, the FPGA calibration module calculates the time-varying consistency response, specifically including: Perform calibration on the reference path and the path to be calibrated separately. Each independent sample is [number] times, with a sample length of [length]. Points were obtained to acquire two time-domain sequences; Perform on each time-domain sequence Point Fast Fourier Transform generates two paths Group of complex sequences in the frequency domain; The target frequency point corresponding to the carrier frequency of the positioning calibration signal is located from... Extracting the complex number of the target frequency point from a group of complex number sequences in the frequency domain; Amplitude and phase errors are calculated based on frequency domain ratios.

8. The calibration method according to claim 7, characterized in that, The two time-domain sequences are expressed as follows: Suggested route: ; Path to be calibrated: ; in, ; ; Two routes The group of complex sequences in the frequency domain is expressed as follows: Suggested route: ; Path to be calibrated: ; in, ; Corresponding frequency point; Extracted target frequency points The complex form of is , Suggested route: ; Path to be calibrated: ; Calculate the frequency domain ratio ; in ; Calculate amplitude error After converting to dB value, take Group average; Calculate phase error ,Pick Group average.

9. The calibration method according to claim 6, characterized in that, In software calibration, the FPGA calibration module calculates the time-varying consistency response, specifically including: The reference path and all paths to be calibrated are sampled synchronously and independently, with each sample length being [length missing]. Points, obtain Path time-domain sequence; right Execution of time-domain sequences Point Fast Fourier Transform, generating Path frequency domain complex sequence; In the frequency domain complex sequence of the corresponding reference path, the frequency point with the largest positioning amplitude is the target frequency point. The reference path and all paths to be calibrated extract the complex number of the target frequency point from their respective frequency domain complex sequences. Calculate the frequency domain ratio of each path to be calibrated to the reference path at the target frequency, and determine the amplitude deviation and phase deviation of each path to be calibrated relative to the reference path.

10. The calibration method according to claim 9, characterized in that, The time-domain sequence of the path is expressed as follows: Suggested route: ; Path to be calibrated: ; The complex sequence of the frequency domain is expressed as follows: Suggested route: ; Path to be calibrated: ; Extracted target frequency points The complex form of is , Suggested route: ; Path to be calibrated: ; Calculate the frequency domain ratio Determine the amplitude compensation factor and phase compensation factor ; The FPGA chip calibration module performs time-domain data calibration on each channel to be calibrated. Apply compensation coefficient Calibration complete: , This is the calibrated data.

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