Avionics system software simulation and bus excitation simulation method

Abstract

The invention discloses an avionics system software simulation and bus excitation simulation method, and the method comprises the steps: employing a unified integrated development environment based on an Eclipse framework, and achieving the development, integration and deployment of multi-product software; the method comprises the following steps of: simulating original embedded target files of two heterogeneous platforms, namely a PowerPC architecture and an ARMv8-A architecture, by adopting a dynamic binary translation technology; a GPU para-virtualization and remote rendering method is adopted; driving-stage bus behavior simulation and single-port data excitation are carried out; and remote deployment, cloud management and continuous integration collaboration mechanism. The development efficiency is improved, a unified integration development environment and a simulation operation environment without hardware dependence are combined, the problems of hardware dependence and environment building repeatability are solved, rapid prototype design and one-key deployment are supported, and the development efficiency of display software is improved.

Description

Technical Field

[0001] This invention relates to the fields of avionics systems, integration and testing, and in particular to a method for software simulation and bus excitation simulation of avionics systems. Background Technology

[0002] With the increasing complexity of modern avionics display terminals, display system software faces severe challenges in terms of real-time performance, high reliability, and high efficiency during the design and verification process.

[0003] Existing technologies and existing problems High dependence on physical hardware: Traditional display system software development and testing heavily rely on scarce and expensive physical avionics display terminal hardware. This results in development progress being limited by hardware, making it difficult to debug and access the system at any time.

[0004] Inefficient integration and debugging of heterogeneous multi-core systems: Modern avionics systems typically employ complex heterogeneous multi-core architectures. The two configurations involved in this solution are based on PowerPC and ARMv8-A architecture processors, respectively, running different real-time operating systems. Repeatedly building development environments for different heterogeneous platforms is time-consuming and labor-intensive, and inefficient during system integration and code debugging.

[0005] Lack of high-performance, high-fidelity real-time simulation capabilities: Existing general-purpose simulation tools struggle to accurately simulate the timing of real-time embedded systems at the instruction level. It is difficult to achieve simulations that strictly match the actual hardware runtime cycle (technically requiring an error within 0.1ms), and the traditional interpreted execution mode suffers from severe performance bottlenecks.

[0006] Integration and verification challenges of complex avionics buses: avionics bus protocols have complex low-level driver and register interaction logic. Traditional network simulations often only focus on application-layer data transmission, making it difficult to achieve equivalent, high-fidelity simulation of low-level driver behavior and register operations. Summary of the Invention

[0007] In view of the above problems, the present invention is proposed to provide a method for software simulation and bus excitation simulation of avionics systems that overcomes or at least partially solves the above problems.

[0008] According to one aspect of the present invention, a method for software simulation and bus excitation simulation of an avionics system is provided, the simulation method comprising: A unified integrated development environment based on the Eclipse framework is used to realize the development, integration, and deployment of multi-product software; Dynamic binary translation technology is used to simulate native embedded target files for two heterogeneous platforms, PowerPC architecture and ARMv8-A architecture; Utilize GPU semi-virtualization and remote rendering methods; Driver-level bus behavior simulation and single-port data stimulation; Remote deployment, cloud management, and continuous integration collaboration mechanism.

[0009] Optionally, the adoption of a unified integrated development environment based on the Eclipse framework to realize the development, integration, and deployment of multi-product software specifically includes: Front-end interaction and development: Provides a unified front-end interface, supports the writing of multi-product software code, syntax highlighting, and basic debugging functions; Automated compilation and dependency management: Supports configuration of external compilation toolchains, which can automatically select functional components, generate compilation dependencies, and perform automated compilation to generate embedded target binary files based on device configuration, requirements, and dependencies; Graphical Modeling and Deployment: Provides drag-and-drop graphical modeling tools for quickly building virtual hardware simulation systems for avionics display terminals; configures startup scripts to enable one-click deployment and execution of compiled binary files to the simulation environment; Remote collaboration and concurrent preview: The environment supports running multiple simulation instances concurrently and provides a unified preview interface, making it convenient for developers to quickly preview various product screens and perform differentiated development.

[0010] Optionally, the various products specifically include: avionics display terminals and avionics system supporting software.

[0011] Optionally, the simulation of native embedded target files for two heterogeneous platforms, PowerPC architecture and ARMv8-A architecture, using dynamic binary translation technology specifically includes: The simulation process and architecture include: Processor Modeling and Loading: Implement high-precision behavioral-level modeling of registers, instruction sets, interrupt handling logic, and memory management units for PowerPC and ARMv8-A architecture processors; load native binary programs compiled for the target platform into the simulation memory; Dynamic binary translation: During program execution, the dynamic binary translation module converts the source machine instructions into an intermediate representation of the compiler optimization framework in real time; Optimization and Execution: The compilation optimization framework's compilation infrastructure optimizes the IR and generates efficient native machine code for the host machine for execution; Accuracy assurance: Through the above-mentioned instruction-level translation and optimization, the simulation application's operating cycle is ensured to be consistent with that of the actual avionics display terminal, with an error within 0.1ms; Key performance optimizations were implemented during the dynamic binary translation process.

[0012] Optionally, the key performance optimizations implemented during the dynamic binary translation process specifically include: Dynamic memory access optimization: For processors with MMU, TLB simulation and memory access type classification mechanism are used; Endianness optimization: To address the conflict between the target processor and the host machine, the data segments are pre-converted between endianness when loading the application image; this makes the simulated memory logically equivalent to little-endian mode, and the operation is performed directly on the little-endian host machine at runtime; Register mapping optimization: To address the issue that the number of general-purpose registers on the host machine is less than that of the embedded processor, a local variable mapping strategy is adopted: when entering the JITFunction, all target register values ​​are loaded into the local variables of the host function for operation; upon exiting, the modified values ​​are stored back to the memory simulation area in batches; batch memory operations replace the time-consuming load / store operations required for each register operation.

[0013] Optionally, the method of employing GPU semi-virtualization and remote rendering specifically includes: API interception: When a target application calls the OpenGL API and its parameters, the GPU paravirtualization module intercepts and encodes them into network packets; Remote transmission: The encoded data packets are transmitted to the local PC in real time over the network; Local rendering: The local PC runs a local graphics decoding and rendering program. After the decoder receives the data packet, it parses and calls the OpenGL interface of the local PC to render and display the image using local GPU resources. Performance assurance: Through optimizations such as data compression, transmitting only changed data, asynchronous rendering, and multi-threaded processing, the display frame rate of the avionics display terminal is ensured to be greater than or equal to 30fps, and the display latency is less than or equal to 0.5s.

[0014] Optionally, the driver-level bus behavior simulation and single-port data stimulus specifically include: Driver-level behavior simulation: Accurate simulation of the underlying registers and driver logic of the ARINC664 / 825 / 429 bus; A664: Simulates the read / write logic of registers such as RECBUFFERFLAGADDR and RECLOCKADDR to implement port caching and message processing; A825: Simulates the combined behavior of an FPGA and a CAN controller chip, realizing the process of retrieving data from a FIFO and writing it to an FPGA register by reading and writing the CAN controller register; A429: Simulates the status update of the RX_STATUS register and the writing of the RX_COMMAND register, and retrieves control data from the FIFO and writes it to the RXTX_DATA_BASE register for the driver to read; Single-port message forwarding mechanism.

[0015] Optionally, the single-port message forwarding mechanism specifically includes: Step a: The external excitation source host computer sends UDP data packets to a single fixed external network port that the forwarding module is listening on; Step b: A 16-byte custom header is added before the packet payload, which contains the original message type, destination IP, and destination port number; Step c: After receiving the data packet, the forwarding module parses the custom message header and then forwards the payload data to the corresponding driver-level bus simulation module in the simulation environment; the mechanism enables multiple bus protocols to share a single external network port.

[0016] Optionally, the remote deployment, cloud management, and continuous integration collaboration mechanism specifically includes: Containerized deployment and resource isolation: The software prototype runtime environment supports Docker containerized deployment on remote high-performance workstations; Cloud management system and concurrency support: The platform provides a unified cloud management system, developed based on container orchestration frameworks such as Kubernetes; Remote control and access control: The cloud management system provides a remote control and monitoring interface, supporting users to remotely control the simulation instances by starting, stopping, pausing, and restarting them; Continuous Integration Interface: The platform provides a standardized interface for external continuous integration environments, supporting remote access via SSH to execute automatic integration, deployment, and startup scripts, enabling automated deployment, operation, debugging, and testing of display application software.

[0017] This invention provides a method for avionics system software simulation and bus excitation simulation. The simulation method includes: employing a unified integrated development environment (IDE) based on the Eclipse framework to achieve the development, integration, and deployment of multi-product software; using dynamic binary translation technology to simulate native embedded target files for two heterogeneous platforms, PowerPC and ARMv8-A architectures; employing GPU semi-virtualization and remote rendering methods; driver-level bus behavior simulation and single-port data excitation; and a collaborative mechanism for remote deployment, cloud management, and continuous integration. This improves development efficiency: the combination of the unified IDE and the hardware-independent simulation runtime environment solves the problems of hardware dependence and repetitive environment setup, supports rapid prototyping and one-click deployment, and improves the development efficiency of display software.

[0018] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating a software simulation and bus excitation simulation method for an avionics system provided in this embodiment of the invention; Figure 2 A block diagram of the overall architecture of the avionics system software system provided in the embodiments of the present invention; Figure 3 The overall operation flowchart provided for embodiments of the present invention. Detailed Implementation

[0021] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0022] The terms "comprising" and "having," and any variations thereof, in the specification, embodiments, claims, and drawings of this invention are intended to cover non-exclusive inclusion, such as including a series of steps or units.

[0023] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0024] like Figure 1 As shown, an avionics system software simulation and bus excitation simulation method is described, the simulation method comprising: A unified integrated development environment based on the Eclipse framework is used to realize the development, integration, and deployment of multi-product software; Dynamic binary translation technology is used to simulate native embedded target files for two heterogeneous platforms, PowerPC architecture and ARMv8-A architecture; Utilize GPU semi-virtualization and remote rendering methods; Driver-level bus behavior simulation and single-port data stimulation; Remote deployment, cloud management, and continuous integration collaboration mechanism.

[0025] This invention provides a high-performance instruction-level simulation and bus excitation method for heterogeneous multi-core software in avionics systems, which mainly includes: providing a unified integrated development environment and a high-performance, high-fidelity software prototype runtime environment.

[0026] The core innovations are: high-performance heterogeneous instruction-level simulation (based on dynamic binary translation), GPU semi-virtualization remote rendering, and driver-level bus behavior simulation and single-port message forwarding mechanism.

[0027] The overall architecture of the present invention is shown in the attached figures. Figure 2 As shown.

[0028] Figure 2 The simulation is divided into two environments: a host environment (104) for running image display and upper computer data stimulus software, and a cloud platform environment (105). The cloud platform environment is mainly used to create Docker containers (106) and run simulation models (107). The simulation model is used to simulate the hardware environment of the heterogeneous multi-core software of the avionics system. The OpenGL-related data packets of the heterogeneous multi-core software of the avionics system are transmitted to the OpenGL image display unit on the host via the network. The image display unit then uses the GPU hardware resources on the host to draw the image. After the heterogeneous multi-core software of the avionics system is running, it can send A664 / A824 / A429 data stimulus through the upper computer software (103) on the host via the UDP protocol. After receiving the data stimulus, the simulation model processes the data to generate image response changes.

[0029] The overall operation process is as follows: Figure 3 As shown. First, the binary file needs to be compiled and uploaded to the cloud platform environment (step 201); second, a container needs to be created (step 202), and the OpenGL graphics display unit and simulation model need to be run (step 203) and (step 204). Under normal circumstances, the simulation model can run normally and the OpenGL graphics display unit on the host side can display the correct image. If it cannot run correctly or the image is displayed abnormally, further investigation of code problems is required.

[0030] This invention involves five major modules: unified integrated development environment and rapid deployment, high-performance heterogeneous instruction-level simulation implementation, GPU semi-virtualization and remote rendering methods, driver-level bus behavior simulation and single-port data stimulation and remote deployment, and cloud management and continuous integration collaboration mechanism. The detailed descriptions of each module are as follows.

[0031] 1. Unified integrated development environment and rapid deployment This invention employs a unified integrated development environment based on the Eclipse framework to realize the development, integration, and deployment of software for multiple products (avionics display terminals and supporting software for avionics systems). Front-end interaction and development: Provides a unified front-end interface, supports the writing of multi-product software code, syntax highlighting, and basic debugging functions.

[0032] Automated compilation and dependency management: Supports configuration of external compilation toolchains, which can automatically select functional components, generate compilation dependencies, and perform automated compilation to generate embedded target binary files based on device configuration, requirements, and dependencies.

[0033] Graphical Modeling and Deployment: Provides drag-and-drop graphical modeling tools for quickly building virtual hardware simulation systems such as avionics display terminals (IOM, GPM1, GPM2); configures startup scripts to achieve one-click deployment and operation of compiled binary files to the simulation environment.

[0034] Remote collaboration and concurrent preview: The environment supports the concurrent running of multiple simulation instances and provides a unified preview interface, which facilitates developers to quickly preview and differentiate different product screens (such as avionics display terminals and avionics system supporting software) to maximize code reuse.

[0035] High-performance heterogeneous instruction-level simulation implementation To address problems C and B, this invention employs Dynamic Binary Translation (DBT) technology to ensure high real-time performance and high precision simulation of native embedded target files for two heterogeneous platforms: PowerPC architecture and ARMv8-A architecture.

[0036] Simulation process and architecture Processor Modeling and Loading: This section describes high-precision behavioral modeling of the registers, instruction sets, interrupt handling logic, and memory management units (MMU / TLB) of PowerPC and ARMv8-A architecture processors. It also loads native binary programs compiled for the target platform into the simulation memory.

[0037] Dynamic Binary Translation (DBT): During program execution, the dynamic binary translation module converts source machine instructions (such as PowerPC or ARM instructions) into intermediate representations (IRs) of the compiler optimization framework in real time.

[0038] Optimization and Execution: The compilation infrastructure of the compilation optimization framework optimizes the IR and generates efficient native machine code (JITFunction) for the host machine (x86) and executes it.

[0039] Accuracy Guarantee: Through the above-mentioned instruction-level translation and optimization, the simulation application's operating cycle is ensured to be consistent with that of the actual avionics display terminal, with an error within 0.1ms.

[0040] Key performance optimization steps To achieve ultra-high real-time performance requirements, the following optimization measures were adopted during the dynamic binary translation process: Dynamic memory access optimization: For processors with MMU, mechanisms such as TLB emulation and memory access type classification are used to avoid each memory access instruction from being translated by a complex virtual MMU system, thereby accelerating memory access operations.

[0041] Endianness optimization: To address the conflict between the target processor (e.g., PowerPC, which is big-endian) and the host machine (x86, which is little-endian), data segments are pre-converted to 32-bit endianness when loading the application image. This makes the simulated memory logically equivalent to little-endian mode, allowing runtime operations to be performed directly on the little-endian host machine, avoiding the real-time conversion overhead of each memory access.

[0042] Register mapping optimization: To address the issue of the host machine having fewer general-purpose registers than the embedded processor, a local variable mapping strategy is adopted: upon entering the JITFunction, all target register values ​​are loaded into the local variables of the host function for operation; upon exiting, the modified values ​​are then stored back to the memory simulation area in batches. This replaces the time-consuming load / store operations required for each register operation with batch memory operations.

[0043] GPU semi-virtualization and remote rendering methods To address image display issues during remote deployment and debugging, this invention employs GPU semi-virtualization technology, supporting EGL 1.5 and OpenGL SC 1.1 / 2.0 standard interfaces.

[0044] API interception: When the target application (running in a remote Docker container) calls the OpenGL API and parameters, the GPU semi-virtualization module intercepts and encodes them into network packets.

[0045] Remote transmission: The encoded data packets are transmitted to the local PC in real time over the network.

[0046] Local rendering: The local PC runs a local graphics decoding and rendering program. After the decoder receives the data packet, it parses and calls the OpenGL interface of the local PC, and uses local GPU resources (such as NVDIARTX4080 and above) to render and display the screen.

[0047] Performance assurance: Through optimizations such as data compression, transmitting only changed data, asynchronous rendering, and multi-threaded processing, the display frame rate of the avionics display terminal is ensured to be greater than or equal to 30fps, and the display latency is less than or equal to 0.5s.

[0048] Driver-level bus behavior simulation and single-port data excitation To address problem D, this invention performs high-fidelity driver-level behavior simulation of the ARINC bus protocol and designs an innovative data incentive forwarding mechanism.

[0049] Driver-level behavior simulation: Accurate simulation of the underlying registers and driver logic of the ARINC664 / 825 / 429 bus.

[0050] A664: Simulates the read and write logic of registers such as RECBUFFERFLAGADDR and RECLOCKADDR to implement port caching and message processing (such as the logic of AFDX_SAMPLE_PORT caching only the latest message).

[0051] A825: Simulates the combined behavior of an FPGA and a CAN controller chip, implementing the process of retrieving data from a FIFO and writing it to an FPGA register by reading and writing the CAN controller register.

[0052] A429: Simulates the status update of the RX_STATUS register and the writing of the RX_COMMAND register, and retrieves control data from the FIFO and writes it to the RXTX_DATA_BASE register for the driver to read.

[0053] Single-port message forwarding mechanism (core innovation): To solve the problem of complex configuration of multi-bus protocol I / O and the need for custom port numbers, this invention designs a virtual message forwarding module.

[0054] Step a: The external excitation source host computer sends UDP data packets to a single fixed external network port that the forwarding module is listening on.

[0055] Step b: A 16-byte custom header is added before the payload of the data packet, which contains the original message type, the destination IP, and the destination port number.

[0056] Step c: After receiving the data packet, the forwarding module parses the custom message header and then forwards the load data to the corresponding driver-level bus simulation module (A664, A825, A429) in the simulation environment.

[0057] The mechanism enables multiple bus protocols to share a single external network port, simplifying network configuration complexity.

[0058] Remote deployment, cloud management and continuous integration collaboration mechanism To address issues A (hardware dependency) and B (inefficiency), this invention employs advanced cloud-native technologies to provide a high-concurrency, scalable, and remotely accessible integrated development and testing environment.

[0059] Containerized deployment and resource isolation: The software prototype runtime environment supports Docker containerized deployment on remote high-performance workstations (configured with at least 96 CPU cores and 512GB of memory). Each simulation instance runs in an independent Docker container, thus ensuring environment consistency, supporting remote independent use and debugging by multiple users, and allowing them to run independently without affecting each other.

[0060] Cloud Management System and Concurrency Support: The platform provides a unified cloud management system developed based on container orchestration frameworks such as Kubernetes. Kubernetes is responsible for container scheduling, load balancing, and status monitoring, and can schedule simulation instances to run on the most suitable resources based on the availability of physical machine resources. The workstation configuration can support at least 25 avionics display terminal simulation programs running normally simultaneously.

[0061] Remote Control and Access Management: The cloud management system provides a remote control and monitoring interface, supporting users to remotely start, stop, pause, and restart simulation instances. The system provides a user center with access authentication, role management (administrator / regular user), and access control functions to ensure that only authorized users can access resources.

[0062] Continuous Integration Interface: The platform provides standardized interfaces for external continuous integration environments (such as Jenkins and Bamboo), supporting remote access via SSH to execute automatic integration, deployment, and startup scripts, thereby enabling automated deployment, operation, debugging, and testing of application software.

[0063] Beneficial effects: This invention provides an "avionics system software verification platform" that, through technological innovation, provides developers with a unified, efficient, and high-fidelity virtualized environment, enabling rapid prototype development and verification of two key heterogeneous avionics display terminal platforms, thereby significantly improving the development efficiency of display software.

[0064] Extremely high timing fidelity: The error between the running cycle of the display application software and the actual avionics display terminal is less than 0.1ms, which meets the stringent requirements of avionics systems for precise real-time performance.

[0065] Significantly improves development efficiency: The combination of a unified integrated development environment and a hardware-independent simulation runtime environment solves the problems of hardware dependence and repetitive environment setup, supports rapid prototyping and one-click deployment, thereby significantly improving the development efficiency of display software.

[0066] Powerful concurrent testing capabilities: Through containerization technology and high-performance host hardware, the platform can support at least 25 simulation instances running normally at the same time, meeting the needs of large-scale parallel development and integration testing.

[0067] Enhanced verification comprehensiveness: Bus driver-level simulation and single-port stimulus mechanism enable complete and flexible verification of the underlying driver interaction and data stimulus logic of complex protocols such as A664, A825, and A429, improving the coverage and depth of system verification.

[0068] Optimizing user experience and collaboration: Remote rendering technology ensures that the simulated avionics display terminal displays a frame rate of ≥30fps and an average response time of ≤0.5s. The remote cloud management system supports multi-user remote independent use and online debugging, facilitating remote collaborative development.

[0069] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for software simulation and bus excitation simulation of avionics systems, characterized in that, The simulation method includes: A unified integrated development environment based on the Eclipse framework is used to realize the development, integration, and deployment of multi-product software; Dynamic binary translation technology is used to simulate native embedded target files for two heterogeneous platforms, PowerPC architecture and ARMv8-A architecture; Utilize GPU semi-virtualization and remote rendering methods; Driver-level bus behavior simulation and single-port data stimulation; Remote deployment, cloud management, and continuous integration collaboration mechanism.

2. The method for software simulation and bus excitation simulation of an avionics system according to claim 1, characterized in that, The adoption of a unified integrated development environment based on the Eclipse framework to achieve the development, integration, and deployment of multi-product software specifically includes: Front-end interaction and development: Provides a unified front-end interface, supports the writing of multi-product software code, syntax highlighting, and basic debugging functions; Automated compilation and dependency management: Supports configuration of external compilation toolchains, which can automatically select functional components, generate compilation dependencies, and perform automated compilation to generate embedded target binary files based on device configuration, requirements, and dependencies; Graphical Modeling and Deployment: Provides drag-and-drop graphical modeling tools for quickly building virtual hardware simulation systems for avionics display terminals; configures startup scripts to enable one-click deployment and execution of compiled binary files to the simulation environment; Remote collaboration and concurrent preview: The environment supports running multiple simulation instances concurrently and provides a unified preview interface, making it convenient for developers to quickly preview various product screens and perform differentiated development.

3. The method for software simulation and bus excitation simulation of an avionics system according to claim 2, characterized in that, The various products specifically include: avionics display terminals and avionics system supporting software.

4. The method for software simulation and bus excitation simulation of an avionics system according to claim 1, characterized in that, The simulation of native embedded target files for two heterogeneous platforms, PowerPC architecture and ARMv8-A architecture, using dynamic binary translation technology specifically includes: The simulation process and architecture include: Processor Modeling and Loading: Implement high-precision behavioral-level modeling of registers, instruction sets, interrupt handling logic, and memory management units for PowerPC and ARMv8-A architecture processors; load native binary programs compiled for the target platform into the simulation memory; Dynamic binary translation: During program execution, the dynamic binary translation module converts the source machine instructions into an intermediate representation of the compiler optimization framework in real time; Optimization and Execution: The compilation optimization framework's compilation infrastructure optimizes the IR and generates efficient native machine code for the host machine for execution; Accuracy assurance: Through the above-mentioned instruction-level translation and optimization, the simulation application's operating cycle is ensured to be consistent with that of the actual avionics display terminal, with an error within 0.1ms; Key performance optimizations were implemented during the dynamic binary translation process.

5. The avionics system software simulation and bus excitation simulation method according to claim 4, characterized in that, The key performance optimizations adopted in the dynamic binary translation process specifically include: Dynamic memory access optimization: For processors with MMU, TLB simulation and memory access type classification mechanism are used; Endianness optimization: To address the conflict between the target processor and the host machine, the data segments are pre-converted between endianness when loading the application image; this makes the simulated memory logically equivalent to little-endian mode, and the operation is performed directly on the little-endian host machine at runtime; Register mapping optimization: To address the issue that the number of general-purpose registers on the host machine is less than that of the embedded processor, a local variable mapping strategy is adopted: when entering the JITFunction, all target register values ​​are loaded into the local variables of the host function for operation; upon exiting, the modified values ​​are stored back to the memory simulation area in batches; batch memory operations replace the time-consuming load / store operations required for each register operation.

6. The method for software simulation and bus excitation simulation of an avionics system according to claim 1, characterized in that, The specific methods employed, including GPU semi-virtualization and remote rendering, include: API interception: When a target application calls the OpenGL API and its parameters, the GPU paravirtualization module intercepts and encodes them into network packets; Remote transmission: The encoded data packets are transmitted to the local PC in real time over the network; Local rendering: The local PC runs a local graphics decoding and rendering program. After the decoder receives the data packet, it parses and calls the OpenGL interface of the local PC to render and display the image using local GPU resources. Performance assurance: Through optimizations such as data compression, transmitting only changed data, asynchronous rendering, and multi-threaded processing, the display frame rate of the avionics display terminal is ensured to be greater than or equal to 30fps, and the display latency is less than or equal to 0.5s.

7. The method for software simulation and bus excitation simulation of an avionics system according to claim 1, characterized in that, The driver-level bus behavior simulation and single-port data stimulus specifically include: Driver-level behavior simulation: Accurate simulation of the underlying registers and driver logic of the ARINC664 / 825 / 429 bus; A664: Simulates the read / write logic of registers such as RECBUFFERFLAGADDR and RECLOCKADDR to implement port caching and message processing; A825: Simulates the combined behavior of an FPGA and a CAN controller chip, realizing the process of retrieving data from a FIFO and writing it to an FPGA register by reading and writing the CAN controller register; A429: Simulates the status update of the RX_STATUS register and the writing of the RX_COMMAND register, and retrieves control data from the FIFO and writes it to the RXTX_DATA_BASE register for the driver to read; Single-port message forwarding mechanism.

8. The method for software simulation and bus excitation simulation of an avionics system according to claim 7, characterized in that, The single-port message forwarding mechanism specifically includes: Step a: The external excitation source host computer sends UDP data packets to a single fixed external network port that the forwarding module is listening on; Step b: A 16-byte custom header is added before the packet payload, which contains the original message type, destination IP, and destination port number; Step c: After receiving the data packet, the forwarding module parses the custom message header and then forwards the payload data to the corresponding driver-level bus simulation module in the simulation environment; the mechanism enables multiple bus protocols to share a single external network port.

9. The method for software simulation and bus excitation simulation of an avionics system according to claim 1, characterized in that, The aforementioned remote deployment, cloud management, and continuous integration collaboration mechanism specifically includes: Containerized deployment and resource isolation: The software prototype runtime environment supports Docker containerized deployment on remote high-performance workstations; Cloud management system and concurrency support: The platform provides a unified cloud management system, developed based on container orchestration frameworks such as Kubernetes; Remote control and access control: The cloud management system provides a remote control and monitoring interface, supporting users to remotely control the simulation instances by starting, stopping, pausing, and restarting them; Continuous Integration Interface: The platform provides a standardized interface for external continuous integration environments, supporting remote access via SSH to execute automatic integration, deployment, and startup scripts, enabling automated deployment, operation, debugging, and testing of display application software.

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