Decoding control method, memory storage device and memory control circuit unit

Abstract

The invention provides a decoding control method, a memory storage device and a memory control circuit unit. The decoding control method comprises the following steps: reading a first code word from a rewritable nonvolatile memory module; reading a first decoding parameter corresponding to the target parity check matrix; performing a first decoding operation on the first codeword using the first decoding parameter; in response to a failure of the first decoding operation, a parameter operation is performed on the target parity check matrix to obtain a second decoding parameter, and a second decoding operation is performed on the first codeword using the second decoding parameter.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory management technique, and more particularly, to a decoding control method, a memory storage device and a memory control circuit unit. BACKGROUND

[0002] The growth of portable electronic devices such as mobile phones and notebook computers has been very rapid in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memories) are very suitable for being built into the above-mentioned portable electronic devices because of their data non-volatility, power saving, small size, and lack of mechanical structure.

[0003] Data in a rewritable non-volatile memory module is decoded according to a parity check matrix when being read. In each decoding process, the parity check matrix is initialized to obtain information about each column of the parity check matrix and to obtain decoding parameters, and the decoded data is then decoded using the decoding parameters. However, the initialization operation consumes a large amount of time, resulting in a reduction in decoding speed. SUMMARY

[0004] The present application provides a decoding control method, a memory storage device and a memory control circuit unit, which can improve decoding speed.

[0005] According to an embodiment of the present application, an example embodiment of the present application provides a decoding control method for a rewritable non-volatile memory module, and the decoding control method comprises: reading a first codeword from the rewritable non-volatile memory module; reading a first decoding parameter corresponding to a target parity check matrix; performing a first decoding operation on the first codeword using the first decoding parameter; and in response to a failure of the first decoding operation, performing a parameter operation on the target parity check matrix to obtain a second decoding parameter, and performing a second decoding operation on the first codeword using the second decoding parameter.

[0006] In an example embodiment of the present application, the first decoding parameter comprises a first index value of a first minimum value of each column of the target parity check matrix.

[0007] In an example embodiment of the present application, the first index value is used to indicate a position of a non-zero bit corresponding to the first minimum value.

[0008] In an example embodiment of the present application, the first minimum value is a minimum value of absolute values of a plurality of log-likelihood ratios corresponding to a plurality of non-zero bits in each column of the target parity check matrix.

[0009] In an example embodiment of the present invention, the first decoding parameters further comprise the first minimum values in response to the first minimum values of each column of the target parity check matrix being not all identical.

[0010] In an example embodiment of the present invention, the first minimum value is zero and the first index value is used to indicate the position of the puncturing bit in response to the target parity check matrix having a puncturing bit.

[0011] In an example embodiment of the present invention, the first decoding parameters further comprise a first second minimum value and a second index value of the first second minimum value in response to the first minimum value of each column of the target parity check matrix being different from the first second minimum value, wherein the second index value is used to indicate the position of the non-zero bit corresponding to the first second minimum value, and the first second minimum value is a second smallest value among absolute values of a plurality of log-likelihood ratio values corresponding to a plurality of non-zero bits in each column of the target parity check matrix.

[0012] In an example embodiment of the present invention, the second decoding parameters comprise a second minimum value of each column of the target parity check matrix and a third index value of the second minimum value.

[0013] In an example embodiment of the present invention, the step of performing a parameter operation on the target parity check matrix to obtain the second decoding parameters comprises: taking a minimum value of a plurality of absolute values of a plurality of log-likelihood ratio values corresponding to a plurality of non-zero bits in each column of the target parity check matrix as the second minimum value; and taking an index value of the position of the non-zero bit corresponding to the second minimum value as the third index value.

[0014] In an example embodiment of the present invention, the first decoding operation is a hard bit decoding operation.

[0015] An example embodiment of the present invention further provides a memory storage device, which comprises a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to read a first codeword from the rewritable non-volatile memory module. The memory control circuit unit is further used to read first decoding parameters corresponding to a target parity check matrix. The memory control circuit unit is further used to perform a first decoding operation on the first codeword using the first decoding parameters. In response to the first decoding operation failing, the memory control circuit unit is further used to perform a parameter operation on the target parity check matrix to obtain second decoding parameters, and perform a second decoding operation on the first codeword using the second decoding parameters.

[0016] In an example embodiment of the present application, the memory control circuit unit is further configured to obtain a minimum value of absolute values of a plurality of log-likelihood ratio values corresponding to a plurality of non-zero bits in each column of the target parity check matrix. The memory control circuit unit is further configured to obtain an index value of a position of the non-zero bit corresponding to the minimum value as a third index value.

[0017] An example embodiment of the present application further provides a memory control circuit unit configured to control a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is connected to the connection interface unit. The memory interface is connected to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to read a first codeword from the rewritable non-volatile memory module. The memory management circuit is further configured to read a first decoding parameter corresponding to a target parity check matrix. The memory management circuit is further configured to perform a first decoding operation on the first codeword using the first decoding parameter. In response to a failure of the first decoding operation, the memory management circuit is further configured to perform a parameter operation on the target parity check matrix to obtain a second decoding parameter, and perform a second decoding operation on the first codeword using the second decoding parameter.

[0018] In an example embodiment of the present application, the memory management circuit is further configured to obtain a minimum value of absolute values of a plurality of log-likelihood ratio values corresponding to a plurality of non-zero bits in each column of the target parity check matrix as a second minimum value of each column of the target parity check matrix. The memory management circuit is further configured to obtain an index value of a position of the non-zero bit corresponding to the second minimum value as a third index value.

[0019] Based on the above, the decoding control method, the memory storage device, and the memory control circuit unit of the present application perform a first decoding operation (i.e., a hard bit decoding operation) using a first decoding parameter stored in advance to improve decoding speed. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an example embodiment of the present application;

[0021] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an example embodiment of the present application;

[0022] Figure 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the present application;

[0023] Figure 4is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0024] Figure 5 is a schematic diagram of a memory control circuit unit shown in accordance with an example embodiment of the present invention;

[0025] Figure 6 is a schematic diagram of a management rewritable non-volatile memory module shown in accordance with an example embodiment of the present invention;

[0026] Figure 7 is a schematic diagram of a parity check matrix shown in accordance with an example embodiment of the present invention;

[0027] Figure 8 is a schematic diagram of a management decoding parameter shown in accordance with an example embodiment of the present invention;

[0028] Figure 9 is a schematic diagram of a partial parity check matrix shown in accordance with an example embodiment of the present invention;

[0029] Figure 10 is a flowchart of a decoding control method shown in accordance with an example embodiment of the present invention. DETAILED DESCRIPTION

[0030] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0031] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0032] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown in accordance with an example embodiment of the present invention.

[0033] Reference will now be made to Figure 1 and Figure 2The host system 11 can include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 can be connected to a system bus 110.

[0034] In an example embodiment, the host system 11 can be connected to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 can be connected to the I / O device 12 through the system bus 110. For example, the host system 11 can transmit an output signal to or receive an input signal from the I / O device 12 via the system bus 110.

[0035] In an example embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 can be disposed on a host board 20 of the host system 11. The number of the data transmission interface 114 can be one or more. Through the data transmission interface 114, the host board 20 can be connected to the memory storage device 10 via a wired or wireless manner.

[0036] In an example embodiment, the memory storage device 10 can be, for example, a USB 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the host board 20 can also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like, through the system bus 110. For example, in an example embodiment, the host board 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

[0037] In an example embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 can respectively comprise Figure 3 a memory storage device 30 and a host system 31 according to an example embodiment of the present application.

[0038] Figure 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the present application. Please refer to Figure 3 , the memory storage device 30 can be used with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a camcorder, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be a non-volatile memory storage device such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342, which is an embedded storage device that directly connects a memory module on a substrate of the host system.

[0039] Figure 4 is a schematic diagram of a memory storage device according to an example embodiment of the present application. Please refer to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0040] The connection interface unit 41 is configured to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an example embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an example embodiment, the connection interface unit 41 can also be compatible with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip that includes the memory control circuit unit 42.

[0041] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is configured to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to instructions from the host system 11.

[0042] The rewritable nonvolatile memory module 43 stores data written by the host system 11. The rewritable nonvolatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one bit can be stored in one memory cell), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which two bits can be stored in one memory cell), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which three bits can be stored in one memory cell), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which four bits can be stored in one memory cell), another flash memory module, or another memory module having the same characteristics.

[0043] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons of the charge trapping layer is changed, and thus the threshold voltage of the memory cell is changed. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage is changed, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, and thus it is possible to acquire one or more bits stored in the memory cell.

[0044] In an example embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute a plurality of physical program units, and the physical program units can constitute a plurality of physical erase units. Specifically, the memory cells on the same word line can form one or more physical program units. If each memory cell can store more than two bits, the physical program units on the same word line can be classified into at least lower physical program units and upper physical program units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical program unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical program unit. Generally, in an MLC NAND type flash memory, the write speed of a lower physical program unit is greater than that of an upper physical program unit, and / or the reliability of a lower physical program unit is higher than that of an upper physical program unit.

[0045] In an example embodiment, a physical program unit is the smallest unit of programming. That is, a physical program unit is the smallest unit of writing data. For example, a physical program unit can be a physical page or a physical sector. If a physical program unit is a physical page, the physical program units can include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is for storing system data (e.g., management data such as error correction codes). In an example embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit area can include 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector can be greater or smaller. On the other hand, a physical erase unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased together. For example, a physical erase unit is a physical block.

[0046] Figure 5 FIG. 1 is a schematic diagram of a memory control circuit unit according to an example embodiment of the present application. Referring to FIG. 1, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. Figure 5

[0047] ​The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and these control instructions are executed to perform data write, read and erase operations, etc. when the memory storage device 10 is in operation. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0048] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read and erase operations, etc.

[0049] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code form in a specific area (e.g., a system area in the memory module for storing system data) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform data write, read and erase operations, etc.

[0050] In an example embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct to perform corresponding operations.

[0051] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify the instructions and data of the host system 11. For example, the instructions and data of the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In the present example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present application is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0052] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written into the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 transmits corresponding instruction sequences. For example, the instruction sequences can include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and corresponding instruction sequences to indicate various memory operations (e.g., change the read voltage level or perform a garbage collection (GC) operation, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on a bus. These signals or data can include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, etc. is included.

[0053] In an example embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0054] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 obtains a write instruction from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for data corresponding to the write instruction, and the memory management circuit 51 writes the data corresponding to the write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Later, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the corresponding error correcting code and / or error detecting code corresponding to the data is also read, and the error checking and correction circuit 54 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0055] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

[0056] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0057] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 51 can logically group the physical cells 610(0)~610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0058] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may include one or more entity erase units.

[0059] The physical units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 may store valid and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0060] The memory management circuit 51 can configure the logical units 612(0)~612(C) to map the physical units 610(0)~610(A) in the storage area 601. In an example embodiment, each logical unit corresponds to a logical address. For example, a logical address can include one or more logical block addresses (LBAs) or other logical management units. In an example embodiment, a logical unit can also correspond to a logical program unit or be composed of multiple contiguous or non-contiguous logical addresses.

[0061] It should be noted that one logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit is invalid data.

[0062] The memory management circuit 51 can record management data (also referred to as logical-to-physical mapping information) describing the mapping relationship between the logical units and the physical units in at least one logical-to-physical mapping table. When the host system 11 desires to read data from or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0063] In an example embodiment, the error checking and correction circuit 54 can include an encoding circuit 541 and a decoding circuit 542. The encoding circuit 541 is used to encode data. The decoding circuit 542 is used to decode data. In an example embodiment, the encoding circuit 541 and the decoding circuit 542 can also be combined as a single encoding / decoding circuit.

[0064] In an example embodiment, before the memory management circuit 51 writes data to the rewritable non-volatile memory module 43, the data is first encoded to generate corresponding parity data, and the data and the parity data are then stored to the rewritable non-volatile memory module 43. The data that the memory management circuit 51 desires to write to the rewritable non-volatile memory module 43 (also referred to as write data) can be, for example, user data written by the host system 11 or management data of the memory management circuit 51. When the memory management circuit 51 desires to read a physical unit, the memory management circuit 51 can read the data in the physical unit and its corresponding parity data. The decoding circuit 542 in the error checking and correction circuit 54 can perform a decoding operation according to the parity data and the data read from the physical unit to detect and correct errors in the data.

[0065] In an example embodiment, the error checking and correction circuit 54 employs a low density parity check code for encoding and decoding. In a low density parity check code, a valid codeword is defined by a parity check matrix (also referred to as a parity check matrix). The parity check matrix is denoted by H and the codeword is denoted by CW. A codeword CW is valid if the parity check matrix H multiplied by the codeword CW is a zero vector, according to the following equation (1). The operator x denotes matrix multiplication modulo 2. In other words, the null space of the matrix H contains all valid codewords. However, the present application is not limited to the content of the codeword CW. For example, the codeword CW can also include an error correction code or an error checking code generated by any algorithm.

[0066] CW x H T = 0 (1)

[0067] In an example embodiment, the codeword CW can include information bits and parity bits, i.e., the codeword CW can be represented as [MP]. The vector M is composed of information bits. The vector P is composed of parity bits. The vector M is also referred to as write data (or data to be encoded). The vector P is also referred to as parity data. In a codeword, the parity bits (i.e., parity data) are used to protect the information bits (i.e., write data) and can be considered as an error correction code or an error checking code generated corresponding to the information bits. In addition, protecting the information bits means maintaining the correctness of the information bits. For example, when reading the information bits from the rewritable non-volatile memory module 43, the parity bits corresponding to the information bits can be used to correct errors that can exist in the information bits.

[0068] In an example embodiment, when decoding a codeword CW, a parity check operation is first performed on the codeword CW, such as multiplying the matrix H by the codeword CW to generate a vector (denoted by S, as shown in the following equation (2)). Each element in the vector S is also referred to as a syndrome. The vector S is also referred to as syndrome data. If the vector S is a zero vector (i.e., each element in the vector S is zero), the codeword CW can be directly output. If the vector S is not a zero vector (i.e., at least one element in the vector S is not zero), it means that there is at least one error in the codeword CW and the codeword CW is not a valid codeword. If the codeword CW is not a valid codeword, the error checking and correction circuit 54 can perform a decoding operation to attempt to correct the error in the codeword CW.

[0069] CW x H T = S (2)

[0070] In an example embodiment, the error checking and correction circuit 54 performs an iteration decoding operation. An iteration decoding operation is used to decode a piece of data from the re-writable non-volatile memory module 43. The decoding unit is, for example, a codeword. In an iteration operation, a parity check operation for checking the correctness of the data and a decoding operation for correcting errors in the data are repeatedly performed until the decoding is successful or the iteration number reaches a termination number. Specifically, if the iteration number reaches the termination number, the decoding fails and the error checking and correction circuit 54 stops the decoding. The value of the termination number can be designed according to actual requirements and the present application does not limit it. In addition, if it is determined through the parity check operation that there is no error in the piece of data, the error checking and correction circuit 54 outputs the piece of data.

[0071] In an example embodiment, the error checking and correction circuit 54 supporting the low-density parity check code can use the reliability information to perform the decoding operation. The reliability information can be, for example, a log likelihood ratio (LLR). Specifically, in the decoding operation, the error checking and correction circuit 54 (or the decoding circuit 542) can use the log likelihood ratio to decode the data read by the memory management circuit 51.

[0072] In an example embodiment, the greater the absolute value of the log likelihood ratio (which can be positive or negative) corresponding to a piece of data (or a bit value), the higher the reliability of the data, that is, the bit value of the data has a high probability of being correct. Conversely, the smaller the absolute value of the log likelihood ratio corresponding to the data, the lower the reliability of the data, that is, the bit value of the data has a high probability of being incorrect. For example, when the log likelihood ratio is zero, it means that the probability of the corresponding data (or bit value) being 0 is the same as that of being 1. For example, when the log likelihood ratio is positive and the value is greater, it means that the probability of the corresponding data (or bit value) being 1 is higher. For example, when the log likelihood ratio is negative and the value is smaller, it means that the probability of the corresponding data (or bit value) being 0 is higher. The representation range of the log likelihood ratio is determined by the bit width supported by the decoding circuit 542. Taking a bit width of 5 bits as an example, the representation range of the log likelihood ratio is -15 to +15.

[0073] Figure 7 is a schematic diagram of a parity check matrix according to an example embodiment of the present application. Please refer to Figure 7The parity check matrix 701 has a dimension of k by n, where k is 6 and n is 13. However, the present application is not limited to the values of the positive integers k and n. Each column of the parity check matrix 701 can represent a constraint. When decoding using the parity check matrix 701, only the non-zero bits in each column of the parity check matrix 701 need to be considered. For example, in the first column (i.e., c0) of the parity check matrix 701, the 1st, 4th, 6th-8th, and 13th bits are non-zero bits (i.e., bits having a value). If a code word is a valid code word, then the sum modulo 2 of the 1st, 4th, 6th-8th, and 13th bits of the code word will be "0". Those skilled in the art will understand how to encode and decode using the parity check matrix 701, and therefore the details will not be repeated here.

[0074] The error checking and correction circuit 54 stores a plurality of parity check matrices and can determine which parity check matrix to use for encoding or decoding based on the actual usage. The parity check matrix 701 is merely an example matrix and is not intended to limit the present application.

[0075] In an example embodiment, the decoding circuit 542 can support a plurality of decoding modes, and the plurality of decoding modes can have different error correction capabilities.

[0076] In an example embodiment, the memory management circuit 51 can send a read instruction sequence to the rewritable non-volatile memory module 43. The rewritable non-volatile memory module 43 can read data (also referred to as a first code word) from the physical cells according to the first read instruction sequence and return the read first code word to the memory management circuit 51.

[0077] Upon receiving the first code word returned by the rewritable non-volatile memory module 43, the decoding circuit 542 can perform a decoding operation (also referred to as a first decoding operation) on the first code word. For example, the decoding circuit 542 can perform the first decoding operation based on a decoding mode to attempt to correct errors in the first code word.

[0078] In an example embodiment, upon receiving the first code word returned by the rewritable non-volatile memory module 43, the memory management circuit 51 (decoding circuit 542) can read decoding parameters (also referred to as first decoding parameters) corresponding to a target parity check matrix (e.g., the parity check matrix 701). It should be noted that the first code word is a code word defined by the target parity check matrix 701, for example.

[0079] In one exemplary embodiment, the first decoding parameter includes the index value (also called the first index value) of the minimum value (also called the first minimum value) of each column of the target parity check matrix 701. The first minimum value is the minimum of the absolute values ​​of the log-probability ratios corresponding to the multiple non-zero bits in each column of the target parity check matrix 701. The first index value is used to indicate the position of the non-zero bit corresponding to the first minimum value. Since the first codeword has not yet been decoded, the log-probability ratios corresponding to the first codeword are all the same preset value. Therefore, the first minimum value is the absolute value of the log-probability ratio. Thus, the first index value (i.e., the first decoding parameter) can be recorded first for use in subsequent decoding of the first codeword, thereby improving the decoding speed. In another exemplary embodiment, the first minimum values ​​of each column of the target parity check matrix 701 are not completely the same. In addition to the first index value, the first minimum value also needs to be recorded first. That is, when the first minimum values ​​of each column of the target parity check matrix 701 are not completely the same, the first decoding parameter also includes the first minimum value of each column of the target parity check matrix 701. In another exemplary embodiment, in addition to the first index value, the first decoding parameter also includes the second smallest value (also referred to as the first smallest value) and its corresponding index value (also referred to as the second index value) of each column of the target parity check matrix 701. The first smallest value is the absolute value of a preset log-probability ratio (i.e., the preset value mentioned above). The second index value is used to indicate the position of the non-zero bit corresponding to the first smallest value. When the first minimum value of each column of the target parity check matrix 701 is different from the first smallest value, the first smallest value and the second index value also need to be recorded first.

[0080] Figure 8 This is a schematic diagram illustrating the management of decoding parameters according to an exemplary embodiment of the present invention. Please refer to... Figure 8 Taking the first column c0 of the target parity check matrix 701 as an example, the 1st, 4th, 6th to 8th, and 13th bits of the first column c0 are non-zero bits. That is to say, the bits located in the first row v0 of the first column c0, the bits located in the fourth row v3 of the first column c0, the bits located in the sixth row v5 of the first column c0, the bits located in the seventh row v6 of the first column c0, the bits located in the eighth row v7 of the first column c0, and the bits located in the thirteenth row v12 of the first column c0 are all non-zero bits.

[0081] Since the first codeword has not yet been decoded, the log-probability ratio corresponding to the non-zero bits of the target parity check matrix 701 is a preset value. For example... Figure 8As shown, the non-zero bits of the first column c0 correspond to log likelihood ratios of +8 or -8. In this case, the first column c0 does not have puncturing bits. Further, since the value of a puncturing bit is either 1 or 0 with equal probability, the log likelihood ratio corresponding to a puncturing bit is zero. Accordingly, the non-zero bits of the first column c0 correspond to non-zero log likelihood ratios, and the first column c0 does not have puncturing bits. In another example embodiment, the target parity check matrix 701 has puncturing bits. Since the size of a physical cell is fixed, in order to cope with the problem of insufficient current writable data size (i.e., insufficient storage space), part of the data is usually deleted in units of "rows" before being stored in the physical cell. Accordingly, the puncturing bits generated due to insufficient storage space are usually in the same row of the target parity check matrix 701. The bits in the same row of the target parity check matrix 701 correspond to log likelihood ratios of zero.

[0082] In an example embodiment, the first minimum value of each column of the target parity check matrix 701 is zero or a preset absolute value of a log likelihood ratio.

[0083] In an example embodiment, the first decoding parameter includes the first index value of each column of the target parity check matrix 701. In this case, the absolute values of the preset log likelihood ratios corresponding to the non-zero bits of each column of the target parity check matrix 701 are the same (e.g., 8). In general, the first minimum value of each column of the target parity check matrix 701 corresponds to the last non-zero bit of each column of the target parity check matrix 701. Therefore, the first index value of the first column c0 is v12, the first index value of the second column c1 is v8, the first index value of the third column c2 is v9, the first index value of the fourth column c3 is v10, the index value of the fifth column c4 is v11, and the index value of the sixth column c5 is v12.

[0084] In an example embodiment, the first decoding parameter includes the first index value and the first minimum value of each column of the target parity check matrix 701. In this case, the first minimum values of each column of the target parity check matrix 701 are not completely the same.

[0085] In an example embodiment, the first decoding parameters include a first index value, a first minimum value, and a second index value of each column of the target parity check matrix 701. In this case, the first minimum value and the first index value of each column of the target parity check matrix 701 are not the same. For example, there are puncturing bits in a same row of the target parity check matrix 701. In this case, the log-likelihood ratio values corresponding to the bits in the same row of the target parity check matrix 701 are all zero. That is, the first minimum value and the first index value of each column of the target parity check matrix 701 are the same. In this case, the first minimum value and the second index value can be recorded for performing the decoding operation, so as to improve the decoding speed.

[0086] In an example embodiment, after receiving the first codeword, the decoding circuit 542 can directly read the first decoding parameters corresponding to the target parity check matrix 701, and perform a first decoding operation on the first codeword using the first decoding parameters. The first decoding parameters can be stored in a buffer (not shown) in the error checking and correction circuit 54, for example. A plurality of first decoding parameters corresponding to a plurality of different parity check matrices can be recorded in a management table, for example, and the decoding circuit 542 can read the first decoding parameters corresponding to the target parity check matrix 701 from the management table.

[0087] In an example embodiment, the first decoding operation can be a hard bit decoding operation. Those skilled in the art should know how to use the hard bit decoding operation to decode data, and therefore it is not repeated here.

[0088] If all the errors in the first codeword are corrected (i.e., the first decoding operation is successful), the memory management circuit 51 can output the correct first codeword. However, if part of the errors in the first codeword cannot be corrected (i.e., the first decoding operation fails), the memory management circuit 51 can perform a next decoding operation (also referred to as a second decoding operation) on the first codeword using another decoding parameter (also referred to as a second decoding parameter).

[0089] In an example embodiment, the memory management circuit 51 (the decoding circuit 542) can perform a parameter operation on the target parity check matrix 701 to obtain the second decoding parameter. The second decoding parameter includes a second minimum value and an index value (also referred to as a third index value) of the second minimum value of each column in the target parity check matrix 701.

[0090] Figure 9 is a schematic diagram of a partial parity check matrix according to an example embodiment of the present application. Please refer to Figure 9 After the first decoding operation, the first column c0 of the target parity check matrix 701 can be adjusted to Figure 9 the first column c0' shown in the figure, the positions of the non-zero bits of the first column c0' are different fromFigure 7 the position of the non-zero bit of the first column c0. Further, since the first codeword has been decoded, the log-likelihood ratio value corresponding to the first codeword has been adjusted. That is, the first minimum value and the first index value of each column of the target parity check matrix 701 will be changed. Therefore, the decoding circuit 542 needs to perform the parameter operation on the target parity check matrix 701 to obtain the updated first minimum value (i.e., the second minimum value) and the updated first index value (i.e., the third index value).

[0091] In an example embodiment, the decoding circuit 542 obtains the minimum value of the absolute values of the plurality of reliability information corresponding to all the non-zero bits in each column of the target parity check matrix 701 as the second minimum value, and obtains the index value of the position of the non-zero bit corresponding to the second minimum value as the third index value. For example, the first, 3rd-4th, 6th, 8th and 11th bits of the first column c0' are non-zero bits (i.e., bits with values). The decoding circuit 542 can obtain the minimum value of the absolute values of the log-likelihood ratio values corresponding to the first, 3rd-4th, 6th, 8th and 11th bits of the first column c0' as the second minimum value. For example, the absolute value of the log-likelihood ratio value corresponding to the 11th bit of the first column c0' is the second minimum value, and the third index value of the first column c0' is v10.

[0092] In an example embodiment, the decoding circuit 542 performs a second decoding operation on the first codeword using the second decoding parameters. If all the errors in the first codeword are corrected (i.e., the second decoding operation is successful), the memory management circuit 51 can output the correct first codeword. However, if some of the errors in the first codeword cannot be corrected (i.e., the second decoding operation is unsuccessful), the memory management circuit 51 can perform the parameter operation again to obtain updated decoding parameters, and perform the next decoding operation on the first codeword using the updated decoding parameters until the decoding is successful or the number of iterations reaches a termination number.

[0093] According to the above, after receiving the first codeword, the memory management circuit 51 (the decoding circuit 542) can directly read the first decoding parameters corresponding to the target parity check matrix 701 and perform the first decoding operation (i.e., the hard bit decoding operation) thereon without performing the parameter operation on the target parity check matrix 701, which can save the decoding time.

[0094] Figure 10 is a flowchart of a decoding control method according to an example embodiment of the present application. Please refer to Figure 10In step S1001, the first codeword is read from the rewritable nonvolatile memory module 43. In step S1002, the first decoding parameter corresponding to the target parity check matrix is read. In step S1003, the first decoding operation is performed on the first codeword using the first decoding parameter. In step S1004, in response to the failure of the first decoding operation, the parameter operation is performed for the target parity check matrix to obtain the second decoding parameter, and the second decoding operation is performed on the first codeword using the second decoding parameter. However, Figure 10 The above steps have been described in detail in the foregoing embodiments, and thus will not be described again. It is worth noting that, Figure 10 The steps in the foregoing embodiments can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. In addition, Figure 10 The method of the foregoing embodiments can be used in combination with the foregoing example embodiments, or can be used alone, and the present application is not limited thereto.

[0095] In summary, the decoding control method, the memory storage device, and the memory control circuit unit provided by the example embodiments of the present application can reduce the parameter operation (also referred to as the initialization operation) for the target parity check matrix by performing the first decoding operation (i.e., the hard bit decoding operation) using the first decoding parameter stored in advance, thereby achieving the effect of improving the decoding speed.

[0096] Finally, it should be noted that: the foregoing embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the foregoing embodiments of the present application have been described in detail, those skilled in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the foregoing embodiments of the present application.

Claims

1. A decoding control method for a rewritable non-volatile memory module, the decoding control method comprising: Read the first codeword from the rewritable non-volatile memory module; Read the first decoding parameter corresponding to the target parity check matrix; Perform a first decoding operation on the first codeword using the first decoding parameters; In response to the failure of the first decoding operation, a parameter operation is performed on the target parity check matrix to obtain a second decoding parameter, and the second decoding parameter is used to perform a second decoding operation on the first codeword.

2. The decoding control method according to claim 1, wherein the first decoding parameter includes the first index value of the first minimum value of each column of the target parity check matrix.

3. The decoding control method according to claim 2, wherein the first index value is used to indicate the position of the non-zero bit corresponding to the first minimum value.

4. The decoding control method according to claim 2, wherein the first minimum value is the minimum of the absolute values ​​of the log probability ratios corresponding to the plurality of non-zero bits in each column of the target parity check matrix.

5. The decoding control method according to claim 2, wherein in response to the fact that the first minimum value of each column of the target parity check matrix is ​​not completely identical, the first decoding parameter further includes the first minimum value.

6. The decoding control method according to claim 2, wherein in response to the target parity check matrix having punctured bits, the first minimum value is zero, and the first index value is used to indicate the position of the punctured bits.

7. The decoding control method according to claim 2, wherein in response to the first minimum value being different from the first minimum value in each column of the target parity check matrix, the first decoding parameter further includes the first minimum value and a second index value of the first minimum value. The second index value is used to indicate the position of the non-zero bit corresponding to the first small value, which is the second smallest value among the absolute values ​​of the log probability ratios corresponding to the multiple non-zero bits in each column of the target parity check matrix.

8. The decoding control method according to claim 1, wherein the second decoding parameter includes the second minimum value of each column of the target parity check matrix and the third index value of the second minimum value.

9. The decoding control method according to claim 8, wherein the step of performing the parameter operation on the target parity check matrix to obtain the second decoding parameter includes: The minimum value of the absolute values ​​of the log probability ratios corresponding to the multiple non-zero bits in each column of the target parity check matrix is ​​taken as the second minimum value; as well as The index value corresponding to the position of the non-zero bit of the second minimum value is used as the third index value.

10. The decoding control method according to claim 1, wherein the first decoding operation is a hard bit decoding operation.

11. A memory storage device, comprising: Connect the interface unit to the host system; Rewritable non-volatile memory module; as well as The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: The first codeword is read from the rewritable non-volatile memory module. Read the first decoding parameter corresponding to the target parity check matrix. Perform a first decoding operation on the first codeword using the first decoding parameters. In response to the failure of the first decoding operation, a parameter operation is performed on the target parity check matrix to obtain a second decoding parameter, and the second decoding parameter is used to perform a second decoding operation on the first codeword.

12. The memory storage device of claim 11, wherein the first decoding parameter includes a first index value of the first minimum value of each column of the target parity check matrix.

13. The memory storage device of claim 12, wherein the first index value is used to indicate the location of a non-zero bit corresponding to the first minimum value.

14. The memory storage device of claim 12, wherein the first minimum value is the minimum of the absolute values ​​of the plurality of log probability ratios corresponding to the plurality of non-zero bits in each column of the target parity check matrix.

15. The memory storage device of claim 12, wherein, in response to the first minimum value of each column of the target parity check matrix not being completely identical, the first decoding parameter further includes the first minimum value.

16. The memory storage device of claim 12, wherein the target parity check matrix has punctured bits in response, the first minimum value is zero, and the first index value is used to indicate the position of the punctured bits.

17. The memory storage device of claim 12, wherein, in response to the first minimum value being different from the first minimum value in each column of the target parity check matrix, the first decoding parameter further includes the first minimum value and a second index value of the first minimum value. The second index value is used to indicate the position of the non-zero bit corresponding to the first small value, which is the second smallest value among the absolute values ​​of the log probability ratios corresponding to the multiple non-zero bits in each column of the target parity check matrix.

18. The memory storage device of claim 11, wherein the second decoding parameter includes a second minimum value of each column of the target parity check matrix and a third index value of the second minimum value.

19. The memory storage device according to claim 18, wherein the memory control circuit unit is further configured to: The minimum value of the absolute values ​​of the log probability ratios corresponding to the multiple non-zero bits in each column of the target parity check matrix is ​​taken as the second minimum value, and The index value corresponding to the position of the non-zero bit of the second minimum value is used as the third index value.

20. The memory storage device according to claim 11, wherein the first decoding operation is a hard bit decoding operation.

21. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising: The host interface connects to the connection interface unit; A memory interface is provided for connecting the rewritable non-volatile memory module. as well as The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: The first codeword is read from the rewritable non-volatile memory module. Read the first decoding parameter corresponding to the target parity check matrix. Perform a first decoding operation on the first codeword using the first decoding parameters, and In response to the failure of the first decoding operation, a parameter operation is performed on the target parity check matrix to obtain a second decoding parameter, and the second decoding parameter is used to perform a second decoding operation on the first codeword.

22. The memory control circuit unit of claim 21, wherein the first decoding parameter includes a first index value of the first minimum value of each column of the target parity check matrix.

23. The memory control circuit unit of claim 22, wherein the first index value is used to indicate the position of a non-zero bit corresponding to the first minimum value.

24. The memory control circuit unit of claim 22, wherein the first minimum value is the minimum of the absolute values ​​of the plurality of log probability ratios corresponding to the plurality of non-zero bits in each column of the target parity check matrix.

25. The memory control circuit unit of claim 22, wherein, in response to the first minimum value of each column of the target parity check matrix not being completely identical, the first decoding parameter further includes the first minimum value.

26. The memory control circuit unit of claim 22, wherein the target parity check matrix has punctured bits in response, the first minimum value is zero, and the first index value is used to indicate the position of the punctured bits.

27. The memory control circuit unit of claim 22, wherein, in response to the first minimum value of each column of the target parity check matrix being different from the first minimum value, the first decoding parameter further includes the first minimum value and a second index value of the first minimum value. The second index value is used to indicate the position of the non-zero bit corresponding to the first small value, which is the second smallest value among the absolute values ​​of the log probability ratios corresponding to the multiple non-zero bits in each column of the target parity check matrix.

28. The memory control circuit unit of claim 21, wherein the second decoding parameter includes a second minimum value of each column of the target parity check matrix and a third index value of the second minimum value.

29. The memory control circuit unit according to claim 28, wherein the memory management circuit is further configured to: The minimum value of the absolute values ​​of the log probability ratios corresponding to the multiple non-zero bits in each column of the target parity check matrix is ​​taken as the second minimum value, and The index value corresponding to the position of the non-zero bit of the second minimum value is used as the third index value.

30. The memory control circuit unit according to claim 21, wherein the first decoding operation is a hard-bit decoding operation.

Images