Data replacement method and encoder based on Banyan network in LDPC T1 (Low Density Parity Check) encoding

Abstract

The invention relates to the technical field of channel coding, particularly discloses a data replacement method based on a Banyan network in LDPC T1 coding and an encoder, and aims to solve the problems that in the prior art, a data replacement method based on an address generator is large in resource consumption, complex in wiring and difficult to support high parallelism and high throughput. The method comprises the following steps: reading a pre-stored Banoan network coefficient according to a code rate and a non-zero element position of a check matrix, and setting a Banoan network to finish offset jump of 512-bit parallel information to be replaced. The encoder correspondingly comprises a replacement module, a summing circuit and an accumulation module for realizing the method. According to the method, the non-blocking rearrangement characteristic of the Banoan network under the T1 code standard is utilized, 255 replacement modes of three code rates of the LDPC T1 code are supported through a unified hardware structure, the maximum 512-path parallel is achieved, meanwhile, the resource consumption of a lookup table and a register is remarkably reduced, and the working frequency and the coding throughput are improved through the multi-stage assembly line design.

Description

Technical Field

[0001] This invention relates to the field of channel coding technology, and in particular to a data permutation method and encoder based on Banyan network in LDPC T1 coding. Background Technology

[0002] In satellite communication equipment, channel coding is an indispensable and crucial component of the entire system. LDPC (Low-Density Parity-Check) codes, in particular, achieve superior bit error rate performance and high coding and decoding efficiency in high-noise environments, and are therefore adopted by protocols such as CCSDS (Advisory Committee on Space Data Systems) and DVB-S2 (Digital Broadcasting Satellite 2). Furthermore, in the "Technical Requirements for Low-Density Parity-Check Coding in Relay Satellite Systems," the T1 code group (a type of quasi-cyclic LDPC code) is primarily designed for high-speed satellite-to-ground data transmission applications, with a coding gain exceeding 9dB under 8PSK modulation to meet the high-speed satellite-to-ground transmission requirements of the Gaofen project.

[0003] Low-density parity-check codes (LDPCs) are a type of code based on a coefficient parity-check matrix. The linear block code, whose core constraint in the encoding process is the check equation. ,in It is the encoded codeword. For information bits, The superscript T indicates matrix transpose. LDPC parity check matrix. It is a sparse matrix, with most elements being 0 and only a few non-zero elements. In LDPC T1 encoding, each non-zero element in the parity-check matrix represents an affine permutation identity matrix. Its corresponding offset and jump values ​​specify the offset and step size of the offset jump, ultimately determining how information bits are shifted during the encoding process. In the T1 code encoding process, the parity vector corresponding to each row of the parity-check matrix is ​​obtained by performing a modulo-2 summation on multiple sets of information vectors corresponding to the non-zero elements of each row after offset jumps (i.e., permutation shifts with different offsets and step sizes), and then accumulating these intermediate vectors.

[0004] Currently, data substitution in T1 code encoding is mainly implemented based on an address generator. This module consists of a jump / offset address memory, a multiplexer, and an address accumulator, requiring numerous AND and XOR logic operations to generate the RAM address after the offset jump. For high-throughput scenarios in satellite-to-ground communication, this implementation architecture needs to call multiple encoding kernels to improve parallelism. The lookup table and register resources consumed increase linearly with the number of kernels, potentially leading to excessive resource consumption and difficulties in placement and routing. Summary of the Invention

[0005] This invention provides a data permutation method and encoder based on Banyan network in LDPC T1 encoding. The technical problem it solves is that the data permutation in T1 code encoding based on address generators requires a large amount of logic resources and complex control circuits. In high-parallelism and high-throughput application scenarios (such as satellite data transmission), this implementation method leads to high resource consumption (lookup tables, registers), complex wiring, difficulty in timing optimization, and difficulty in supporting high parallelism (such as 512-channel parallelism).

[0006] To address the above technical problems, this invention provides a data permutation method based on a Banyan network in LDPC T1 encoding, comprising:

[0007] The Banyan network coefficients for 255 offset jump cases with three code rates of LDPC T1 code are calculated and stored in the Banyan network coefficient storage module.

[0008] The 512-bit information to be replaced, corresponding to the non-zero elements of the parity matrix that need to be replaced, is read out from RAM in parallel.

[0009] The read address is calculated based on the code rate and the row and column numbers of the non-zero elements in the parity check matrix, and the corresponding Banyan network coefficients are read from the Banyan network coefficient storage module.

[0010] The 512 bits of information to be permuted and the Banyan network coefficients are fed into the Banyan network for permutation to obtain 512 bits of permutation information.

[0011] Furthermore, before performing the permutation, the input information to be permuted is delayed by the input delay module and aligned with the extracted Banyan network coefficients.

[0012] Furthermore, the Banyan network has 9 levels, with the basic network unit being a 2×2 switching module, and each level having a total of 256 switching modules.

[0013] Furthermore, the Banyan network operates using a three-stage pipeline. The first-stage pipeline outputs the permutation results of the network's first to third stages, the second-stage pipeline outputs the permutation results of the network's fourth to sixth stages, and the third-stage pipeline outputs the permutation results of the network's seventh to ninth stages.

[0014] Furthermore, the Banyan network coefficient storage module has 9 sub-storage modules, which store 256 coefficients for each level of the Banyan network. Among them, addresses 0 to 74 store the coefficients corresponding to 75 offset jump values ​​at 1 / 2 code rate, addresses 75 to 164 store the coefficients corresponding to 2 / 3 code rate, and addresses 165 to 254 store the coefficients corresponding to 5 / 6 code rate.

[0015] Furthermore, the read address is calculated as follows:

[0016] For a 1 / 2 bit rate, read address ;

[0017] For a 2 / 3 bitrate, read address ;

[0018] For 5 / 6 bitrate, read address ;

[0019] in, The row number of the non-zero element. The column number of the non-zero element; This is the address offset, corresponding to 1 / 2 bit rate. For 0, 2 / 3 bitrate For 75, 5 / 6 bitrate It is 165.

[0020] This invention also provides an encoder based on a Banyan network for LDPC T1 encoding, the key feature of which is that it includes:

[0021] The receiving and conversion module is used to convert the bit width of the input information to be encoded to 512.

[0022] The conversion result caching module is used to cache the data information after bit-width conversion;

[0023] The encoding calculation module includes a Banyan permutation network module, a summing circuit, and an accumulation module. The Banyan permutation network module is used to permutate 512-bit parallel data read from the conversion result buffer module according to the data permutation method based on the Banyan network in LDPC T1 encoding. The summing circuit adds the permuted 512-bit data bit by bit. The accumulation module is used to perform bit-by-bit accumulation calculation on the summed data of a single row to obtain the final check bit output.

[0024] The output conversion module is used to convert the bit width of the 512 parallel parity bits obtained after encoding and output them.

[0025] Preferably, the encoder further includes:

[0026] An external parameter control module is used to read the relevant parameters required by the encoding calculation module based on the bit rate information.

[0027] Encoding state control circuit, used to control the entire encoding process through a state machine;

[0028] A check bit caching module is used to cache the check bits calculated by the encoding calculation module;

[0029] The output buffer module is used to buffer information bit data that has not been converted to bit width.

[0030] Preferably, the accumulation module is implemented through a 4-stage pipeline, with each stage performing the accumulation operation of 128 bits of data.

[0031] Preferably, the encoding state control circuit includes a first state machine and a second state machine, wherein the first state machine controls the entire encoding calculation process and the second state machine controls the input and output data streams;

[0032] The first state machine sequentially goes through the following states: initialization state, waiting for data to be ready state, check bit calculation state, waiting for encoding calculation to be completed state, and encoding completion state; the second state machine sequentially goes through the initialization state, waiting for data to be ready state, information bit output state, check bit output state, and output completion state.

[0033] After both state machines have completed initialization and are in a state of waiting for data to be ready, starting from the input of the first frame of information:

[0034] In the first state machine, while waiting for data to be ready, the input data is converted from 16-bit parallel to 512-bit parallel and stored in RAM. This state ends after all the data in the frame has been stored. Then, it jumps to the parity bit calculation state to begin parity bit calculation. This state is controlled by an encoding control counter, where the state count clock cycles are equal to the number of non-zero elements in the parity check matrix for that code rate. For a 1 / 2 code rate, the count is 75; for 2 / 3 and 5 / 6 code rates, it is 90. Next, it enters the waiting for encoding calculation completion state, waiting for the multi-stage encoding pipeline to complete. The entire encoding calculation uses an 11-stage pipeline, so this state lasts for 11 clock cycles. Finally, after passing through the encoding completion state and the initialization state (each lasting 1 clock cycle), it re-enters the waiting for data to be ready state.

[0035] In the data-ready state, the second state machine delays the unconverted information bits according to different code rates and input / output bit widths by a corresponding clock cycle. After the delay state ends, it enters the information bit output state, outputting the delayed input data. With an input / output bit width of 16 bits, the three code rates require 480, 640, and 800 clock cycles respectively. Then, it enters the parity bit output state, outputting the calculated parity bit. With an input / output bit width of 16 bits, the three code rates require 480, 320, and 160 clock cycles respectively. Finally, after passing through the output completion state and the initialization state (each lasting 1 clock cycle), it re-enters the data-ready state.

[0036] The second frame of information can be input when both state machines are in the waiting-for-data-ready state.

[0037] This invention provides a data permutation method and encoder based on a Banyan network in LDPC T1 encoding. The method rapidly reads the corresponding Banyan network coefficients based on the current code rate and non-zero element positions of the information to be permuted. The Banyan network then performs offset jumps on the currently input information to be permuted under the current Banyan network coefficients, resulting in the permuted output. Based on the non-blocking offset jump characteristic of the Banyan network under the T1 standard, this invention can achieve a maximum parallelism of 512 for all offset jumps across the three code rates of LDPC T1 codes, significantly improving encoding throughput while balancing various resources. This invention employs a hardware-friendly unified Banyan network permutation structure, ensuring extremely high data throughput while achieving resource efficiency, optimized timing performance, and simplified system control. It provides an efficient, reliable, and scalable hardware architecture solution for the engineering implementation of high-parallelism LDPC encoders. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a data permutation method based on a Banyan network in LDPC T1 encoding provided by an embodiment of the present invention;

[0039] Figure 2 This is a pipeline example diagram of a data permutation method based on a Banyan network in LDPC T1 encoding provided by an embodiment of the present invention;

[0040] Figure 3 This is an architecture diagram of an encoder based on a Banyan network in LDPC T1 encoding provided by an embodiment of the present invention;

[0041] Figure 4 This is a general state control diagram of the encoder provided in an embodiment of the present invention;

[0042] Figure 5 This is a pipeline example diagram of the check bit calculation process provided in an embodiment of the present invention. Detailed Implementation

[0043] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The embodiments are given for illustrative purposes only and should not be construed as limiting the present invention. The accompanying drawings are for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0044] Example 1

[0045] This invention provides a data permutation method based on a Banyan network in LDPC T1 encoding, as shown in the embodiments of the present invention. Figure 1 As shown in the schematic diagram, the method includes the following steps:

[0046] The Banyan network coefficients for 255 offset jump scenarios with three code rates of LDPC T1 code are calculated and stored in the Banyan network coefficient storage module in a way that maximizes resource utilization.

[0047] The 512-bit information to be replaced, corresponding to the non-zero elements of the parity matrix that need to be replaced, is read out from RAM in parallel.

[0048] The Banyan network coefficient lookup module calculates the address based on the code rate and the row and column numbers of the non-zero elements in the parity check matrix, and reads the corresponding Banyan network coefficient from the Banyan network coefficient storage module.

[0049] The 512-bit permutation information and Banyan network coefficients are fed into the Banyan network for permutation, resulting in 512 bits of permutation information.

[0050] Before performing the permutation, the input information to be permuted needs to be delayed by the input delay module to align with the extracted Banyan network coefficients.

[0051] Since the data length required for each replacement is 512, a 9-level Banyan network is needed. The basic unit of the network is a 2×2 switching module, with a total of 256 switching modules in each level.

[0052] LDPC T1 codes have three code rates: 1 / 2 code rate has 75 offset jump values, and 2 / 3 and 5 / 6 code rates have 90 offset jump values, for a total of 255 offset jump patterns. The Banyan network has 9 levels, each with 256 2×2 switching modules, and uses a three-stage pipeline, requiring all 9 levels (9*256 coefficients) to be read and fed into the pipeline at once. Therefore, the Banyan network coefficient storage module has 9 sub-storage modules (RAM1, RAM2, ..., RAM9), storing the Banyan network coefficients for each level. Each sub-storage module has a depth and data width of 256 bits. Addresses 0-74 store the 256 Banyan network coefficients corresponding to the 75 offset jump values ​​for the 1 / 2 code rate; addresses 75-164 store the coefficients for the 2 / 3 code rate; and addresses 165-254 store the coefficients for the 5 / 6 code rate. This storage scheme maximizes the utilization of FPGA storage resources.

[0053] The Banyan network coefficient lookup module receives the code rate mode and the row and column indices of the parity matrix containing the non-zero element to be replaced from the external parameter control module. Based on this information, it generates a read address and reads the network coefficients from the Banyan network coefficient storage module. The address conversion method is as follows:

[0054] Taking a 1 / 2 bitrate as an example, its basis matrix dimension is There are 75 non-zero elements, and each row has a weight of 5. Therefore, if a non-zero element has a row number of 5, then the row number of the non-zero element is 5. Column number is Its corresponding read address Similarly, in a 2 / 3 bitrate, each line has a weight of 9, with a total of 90 non-zero elements, corresponding to the read address. ; For 5 / 6 bitrate, each line has a weight of 18, corresponding to the read address There are 90 non-zero elements in total; among them This is the address offset, corresponding to 1 / 2 bit rate. The bit rate is 0, 2 / 3 has a bit rate of 75, and 5 / 6 has a bit rate of 165.

[0055] The pipeline of this method is as follows Figure 2 As shown, the specific process is as follows:

[0056] The external parameter control module will control the bitrate information. ( Figure 2 (Taking a 1 / 2 bit rate as an example) and the row and column numbers of non-zero elements. and The input parameters are fed into the Banyan network coefficient lookup module, which implements the lookup through a two-stage pipeline. The first stage completes the input register and address calculation, converting the input parameters into network coefficient addresses. The second stage involves accessing the BRAM using the generated read address and completing the output register to obtain the data to be replaced.

[0057] The data to be replaced is read from the BRAM and then delayed, and the network coefficients are read out. Alignment is performed to obtain the input data. The input is fed into the Banyan network for permutation. If combinational logic is directly combined in a 9-stage switching network, the input-to-output delay will be significant, limiting the system's operating frequency. This embodiment designs a Banyan network that operates in a three-stage pipeline. The pipeline breaks a long combinational logic path into multiple shorter segments, inserting registers between segments, thereby allowing for higher clock frequencies and improving throughput. Specifically, the permutation results of stages 1-3 of the first-stage output network... The second-level output network shows the permutation results for levels 4-6. The permutation results of levels 7-9 of the third-level output network. The final output is the data after the offset jump. This design divides the 9-level switching network into three pipelines: the first pipeline handles the first three levels (3 levels total), the second pipeline handles the fourth to sixth levels (3 levels total), and the third pipeline handles the seventh to ninth levels (3 levels total). After each pipeline stage, the intermediate results are stored in a register (i.e., the pipeline register), and then the next pipeline stage begins in the next clock cycle. The advantages of this design are:

[0058] Increasing the clock frequency reduces the combinational logic delay within each pipeline stage, allowing the system to operate at a higher clock frequency.

[0059] Increase throughput: Once the pipeline is full, a new set of data can be input and a set of processed data can be output each clock cycle, thus enabling a replacement operation to be completed each clock cycle.

[0060] Suppose there is a three-stage pipeline, where each stage requires one clock cycle for processing (in reality, the combinational logic delay of each stage determines the clock cycle). The pipeline operation process is as follows:

[0061] Clock cycle 1: Data A enters the first stage pipeline (network levels 1-3);

[0062] Clock cycle 2: Data A enters the second-stage pipeline (network stages 4-6), while data B enters the first-stage pipeline;

[0063] Clock cycle 3: Data A enters the third-stage pipeline (network stages 7-9), data B enters the second-stage pipeline, and data C enters the first-stage pipeline;

[0064] Clock cycle 4: Data A is output, data B enters the third stage pipeline, data C enters the second stage pipeline, and data D enters the first stage pipeline.

[0065] As can be seen, starting from the 4th clock cycle, a result can be output every clock cycle, with a throughput of one per-cycle per substitution. However, if it were a single-stage output, a result would only be output every 3 cycles (assuming the delay of each segment is the same, the total delay of combinational logic is actually greater and the cycle is longer).

[0066] The number of pipeline stages is a design trade-off. More stages allow for higher frequencies, but also increase register resource overhead and pipeline latency (total time from data input to output). Choosing three stages is the most reasonable division to achieve a clock frequency of 225MHz on the target FPGA after timing analysis.

[0067] The encoder was designed using VHDL hardware description language for RTL, and based on the Xilinx ZYNQ UltraScale+RFSOC ZU47DR chip, the FPGA implementation of the encoder under a 225MHz clock speed was synthesized and placed and routed using the Vivado 2021.2 platform. Resource consumption results are as follows: the encoder consumes 3820 lookup table (LUT) resources, 9569 register (FF) resources, and 4.5 block RAM (BRAM) resources. Timing results are as follows: there is a 1.157ns relaxation in hold time and a 0.01ns relaxation in setup time. By changing the input information parallelism (8~512), the encoder can achieve a maximum encoding throughput of 1.76~21.33Gbps.

[0068] In summary, the data permutation method based on the Banyan network in LDPC T1 encoding provided by this invention quickly reads the corresponding Banyan network coefficients based on the current code rate and non-zero element positions of the information to be permuted. The Banyan network then performs offset jumps on the currently input information to be permuted under the current Banyan network coefficients to obtain the permuted output. Based on the non-blocking and reorderable characteristics of the Banyan network under the T1 code standard, this invention can achieve a maximum parallelism of 512 for all offset jumps of the three code rates of LDPC T1 codes, greatly improving the encoding throughput while balancing various resources.

[0069] Specifically, the present invention has the following significant beneficial effects:

[0070] 1. Significantly reduced hardware resource consumption and simplified placement and routing: By adopting pre-computed Banyan network coefficient storage and static network configuration mechanisms to replace traditional dynamic address generation and multiplexing logic, hardware resource consumption no longer increases linearly with parallelism. While achieving a maximum of 512 parallel paths, the encoder consumes only 3820 lookup tables (LUTs), 9569 registers (FFs), and 4.5 block RAMs (BRAMs), resulting in extremely low resource consumption and greatly alleviating the engineering challenges of complex placement and routing and difficult timing optimization under high parallelism.

[0071] 2. Superior timing performance, supporting stable high-frequency operation: The Banyan network adopts a three-stage pipeline structure, and the accumulation module adopts a four-stage pipeline design, effectively segmenting the critical path and improving the system operating frequency. At a clock speed of 225MHz, the setup time relaxation reaches 0.01ns, and the hold time relaxation reaches 1.157ns, with sufficient timing margin to ensure stable and reliable operation of the encoder at high frequencies;

[0072] 3. Significantly improved encoding throughput, adapting to high-speed data transmission scenarios: At a working frequency of 225MHz, the encoder supports 8~512 bits of variable parallelism input, and can achieve a maximum encoding throughput of 21.33Gbps, perfectly meeting the needs of high-bandwidth and high-real-time communication systems such as satellite data transmission.

[0073] 4. Supports multiple code rates and modes, with high flexibility and configurability: The Banyan network coefficient storage module uniformly stores the Banyan network coefficients corresponding to 255 permutation modes of LDPC T1 codes with three code rates (1 / 2, 2 / 3, 5 / 6). It can adapt to different encoding scenarios by simply switching external parameters, without the need to design dedicated circuits for each mode, thus enhancing the system's versatility and reconfigurability.

[0074] 5. Strong engineering feasibility and potential for industrial application: The encoder has been based on the Xilinx ZYNQ UltraScale+ RFSoC ZU47DR chip and has completed synthesis, placement and routing, and timing verification through the Vivado 2021.2 platform. All performance indicators have met or exceeded the design expectations, indicating that the invention has good feasibility and engineering promotion value.

[0075] Example 2

[0076] Based on Example 1, this example provides an encoder based on a Banyan network for LDPC T1 encoding, the architecture of which is as follows: Figure 3 As shown, it includes:

[0077] External parameter control module: Reads the relevant parameters required by the encoding calculation module based on the bitrate information.

[0078] Encoding state control circuit: The encoding state machine related circuits control the entire encoding process.

[0079] Receiver conversion module: The receiver conversion module converts the bit width of the input information to be encoded to 512.

[0080] Conversion result caching module: caching the data information after bit width conversion.

[0081] Encoding Calculation Module: The encoding calculation module mainly includes a Banyan permutation network module, a summing circuit, and an accumulation module. The Banyan permutation network module permutes the 512 parallel data read from the conversion result buffer module according to the code rate and the row and column information of non-zero elements, as described in Example 1. The summing circuit performs bit-by-bit summation with the multiple sets of 512-bit data after permutation in the same row. The accumulation module is used to perform bit-by-bit accumulation calculation on the accumulated data to obtain the final check bit output. The accumulation is implemented through a 4-stage pipeline, with each stage completing the accumulation operation of 128 bits of data.

[0082] Check bit caching module: Caches the check bits obtained from the encoding calculation for bit width conversion.

[0083] Output buffer module: Buffers information bit data that has not been converted to bit width, and outputs it after the check bit calculation is completed.

[0084] Output conversion module: Converts the 512 parallel parity bits obtained after encoding to the required bit width.

[0085] The general state control of the encoder is as follows: Figure 4 As shown, the entire encoding process is controlled by two state machines. The first state machine (state machine 1) controls the entire encoding process, and the second state machine (state machine 2) controls the input and output data flow. The first state machine sequentially goes through the following states: initialization state ( ), waiting for data to be ready ( ), check bit calculation status ( ), waiting for encoding calculation to complete status ( ), Encoding completion status ( The second state machine sequentially goes through the initialization state (); ), waiting for data to be ready ( ), Information bit output status ( ), Check bit output status ( Output completion status ( ).

[0086] The general process is as follows:

[0087] 1) During the initialization of the two state machines ( After completion, all are in a state of waiting for data to be ready. When the first frame of information is input, the process begins.

[0088] 2) After the information data arrives, it is processed in two ways: one way is directly buffered and delayed output is controlled by state machine 2; the other way is controlled by state machine 1 to perform bit width conversion, converting the input 8 / 16 / 32... parallel information bits into 512 parallel bits for subsequent encoding operations.

[0089] 3) After the bit width conversion is complete, state machine 1 enters the parity bit calculation state. Then, the parity bit encoding calculation begins. Taking a 1 / 2 code rate as an example, the parity value p is calculated as follows:

[0090] ,

[0091] in, , These are the verification matrices. The corresponding information bits and check bits, It is the identity matrix; in the GF(2) field, This is a special matrix where all elements in the upper triangular region and diagonal are 1, and all elements in the lower triangular region are 0. This is the transpose of the information data. An intermediate vector is defined to break down the computation process. The entire encoding update is performed according to the row order of the parity-check matrix, that is, the intermediate sub-vector corresponding to each row is calculated sequentially. After obtaining the subvector corresponding to the k-th row Then, subsequent calculations for that row can be performed immediately. That is, for subvectors Perform an accumulation operation to obtain the check vector corresponding to the k-th row. Following the above procedure, the verification matrix is ​​updated and calculated sequentially according to row order. Finally, the complete check digit can be obtained. .

[0092] In terms of implementation, taking a 1 / 2 bitrate as an example, the entire encoding implementation is as follows: Figure 5 As shown, the entire check bit calculation process is rationally designed as a multi-stage pipeline, with each stage responsible for a specific calculation task, ensuring that data can flow seamlessly and efficiently between stages.

[0093] In the intermediate sub-vector In the computation phase, the implementation involves offsetting and jumping the 512-bit data corresponding to all non-zero elements of the layer, followed by bitwise summation. State machine 1 generates state count values ​​according to the layer order. Since the line weight of a 1 / 2 bitrate is 5, it first counts states 1-5 of the first layer, and then obtains the addresses corresponding to the non-zero elements of the first layer based on the state count values. The 512 parallel data corresponding to the non-zero elements of this layer are retrieved from the input transformation result caching module. Read out sequentially as input to the permutation network. The data is fed into a three-level Banyan network for jump offset to obtain the permutation output. Intermediate subvector Corresponding signal After obtaining the first output of the permutation network at this layer When a valid value is obtained, its value is set to 0. Then, based on this, the subsequent results obtained from this layer The values ​​are summed modulo 2, and the summation is completed at the 5th clock cycle. That is, the first layer of valid intermediate sub-vectors Then at the next clock The value is set to the first valid value of the second layer. The value is calculated repeatedly to complete the calculation for all layers.

[0094] During the accumulation phase, the entire accumulation operation is designed as a four-stage pipeline, which divides the accumulation operation of 512-bit data into four stages, with each stage performing 128-bit accumulation sequentially to ensure good timing performance. The signal is continuously fed into the accumulation pipeline, and the pipeline outputs the corresponding calculation result after 4 clock cycles. When each layer of intermediate sub-vectors The corresponding valid After input, the pipeline outputs after 4 clock cycles. That is, the check vector Once the valid value is obtained, it is stored in the verification result cache module, and then waits for state machine 2 to read and output it.

[0095] The entire encoding process uses an 11-stage pipeline, meaning there is a delay of 11 clock cycles from the input of the last set of data to the output of the last set of parity bit subvectors. Therefore, this delay is introduced into the state design of state machine 1. The state is buffered to ensure that the encoding calculation for a frame of data can be completed within the current state cycle, thus ensuring the stable operation of the encoder.

[0096] 4) The output of information bits and parity bits is controlled by state machine 2. Its core idea is to maximize throughput while ensuring the output of information bits and parity bits by delaying the input information bits. When the input / output bit width is small, the first set of parity sub-vectors needs to be output after the delayed information bits have been completely processed. Completed just in time, output can be started immediately. This is thanks to the 512 high-parallel encoding streaming architecture, when a set of 512-bit check vectors... After the output of the small bit width is completed, the second set of parity bits will follow. The calculations and storage have been completed, ensuring continuous output of the parity bits. As the input and output bit widths continue to increase, the time required to convert from a large bit width to a small bit width output becomes insufficient to cover the calculation time of a set of parity sub-vectors, i.e., the first set of parity sub-vectors... When the output is complete, the second set of check vectors If the calculation is not yet complete, the delay time needs to be increased to ensure that the entire check bit can be output continuously. After determining the minimum delay for each case, the maximum throughput of the encoder can be calculated. Table 1 shows the maximum throughput of the encoder at a working frequency of 225MHz under different input and output bit widths.

[0097] Table 1. Throughput of different bit widths under 225MHz clock speed

[0098]

[0099] 5) When both state machines are in an idle state, that is, both are waiting for data to arrive ( When the signal is received, the next frame of information data can be received and processed.

[0100] In summary, this encoder achieves an excellent balance between resource efficiency, computational throughput, and design flexibility at the architectural level. Its core advantage lies in the use of reconfigurable Banyan network hardware replacement units, which replace the traditional multi-address generation and selection logic. Specifically: First, it significantly optimizes hardware resource consumption. By pre-calculating and storing network configuration coefficients, complex dynamic address calculations are transformed into efficient memory reads and static network configurations. This prevents resource consumption (lookup tables, registers) from increasing linearly with parallelism, thus maintaining low resource consumption (only a few thousand levels of lookup tables) even at a maximum parallelism of 512 channels. This solves the fundamental problem of difficult layout and routing in high-parallel scenarios using traditional methods. Second, it significantly improves coding throughput and timing performance. Thanks to the non-blocking characteristics of the Banyan network under the T1 code specification and its carefully designed three-stage pipeline structure, data permutation can be completed within a single clock cycle, greatly increasing the system operating frequency (up to 225MHz) and achieving a throughput of up to 21.33Gbps, perfectly matching the high-bandwidth application requirements of satellite data transmission. Third, it enhances the system's versatility and configurability. This design uniformly supports three code rates and 255 permutation modes of LDPC T1 codes through the Banyan network coefficient storage module. It can adapt to different coding scenarios simply by switching external parameters, avoiding the redundancy of customizing dedicated circuits for different modes. In summary, this design, with its hardware-friendly unified replacement structure, ensures extremely high data throughput while achieving resource efficiency and simplified control, providing an efficient, reliable, and scalable hardware architecture solution for the engineering implementation of high-parallelism LDPC encoders.

[0101] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A data permutation method based on Banyan network in LDPC T1 encoding, characterized in that, include: The Banyan network coefficients for 255 offset jump cases with three code rates of LDPC T1 code are calculated and stored in the Banyan network coefficient storage module. The 512-bit information to be replaced, corresponding to the non-zero elements of the parity matrix that need to be replaced, is read out from RAM in parallel. The read address is calculated based on the code rate and the row and column numbers of the non-zero elements in the parity check matrix, and the corresponding Banyan network coefficients are read from the Banyan network coefficient storage module. The 512 bits of information to be permuted and the Banyan network coefficients are fed into the Banyan network for permutation to obtain 512 bits of permutation information.

2. The data permutation method based on Banyan network in LDPC T1 encoding according to claim 1, characterized in that: Before the permutation is performed, the input information to be permuted is delayed by the input delay module and aligned with the extracted Banyan network coefficients.

3. A data permutation method based on Banyan network in LDPC T1 encoding according to claim 1 or 2, characterized in that: The Banyan network has 9 levels, and the basic network unit adopts a 2×2 switching module, with a total of 256 switching modules in each level.

4. The data permutation method based on Banyan network in LDPC T1 encoding according to claim 3, characterized in that: The Banyan network operates using a three-stage pipeline. The first-stage pipeline outputs the permutation results for stages 1 to 3 of the network, the second-stage pipeline outputs the permutation results for stages 4 to 6 of the network, and the third-stage pipeline outputs the permutation results for stages 7 to 9 of the network.

5. The data permutation method based on Banyan network in LDPC T1 encoding according to claim 1, characterized in that: The Banyan network coefficient storage module has 9 sub-storage modules, which store 256 coefficients for each level of the Banyan network. Among them, addresses 0 to 74 store the coefficients corresponding to 75 offset jump values ​​at 1 / 2 code rate, addresses 75 to 164 store the coefficients corresponding to 2 / 3 code rate, and addresses 165 to 254 store the coefficients corresponding to 5 / 6 code rate.

6. The data permutation method based on Banyan network in LDPC T1 encoding according to claim 5, characterized in that, The read address is calculated as follows: For a 1 / 2 bit rate, read address ; For a 2 / 3 bitrate, read address ; For 5 / 6 bitrate, read address ; in, The row number of the non-zero element. The column number of the non-zero element; This is the address offset, corresponding to 1 / 2 bit rate. For 0, 2 / 3 bitrate For 75, 5 / 6 bitrate It is 165.

7. An encoder based on a Banyan network in LDPC T1 encoding, characterized in that, include: The receiving and conversion module is used to convert the bit width of the input information to be encoded to 512. The conversion result caching module is used to cache the data information after bit-width conversion; The encoding calculation module includes a Banyan permutation network module, a summing circuit, and an accumulation module. The Banyan permutation network module is used to permutate 512-bit parallel data read from the conversion result buffer module according to any one of claims 1 to 6, based on a Banyan network-based data permutation method in LDPC T1 encoding. The summing circuit performs bit-by-bit summation with the permuted 512-bit data in the same row. The accumulation module performs bit-by-bit accumulation on the permuted and summed data in the current row to obtain the final check bit output. The output conversion module is used to convert the bit width of the 512 parallel parity bits obtained after encoding and output them.

8. The encoder based on a Banyan network in LDPC T1 encoding according to claim 7, characterized in that, The encoder also includes: An external parameter control module is used to read the relevant parameters required by the encoding calculation module based on the bit rate information. Encoding state control circuit, used to control the entire encoding process through a state machine; A check bit caching module is used to cache the check bits calculated by the encoding calculation module; The output buffer module is used to buffer information bit data that has not been converted to bit width.

9. An encoder based on a Banyan network in LDPC T1 encoding according to claim 8, characterized in that: The accumulation module is implemented through a 4-stage pipeline, with each stage performing the accumulation operation on 128 bits of data.

10. An encoder based on a Banyan network in LDPC T1 encoding according to claim 9, characterized in that: The encoding state control circuit is provided with a first state machine and a second state machine. The first state machine controls the entire encoding calculation process, and the second state machine controls the input and output data streams. The first state machine sequentially goes through the following states: initialization state, waiting for data to be ready state, parity bit calculation state, waiting for encoding calculation to be completed state, and encoding completion state; the second state machine sequentially goes through the initialization state, waiting for data to be ready state, information bit output state, parity bit output state, and output completion state. After both state machines have completed initialization and are in a state of waiting for data to be ready, starting from the input of the first frame of information: In its waiting-for-data-ready state, the first state machine converts the input data from 16-bit parallel to 512-bit parallel and stores it in RAM. This state ends after all the data in the frame has been stored. Then, it jumps to the parity bit calculation state to start the parity bit calculation. This state is controlled by the encoding control counter, where the state count clock is the number of non-zero elements in the parity check matrix of the code rate. Then, it enters the waiting-for-encoding-completion state, waiting for the multi-stage encoding pipeline to complete the calculation. Finally, after passing through the encoding-completion state and the initialization state, it re-enters the waiting-for-data-ready state. The second state machine, in its waiting-for-data-ready state, delays the unconverted information bit data by a corresponding clock cycle according to different code rates and input / output bit widths; after the delay state ends, it enters the information bit output state and outputs the delayed input data; then it enters the parity bit output state and outputs the calculated parity bit; finally, after passing the output completion state and the initialization state, it re-enters the waiting-for-data-ready state. When both state machines are in the waiting-for-data-ready state, input the next frame of information.

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