Algorithm test system and method, and computer readable storage medium
By verifying the error correction algorithm on automated testing equipment, the long cycle and high cost problems caused by post-tape-out verification in existing technologies are solved, enabling fast and low-cost algorithm testing and improving verification efficiency and result reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 合肥康芯威存储技术有限公司
- Filing Date
- 2026-01-27
- Publication Date
- 2026-04-10
AI Technical Summary
Existing error correction algorithms require verification after tape-out, resulting in long verification cycles, low iteration efficiency, and high costs. Furthermore, it is difficult to perform effective verification before hardware implementation.
An algorithm testing system is provided, which uses automated testing equipment and connection fixtures to verify error correction algorithms before the chip is fabricated. The automated testing equipment provides test data, drives algorithm processing, and receives feedback data for verification. The performance of the algorithm is evaluated using verification metrics.
This enables rapid verification of the error correction algorithm before tape-out, reducing verification cycle and cost, improving iteration efficiency, and allowing verification of algorithm performance under different conditions.
Smart Images
Figure CN121833535A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip testing, and in particular to an algorithm testing system and method and a computer readable storage medium. BACKGROUND
[0002] As a key technology for improving the reliability of communication and storage systems, error correction algorithms are widely used in wireless communication, data storage, data transmission, high-speed interfaces and other fields. With the increasing requirements of application scenarios for high throughput, low error rate and high reliability, the complexity and implementation difficulty of error correction algorithms continue to increase.
[0003] The existing verification methods of error correction algorithms generally include two types: one is to implement the algorithm in hardware after completion, and then transplant it to a programmable logic platform for debugging and verification; the other is to evaluate the function and performance of the error correction algorithm in a test environment through actual chips or samples after chip tape-out. Although the above methods can achieve a certain degree of verification, they generally have the problems of long verification period and low iteration efficiency. The verification based on the programmable logic platform needs to go through the processes of hardware architecture design, interface adaptation, timing convergence and repeated debugging, which requires a large amount of research and development resources and the verification efficiency is limited; and the verification based on tape-out must wait for the completion of the sample, and once it is found that the algorithm parameters, implementation strategies or test coverage are insufficient, a high modification cost and additional cost will be paid, and even project progress risks will be brought. SUMMARY
[0004] The technical problem solved by the present application is to provide an algorithm testing system and method that can verify error correction algorithms without tape-out.
[0005] According to a first aspect, an algorithm testing system is provided in an embodiment, comprising:
[0006] An automatic test equipment, wherein the automatic test equipment stores a to-be-verified algorithm and a test program;
[0007] A connection fixture, wherein the connection fixture is electrically connected with the automatic test equipment and is used to establish electrical connection with an external chip;
[0008] The automatic test equipment executes the test program to provide test data to the to-be-verified algorithm and drive the to-be-verified algorithm to process the test data to obtain processing data output by the to-be-verified algorithm; the automatic test equipment sends the processing data to the external chip through the connection fixture and receives return data generated by the external chip based on the processing data through the connection fixture; and the automatic test equipment verifies the to-be-verified algorithm according to the return data.
[0009] In an embodiment, the automatic test equipment verifies the to-be-verified algorithm according to the backhaul data, including:
[0010] comparing the backhaul data with preset reference data to determine difference information;
[0011] calculating at least one verification index according to the difference information, and determining a verification conclusion of the to-be-verified algorithm according to the verification index.
[0012] In an embodiment, the verification index includes at least one of an error count, an error rate, and a correction success rate, wherein the error count is used to represent the number of inconsistent data units between the backhaul data and the preset reference data; the error rate is used to represent the proportion of the number of inconsistent data units to the total number of data units participating in comparison; and the correction success rate represents the proportion of the number of times that the backhaul data is consistent with the preset reference data to the total number of tests.
[0013] In an embodiment, the to-be-verified algorithm includes a correction algorithm.
[0014] In an embodiment, the correction algorithm includes at least one of a correction encoding algorithm and a low-density check code algorithm.
[0015] In an embodiment, an error correction encoder is arranged in the automatic test equipment, and the error correction encoder is used to encode according to the correction algorithm; the automatic test equipment drives the to-be-verified algorithm to process the test data when executing the test program, including:
[0016] encoding the test data by the error correction encoder to generate the processing data.
[0017] In an embodiment, the connection jig includes a connection plate electrically connected with the automatic test equipment, and a connection seat for establishing detachable electrical connection with the external chip.
[0018] In an embodiment, the connection plate and the connection seat are replaceably arranged to adapt to different external chips.
[0019] According to a second aspect, an embodiment provides an algorithm testing method, including:
[0020] executing a test program to provide test data to a to-be-verified algorithm and drive the to-be-verified algorithm to process the test data, to obtain processing data output by the to-be-verified algorithm;
[0021] sending the processing data to an external chip, and receiving backhaul data generated by the external chip based on the processing data;
[0022] verify the to-be-verified algorithm according to the backhaul data.
[0023] According to a third aspect, a computer readable storage medium is provided in an embodiment, and the medium stores a computer program which can be executed by a processor to implement the method described in the above embodiments.
[0024] According to the algorithm testing system and method, and the computer readable storage medium, the algorithm testing system comprises an automatic testing device and a connecting jig electrically connected to the automatic testing device. The automatic testing device stores a to-be-verified algorithm and a test program, and provides test data to the to-be-verified algorithm by executing the test program, drives the to-be-verified algorithm to process to obtain processing data, sends the processing data to an external chip through the connecting jig, receives backhaul data generated by the external chip, and finally verifies the to-be-verified algorithm according to the backhaul data. The present application migrates the verification of the to-be-verified algorithm to the pre-flow stage, that is, the verification can be performed on the automatic testing device, thereby reducing the long period and high cost investment caused by the traditional verification after the hardware implementation is completed and the testing after the programmable logic platform is transplanted, and the present application connects different external chips by using the connecting jig, so that the to-be-verified algorithm can be verified under different test data and different test conditions, to ensure the consistency and reliability of the test results. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 FIG. 1 is a structural schematic diagram of an algorithm testing system according to an embodiment;
[0026] Figure 2 FIG. 2 is a schematic diagram of the connection relationship between the connecting plate and the connecting seat in the algorithm testing system according to an embodiment;
[0027] Figure 3 FIG. 3 is a schematic diagram of the connection relationship between the error correction encoder and the connecting plate in the algorithm testing system according to an embodiment;
[0028] Figure 4 FIG. 4 is a method flowchart of an algorithm testing method according to an embodiment. DETAILED DESCRIPTION
[0029] The application will be described in further detail below with specific reference being made to the drawings. Like elements are referred to with like reference numerals throughout the specification. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the application. However, it will be apparent to one skilled in the art that the application can be practiced without the specific details given. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure the application. Embodiments of the application will support these various approaches, and, where appropriate, materials, elements and / or methods described can be substituted, removed and / or modified.
[0030] In addition, features, operations or steps described in the specification can be combined in any suitable manner without departing from the scope of the application. Similarly, steps in the methods described can be performed in an order different from the one described without departing from the scope of the application. Therefore, the various embodiments described in the specification should be understood to be illustrative only and not restrictive.
[0031] In this document, references will be made to parts, such as "first", "second", etc., which are only used to distinguish between the described objects, and do not have any sequential or technical meaning. In this document, "connected" or "coupled" means direct and indirect connections (couplings) unless otherwise specified.
[0032] In one embodiment, the application provides an algorithm test system 1 for fast verification and evaluation of an algorithm to be verified on an automatic test equipment 11, so as to reduce the cycle and cost caused by traditional verification on a programmable logic platform or post-fabrication verification. The following will be described in detail.
[0033] Reference is made to Figure 1 In one embodiment, the algorithm test system 1 includes an automatic test equipment 11 and a connection fixture 12.
[0034] In one embodiment, the automatic test equipment 11 is a host computer or a master, and stores an algorithm to be verified and a test program for driving the algorithm to be verified. The automatic test equipment 11 is an ATE machine, which is a special setting for automatically testing chips or electronic devices. The algorithm to be verified is an error correction algorithm, which includes at least one of an error correction coding algorithm and a low-density parity-check code algorithm. The test program is a test sequence or a test vector set running on the automatic test equipment 11, which is used to generate test data and trigger the algorithm to be verified to process the test data.
[0035] In one embodiment, the connection fixture 12 is electrically connected with the automatic test equipment 11, and the connection fixture 12 is also used to establish electrical connection with the external chip, so as to form a data transmission channel between the automatic test equipment 11 and the external chip. The connection fixture 12 can adopt a fixture structure designed for the interface form of the external chip, and is used to realize signal leading-out, contact matching and electrical connection.
[0036] Please refer to Figure 2 In one embodiment, the connection fixture 12 includes a connection plate 121 and a connection seat 122. The connection plate 121 is electrically connected with the port of the automatic test equipment 11, and the connection seat 122 is used to establish detachable electrical connection with the external chip, so as to facilitate assembly, replacement and testing of the external chip.
[0037] It should be noted that, in order to adapt to different types of external chips, the connection plate 121 and / or the connection seat 122 can be respectively provided with corresponding adaptive structures for different external chips, or multiple sets of connection plates 121 and connection seats 122 can be configured in a replaceable manner, so as to realize rapid switching test of different external chips by the same automatic test equipment 11, thereby improving the universality and expansibility of the test system.
[0038] In one embodiment, when the automatic test equipment 11 executes a test program, it first provides test data to the algorithm to be verified, and drives the algorithm to be verified to process the test data to obtain processing data output by the algorithm to be verified. The automatic test equipment 11 sends the processing data to the external chip through the connection fixture 12. After receiving the processing data, the external chip executes a preset data processing or response process based on the processing data, so as to generate return data, and returns the return data to the automatic test equipment 11 through the connection fixture 12. After receiving the return data through the connection fixture 12, the automatic test equipment 11 verifies the algorithm to be verified according to the return data.
[0039] It should be noted that the processing data is algorithm processing result data generated by the algorithm to be verified for the test data, such as encoding result, decoding result or other intermediate / output data, which is used as input for subsequent external chip testing or verification.
[0040] In an embodiment, the automatic test equipment 11 can perform verification according to a preset verification procedure when verifying the to-be-verified algorithm based on the feedback data. Specifically, after receiving the feedback data fed back by the external chip, the automatic test equipment 11 can first compare the feedback data with preset reference data to obtain difference information. The difference information is used to indicate the difference position, the number of differences, and / or the difference distribution between the feedback data and the preset reference data, for example, to identify the inconsistent data units and their corresponding index positions in the data sequence, or to count the number of differences of each data segment. Subsequently, the automatic test equipment 11 calculates at least one verification index based on the difference information, and outputs a verification conclusion according to the verification index. The verification conclusion can include a determination result of whether the to-be-verified algorithm passes the verification, as well as statistical results or report information indicating the processing effect of the algorithm, thereby realizing automatic verification and quantitative evaluation of the to-be-verified algorithm.
[0041] In an embodiment, the verification index can include, but is not limited to, at least one of the error count, the error rate, and the error correction success rate, and can also be statistically summarized for multiple tests or multiple sets of test data. The error count is used to indicate the number of inconsistent data units between the feedback data and the preset reference data; the error rate is used to indicate the proportion of the number of inconsistent data units to the total number of data units participating in comparison; and the error correction success rate is used to indicate the proportion of the number of tests in which the feedback data satisfies the consistency condition with the preset reference data to the total number of tests.
[0042] It should be noted that the automatic test equipment 11 can statistically record the verification index under different test conditions, for example, output corresponding verification indexes for different test data, different working conditions of external chips, or different noise scenes, so as to compare and evaluate the processing effect of the to-be-verified algorithm under different scenes. The automatic test equipment 11 can also perform threshold determination on the verification index based on a preset determination rule, for example, determine that the to-be-verified algorithm passes the verification when the error rate is lower than a preset threshold and / or the error correction success rate is higher than a preset threshold. When the verification index does not satisfy the threshold condition, it is determined that the to-be-verified algorithm does not pass the verification, and the corresponding difference information or statistical results are output to assist in locating the problem.
[0043] In summary, the algorithm test system 1 provided in the present application can realize the verification closed loop of the to-be-verified algorithm by using the automatic test equipment 11. Specifically, the test program drives the to-be-verified algorithm to output processing data, the processing data is sent to the external chip through the connection fixture 12, the external chip generates feedback data, and the automatic test equipment 11 completes verification based on the feedback data, thereby completing the algorithm effectiveness evaluation in a short period and reducing the verification cost.
[0044] Please refer to Figure 3In one embodiment, the automatic test equipment 11 provides test data to the algorithm under test for processing. To implement the encoding processing of the error correction algorithm, the automatic test equipment 11 is provided with an error correction encoder 111, which is configured to encode according to the error correction algorithm. When the automatic test equipment 11 executes the test program to drive the algorithm under test to process the test data, it specifically encodes the test data through the error correction encoder 111 to generate processing data corresponding to the test data. The processing data is encoded data containing information data and check data, which is output data of the subsequent verification link.
[0045] In one embodiment, after the error correction encoder 111 generates the processing data, the automatic test equipment 11 sends the processing data to the external chip through the connection fixture 12. For example, when the external chip is a storage chip or a control object related to the storage chip, the external chip can perform write, access or other response operations based on the processing data, thereby forming return data for verification. The return data generated by the external chip is returned to the automatic test equipment 11 through the connection fixture 12, which is collected by the automatic test equipment 11.
[0046] Specifically, the external chip may, in the working process, be affected by a noise scenario to introduce data errors or disturbance effects. The noise scenario includes but is not limited to data retention degradation, read interference, and programming interference, etc. By introducing a noise scenario in the external chip, an error condition of the external chip can be artificially constructed in the verification phase, so that the test environment is closer to the actual application working condition. Specifically, the automatic test equipment 11 can configure the test conditions through the test program and control the operation process of the external chip, such as setting the read-write cycle number, read-write sequence and timing parameters, etc., so as to produce the expected error or disturbance effect on the external chip. Subsequently, the automatic test equipment 11 acquires the return data of the external chip under the above noise environment, and compares and counts it with the preset reference data to evaluate the error correction capability of the error correction algorithm under different error distributions and different working conditions.
[0047] It should be noted that data retention degradation refers to the leakage of charge in the storage unit or the drift of threshold voltage distribution over time after data is written, causing the readout value to deviate from the original written value, thereby increasing the accumulation of error codes over time. Read disturbance refers to the voltage stress applied by the read operation when data is frequently read, which can disturb the adjacent cells in the same storage block that are not read, causing the threshold voltage to slowly drift. Even if the data is not reprogrammed, error codes may gradually appear, and the error code level is usually related to the number of reads. Programming disturbance refers to the effects of programming pulses and capacitive coupling when programming and writing target data, which can affect adjacent cells, causing their threshold voltages to change unexpectedly, thereby introducing error codes during the writing process. Such error codes are often related to writing frequency, adjacent data patterns, and programming order.
[0048] Please refer to Figure 4 Another embodiment provides an algorithm testing method applied in the above algorithm testing system 1, which specifically includes the following steps.
[0049] Step S110: Execute the test program to provide test data to the algorithm to be verified and drive the algorithm to be verified to process the test data to obtain processing data output by the algorithm to be verified.
[0050] Step S120: Send the processing data to the external chip and receive the feedback data generated by the external chip based on the processing data.
[0051] In one embodiment, when the automatic test equipment 11 executes the test program, it first provides test data to the algorithm to be verified and drives the algorithm to be verified to process the test data to obtain processing data output by the algorithm to be verified. The automatic test equipment 11 sends the processing data to the external chip through the connection jig 12. After receiving the processing data, the external chip executes a preset data processing or response process based on the processing data, thereby generating feedback data and feeding the feedback data back to the automatic test equipment 11 through the connection jig 12.
[0052] Step S130: Verify the algorithm to be verified according to the feedback data.
[0053] In one embodiment, the automatic test equipment 11 can perform verification according to a preset verification procedure when verifying the to-be-verified algorithm according to the feedback data. Specifically, after receiving the feedback data fed back by the external chip, the automatic test equipment 11 can first compare the feedback data with preset reference data to obtain difference information. The difference information is used to represent the difference position, difference quantity and / or difference distribution between the feedback data and the preset reference data, for example, to identify the inconsistent data units and their corresponding index positions in the data sequence, or to count the difference quantity of each data segment. Subsequently, the automatic test equipment 11 calculates at least one verification index based on the difference information, and outputs a verification conclusion according to the verification index. The verification conclusion can include a determination result of whether the to-be-verified algorithm passes the verification, and statistical results or report information representing the algorithm processing effect, thereby realizing automatic verification and quantitative evaluation of the to-be-verified algorithm.
[0054] Those skilled in the art can understand that all or part of the functions of the various methods in the above embodiments can be realized by hardware or by a computer program. When all or part of the functions in the above embodiments are realized by a computer program, the program can be stored in a computer readable storage medium, which can include read-only memory, random access memory, magnetic disk, optical disk, hard disk, etc. The above functions are realized by executing the program by a computer. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, the above functions are realized. In addition, when all or part of the functions in the above embodiments are realized by a computer program, the program can also be stored in a server, another computer, a storage medium such as a disk, an optical disk, a flash disk or a mobile hard disk, and is downloaded or copied into the memory of the local device, or the system of the local device is updated, and when the program in the memory is executed by the processor, the above functions are realized.
[0055] The above application of specific examples is used to illustrate the present application and is not intended to limit the present application. Those skilled in the art can make some simple deductions, modifications or substitutions according to the idea of the present application.
Claims
1. An algorithm test system, characterized by, The application relates to an automatic test device, a connecting jig and a method for verifying an algorithm. The automatic test device stores a to-be-verified algorithm and a test program; The connecting jig is electrically connected with the automatic test device and is used for establishing electrical connection with an external chip; The automatic test device executes the test program to provide test data for the to-be-verified algorithm and drive the to-be-verified algorithm to process the test data, so as to obtain processing data output by the to-be-verified algorithm; the automatic test device sends the processing data to the external chip through the connecting jig and receives return data generated by the external chip based on the processing data through the connecting jig; and the automatic test device verifies the to-be-verified algorithm according to the return data.
2. The algorithm test system of claim 1, wherein, The automatic test device verifies the to-be-verified algorithm according to the return data, which comprises the following steps: Comparing the return data with preset reference data to determine difference information; According to the difference information, at least one verification index is calculated, and a verification conclusion of the to-be-verified algorithm is determined according to the verification index.
3. The algorithm test system of claim 2, wherein, The verification index comprises at least one of error count, error rate and error correction success rate, wherein the error count is used for representing the number of inconsistent data units between the return data and the preset reference data; the error rate is used for representing the proportion of the number of inconsistent data units to the total number of data units participating in comparison; and the error correction success rate represents the proportion of the number of times that the return data is consistent with the preset reference data to the total number of tests.
4. The algorithm test system of claim 1, wherein, The to-be-verified algorithm comprises an error correction algorithm.
5. The algorithm test system of claim 4, wherein, The error correction algorithm comprises at least one of an error correction coding algorithm and a low-density parity-check code algorithm.
6. The algorithm test system of claim 4, wherein, An error correction encoder is arranged in the automatic test device, and the error correction encoder is used for encoding according to the error correction algorithm; The automatic test device executes the test program to drive the to-be-verified algorithm to process the test data, which comprises the following steps: The test data is encoded by the error correction encoder to generate the processing data.
7. The algorithm test system of claim 1, wherein, The connecting jig comprises a connecting plate electrically connected with the automatic test device and a connecting seat used for establishing detachable electrical connection with the external chip.
8. The algorithm test system of claim 7, wherein, The connecting plate and the connecting seat are replaceably arranged to adapt to different external chips.
9. An algorithm testing method characterized by, The application relates to an automatic test device, a connecting jig and a method for verifying an algorithm. The automatic test device stores a to-be-verified algorithm and a test program; The connecting jig is electrically connected with the automatic test device and is used for establishing electrical connection with an external chip; The automatic test device executes the test program to provide test data for the to-be-verified algorithm and drive the to-be-verified algorithm to process the test data, so as to obtain processing data output by the to-be-verified algorithm; the automatic test device sends the processing data to the external chip through the connecting jig and receives return data generated by the external chip based on the processing data through the connecting jig; and the automatic test device verifies the to-be-verified algorithm according to the return data.
10. A computer-readable storage medium, characterized in that, The automatic test device verifies the to-be-verified algorithm according to the return data, which comprises the following steps: Comparing the return data with preset reference data to determine difference information; According to the difference information, at least one verification index is calculated, and a verification conclusion of the to-be-verified algorithm is determined according to the verification index. The verification index comprises at least one of error count, error rate and error correction success rate, wherein the error count is used for representing the number of inconsistent data units between the return data and the preset reference data; the error rate is used for representing the proportion of the number of inconsistent data units to the total number of data units participating in comparison; and the error correction success rate represents the proportion of the number of times that the return data is consistent with the preset reference data to the total number of tests. The to-be-verified algorithm comprises an error correction algorithm. The error correction algorithm comprises at least one of an error correction coding algorithm and a low-density parity-check code algorithm. An error correction encoder is arranged in the automatic test device, and the error correction encoder is used for encoding according to the error correction algorithm; The automatic test device executes the test program to drive the to-be-verified algorithm to process the test data, which comprises the following steps: The test data is encoded by the error correction encoder to generate the processing data. The connecting jig comprises a connecting plate electrically connected with the automatic test device and a connecting seat used for establishing detachable electrical connection with the external chip. The connecting plate and the connecting seat are replaceably arranged to adapt to different external chips. The application relates to an automatic test device, a connecting jig and a method for verifying an algorithm. The medium stores a computer program, and the computer program can be executed by a processor to realize the method in claim 9.