In-memory computing unit, operating method thereof and in-memory computing array

Abstract

The invention relates to an in-memory computing unit, an operation method thereof and an in-memory computing array. The in-memory computing unit comprises a write transistor, a read transistor and a nonvolatile memory, a first electrode of the write transistor is connected with a grid electrode of the read transistor to form a storage node, a second electrode of the write transistor is connected to a write bit line, and the grid electrode is connected to a write word line; a first electrode of the read transistor is connected to a read word line, and a second electrode is connected with a first electrode of the nonvolatile memory; a second electrode of the non-volatile memory is connected to the read bit line. By integrating a write transistor, a read transistor, and a non-volatile memory, cell area overhead can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to an in-memory computing unit and an operation method thereof and an in-memory computing array. BACKGROUND

[0002] With the development of artificial intelligence, the Von Neumann architecture computer faces a bottleneck between data transmission and calculation, and in-memory computing can effectively reduce the power consumption and delay caused by data transfer by utilizing the characteristics of the storage unit itself to perform calculation inside the storage unit.

[0003] At present, in-memory computing units are based on a storage medium for calculation, among which in-memory computing units based on volatile memory have the advantages of high durability and fast erase and write speed, but the multi-bit storage capacity is limited, and the data needs to be refreshed continuously, resulting in high power consumption; in-memory computing units based on non-volatile memory have good multi-level storage capacity and can maintain data for a long time, but the number of erase and write times is limited, and the durability is poor.

[0004] Therefore, there is an urgent need in the art for an integrated in-memory computing unit structure that can achieve high durability, long retention time and low power consumption. SUMMARY

[0005] Therefore, it is necessary to provide an in-memory computing unit with high durability, long retention time and low power consumption, and an operation method thereof and an in-memory computing array to solve the problems in the prior art.

[0006] To achieve the above-mentioned purpose, in a first aspect, the present application provides an in-memory computing unit, comprising: a write transistor, a read transistor and a non-volatile memory.

[0007] The first electrode of the write transistor and the gate electrode of the read transistor are connected to form a storage node, the second electrode of the write transistor is connected to a write bit line, and the gate electrode is connected to a write word line.

[0008] The first electrode of the read transistor is connected to a read word line, and the second electrode is connected to the first electrode of the non-volatile memory.

[0009] The second electrode of the non-volatile memory is connected to a read bit line.

[0010] Optionally, the non-volatile memory comprises one of a resistive random access memory, a phase change memory, a ferroelectric memory or a magnetic tunnel junction memory.

[0011] Optionally, the write transistor is an oxide semiconductor channel transistor, and the read transistor is a silicon-based transistor.

[0012] Optionally, the write transistor, the read transistor and the non-volatile memory are stacked in a vertical direction; wherein the first electrode of the write transistor and the gate of the read transistor are electrically connected in the vertical direction.

[0013] Optionally, the write transistor, the storage node, the non-volatile memory and the read transistor are sequentially arranged from top to bottom.

[0014] Alternatively, the non-volatile memory, the write transistor and the read transistor are sequentially arranged from top to bottom.

[0015] Optionally, the non-volatile memory is arranged above the second electrode of the read transistor; the non-volatile memory comprises a first electrode, a functional layer and a second electrode which are sequentially stacked.

[0016] The first electrode of the non-volatile memory is connected to the second electrode of the read transistor through a first vertical interconnection structure; and the second electrode of the non-volatile memory is connected to the read bit line through a second vertical interconnection structure.

[0017] Optionally, in the vertical direction, the first electrode, the channel and the second electrode of the write transistor are sequentially arranged in a direction away from the gate of the read transistor; the gate of the write transistor surrounds the channel of the write transistor; and the first electrode of the write transistor is directly connected to the gate of the read transistor to form a storage node.

[0018] Optionally, the storage node further comprises:

[0019] a node conductor layer arranged between the gate of the read transistor and the first electrode of the write transistor in the vertical direction; the node conductor layer is electrically connected to the gate of the read transistor through a first connection layer and electrically connected to the first electrode of the write transistor through a second connection layer.

[0020] In a second aspect, the present application provides an operation method of an in-memory computing unit, wherein the in-memory computing unit is as described in the first aspect; the operation method comprises a volatile storage mode, a non-volatile storage mode and an in-memory computing mode.

[0021] In the volatile storage mode, the storage node is written through the write bit line and the write word line, and the storage node is read through the read bit line and the read word line.

[0022] In the non-volatile storage mode, the non-volatile memory is written, erased or read through the read bit line and the read word line.

[0023] In the in-memory computing mode, weight data is stored in the non-volatile memory, mask data is stored in the storage node, an output current is obtained on the read word line by applying an input voltage to the read bit line; the output current is a function of the input voltage, the weight data and the mask data, wherein when the mask data is a first logic value, the weight data participates in the calculation, and when the mask data is a second logic value, the weight data does not participate in the calculation.

[0024] Optionally, the operation of the volatile storage mode includes:

[0025] When a first logic value is written to the storage node, the write word line is set to a high level to turn on the write transistor, and the write bit line is set to the high level to charge the storage node;

[0026] When a second logic value is written to the storage node, the write word line is set to a high level to turn on the write transistor, and the write bit line is set to a low level to discharge or maintain the discharge state of the storage node;

[0027] When reading the data stored in the storage node, the write word line and the write bit line are set to an off level to turn off the write transistor, a read voltage is applied to the read bit line, and a sensing current of the read word line is read to read the data stored in the storage node.

[0028] Optionally, the non-volatile storage mode includes:

[0029] The write word line and the write bit line are set to a high level to turn on the write transistor and the read transistor;

[0030] A programming voltage is applied between the non-volatile memory and the first electrode and the second electrode through the read bit line and the read word line to write or erase data to the non-volatile memory;

[0031] A read voltage is applied between the non-volatile memory and the first electrode and the second electrode through the read bit line and the read word line, and a current of the read word line is read to read the data stored in the non-volatile memory.

[0032] Optionally, in the in-memory computing mode, when the mask data is a first logic value, the read transistor is turned on and the weight data participates in the calculation; when the mask data is a second logic value, the read transistor is turned off and the weight data does not participate in the calculation.

[0033] Optionally, the write operation of the in-memory computing mode includes:

[0034] setting the write bit line and the write word line to high level, turning on the write transistor, charging the storage node to turn on the read transistor;

[0035] writing weight data to the non-volatile memory through the read bit line and the read word line;

[0036] writing mask data to the storage node through the write word line and the write bit line;

[0037] setting the write word line, the write bit line, the read word line and the read bit line to off level to turn off the write transistor.

[0038] In a third aspect, the present application provides an in-memory computing array, comprising the in-memory computing unit of the first aspect, a plurality of common write word lines, a plurality of common read word lines, a plurality of common write bit lines and a plurality of common read bit lines; the in-memory computing units are arranged in an array along a row direction and a column direction;

[0039] The write word lines of the in-memory computing units in the same row are connected to the same common write word line, and the read bit lines are connected to the same common read bit line;

[0040] The write bit lines of the in-memory computing units in the same column are connected to the same common write bit line, and the read word lines are connected to the same common read word line.

[0041] Optionally, the in-memory computing array is configured to perform:

[0042] applying a write signal to at least one of the common write word lines and at least one of the common write bit lines to write mask data into the storage nodes of at least one row of the in-memory computing units; at the same time, applying an input voltage vector to a plurality of the common read bit lines;

[0043] reading the output current of each of the common read word lines, wherein the output current value on each of the common read word lines is the product of the weight data stored by the non-volatile memory in the in-memory computing unit in the corresponding column, which is gated by the mask data of the corresponding storage node, and the input voltage component applied to the corresponding column, and is accumulated;

[0044] The output currents of all the common read word lines are collectively used as an output current, and the output current vector is the product of the mask data matrix of the storage nodes corresponding to the in-memory computing array and the weight data matrix stored by the in-memory computing array, and the product of the input voltage vector.

[0045] The in-memory computing unit and the operation method thereof, and the in-memory computing array of the present application can reduce the unit area overhead by integrating a write transistor, a read transistor and a non-volatile memory, the first electrode of the write transistor is connected with the gate electrode of the read transistor to jointly form a storage node, the storage node is connected with a write word line and a write bit line through the write transistor, and is connected with a read word line and a read bit line through the read transistor, thereby forming a high-durability volatile memory, the storage node can be used as a volatile memory to temporarily store dynamic data, or can be used as a controller to control the opening and closing of the read transistor by controlling the potential of the storage node, so that the storage and computing functions are realized through the in-memory computing unit; the non-volatile memory has the characteristics of long data retention time, and can stably store weight data, the combination of the non-volatile memory and the storage node enables the in-memory computing unit to support in-memory computing based on Kirchhoff's law, and high-efficiency in-memory computing can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0047] Figure 1 The circuit structure diagram of the in-memory computing unit provided in an embodiment is shown in FIG. 1.

[0048] Figure 2 The structural schematic diagram of the in-memory computing unit provided in an embodiment is shown in FIG. 2.

[0049] Figure 3 The structural schematic diagram of the in-memory computing unit provided in another embodiment is shown in FIG. 3.

[0050] Figure 4 The structural schematic diagram of the in-memory computing unit provided in another embodiment is shown in FIG. 4.

[0051] Figure 5 The operation waveform diagram of the in-memory computing unit in a volatile storage mode provided in an embodiment is shown in FIG. 5.

[0052] Figure 6 The operation waveform diagram of the in-memory computing unit in a non-volatile storage mode provided in an embodiment is shown in FIG. 6.

[0053] Figure 7 The circuit schematic diagram of the in-memory computing unit in an in-memory computing mode provided in an embodiment is shown in FIG. 7.

[0054] Figure 8 The operation waveform diagram of the in-memory computing unit in an in-memory computing mode provided in an embodiment is shown in FIG. 8.

[0055] Figure 9 A schematic diagram of storing data in a volatile storage mode for an in-memory computing unit in an embodiment;

[0056] Figure 10 A schematic diagram of storing data in a non-volatile storage mode for an in-memory computing unit in an embodiment;

[0057] Figure 11 A schematic diagram of storing data in an in-memory computing mode for an in-memory computing unit in an embodiment;

[0058] Figure 12 A circuit structure diagram of an in-memory computing array provided in an embodiment.

[0059] BRIEF DESCRIPTION OF DRAWINGS

[0060] WT, write transistor; RT, read transistor; NVM, non-volatile memory; SN, storage node; WWL, write word line; WBL, write bit line; RWL, read word line; RBL, read bit line; X, row direction; Y, column direction; Z, vertical direction

[0061] 100, in-memory computing unit; 10, substrate; 11, first electrode of write transistor; 12, second electrode of write transistor; 13, gate of write transistor; 14, first gate dielectric layer; 15, channel layer of write transistor; 21, first electrode of read transistor; 22, second electrode of read transistor; 23, gate of read transistor; 24, second gate dielectric layer; 31, first electrode; 32, second electrode; 33, functional layer; 331, resistive layer; 332, phase change layer; 41, first vertical interconnect structure; 42, second vertical interconnect structure; 43, third vertical interconnect structure; 50, node conductor layer; 51, first connection layer; 52, second connection layer; 60, insulating dielectric layer. DETAILED DESCRIPTION

[0062] For the purpose of promoting an understanding of the application, the application will now be described in greater detail with reference to the figures. The preferred embodiments of the application are illustrated in the figures. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0064] According to an exemplary embodiment, the application provides an in-memory computing unit 100, with reference to Figure 1、 Figure 2 、 Figure 3 、 Figure 4 As shown in FIG. 1, the in-memory computing unit 100 comprises a write transistor WT, a read transistor RT and a non-volatile memory NVM.

[0065] The first electrode 11 of the write transistor WT is connected with the gate 23 of the read transistor RT, and together forms a storage node SN. The second electrode 12 of the write transistor WT is connected to a write bit line WBL. The gate 13 of the write transistor WT is connected to a write word line WWL. The write transistor WT and the read transistor RT form a 2T0C (two-transistor-capacitor-less) volatile dynamic random memory. Data is stored in the form of potential in the storage node SN. The storage capacitor is removed, which reduces the unit area, is conducive to high-density integration, and simplifies the manufacturing process. The 2T0C volatile dynamic random memory can be used to store dynamic data (such as mask data) that needs to be frequently written and erased in the computing process. The data is stored in the node capacitor of the storage node SN, and is controlled by the switching of the write transistor WT and the read transistor RT. The 2T0C volatile dynamic random memory has high read-write durability.

[0066] The first electrode 21 of the read transistor RT is connected to a read word line RWL. The second electrode 22 of the read transistor RT is connected with the first electrode 31 of the non-volatile memory NVM RBL. The second electrode 32 of the non-volatile memory NVM is connected to a read bit line RBL. The second electrode 32 of the non-volatile memory NVM is a top electrode. The non-volatile memory NVM stores information through resistance value. The resistance state represents the data stored in the non-volatile memory NVM.

[0067] The first electrode 11 of the write transistor WT can be one of the source or the drain, and the second electrode can be the other of the drain or the source. The first electrode 21 of the read transistor RT can be one of the source or the drain, and the second electrode can be the other of the drain or the source.

[0068] For example, the source of the write transistor WT is connected with the gate 23 of the read transistor RT, and together forms a storage node SN. The drain of the write transistor WT is connected to a write bit line WBL. The source of the read transistor RT is connected to a read word line RWL. The drain of the read transistor RT is connected with the bottom electrode of the non-volatile memory NVM RBL. The top electrode is connected to a read bit line RBL.

[0069] The in-memory computing unit 100 can reduce the unit area overhead by integrating the write transistor WT, the read transistor RT, and the non-volatile memory NVM. The first electrode 11 of the write transistor WT is connected with the gate 23 of the read transistor RT to form a storage node SN. The storage node SN is connected with the write word line WWL and the write bit line WBL through the write transistor WT, and is connected with the read word line RWL and the read bit line RBL through the read transistor RT, thereby forming a high-durability volatile memory. The storage node SN can be used as a volatile memory to temporarily store dynamic data, or can be used as a controller to control the opening and closing of the read transistor RT by controlling the potential of the storage node SN, thereby realizing the storage and computing functions of the in-memory computing unit 100. The non-volatile memory NVM has the characteristics of long data retention time and can stably store weight data. The combination of the non-volatile memory NVM and the storage node SN enables the in-memory computing unit 100 to support in-memory computing based on Kirchhoff's law, thereby realizing efficient in-memory computing.

[0070] In some embodiments, as shown in Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 The non-volatile memory NVM includes one of resistive random access memory (RRAM), phase change memory (PCM), ferroelectric memory (FeRAM), or magnetic tunnel junction random access memory (MRAM). The non-volatile memory NVM has non-volatility and long data retention time, and is suitable for storing weight data. The non-volatile memory NVM also has multi-level storage capability and can realize multi-bit storage.

[0071] The resistive random access memory has simple structure, fast operation speed, and good compatibility with complementary metal oxide semiconductor (CMOS) process.

[0072] The phase change memory has good linearity and consistency of resistance value, which is beneficial to improve the computing accuracy.

[0073] The ferroelectric memory or the magnetic tunnel junction memory respectively stores data by using ferroelectric domain polarization or electron spin direction, and has very high read-write durability.

[0074] The resistance state of the non-volatile memory NVM is used to directly represent the weight value, so that the in-memory computing unit 100 can complete in-memory computing based on Kirchhoff's law.

[0075] In some embodiments, as shown in Figure 1 , Figure 2 , Figure 3 , Figure 4 , the write transistor WT is an oxide semiconductor channel transistor, which has low leakage characteristics, can extend the data retention time of the 2T0C volatile dynamic random memory, has low refresh frequency and power consumption, and has low process thermal budget, so that it can be integrated into the back-end three-dimensional heterogeneous integration, thereby reducing the unit area overhead.

[0076] For example, the write transistor WT uses indium gallium zinc oxide (IGZO) as the channel material, such as indium oxide (In2O3), zinc oxide (ZnO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), and indium tin oxide (ITO).

[0077] In some embodiments, as shown in Figure 1 , Figure 2 , Figure 3 , Figure 4 , the read transistor RT is a silicon-based transistor, which has large driving current, stable threshold and performance, and can provide current for operating the non-volatile memory NVM, while increasing the read speed.

[0078] In some embodiments, as shown in Figure 2 , Figure 3 , Figure 4 , the write transistor WT, the read transistor RT, and the non-volatile memory NVM are stacked in the vertical direction Z; wherein the first electrode 11 of the write transistor WT and the gate electrode 23 of the read transistor RT are electrically connected in the vertical direction Z, and the connection point constitutes the storage node SN.

[0079] In this embodiment, the write transistor WT, the read transistor RT, and the non-volatile memory NVM are stacked in the vertical direction Z by three-dimensional heterogeneous integration process, which reduces the occupied area of the in-memory computing unit 100 and is beneficial to improve the integration density.

[0080] In some embodiments, the write transistor WT, the storage node SN, the read transistor RT, and the non-volatile memory NVM are sequentially arranged from top to bottom, and the write transistor WT is located at the topmost layer; or, as shown in Figure 1 , Figure 2 , Figure 3 , Figure 4 , the non-volatile memory NVM, the write transistor WT, and the read transistor RT are sequentially arranged from top to bottom, and the non-volatile memory NVM is located at the topmost layer.

[0081] In some embodiments, as shown inFigure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the non-volatile memory (NVM) is located above the second electrode 22 of the read transistor RT; the non-volatile memory (NVM) includes a first electrode 31, a functional layer 33, and a second electrode 32 stacked in sequence.

[0082] The first electrode 31 of the non-volatile memory NVM is connected to the second electrode 22 of the read transistor RT through the first vertical interconnect structure 41, establishing an access path for the read transistor RT to the non-volatile memory NVM; the second electrode 32 of the non-volatile memory NVM is connected to the read bit line RBL through the second vertical interconnect structure 42, forming a current output path during calculation.

[0083] In one example, refer to Figure 2 , Figure 3 As shown, the non-volatile memory (NVM) is a resistive switching memory. The non-volatile memory (NVM) includes a first electrode 31, a resistive switching layer, and a second electrode 32 stacked sequentially along the vertical direction Z. The functional layer 33 includes a single-layer resistive switching layer.

[0084] In another example, refer to Figure 4 As shown, the non-volatile memory (NVM) is a phase-change memory. The volatile memory (NVM) includes a first electrode 31, a resistive layer 331, a phase-change layer 332, and a second electrode 32, which are stacked sequentially along the vertical direction Z. The functional layer 33 includes the stacked resistive layer 331 and the phase-change layer 332.

[0085] In this embodiment, by directly stacking the non-volatile memory NVM above the second electrode 22 of the read transistor RT and connecting it using the first vertical interconnect structure 41, the planar area occupied by the in-memory computing unit 100 is minimized. At the same time, the non-volatile memory NVM is vertically interconnected with the read transistor RT and the read bit line RBL respectively, resulting in a short transmission distance, which helps to reduce interconnect parasitic capacitance and improve read / write speed and computing energy efficiency.

[0086] In some embodiments, refer to Figure 2 As shown, the write transistor WT is a vertical channel gate-around transistor; in the vertical direction Z, the first electrode 11, the channel (not labeled in this embodiment), and the second electrode 12 of the write transistor WT are arranged sequentially along the direction away from the gate 23 of the read transistor RT; wherein, the gate 13 of the write transistor WT surrounds the channel of the write transistor WT; the first electrode 11 of the write transistor WT is directly connected to the gate 23 of the read transistor RT to form a storage node SN.

[0087] like Figure 2As shown, the in-memory computing unit 100 of this embodiment includes a substrate 10. For example, the substrate 10 can be a silicon substrate. The source (first electrode 21) and drain (second electrode 22) of the read transistor RT are formed in the substrate 10 at intervals. The gate 23 of the read transistor RT is disposed on the substrate 10 and located between the source and drain of the read transistor RT. The gate 23 of the read transistor RT is separated from the substrate 10 by a second gate dielectric layer 24.

[0088] like Figure 2 As shown, a read word line RWL is disposed above the source of the read transistor RT and electrically connected to it. The read word line RWL extends along the row direction X parallel to the substrate 10. In this embodiment, the source of the read transistor RT is electrically connected to the read word line RWL through a third vertical interconnect structure 43.

[0089] like Figure 2 As shown, the non-volatile memory (NVM) is disposed above the drain (second electrode 22) of the read transistor RT. The NVM includes a first electrode 31, a functional layer 33, and a second electrode 32 stacked perpendicularly to the substrate 10. The first electrode 31 of the NVM is connected to the drain of the read transistor RT through a first vertical interconnect structure 41. The second electrode 32 of the NVM is connected to the read bit line RBL through a second vertical interconnect structure 42. The read bit line RBL is located above the second electrode 32 and extends along the column direction Y parallel to the substrate 10.

[0090] A semiconductor layer (not highlighted in red) is provided on the gate 23 of the read transistor RT. The semiconductor layer extends in the vertical direction Z and is in contact with the gate 23 of the read transistor RT. The source, channel, and drain of the write transistor WT are sequentially disposed in the semiconductor layer in a direction perpendicular to the substrate 10. The gate 13 of the write transistor WT surrounds the channel of the write transistor WT, and a first gate dielectric layer 14 is disposed between the gate 13 and the channel of the write transistor WT. The gate 13 of the write transistor WT is connected to the write word line WWL, which extends in the column direction Y parallel to the substrate 10. The write bit line WBL is disposed above the semiconductor layer and extends in the row direction X parallel to the substrate 10. The drain of the write transistor is in contact with the write bit line WBL.

[0091] In some embodiments, such as Figure 3 , Figure 4As shown, the storage node SN also includes a node conductor layer 50. Along the vertical direction Z, the node conductor layer 50 is disposed between the gate 23 of the read transistor RT and the first electrode 11 of the write transistor WT. The node conductor layer 50 is electrically connected to the gate 23 of the read transistor RT through a first connection layer 51 and to the first electrode 11 of the write transistor WT through a second connection layer 52. In this embodiment, the write transistor WT is an oxide channel thin-film transistor disposed above the second connection layer 52.

[0092] In this embodiment, the read transistor RT and the non-volatile memory NVM are configured the same as in the above embodiment, and will not be described again in this embodiment.

[0093] like Figure 3 , Figure 4 As shown, along a direction perpendicular to the substrate 10, a write transistor WT is disposed above the read transistor RT. The channel layer 15 of the write transistor WT is disposed on the gate 13. Along a direction parallel to the substrate 10, the source (first electrode 11) and drain (second electrode 12) of the write transistor WT are formed on both sides of the gate 13. The source and drain of the write transistor WT can extend to the channel layer 15 and make ohmic contact with the two ends of the channel layer 15, respectively. A second gate dielectric layer 24 is disposed between the gate 13 of the write transistor WT and the channel layer 15, the source, and the drain. The gate 13 of the write transistor WT is connected to the write word line WWL, which extends along the row direction X parallel to the substrate 10. The source of the write transistor WT is in contact with the second connection layer 52, realizing an electrical connection with the memory node SN. Its drain is connected to the write bit line WBL, which extends along the row direction X parallel to the substrate 10.

[0094] For example, the materials of the first vertical interconnect structure 41, the second vertical interconnect structure 42, the third vertical interconnect structure 43, the read word line RWL, the read bit line RBL, the write word line WWL, and the write bit line WBL are conductor materials, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), aluminum nitride (AlN), tungsten nitride (WN), copper (Cu), platinum (Pt), molybdenum (Mo), nickel (Ni), indium tin oxide (ITO), heavily doped polycrystalline silicon, etc.

[0095] For example, the source and drain of the read transistor RT are composed of one or more elements doped into the substrate 10. The doping elements can be selected from nitrogen (N), phosphorus (P), arsenic (As), boron (B), gallium (Ga), indium (In), etc.

[0096] For example, the channel layer 15 of the write transistor WT is composed of a single layer or multiple layers of composite oxide semiconductor material thin film, such as indium oxide (In2O3), zinc oxide (ZnO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), indium tin oxide (ITO), etc.

[0097] For example, the second gate dielectric layer 24 and the first gate dielectric layer 14 are composed of a single layer or multiple layers of composite material thin film, such as silicon oxide (SiOx), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), zirconium oxide (ZrOx), etc.

[0098] For example, the node conductor layer 50, the first connection layer 51, and the second connection layer 52 are made of a conductive material, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), aluminum nitride (AlN), tungsten nitride (WN), copper (Cu), platinum (Pt), molybdenum (Mo), nickel (Ni), indium tin oxide (ITO), heavily doped polysilicon, etc.

[0099] For example, the thickness of the channel layer 15 of the write transistor WT can be 5 nm-1000 nm; the thickness of the second gate dielectric layer 24 can be 5 nm-1000 nm; the thickness of the first gate dielectric layer 14 can be 5 nm-1000 nm; the thickness of the first electrode 31 of the non-volatile memory NVM can be 5 nm-1000 nm; the thickness of the functional layer 33 can be 5 nm-1000 nm; and the thickness of the second electrode 32 can be 5 nm-1000 nm.

[0100] In some embodiments, an insulating dielectric layer 60 is filled between the write transistor WT, the read transistor RT, and the non-volatile memory NVM, which is used for insulation between devices to avoid short circuiting of the devices.

[0101] According to an exemplary embodiment, the present embodiment provides an operating method of an in-memory computing unit 100, which is as described in the above embodiments; the operating method includes a volatile storage mode, a non-volatile storage mode, and an in-memory computing mode.

[0102] In the volatile storage mode, the storage node SN is written by the write bit line WBL and the write word line WWL, and the storage node SN is read by the read bit line RBL and the read word line RWL.

[0103] That is, in the volatile storage mode, the in-memory computing unit 100 is regarded as an independent 2T0C volatile dynamic random access memory (DRAM) for operation, and data is stored in the storage node SN; in this mode, no operation is performed on the non-volatile memory NVM.

[0104] AsFigure 9 As shown, in volatile memory mode, data is only stored at the storage node SN, and any data stored in the non-volatile memory NVM does not affect the overall stored data of the cell. Taking the non-volatile memory NVM as an example of resistive random access memory (RRAM), the storage node SN stores the data "1", regardless of whether the resistive random access memory RRAM is written to the high-conductivity state G. high Medium conductivity state G middle or low conductivity state G low The stored data read by the in-memory computing unit 100 is all "1". Similarly, when the stored data of the storage node SN is "0", the stored data read by the in-memory computing unit 100 is all "0".

[0105] In non-volatile memory mode, write, erase, or read operations are performed on the non-volatile memory NVM through the read bit line RBL and the read word line RWL.

[0106] In other words, in non-volatile memory mode, the in-memory computing unit 100 is operated as a non-volatile memory. Data storage is entirely handled by the non-volatile memory NVM. The write transistor WT and read transistor RT only serve to establish access paths in this mode, and the memory node SN is not used to store valid data. The non-volatile memory NVM has multiple levels of resistance states. In this mode, a single in-memory computing unit 100 can store multiple bits (e.g., 2-bit, 4-bit) of data, thereby increasing storage density.

[0107] like Figure 10 As shown, in non-volatile memory mode, the storage node SN needs to be kept high. At this time, the total stored data of the in-memory computing unit 100 is the data stored in the non-volatile memory NVM. Taking resistive random access memory (RRAM) as an example, the RRAM is written to a high-conductivity state G. high At that time, the data stored in the in-memory computing unit 100 is G, represented by the resistive random access memory (RRAM). high State data, resistive random access memory (RRAM) write in conductance state G middle At that time, the data stored in the in-memory computing unit 100 is G, represented by the resistive random access memory (RRAM). middle State data, resistive random access memory (RRAM) write in conductance state G low At that time, the data stored in the in-memory computing unit 100 is G, represented by the resistive random access memory (RRAM). low Status data.

[0108] In the in-memory computing mode, the weight data is stored in the non-volatile memory NVM, the mask data is stored in the storage node SN, and the output current is obtained on the read word line RWL by applying an input voltage to the read bit line RBL; the output current is a function of the input voltage, the weight data and the mask data, wherein when the mask data is a first logic value, the weight data participates in the calculation, and when the mask data is a second logic value, the weight data does not participate in the calculation. In the in-memory computing mode, the in-memory computing unit 100 as a whole operates, and the internal components cooperatively complete the computing task.

[0109] As shown in Figure 11 In the in-memory computing mode, when the storage node SN stores data as "0", the in-memory computing unit 100 as a whole stores data as "0"; when the storage node SN stores data as "1", the in-memory computing unit 100 as a whole stores data as the data stored in the non-volatile memory NVM, such as the state data represented by the resistive random access memory RRAM.

[0110] The operation method of the above-mentioned in-memory computing unit 100, the 2T0C volatile memory composed of the write transistor WT and the read transistor RT of the in-memory computing unit 100 is heterogeneously integrated with the non-volatile memory NVM, and the long data retention time and multi-value storage capability of the non-volatile memory NVM are utilized to complete complex mask operators in one in-memory computing unit 100 without increasing the unit area; the operation method configures the in-memory computing unit 100 to have three different functions through three operation modes, stores the data that needs to be frequently modified in the computing process in the storage node SN with high durability, and stores the data that does not need to be frequently modified in the non-volatile memory NVM with long retention time and multi-value storage capability, optimizes the data storage strategy, improves the overall durability of the in-memory computing unit 100, and fully utilizes the multi-bit capability and persistence advantage of the non-volatile storage; in the in-memory computing mode, the in-memory computing is realized in the in-memory computing unit 100 through the dynamic control function of the volatile storage node SN and the weight storage and computing function of the non-volatile memory NVM, the power consumption and computing overhead are reduced, and the operation flexibility is high.

[0111] In some embodiments, the operation of the volatile storage mode includes a write operation and a read operation.

[0112] Write operation: by cooperatively controlling the voltages of the write word line WWL and the write bit line WBL, the storage node SN is charged or discharged, so that the data is stored in the storage node SN in the form of potential.

[0113] Further, referring to Figure 5When writing the first logic value (e.g. "1") to the storage node SN, the write word line WWL is set to high level to turn on the write transistor WT, and the write bit line WBL is set to high level to charge the storage node SN through the turned-on write transistor WT, so that the potential of the storage node SN is raised to the level of the first logic value (e.g. "1").

[0114] Then, referring to Figure 5 , the write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL are set to low level to turn off the write transistor WT, so that the data is stored in the storage node SN, and at this time the storage node SN stores the first logic value (e.g. "1").

[0115] Referring to Figure 5 , when writing the second logic value (e.g. "0") to the storage node SN, the write word line WWL is set to high level to turn on the write transistor WT, and the write bit line WBL is set to low level to discharge the storage node SN or maintain the discharge state of the storage node SN through the turned-on write transistor WT, so that the potential of the storage node SN is lowered to the level of the second logic value (e.g. "0").

[0116] Then, the write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL are set to low level to turn off the write transistor WT, so that the data is stored in the storage node SN, and at this time the storage node SN stores the second logic value (e.g. "0").

[0117] Reading operation: the data stored in the storage node SN is read by controlling the read word line RWL and the read bit line RBL to sense the channel current of the read transistor RT controlled by the potential state of the storage node SN.

[0118] Further, referring to Figure 5 , when reading the data stored in the storage node SN, the write word line WWL and the write bit line WBL are set to off level to turn off the write transistor WT, a read voltage V read is applied to the read bit line RBL, and the sensing current of the read word line RWL is read to read the data stored in the storage node SN.

[0119] In this embodiment, the data stored in the storage node SN is determined according to the size of the sensing current of the word line RWL. When the storage node SN stores the first logic value, the read transistor RT is turned on, and the sensing current is large (the sensing current is higher than the reference current I ref ); when the storage node SN stores the second logic value, the read transistor RT is turned off, and the sensing current is very small or zero (the sensing current is lower than the reference current I ref ).

[0120] The operation method of the embodiment realizes reliable writing and reading of data of the storage node SN by time sequence control of the voltage in the volatile storage mode, and uses the ultra-low off-state leakage current of the write transistor WT to enable the charge on the storage node SN to be maintained for a long time, thereby greatly reducing the refresh frequency and power consumption.

[0121] In some embodiments, the operation of the non-volatile storage mode includes writing, erasing and reading operations on the non-volatile memory NVM. The following takes the resistive random access memory as an example for specific description, and the operation time sequence of the non-volatile storage mode can refer to the diagram shown in Figure 6 .

[0122] The write word line WWL and the write bit line WBL are set to high level, the write transistor WT is turned on, and the read transistor RT is turned on.

[0123] The programming voltage is applied between the non-volatile memory NVM and the first electrode 31 and the second electrode 32 through the read bit line RBL and the read word line RWL to write or erase data in the non-volatile memory NVM. When reading data, the reading voltage is applied between the non-volatile memory NVM and the first electrode 31 and the second electrode 32 through the read bit line RBL and the read word line RWL, and the current of the read word line RWL is read to read the data stored in the non-volatile memory NVM.

[0124] When writing data "w", the write word line WWL and the write bit line WBL are set to high level, the write transistor WT is turned on, and the read transistor RT is turned on, the read word line RWL is set to low level (such as 0V or negative potential), and the write voltage V set is applied at the end of the read bit line RBL to form a sufficient voltage difference across the non-volatile memory NVM, so that it is converted from the high resistance state to the low resistance state, and the writing of the data "w" is completed.

[0125] When erasing data, the write word line WWL and the write bit line WBL are set to high level, the write transistor WT is turned on, and the read transistor RT is turned on, the read bit line RBL is set to low level (such as 0V), and the erase voltage V reset is applied at the end of the read word line RWL to form a reverse voltage difference across the non-volatile memory NVM, so that it is restored from the low resistance state to the high resistance state, and the erasing operation is completed.

[0126] When reading data, the write word line WWL and the write bit line WBL are set to high level, the write transistor WT is turned on, and the read transistor RT is turned on, the read word line RWL is set to low level (such as 0V), and the reading voltage V read is applied at the end of the read bit line RBL, and the reading current I read at the end of the read word line RWL is sensed to obtain the data stored in the non-volatile memory NVM after analog-digital conversion to digital signal.

[0127] The operation method of the embodiment realizes the operation of the non-volatile memory NVM by controlling the voltage timing and using the gating of the write transistor WT and the read transistor RT in the in-memory computing unit 100, and has high stability and consistency when programming and reading the non-volatile memory NVM.

[0128] In some embodiments, the write operation of the in-memory computing mode includes:

[0129] The write bit line WBL and the write word line WWL are set to high level, the write transistor WT is turned on, the storage node SN is charged to turn on the read transistor RT;

[0130] The weight data "w" is written to the non-volatile memory NVM through the read bit line RBL and the read word line RWL. The way of writing the weight data "w" to the non-volatile memory NVM refers to the write operation of the volatile storage mode, which will not be repeated here.

[0131] The mask data "m" is written to the storage node SN through the write word line WWL and the write bit line WBL. The way of writing the mask data "m" to the storage node SN refers to the write operation of the non-volatile storage mode, which will not be repeated here.

[0132] The write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL are set to off level to turn off the write transistor WT.

[0133] The write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL are set to off level to turn off the write transistor WT, so that the unit enters a data retention state.

[0134] The computing operation of the in-memory computing mode includes: setting the write word line WWL, the write bit line WBL and the read word line RWL to off level, and applying an input voltage V in to the read bit line RBL to obtain an output current I out on the read word line RWL; the output current I out is the calculation result.

[0135] In the in-memory computing mode, when the mask data is a first logic value (such as "1"), the read transistor RT is turned on and the weight data participates in the calculation; when the mask data is a second logic value (such as "0"), the read transistor RT is turned off and the weight data does not participate in the calculation.

[0136] It can be understood that the application controls the opening and closing of the read transistor RT by controlling the potential of the storage node SN, realizes the mask operation between the mask data "m" stored in the storage node SN and the weight data "w" stored in the non-volatile memory NVM, m⊙w: refer to Figure 7As shown in part a, when m is "1", the read transistor RT is turned on, and the weight data "w" stored in the non-volatile memory NVM can be read out and participate in the in-memory computing; refer to Figure 7 As shown in part b, when m is "0", the read transistor RT is turned off, and the weight data "w" stored in the RRAM cannot be read out and participate in the in-memory computing. The result of the mask operation m⊙w is compared with the input voltage V in The in-memory computing result I is obtained at the read word line RWL end through the multiplication operation by the Kirchhoff's law out = V in × (m⊙w).

[0137] Hereinafter, taking the non-volatile memory NVM as a resistive random access memory (RRAM) for example, taking the RRAM writing a low resistance state (i.e. a high conductance G high ) and the storage node SN writing data mask data "0" for example, the voltage waveforms of the write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL, and the current waveform at the read word line RWL end are shown in Figure 8

[0138] After the weight data "w" is written into the non-volatile memory NVM, the write word line WWL and the write bit line WBL are kept at high level, and the current of the non-volatile memory NVM is read through the read bit line RBL to confirm that the non-volatile memory NVM is successfully written into the low resistance state.

[0139] Then, the write word line WWL is kept at high level to turn on the write transistor WT, and the write bit line WBL is set to low level to discharge the storage node SN to write data "0". After the writing is completed, the write word line WWL is pulled low to turn off the write transistor WT; subsequently, the read voltage is applied to the read bit line RBL to read the unit data, and the read result is I out = V in × (0⊙G high ) = 0, which proves that the operation mode can successfully realize data writing and accurately perform the in-memory computing function.

[0140] According to an exemplary embodiment, the present embodiment provides an in-memory computing array, as shown in Figure 12 ​As shown, the in-memory computing array includes in-memory computing units 100, a plurality of common write word lines C-WWL, a plurality of common read word lines C-RWL, a plurality of common write bit lines C-WBL, and a plurality of common read bit lines C-RBL; the in-memory computing units 100 are arranged in an array along the row direction X and the column direction Y, which can be understood as that the in-memory computing units 100 are arranged in a regular array of M x N along the row direction X and the column direction Y, and M and N are both positive numbers greater than 1; the write word lines WWL of the in-memory computing units 100 in the same row are connected to the same common write word line C-WWL, and the read bit lines RBL are connected to the same common read bit line C-RBL. The write bit lines WBL of the in-memory computing units 100 in the same column are connected to the same common write bit line C-WBL, and the read word lines RWL are connected to the same common read word line C-RWL.

[0141] In some embodiments, the in-memory computing array is configured to perform:

[0142] applying a write signal to at least one common write word line C-WWL and at least one common write bit line C-WBL to write mask data into the storage nodes SN of at least one row of in-memory computing units 100; at the same time, applying an input voltage vector to the plurality of common read bit lines C-RBL.

[0143] reading the output current of each common read word line C-RWL, wherein the output current value on each common read word line C-RWL is the product of the weight data stored in the non-volatile memory NVM of the in-memory computing unit 100 in the corresponding column, which is gated by the mask data of the corresponding storage node SN, and the input voltage component applied to the corresponding column.

[0144] The output currents of all common read word lines C-RWL together serve as an output current, and the output current vector is the product of the mask data matrix of the storage nodes SN corresponding to the in-memory computing array and the weight data matrix stored in the in-memory computing array 100 after bit-by-bit multiplication, and the input voltage vector.

[0145] The in-memory computing array of the embodiment interconnects a plurality of in-memory computing units 100 into an array to construct a highly parallel in-memory computing array, which can complete the entire vector-matrix multiplication operation at one time, the calculation speed is not affected by the size of the matrix, and the calculation throughput is greatly improved; at the same time, since the calculation is completely completed in parallel in the analog domain through the physical law (Kirchhoff's current law), the energy consumption bottleneck of data transfer in the traditional architecture is completely eliminated, and a high energy efficiency ratio is achieved, which provides an ideal hardware acceleration scheme for data-intensive applications such as artificial intelligence reasoning.

[0146] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as there is no conflict, any combination of the technical features should be considered within the scope of the present disclosure.

[0147] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An in-memory computing unit, characterized in that, include: Write transistors, read transistors, and non-volatile memory; The first terminal of the write transistor is connected to the gate of the read transistor to form a memory node. The second terminal of the write transistor is connected to the write bit line, and the gate is connected to the write word line. The first electrode of the read transistor is connected to the read word line, and the second electrode is connected to the first electrode of the non-volatile memory. The second electrode of the non-volatile memory is connected to the read line.

2. The in-memory computing unit according to claim 1, characterized in that, The non-volatile memory includes one of resistive switching memory, phase change memory, ferroelectric memory, or magnetic tunnel junction memory.

3. The in-memory computing unit according to claim 1, characterized in that, The write transistor is an oxide semiconductor channel transistor; the read transistor is a silicon-based transistor.

4. The in-memory computing unit according to claim 1, characterized in that, The write transistor, the read transistor, and the non-volatile memory are stacked in a vertical direction; wherein the first terminal of the write transistor and the gate of the read transistor are electrically connected in a vertical direction.

5. The in-memory computing unit according to claim 4, characterized in that, The write transistor, the storage node, the non-volatile memory, and the read transistor are arranged sequentially from top to bottom; Alternatively, the non-volatile memory, the write transistor, and the read transistor may be arranged sequentially from top to bottom.

6. The in-memory computing unit according to claim 1, characterized in that, The non-volatile memory is disposed above the second electrode of the read transistor; the non-volatile memory includes a first electrode, a functional layer, and a second electrode stacked in sequence; The first electrode of the non-volatile memory is connected to the second electrode of the read transistor through a first vertical interconnect structure; the second electrode of the non-volatile memory is connected to the read bit line through a second vertical interconnect structure.

7. The in-memory computing unit according to any one of claims 1, 4, or 5, characterized in that, In the vertical direction, the first electrode, channel, and second electrode of the write transistor are arranged sequentially in a direction away from the gate of the read transistor; the gate of the write transistor surrounds the channel of the write transistor; the first electrode of the write transistor is directly connected to the gate of the read transistor to form a memory node.

8. The in-memory computing unit according to any one of claims 1, 4, or 5, characterized in that, The storage node also includes: A node conductor layer is disposed vertically between the gate of the read transistor and the first electrode of the write transistor; the node conductor layer is electrically connected to the gate of the read transistor through a first connection layer and electrically connected to the first electrode of the write transistor through a second connection layer.

9. A method for operating an in-memory computing unit, characterized in that, The in-memory computing unit is as described in any one of claims 1-8; the operation method includes volatile storage mode, non-volatile storage mode, and in-memory computing mode; In the volatile storage mode, the storage node is written to using the write bit line and the write word line, and the storage node is read from using the read word line and the read bit line. In the non-volatile memory mode, write, erase, or read operations are performed on the non-volatile memory through the read bit line and the read word line; In the in-memory computing mode, weight data is stored in the non-volatile memory, mask data is stored in the memory node, and output current is obtained on the read word line by applying an input voltage to the read bit line. The output current is a function of the input voltage, the weight data, and the mask data. When the mask data is a first logic value, the weight data participates in the calculation; when the mask data is a second logic value, the weight data does not participate in the calculation.

10. The method of operating the in-memory computing unit according to claim 9, characterized in that, The operation of the volatile storage mode includes: When writing a first logic value to the memory node, the write word line is set to a high level to enable the write transistor, and the write bit line is set to the high level to charge the memory node. When writing a second logic value to the memory node, the write word line is set to a high level to enable the write transistor, and the write bit line is set to a low level to discharge the memory node or maintain its discharge state. When reading data stored in the memory node, the write word line and the write bit line are set to the off level to turn off the write transistor, a read voltage is applied to the read bit line, and the sensing current of the read word line is read to read the data stored in the memory node.

11. The method of operating the in-memory computing unit according to claim 9, characterized in that, The non-volatile storage mode includes: Set the write word line and the write bit line to high level to enable the write transistor and the read transistor; A programming voltage is applied between the non-volatile memory and the first and second electrodes via the read bit lines and the read word lines to write or erase data to the non-volatile memory. A read voltage is applied between the non-volatile memory and the first and second electrodes via the read bit lines and the read word lines, and the current of the read word lines is read to read the data stored in the non-volatile memory.

12. The method of operating the in-memory computing unit according to claim 9, characterized in that, In the in-memory computing mode, when the mask data is a first logic value, the read transistor is turned on and the weight data participates in the calculation; when the mask data is a second logic value, the read transistor is turned off and the weight data does not participate in the calculation.

13. The method of operating the in-memory computing unit according to claim 9, characterized in that, The write operation in the in-memory computing mode includes: Set the write bit line and the write word line to high level to turn on the write transistor and charge the memory node to turn on the read transistor. Weight data is written to the non-volatile memory through the read bit line and the read word line; Mask data is written to the storage node through the write word line and the write bit line; Set the write word line, the write bit line, the read word line, and the read bit line to the off level to turn off the write transistor.

14. An in-memory computing array, characterized in that, Includes an in-memory computing unit as described in any one of claims 1-8, multiple common write lines, multiple common read lines, multiple common write bit lines, and multiple common read bit lines; The in-memory computing units are arranged in an array along the row and column directions; The write lines of the in-memory computing units in the same row are connected to the same common write line, and the read lines are connected to the same common read line; The write bit lines of the in-memory computing units in the same column are connected to the same common write bit line, and the read bit lines are connected to the same common read bit line.

15. The in-memory computing array according to claim 14, characterized in that, The in-memory computing array is configured to perform: A write signal is applied to at least one of the common write word lines and at least one of the common write bit lines to write mask data into the memory node of at least one row of the in-memory computing units; simultaneously, an input voltage vector is applied to multiple of the common read bit lines. Read the output current of each of the common read word lines, wherein the output current value of each of the common read word lines is the sum of the weight data stored in the non-volatile memory of the in-memory computing unit in its corresponding column, which is selected by the mask data of the corresponding memory node, and the input voltage component applied to the corresponding column. The output current of all the common read word lines is used together as the output current. The output current vector is the product of the mask data matrix of the storage node corresponding to the in-memory computing array and the weight data matrix stored in the in-memory computing array, multiplied bitwise, and the input voltage vector.

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