Key technical scheme intelligent screening and positioning method and system for integrated circuit research and development

Abstract

The invention relates to a key technical scheme intelligent screening and positioning method and system oriented to integrated circuit research and development, and the method comprises the steps: respectively extracting technical entities representing specific process steps and device structures and legal entities representing legal protection boundaries through building a semiconductor field heterogeneous data stream and utilizing a large language model; constructing a bimodal semantic topology network comprising technical association, legal association and cross-modal alignment edges; heterogeneous graph attention representation learning is executed, and deep semantic dependence between nodes is captured; generating a global semantic representation vector representing the logic consistency of the technical scheme based on the topological connection density and the cross-modal semantic alignment strength of the nodes; and finally, accurately positioning a key technical scheme based on the logic consistency confidence coefficient. According to the method, the process-protection logic consistency can be automatically verified, the problems that traditional keyword retrieval is loud in noise and a semantic model lacks logic support are solved, and objective and high-reliability data support is provided for technology pre-research, design avoidance and research and development path planning.

Description

Technical Field

[0001] This invention relates to the fields of natural language processing and intelligent intelligence mining, specifically to an intelligent screening and positioning method and system for key technical solutions in integrated circuit research and development. Background Technology

[0002] In technology-intensive fields such as integrated circuit design and semiconductor manufacturing, technological iteration follows Moore's Law, resulting in a rapid evolution and the generation of massive amounts of technical documentation as processes transition from mature to advanced technologies. Researchers face the significant challenge of accurately identifying core technologies from a vast pool of technical solutions in global patent databases when designing next-generation chip architectures or developing advanced process technologies. Accurately identifying high-quality technical solutions with complete implementation details and clear rights protection is crucial for assisting engineers in designing to circumvent technology barriers, preventing infringement in R&D paths, and optimizing process routes.

[0003] However, faced with the exponentially growing volume of patent text data, existing methods for assessing and screening technical solutions still suffer from several intractable technical challenges: First, traditional search methods, centered on keyword matching, have inherent technical flaws. They cannot effectively distinguish between the core descriptions of a technical solution and incidental mentions of non-core content, easily leading to significant search redundancy. Existing screening technologies generally rely on keyword matching or basic classification number filtering. In the semiconductor technology field, some non-core technology-oriented patent applications often pile up popular technical terms, but their specifications do not record specific process parameters supporting the implementation of the technical solution. The objective limitations of such shallow character matching mechanisms result in a large amount of invalid information in the search system output, requiring R&D personnel to invest significant manpower in manual screening. Second, existing text analysis methods struggle to effectively verify the logical consistency between the disclosed process solutions and the boundaries of rights protection. The patent system follows the basic principle of exchanging disclosure for protection; the technical field content recorded in the patent specification should fully support the scope of protection defined in the claims. However, two types of defective texts commonly exist in massive patent data: one is the vague patent text, where the technical effects described in the specification are broad, but the scope of protection defined by the claims is significantly narrow; the other is the logically disjointed patent text, where the scope of protection defined by the claims is too broad, but the specification fails to describe specific technical means sufficient to support that scope. Most existing natural language processing methods treat the patent specification and claims as independent text modules, lacking a deep verification mechanism for the mapping relationship between technical means and legal protection features, thus making it difficult to effectively filter out the aforementioned logically inconsistent technical solutions. Third, existing technologies lack the ability to perform deep topological analysis of complex processes. Chip manufacturing is a complex system involving multiple processes, with strict upstream and downstream functional dependencies between technical entities. Existing shallow feature extraction techniques struggle to capture this deep engineering topology and cannot analyze the logical transmission relationship between "previous process parameters" and "subsequent device performance," leading to misjudgments when models process complex combined inventions due to the loss of structural information.

[0004] In summary, there is an urgent need in this field for a key technical solution that can be adapted to complex engineering fields such as integrated circuits, and that can accurately locate key technical solutions with rigorous technical logic and substantial feature support by deeply integrating technical engineering semantics and legal protection semantics and utilizing objectively existing logical mapping rules. Summary of the Invention

[0005] Based on the aforementioned shortcomings and deficiencies in the existing technology, one of the objectives of this invention is to at least solve one or more of the aforementioned problems in the existing technology. In other words, one of the objectives of this invention is to provide an intelligent screening and positioning method and system for key technology solutions in integrated circuit research and development that meets one or more of the aforementioned requirements.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: A method for intelligent screening and positioning of key technology solutions for integrated circuit R&D includes the following steps: S1. Acquire technical data streams of technical solutions in the semiconductor field; S2. Perform bimodal engineering feature analysis on the technical data flow to obtain the technical entity that represents the specific process steps and component parameters, and the legal entity that represents the protected object and parameter limitation conditions. S3. Construct a technology-law bimodal semantic topology network. Based on the semantic logical relationship between entities, construct a bimodal heterogeneous graph, including technology-related edges representing the dependence of technology functions, legal-related edges representing the logic of legal protection, and cross-modal alignment edges representing the scope of protection substantially supported by technological means. S4. Perform heterogeneous graph attention representation learning, use multi-head attention mechanism to capture deep semantic dependencies between nodes in the topological network, and generate deep semantic embedding vectors of nodes based on high-order logical features of multi-class meta-path mining technology. S5. Construct a global semantic representation vector based on topological and semantic dual features using node-based deep semantic embedding vectors; S6. Input the global semantic representation vector into the pre-trained screening model and output the logical consistency confidence of the technical solution; when the confidence is higher than the preset threshold, mark it as a key technical solution.

[0007] As a preferred embodiment, step S1 specifically includes: The patent literature data stream in the semiconductor field is collected. The data stream includes a first text field describing the implementation details of chip manufacturing process and device structure, a second text field defining the boundaries of legal protection, and structured bibliographic data, and is preprocessed.

[0008] As a preferred embodiment, the preprocessing includes: The first and second text fields are cleaned to obtain standardized text data; The structured bibliographic data were processed using a statistical normalization method to obtain standardized application feature vectors.

[0009] As a preferred embodiment, step S2, the dual-modal engineering feature parsing includes: We construct entity extraction instructions suitable for the semiconductor field, drive a large language model to identify the technical triple subject-operation-object and the legal triple protected object-limitation relationship-technical feature respectively, and perform synonym normalization to obtain technical entities and legal entities.

[0010] As a preferred embodiment, step S3, the process of constructing the bimodal heterogeneous graph, includes: Based on the operational relationships in the technology triplet, directed edges are constructed between related technology entity nodes to obtain technology association edges; Based on the constraint relationship in the legal triplet, directed edges are constructed between legal entity nodes that have logical relationships, resulting in legal relationship edges; The semantic similarity between the technical entity and the legal entity is calculated. When the similarity meets the preset conditions, cross-modal alignment edges are constructed to obtain cross-modal alignment edges.

[0011] As a preferred embodiment, step S4, the heterogeneous graph attention representation learning specifically includes the following steps: S4.1 For any central node in the network, distinguish the types of its nearest neighbor nodes, calculate the semantic association strength using a multi-head attention mechanism, and update the node features by weighted aggregation of neighborhood information; S4.2 Define multiple types of meta-paths, including technology meta-paths that focus on the integrity of the technology functional chain, legal meta-paths that focus on the stability of the legal protection structure, and cross-modal meta-paths that focus on the consistency of technology-law logic. The semantic representation of each node under different meta-paths is calculated separately, and the deep semantic embedding vector of the node is generated by weighted fusion based on the contribution of each path to the screening task.

[0012] As a preferred embodiment, step S5, the process of constructing the global semantic representation vector, includes the following steps: S5.1 Compute the semantic fit of the metapath of the node and the density of the topological connections of the node; For each node, its semantic fit is calculated by combining the importance weight of its meta-path with the number of its nearest neighbors on that path; the sum of the in-degree and out-degree of each node in the same-modal and cross-modal networks is counted and normalized to obtain the density of the node's topological connections. Calculate the cross-modal semantic alignment strength; For related technical and legal nodes, the cosine similarity of their deep semantic vectors is calculated and corrected by combining the weights of cross-modal meta-paths to obtain the cross-modal semantic alignment strength. S5.2 Based on semantic adaptability, topological connection density, and cross-modal semantic alignment strength, a comprehensive importance factor for each node is generated through nonlinear combination. S5.3. Using the comprehensive importance factor as the weight, the semantic embedding vectors of all nodes in the network are weighted and summed, and then nonlinearly transformed through the activation function to generate a global semantic representation vector that represents the overall logical quality of the technical solution.

[0013] As a preferred embodiment, step S6 specifically includes: The global semantic representation vector is concatenated with the standardized application feature vector, input into the feedforward neural network classifier, and the output is the logical consistency confidence of the technical solution. When the confidence level is higher than the preset threshold, the technical solution is determined to be a key technical solution.

[0014] This invention also provides an intelligent screening and positioning system for key technology solutions in integrated circuit R&D, applying the intelligent screening and positioning method for key technology solutions as described in any of the preceding solutions. The intelligent screening and positioning system for key technology solutions includes: The data acquisition layer is used to collect technical data streams from technical solutions in the semiconductor field. The dual-modal feature parsing layer is used to perform dual-modal engineering feature parsing on the technical data stream to obtain the technical entity that represents the specific process steps and component parameters, and the legal entity that represents the protected object and parameter limiting conditions. A deep semantic verification layer is used to construct a technology-law bimodal semantic topology network. Based on the semantic logical relationships between entities, it constructs a bimodal heterogeneous graph, including technology-related edges representing technological functional dependencies, legal-related edges representing legal protection logic, and cross-modal alignment edges representing the scope of protection substantially supported by technological means. It is also used to perform heterogeneous graph attention representation learning, using a multi-head attention mechanism to capture deep semantic dependencies between nodes in the topology network, and mining high-order logical features of technical solutions based on multi-class meta-paths to generate deep semantic embedding vectors for nodes. Furthermore, it is used to generate a global semantic representation vector that integrates topological and semantic features using the deep semantic embedding vectors of nodes, and to generate the logical consistency confidence of the technical solution based on the global semantic representation vector using a pre-trained screening model. The results are output to the interaction layer to obtain the confidence level of the logical consistency; when the confidence level is higher than a preset threshold, it is marked as a key technical solution.

[0015] Compared with the prior art, the beneficial effects of this invention are: This invention constructs a dual-modal topology network that integrates technology and legal semantics, utilizing the objective logical patterns existing in technical documents to solve the high noise problem caused by the reliance on keyword matching in traditional methods. By automatically verifying the logical consistency between the process details in the specification and the scope of protection of the claims, it achieves accurate positioning and noise reduction of key technical solutions, providing objective and high-precision data support for the optimal allocation of enterprise R&D resources. Attached Figure Description

[0016] Figure 1 This is a logical architecture diagram of the intelligent screening and positioning of key technical solutions for integrated circuit R&D according to an embodiment of the present invention; Figure 2 This is a system application scenario diagram for integrated circuit research and development according to an embodiment of the present invention. Detailed Implementation

[0017] To more clearly illustrate the embodiments of the present invention, specific implementation methods will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0018] This invention relates to an intelligent intelligence analysis system for screening and locating key technical solutions in integrated circuit R&D, deployed within the R&D center of semiconductor companies. Addressing the challenges of rapid technological iteration, obscure patent texts, and the presence of numerous engineering parameters in the integrated circuit field, this system automatically performs logic consistency checks by collecting descriptions of chip manufacturing processes and defining the scope of structural protection. It aims to solve the pain point in existing R&D scenarios where engineers struggle to quickly sift through massive amounts of data to eliminate logically flawed and poorly protected "noise patents," assisting engineers in accurately identifying logically consistent key technical solutions in next-generation memory chip development or advanced process design.

[0019] The intelligent screening and positioning method for key technology solutions in integrated circuit R&D of the present invention is implemented according to the process of "data acquisition - bimodal entity parsing - topology network construction - cross-modal semantic alignment - screening and recommendation", and the specific steps are as follows: Step S1: Establish a semiconductor technology data stream. Obtain patent document data streams for the target technology field to be screened. The data streams include technical disclosure texts describing chip manufacturing process implementation details and device structure (first text field, such as the specification), claim texts defining legal protection boundaries (second text field, such as the claims), and structured bibliographic data, and perform preprocessing. The specific preprocessing includes: cleaning the first and second text fields to obtain standardized text data; and processing the structured bibliographic data using statistical normalization methods to obtain standardized application feature vectors.

[0020] Step S2: Perform bimodal engineering feature analysis. Based on the Large Language Model (LLM), perform bimodal entity recognition and mapping. Using natural language processing technology, extract technical entities (T nodes) representing specific process steps and component parameters from the technical disclosure text, and extract legal entities (L nodes) representing the protected object and parameter limiting conditions from the claim text. Specifically, bimodal entity extraction includes: constructing entity extraction instructions suitable for the target technology field, driving a large language model to identify technical triples (subject-operation-object) and legal triples (protected object-limiting relation-technical feature) respectively, and performing synonym normalization processing.

[0021] Step S3: Construct a technology-law bimodal semantic topology network. Based on the semantic logical relationships between entities, construct a heterogeneous graph structure, including technology-related edges (TT edges) representing the dependence of technology functions, legal-related edges (LL edges) representing the legal protection logic, and cross-modal alignment edges (TL edges) representing the "substantial support of the scope of protection by technical means". Specifically, the construction of the bimodal heterogeneous graph includes the following steps: based on the operational relationships in the technical triples, directed edges are constructed between related technical entity nodes to reproduce the functional implementation link of the technical solution; based on the limiting relationships in the legal triples, directed edges are constructed between logically related legal entity nodes to restore the hierarchical protection structure of the claims; the semantic similarity between technical entities and legal entities is calculated, and when the similarity meets the preset conditions, cross-modal alignment edges are constructed to automatically verify whether the technical details disclosed in the specification are substantially covered by the claims.

[0022] Step S4: Perform heterogeneous graph attention representation learning, use multi-head attention mechanism to capture deep semantic dependencies between nodes in the topological network, and generate deep semantic embedding vectors of nodes based on high-order logical features of multi-class meta-path mining technology. Specifically, heterogeneous graph attention representation learning includes the following steps: Step S4.1: For any central node in the network, distinguish the types of its nearest neighbor nodes, calculate the semantic association strength using a multi-head attention mechanism, and update the node features by weighted aggregation of neighborhood information in order to capture the context of local technical details or legal restrictions. Step S4.2: Define multiple types of meta-paths, including technology meta-paths focusing on the integrity of the technology functional chain (T→T→T), legal meta-paths focusing on the stability of the legal protection structure (L→L→L), and cross-modal meta-paths focusing on the consistency of technology-law logic (T→L→T and L→T→L); calculate the semantic representation of each node under different meta-paths, and perform weighted fusion based on the contribution of each path to the screening task.

[0023] Step S5: Construct a global semantic representation vector based on topological and semantic dual features, comprehensively considering the information carrying capacity of each feature node in the process flow (density of topological connections) and the substantive coverage in rights protection (tightness of cross-modal mapping), and generate a global semantic representation vector that can represent the "logical self-consistency" and "protection rigor" of the technical solution. Specifically, the global semantic representation vector is constructed through the following steps: Step S5.1: Calculate the semantic fit of the node's metapath and the density of its topological connections. For semantic fit, the calculation is performed by weighting the attention weight of the node's metapath with the number of its nearest neighbors on the path. This metric quantifies the information carrying capacity of the entity within a specific technical or legal logic. For topological connection density, the sum of the in-degree and out-degree of each node in both the same-modal and cross-modal networks is statistically analyzed and normalized. This metric measures the entity's centralized position within the entire technical solution network. These two metrics together reflect the entity's information carrying capacity and structural importance within the technical solution. Step S5.2: Calculate the cross-modal semantic alignment strength. For related technical and legal nodes, calculate the cosine similarity of their deep semantic vectors and correct it by combining the weights of the cross-modal meta-paths to obtain the cross-modal semantic alignment strength. This indicator is used to determine whether the "technical features disclosed in the specification" and the "scope of protection defined by the claims" are substantially consistent. Step S5.3: Generate the comprehensive importance factor of nodes. Based on the semantic fit, topological connectivity density, and cross-modal semantic alignment strength mentioned above, a comprehensive importance factor for each node is generated through nonlinear combination. Step S5.4: Generate a global semantic representation vector for the technical solution. Using the comprehensive importance factor as weight, the semantic embeddings of all nodes in the network are weighted and summed, and then nonlinearly transformed through an activation function to generate a global semantic representation vector representing the overall logical quality of the technical solution.

[0024] Step S6: Intelligent screening and push of core technology solutions. The generated global semantic representation vector is input into the pre-trained screening model, which outputs the logical consistency confidence score of the technology solution. When the confidence score is higher than the preset threshold, it is marked as a "key technology solution" and pushed to the R&D intelligence system to achieve accurate positioning of target patents.

[0025] Specifically, the intelligent screening of core technical solutions includes: concatenating the global semantic representation vector obtained in step S5.4 with the standardized application feature vector obtained in step S1, and inputting the concatenation into a feedforward neural network classifier. The model outputs the location confidence of the key technical solution. When the confidence is higher than a preset threshold, the document is determined to be a "key technical solution" with logical integrity and included in the core technical solution candidate set, providing data support for technology avoidance design and R&D intelligence analysis; otherwise, it is determined to be a "noise solution" and filtered out.

[0026] The following detailed explanation, through specific application examples, illustrates the key technical solution intelligent screening and positioning method, which includes the following steps: S1: Establish heterogeneous data flow in the semiconductor field. The system collects and preprocesses patent data through the IncoPat global patent literature database interface, specifically including the following steps: S1.1: Data Acquisition: The technical field is limited to "integrated circuit design and semiconductor manufacturing technology," and the search formula is defined as "IPC=(G06F30 / 392 OR G06F17 / 50 OR H01L21 / 822)." The time range is limited to invention patent text data and structured data published between 2014 and 2023. The acquired data includes unstructured text, such as abstracts, specifications, and claims, and structured data, such as the number of classification numbers, the number of patent families, the number of document pages, and the number of inventors. S1.2: Data standardization: The abstract and claim texts are cleaned, segmented, and stop words are removed; Z-score normalization is used for structured data to map feature values ​​to standard intervals and remove the influence of dimensions.

[0027] S2. Perform bimodal engineering feature parsing. The system enables the feature extraction module, utilizing the general semantic understanding capabilities of the large language model GPT-4o to extract entities from two text domains. The specific steps include: S2.1: Technical Entity Extraction: The prompt instruction requires the model to identify and extract "technical entities" that represent specific process steps and component parameters. For example: "Input: ...a [FinFET] [manufacturing method] for [reducing] [leakage current].... Output: T entity: [FinFET], [manufacturing method], [leakage current]; feature triple: ([manufacturing method], reduce, [leakage current])"; S2.2: Legal Boundary Extraction (L-node): The model is required to identify and extract the "legal entities" that represent the protected object and the parameter limiting conditions. For example: "Input: 1. A [semiconductor device], characterized in that it comprises: a [substrate] having a thickness of less than [10nm]... Output: L-entity: [semiconductor device], [substrate]; Feature triple: ([semiconductor device], comprises, [substrate])"; By using a large language model, unstructured text is transformed into fine-grained engineering elements that can be understood by machines, laying the foundation for subsequent logical verification.

[0028] S3: Constructing a bimodal graph, specifically including the following steps: S3.1: Construct a bimodal heterogeneous graph G=(V,E), where the node set V=T∪L (where T is the set of T-type nodes and L is the set of L-type nodes), assign a unique ID to each node, and E is the set of edges of the heterogeneous graph. Unlike the prior art, which treats "patent" as a node, this invention treats "semantic entities" extracted from the patent text as nodes. S3.2: Based on the "operation" relationship in the technology triple, construct directed edges between associated T-shaped nodes to reproduce the engineering implementation path of the technical solution; S3.3: Based on the "limitation" relationship in the legal triplet, directed edges are constructed between logically related L-shaped nodes to restore the hierarchical protection structure of the claims; S3.4: Input the node text into the Sentence-BERT (SBERT) model to generate embedding vectors. Calculate the cosine similarity between T-shaped and L-shaped nodes. When the similarity is higher than a threshold, construct undirected cross-modal alignment edges to connect the technical entity and the corresponding legal entity. The physical significance of this step is to automatically verify whether the "specific process parameters" disclosed in the specification are substantially covered by the "scope of protection" of the claims. If the T-L connection is missing, it means that there is a risk of "logical gap" or "omission in protection" for this technical point.

[0029] S4: Perform heterogeneous graph attention representation learning, which includes the following steps: S4.1: Node-level attention learning, specifically including the following steps: S4.1.1: Employs an 8-head independent attention mechanism with a linear transformation matrix. The activation function chosen is LeakyReLU, and the attention coefficients between the center node and its nearest neighbors are calculated. The formula is as follows: =LeakyReLU( ); in, Let v be the attention coefficient between node v and its nearest neighbor u in the k-th attention head; , The initial embeddings (dimension d) for nodes v and u are respectively. ∈ Let d' be the linear transformation matrix of the k-th attention head, where d' is the transformed dimension; ⊕ denotes the vector concatenation operation; S4.1.2: The weights are obtained by Softmax normalization. After averaging and aggregating the output feature vectors generated by the eight attention heads, ReLU activation is applied to obtain the preliminary node embedding. ; S4.2: Semantic-level attention fusion, specifically including the following steps: S4.2.1: Define multiple types of logic verification paths: including technical paths focusing on the integrity of the process chain. (T→T→T), focusing on legal pathways to protect stability (L→L→L) and cross-modal meta-path focusing on disclosure consistency (T→L→T) (L→T→L); S4.2.2: Generate path semantic vectors. For each meta-path, perform mean pooling on the embeddings of all nodes covered by the path to generate a path semantic vector representing that perspective. ; S4.2.3: Adaptive fusion of different perspectives: The model automatically learns the importance weights of different meta-paths through a semantic-level attention network. ; S4.2.4: Based on the path weights learned above, the features from different semantic spaces are weighted and fused to obtain the final embedding vector of the node. .

[0030] Step S5: Construct a global semantic representation vector for the technical solution, generating a high-dimensional feature vector that can represent the "logical quality" of the solution. This includes the following steps: S5.1: Calculate semantic fit ( ) and the density of topological connections ( ): Regarding semantic adaptability ( This metric quantifies the information carrying capacity of an entity within a specific technical or legal logic by weighting the attention weight of the meta-path to which the aggregation node belongs with the number of its nearest neighbors on that path; it also addresses the density of topological connections. By statistically analyzing the sum of the in-degree and out-degree of each node in the same-modal and cross-modal networks and normalizing it, this indicator is used to measure the centralized position of the entity in the entire technical solution network. These two indicators together reflect the information carrying capacity and structural importance of the entity in the technical solution. S5.2: Calculate the cross-modal semantic alignment weight β for the associated technology nodes. With legal nodes Calculate its semantic alignment strength The formula is as follows: = ; in For nodes and semantic alignment weights, It is a cross-modal meta-path Importance weights It is a node and The embedding vector obtained through step S4 above is used by this formula to check the distance between the "technical feature" and the "claims" using cosine similarity. The higher the β value, the more concrete the description of the technical point, and the more stringent the legal protection. S5.3: Based on the above indicators, calculate the overall importance of nodes. ; For T-shaped nodes Based on the semantic adaptability of this node and the density of topological connections According to the formula calculate; For L-shaped nodes Then, based on the semantic adaptability of that node... and the density of topological connections According to the formula calculate; in, This represents the set of heterogeneous nodes that have a direct cross-modal association with the current node. Then, all calculated... The values ​​are normalized to the [0, 1] interval using Min-Max; S5.4: with Using weights, a weighted summation and nonlinear activation are performed on the semantic embeddings of all nodes to generate a global semantic representation vector representing the overall logical quality of the patent document. The formula is as follows: = ReLU ( ); Where V = T∪L (T is the set of T-type nodes, and L is the set of L-type nodes), It is the comprehensive importance factor of node v. It is the final embedding vector of node v, and ReLU is the activation function.

[0031] S6: Intelligent screening and recommendation of key technology solutions. This involves using global semantic representation vectors... The data is concatenated with standardized application features and input into a pre-trained feedforward neural network. During the training phase, the network selects mature patents verified based on objective statistical indicators (such as high citation counts, long maintenance periods, and multiple patent families) as positive samples, and patents lacking citations or short-term expiration as negative samples. Highly cited and long-maintained patents typically possess characteristics such as detailed technical disclosure, clear rights protection, and rigorous logic. This system uses such objective data as proxy labels for "logical consistency" to drive the model to learn the deep semantic topology of high-quality solutions. The model outputs the "positional confidence" of the technical solution. When the confidence score is ≥0.5, the document is determined to be a "key technical solution," that is, a target solution with complete technical logic and clear legal protection. Simultaneously, it is pushed to the R&D intelligence dashboard, providing core data support for technology circumvention design and R&D path planning.

[0032] It should be further noted that the intelligent screening method for the above-mentioned key technical solutions can be implemented using a computer system, see [link to relevant documentation]. Figure 1 The intelligent screening and positioning system for key technologies is logically divided into four layers, specifically including the following core processing modules: (1) Data Acquisition Module: Corresponding to the first layer, this module is used to execute step S1. This module is equipped with an API interface for connecting to the global patent database (IncoPat), and is responsible for acquiring unstructured text streams and structured bibliographic data in the field of integrated circuits; (2) Dual-modal feature parsing module: Corresponding to the second layer, it is used to execute step S2. This module has a built-in Large Language Model (LLM) interface, which includes a technical entity parsing unit and a legal boundary parsing unit, and is responsible for extracting process technology entities and legal protection entities in parallel; (3) Logical Topology Construction Module: Corresponding to the front end of the third layer, it is used to execute step S3. It is responsible for constructing a heterogeneous graph data structure in memory that includes technical association edges (TT), legal association edges (LL), and cross-modal alignment edges (TL); (4) Deep semantic verification module: corresponding to the middle and back end of the third layer, used to execute steps S4 and S5. It embeds a heterogeneous graph attention calculation unit and a global semantic representation generator, which is responsible for calculating the attention coefficients between nodes and generating a global semantic representation vector that represents the logical quality of the scheme. It also uses a pre-trained screening model (which is specifically a feedforward neural network classifier in this embodiment) to generate the logical consistency confidence of the scheme based on the global semantic representation vector. (5) Intelligent Filtering and Result Output Module: Corresponding to the fourth layer, this module is used to execute step S6. This module is responsible for receiving the confidence and positioning results output by the deep semantic verification module, generating a key solution filtering list based on preset thresholds, and providing cross-modal alignment weight analysis and core intelligence data export functions to provide intuitive data support for R&D personnel.

[0033] At the hardware level, the system includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor. When the processor executes the program, it implements the methods described in steps S1 to S6 above.

[0034] The following further illustrates the practical application environment and workflow of this invention in integrated circuit R&D scenarios: like Figure 2 As shown, the left side of the system is the data acquisition source for the semiconductor field, mainly connected to the global patent database (IncoPat) interface, responsible for ingesting massive unstructured text streams involving integrated circuit design and semiconductor manufacturing technologies. The middle section represents the system of this invention. This system, through its built-in dual-modal feature parsing module, automatically extracts process parameters (technical entities) and protection boundaries (legal entities) from obscure patent documents, and performs deep logical consistency checks.

[0035] On the right is the integrated circuit R&D application terminal. The system will distribute the selected high-confidence solutions to two types of scenarios through the enterprise intranet: one is the R&D intelligence dashboard, which is used to help engineers quickly lock in reference solutions in the R&D of next-generation memory chips or advanced process design; the other is the core data support module, which is used to output cross-modal alignment weights to provide quantitative basis for the R&D team to carry out technology avoidance design and process route planning.

[0036] The following is a verification of the implementation effect, and the specific process is as follows: Experimental Setup: This experiment aims to verify the system's ability to accurately locate key technical solutions from massive datasets by utilizing the objective logical laws of "technology-law". The experimental dataset contains over 4,000 patents in the field of integrated circuits, including "target patents" (positive samples) with rigorous technical logic and clear protection scope verified by objective logical rules, and "noise patents" (negative samples) with logical flaws or that only involve keyword stuffing.

[0037] To objectively verify the technical advantages of this invention in terms of positioning accuracy and noise reduction capability, a comparison was made between this invention and two representative methods in the prior art. All three methods used the same patent specification text as input A and the claims text as input B, calculating the matching scores and classifying the results.

[0038] Existing Method 1: A keyword weighted matching method based on the Term Frequency-Inverse Document Frequency (TF-IDF) algorithm is used; this is the most commonly used objective retrieval benchmark in traditional existing technologies.

[0039] Existing technology 2: Employing a deep semantic matching method based on SBERT, which is currently the mainstream single-modal technology in the field of natural language processing.

[0040] "Location accuracy" and "noise filtering rate" were used as the core objective indicators. The noise filtering rate refers to the proportion of negative samples that the model correctly removes. The experimental results are shown in Table 1.

[0041] Table 1. Experimental Comparison Results ; As shown in Table 1, the keyword TF-IDF method achieves a positioning accuracy of only 46.2%. This is because the integrated circuit field contains a large number of noisy documents that "stuff keywords" but lack substantial protection, which traditional methods cannot distinguish. While the semantic vector SBERT method improves the accuracy to 68.5%, it still misclassifies many patents that "disclose technology but are not protected" as target patents due to the lack of verification of cross-modal logic between the specification and claims. The method of this invention significantly improves the positioning accuracy to 85.7% by introducing a dual-modal logic consistency verification between technology and law. This demonstrates that this invention utilizes objectively existing logical mapping rules to effectively eliminate logically fragmented noisy data and achieve accurate positioning of the target technical solution.

[0042] In summary, the above experiments verify that, in the field of integrated circuit design and semiconductor manufacturing technology, this system can effectively solve the problems of inaccurate screening and high noise caused by the reliance on surface keywords in traditional methods. By constructing an objective logical model that integrates the semantics of technology disclosure and rights protection, the system achieves accurate positioning and real-time identification of forward-looking key technology solutions.

[0043] This invention is mainly applied to the intellectual property analysis system of semiconductor enterprise R&D centers. It is used to accurately locate the target technical solution with logical consistency in a complex semantic topology space by using the objective mapping law between technical logic and legal boundaries from massive unstructured engineering texts, thereby providing direct and accurate data support for lithography process R&D, chip architecture design and technology avoidance design.

[0044] The above description is merely a detailed explanation of preferred embodiments and principles of the present invention. For those skilled in the art, there may be changes in specific implementation methods based on the ideas provided by the present invention, and these changes should also be considered within the scope of protection of the present invention.

Claims

1. A method for intelligent screening and positioning of key technology solutions for integrated circuit R&D, characterized in that, Includes the following steps: S1. Acquire technical data streams of technical solutions in the semiconductor field; S2. Perform bimodal engineering feature analysis on the technical data flow to obtain the technical entity that represents the specific process steps and component parameters, and the legal entity that represents the protected object and parameter limitation conditions. S3. Construct a technology-law bimodal semantic topology network. Based on the semantic logical relationship between entities, construct a bimodal heterogeneous graph, including technology-related edges representing the dependence of technology functions, legal-related edges representing the logic of legal protection, and cross-modal alignment edges representing the scope of protection substantially supported by technological means. S4. Perform heterogeneous graph attention representation learning, use multi-head attention mechanism to capture deep semantic dependencies between nodes in the topological network, and generate deep semantic embedding vectors of nodes based on high-order logical features of multi-class meta-path mining technology. S5. Construct a global semantic representation vector based on topological and semantic dual features using node-based deep semantic embedding vectors; S6. Input the global semantic representation vector into the pre-trained screening model and output the logical consistency confidence of the technical solution; when the confidence is higher than the preset threshold, mark it as a key technical solution.

2. The intelligent screening and positioning method for the key technical solution according to claim 1, characterized in that, Step S1 specifically includes: The patent literature data stream in the semiconductor field is collected. The data stream includes a first text field describing the implementation details of chip manufacturing process and device structure, a second text field defining the boundaries of legal protection, and structured bibliographic data, and is preprocessed.

3. The intelligent screening and positioning method for the key technical solution according to claim 2, characterized in that, The preprocessing includes: The first and second text fields are cleaned to obtain standardized text data; The structured bibliographic data were processed using a statistical normalization method to obtain standardized application feature vectors.

4. The intelligent screening and positioning method for the key technical solution according to claim 3, characterized in that, In step S2, the dual-modal engineering feature analysis includes: We construct entity extraction instructions suitable for the semiconductor field, drive a large language model to identify the technical triple subject-operation-object and the legal triple protected object-limitation relationship-technical feature respectively, and perform synonym normalization to obtain technical entities and legal entities.

5. The intelligent screening and positioning method for the key technical solution according to claim 4, characterized in that, In step S3, the process of constructing the bimodal heterogeneous graph includes: Based on the operational relationships in the technology triplet, directed edges are constructed between related technology entity nodes to obtain technology association edges; Based on the constraint relationship in the legal triplet, directed edges are constructed between legal entity nodes that have logical relationships, resulting in legal relationship edges; The semantic similarity between the technical entity and the legal entity is calculated. When the similarity meets the preset conditions, cross-modal alignment edges are constructed to obtain cross-modal alignment edges.

6. The intelligent screening and positioning method for the key technical solution according to claim 5, characterized in that, In step S4, heterogeneous graph attention representation learning specifically includes the following steps: S4.1 For any central node in the network, distinguish the types of its nearest neighbor nodes, calculate the semantic association strength using a multi-head attention mechanism, and update the node features by weighted aggregation of neighborhood information; S4.2 Define multiple types of meta-paths, including technology meta-paths that focus on the integrity of the technology functional chain, legal meta-paths that focus on the stability of the legal protection structure, and cross-modal meta-paths that focus on the consistency of technology-law logic. The semantic representation of each node under different meta-paths is calculated separately, and the deep semantic embedding vector of the node is generated by weighted fusion based on the contribution of each path to the screening task.

7. The intelligent screening and positioning method for the key technical solution according to claim 6, characterized in that, In step S5, the process of constructing the global semantic representation vector includes the following steps: S5.1 Compute the semantic fit of the metapath of the node and the density of the topological connections of the node; For each node, its semantic fit is calculated by combining the importance weight of its meta-path with the number of its nearest neighbors on that path; the sum of the in-degree and out-degree of each node in the same-modal and cross-modal networks is counted and normalized to obtain the density of the node's topological connections. Calculate the cross-modal semantic alignment strength; For related technical and legal nodes, the cosine similarity of their deep semantic vectors is calculated and corrected by combining the weights of cross-modal meta-paths to obtain the cross-modal semantic alignment strength. S5.2 Based on semantic adaptability, topological connection density, and cross-modal semantic alignment strength, a comprehensive importance factor for each node is generated through nonlinear combination. S5.

3. Using the comprehensive importance factor as the weight, the semantic embedding vectors of all nodes in the network are weighted and summed, and then nonlinearly transformed through the activation function to generate a global semantic representation vector that represents the overall logical quality of the technical solution.

8. The intelligent screening and positioning method for the key technical solution according to claim 7, characterized in that, Step S6 specifically includes: The global semantic representation vector is concatenated with the standardized application feature vector, input into the feedforward neural network classifier, and the output is the logical consistency confidence of the technical solution. When the confidence level is higher than the preset threshold, the technical solution is determined to be a key technical solution.

9. A smart screening and positioning system for key technology solutions in integrated circuit R&D, employing the smart screening and positioning method for key technology solutions as described in any one of claims 1-8, characterized in that, The key technical solution, the intelligent screening and positioning system, includes: The data acquisition layer is used to collect technical data streams from technical solutions in the semiconductor field. The dual-modal feature parsing layer is used to perform dual-modal engineering feature parsing on the technical data stream to obtain the technical entity that represents the specific process steps and component parameters, and the legal entity that represents the protected object and parameter limiting conditions. A deep semantic verification layer is used to construct a technology-law bimodal semantic topology network. Based on the semantic logical relationships between entities, it constructs a bimodal heterogeneous graph, including technology-related edges representing technological functional dependencies, legal-related edges representing legal protection logic, and cross-modal alignment edges representing the scope of protection substantially supported by technological means. It is also used to perform heterogeneous graph attention representation learning, using a multi-head attention mechanism to capture deep semantic dependencies between nodes in the topology network, and mining high-order logical features of technical solutions based on multi-class meta-paths to generate deep semantic embedding vectors for nodes. Furthermore, it is used to generate a global semantic representation vector that integrates topological and semantic features using the deep semantic embedding vectors of nodes, and to generate the logical consistency confidence of the technical solution based on the global semantic representation vector using a pre-trained screening model. The results are output to the interaction layer to obtain the confidence level of the logical consistency; when the confidence level is higher than a preset threshold, it is marked as a key technical solution.

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