PCB layout and theoretical circuit optimization method based on PCB parasitic parameters

Abstract

The invention relates to a PCB layout and theoretical circuit optimization method based on PCB parasitic parameters, and the method comprises the steps: taking the minimization of the transient impedance difference of parallel MOSFET branches as a target, carrying out the optimization of an original PCB layout, and obtaining an optimized PCB layout; for the optimized PCB layout, extracting PCB parasitic parameters, and constructing an RLC parameter matrix; constructing a high-precision transmission line model containing a skin effect and dielectric loss based on the RLC parameter matrix; and embedding the high-precision transmission line model into the ideal circuit to obtain an optimized ideal circuit. According to the invention, the PCB layout is optimized based on the impedance equalization principle for the PCB with the problem of uneven current of the parallel anti-radiation switch tubes, so that the problem of uneven dynamic current distribution of the parallel switch tubes is solved. Meanwhile, based on the optimized PCB layout, a PCB multi-port RLC parasitic network model is established, so that an ideal circuit is optimized, and the simulation consistency of the power switch PCB and a theoretical circuit is improved.

Description

Technical Field

[0001] This application relates to the aerospace field, specifically to a PCB layout and theoretical circuit optimization method based on PCB parasitic parameters. Background Technology

[0002] In aerospace engineering practice, traditional high-voltage switching devices often employ a series-parallel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) architecture to achieve high-voltage switching functionality. However, this approach has significant limitations in practical applications: First, conventional MOSFETs lack sufficient radiation resistance, making them ill-suited for environments exposed to cosmic rays and high-energy particle radiation. Second, under ultra-high voltage (>10kV) conditions, a multi-transistor parallel structure is required to achieve circuit stability. However, due to the asymmetry of distributed parameters (resistance R, inductance L, capacitance C) introduced by PCB layout, the parallel branches exhibit significant current distribution imbalances. The deviation between the board-level switching current value and the theoretical circuit simulation results can reach 24%, leading to local device overheating, decreased system efficiency, and reliability risks. Currently, it is impossible to simultaneously meet the requirements of radiation resistance and flexible high-voltage switching. Summary of the Invention

[0003] To overcome at least one deficiency in the prior art, this application provides a PCB layout and theoretical circuit optimization method based on PCB parasitic parameters.

[0004] Firstly, a method for PCB layout and theoretical circuit optimization based on PCB parasitic parameters is provided, including: With the goal of minimizing the transient impedance difference of the parallel MOSFET branches, the original PCB layout was optimized to obtain the optimized PCB layout. For the optimized PCB layout, PCB parasitic parameters are extracted and an RLC parameter matrix is ​​constructed; based on the RLC parameter matrix, a high-precision transmission line model including skin effect and dielectric loss is constructed. By embedding a high-precision transmission line model into an ideal circuit, an optimized ideal circuit is obtained.

[0005] In one embodiment, optimizing the original PCB layout includes: Move the switch port positions to ensure that the normal directions of the parallel switch ports on the top and bottom layers of the PCB overlap; Remove the bottom ring plane of the PCB to ensure that the stack-up structure, trace length and trace width of the parallel MOSFET branch are consistent; Extend the trace of the source terminal of the MOSFET on the bottom layer of the PCB to ensure that the source terminal of the MOSFET and the PCB on the same side of the TVS diode share a common ground.

[0006] In one embodiment, optimizing the original PCB layout further includes replacing conventional devices with radiation-hardened MOSFETs.

[0007] Compared with existing technologies, this application has the following advantages: This application addresses the issue of uneven current distribution in parallel radiation-resistant switches on PCBs by optimizing the PCB layout based on the principle of impedance balancing, thereby resolving the problem of uneven dynamic current distribution in parallel switches. Simultaneously, based on the optimized PCB layout, a multi-port RLC parasitic network model is established to optimize the ideal circuit, thus improving the consistency between the power switch PCB and the theoretical circuit simulation. Attached Figure Description

[0008] This application can be better understood by referring to the description given below in conjunction with the accompanying drawings, which, together with the detailed description below, are incorporated in and form part of this specification. In the drawings: Figure 1 A schematic diagram showing the simulation results of the original PCB layout and the ideal circuit is presented; Figure 2 A schematic diagram of an ideal circuit embedded in a SPICE-compatible RLC equivalent circuit model is shown. Figure 3 A schematic diagram of the full-wave simulation of the PCB is shown; Figure 4 A flowchart of a PCB layout and theoretical circuit optimization method based on PCB parasitic parameters is shown. Figure 5 The diagram shows the simulation results of the optimized PCB layout and the optimized ideal circuit. Detailed Implementation

[0009] Exemplary embodiments of the present application will be described below with reference to the accompanying drawings. For clarity and brevity, not all features of the actual embodiments are described in the specification. However, it should be understood that many embodiment-specific decisions can be made in the development of any such actual embodiment to achieve the developer’s specific objectives, and these decisions may vary as the embodiments differ.

[0010] It should also be noted that, in order to avoid obscuring this application with unnecessary details, only the device structure closely related to the solution according to this application is shown in the accompanying drawings, while other details that are not closely related to this application are omitted.

[0011] It should be understood that this application is not limited to the described embodiments by virtue of the following description with reference to the accompanying drawings. In this document, embodiments may be combined with each other, features may be substituted or borrowed between different embodiments, and one or more features may be omitted in one embodiment, where feasible.

[0012] The first stage involves PCB prototype simulation and problem diagnosis based on transmission line theory.

[0013] In the electromagnetic field-circuit co-simulation platform, the full-wave electromagnetic field of the original PCB layout is solved to obtain the change of current over time.

[0014] Treating the PCB traces in the original PCB layout as non-ideal transmission line structures, a high-precision transmission line model incorporating skin effect and dielectric loss is constructed by extracting PCB parasitic parameters and building an RLC parameter matrix (resistance R, inductance L, capacitance C). This model is then embedded into an ideal circuit for switching transient simulation. By comparing the simulation results of the ideal circuit (ignoring PCB parasitics) with those of the PCB model including transmission line effects, the dynamic current imbalance of parallel MOSFET branches is quantified. Simulation results show that the original PCB layout leads to a significant dynamic current distribution mismatch between parallel MOSFET branches, with a peak current distribution deviation of up to 24.8% between different parallel MOSFET branches, compared to a deviation of 12.3%–13% compared to the ideal circuit simulation. Figure 1 A schematic diagram showing the original PCB layout and the simulation results of the ideal circuit is presented.

[0015] This stage reveals that the transmission line impedance discontinuity and asymmetric electromagnetic coupling introduced by the original PCB layout are the core reasons for the uneven current distribution of parallel MOSFETs on the PCB.

[0016] In the second phase, in response to the problems identified above, we conducted RLC parameter extraction and parasitic effect verification for PCB multi-port circuits.

[0017] First, define the target PCB area in the original PCB layout. This area must at least cover the parallel switching transistors (Q1~Qn), the drive circuit, and key routing nodes (such as inflection points). Set the source (S), gate (G), drain (D), positive power input (Vin+), and common ground (GND) of each switching transistor as the electrical ports of the network.

[0018] Electromagnetic field simulation tools were used to extract the self-inductance, mutual inductance, resistance, and capacitance parameters between ports in frequency bands 10 times higher than the switching frequency. Based on the extracted parameters, a SPICE-compatible RLC equivalent circuit model was constructed, i.e., a multi-port SPICE model containing the original PCB RLC matrix parameters. This model must include parasitic elements to ground at each port, capacitive coupling between ports, and inductive coupling relationships described by mutual inductance coefficients. The SPICE-compatible RLC equivalent circuit model was embedded into an ideal circuit and simulated to reproduce the current unevenness phenomenon observed in the PCB full-wave simulation. Figure 2 A schematic diagram of an ideal circuit embedded in a SPICE-compatible RLC equivalent circuit model is shown. Figure 3 A schematic diagram of the full-wave simulation of the PCB is shown.

[0019] To address the above problems, embodiments of this application provide a PCB layout and theoretical circuit optimization method based on PCB parasitic parameters. Figure 4 A flowchart illustrating a PCB layout and theoretical circuit optimization method based on PCB parasitic parameters is shown. (See attached image.) Figure 4 The method mainly includes the following steps: Step S1: Optimize the original PCB layout with the goal of minimizing the transient impedance difference of the parallel MOSFET branches to obtain the optimized PCB layout.

[0020] Specifically, the original PCB layout is optimized, including: Move the switch port positions to ensure that the normal directions of the parallel switch ports located on the top and bottom layers of the PCB overlap; Remove the bottom ring plane of the PCB to ensure that the stack-up structure, trace length and trace width of the parallel MOSFET branches are consistent, so as to eliminate the geometric asymmetry of the PCB. Extend the trace of the source terminal of the MOSFET on the bottom layer of the PCB to ensure that the source terminal of the MOSFET and the PCB on the same side of the TVS diode share a common ground.

[0021] Step S2: For the optimized PCB layout, extract PCB parasitic parameters and construct an RLC parameter matrix; based on the RLC parameter matrix, construct a high-precision transmission line model (i.e., PCB multi-port RLC parasitic network model) that includes skin effect and dielectric loss.

[0022] Step S3: Embed the high-precision transmission line model into the ideal circuit to obtain the optimized ideal circuit.

[0023] The optimized PCB layout was then used in an electromagnetic field-circuit co-simulation platform to solve for the full-wave electromagnetic field. Figure 5 The simulation results of the optimized PCB layout and the optimized ideal circuit are shown in the diagram. The simulation results show that the deviation of the parallel MOSFET branch current corresponding to the optimized PCB layout is reduced from 24.8% to 0.2% of that of the original PCB layout. At the same time, the deviation of the current waveform of the PCB switch from the simulation waveform of the ideal circuit is reduced to 0.1%.

[0024] Furthermore, optimizing the original PCB layout also includes replacing conventional components with radiation-resistant MOSFETs to address the reliability issues of switching devices under cosmic ray and high-energy particle radiation environments.

[0025] In summary, this application constructs an RLC parameter matrix, equates PCB parasitic effects to a multi-port SPICE model, and embeds this model into an ideal circuit to form a co-simulation of PCB parasitic parameters and circuit lumped parameters. This is used for impedance balancing design and verification of parallel paths in switching power supplies, thereby reducing the deviation of switching transistor current in board-level simulation and circuit-level simulation to 0.1% and improving the reliability of switching control.

[0026] The above descriptions are merely various embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A PCB layout and theoretical circuit optimization method based on PCB parasitic parameters, characterized in that, include: With the goal of minimizing the transient impedance difference of the parallel MOSFET branches, the original PCB layout was optimized to obtain the optimized PCB layout. For the optimized PCB layout, PCB parasitic parameters are extracted and an RLC parameter matrix is ​​constructed; based on the RLC parameter matrix, a high-precision transmission line model including skin effect and dielectric loss is constructed. The high-precision transmission line model is embedded into the ideal circuit to obtain the optimized ideal circuit.

2. The method as described in claim 1, characterized in that, The optimization of the original PCB layout includes: Move the switch port positions to ensure that the normal directions of the parallel switch ports on the top and bottom layers of the PCB overlap; Remove the bottom ring plane of the PCB to ensure that the stack-up structure, trace length and trace width of the parallel MOSFET branch are consistent; Extend the trace of the source terminal of the MOSFET on the bottom layer of the PCB to ensure that the source terminal of the MOSFET and the PCB on the same side of the TVS diode share a common ground.

3. The method as described in claim 1, characterized in that, The optimization of the original PCB layout also includes replacing conventional components with radiation-resistant MOSFETs.

Images