Gate driving circuit and display device including the same

Abstract

The invention relates to a gate driving circuit and a display device including the same. The display device includes a first GIP driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to sequentially output a scan signal; a first transmission circuit configured to selectively transmit a scan signal of the first GIP driver to a first scan line and a second scan line among the plurality of scan lines; and a second transmission circuit configured to selectively transmit a scan signal of the second GIP driver to the first scan line and the second scan line. Accordingly, the GIP driver design is performed without reducing the size of the GIP driver, and thus the GIP driver design is suitably applied to a high PPI or DRD type display panel.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a gating drive circuit capable of improving image quality and a display device including the gating drive circuit. Background Technology

[0002] Organic light-emitting diode (OLED) displays are self-emissive display devices. Unlike liquid crystal displays (LCDs), OLEDs do not require a separate light source. Therefore, OLEDs can be manufactured in a lightweight and thin manner. Furthermore, OLEDs are advantageous in terms of power consumption due to their low-voltage operation, and they also possess excellent color gamut, fast response time, wide viewing angle, and high contrast ratio (CR), thus they are being researched as next-generation displays.

[0003] The display device includes a gating driver that provides scan signals to scan lines of the display panel, and the gating driver is disposed on each of two opposite sides of the display panel in a gating-in-panel (GIP) manner.

[0004] The descriptions provided in the discussion of the Related Art section should not be assumed to be prior art simply because they are mentioned in or associated with that section. The discussion of the Related Art section may include information describing one or more aspects of the art of this subject matter, and the descriptions in this section do not limit this disclosure. Summary of the Invention

[0005] In a display device that includes a single-fed GIP driver, the left GIP driver is connected to the odd-numbered scan lines, and the right GIP driver is connected to the even-numbered scan lines. A limitation of this display device is that, in the edge areas of the display panel, image quality degrades due to the difference between the output inputs to locations farther from the left or right GIP driver and those to locations closer to the left or right GIP driver.

[0006] Furthermore, in display devices including dual-feed type GIP drivers, the number of scans in a DRD (dual-rate drive) type display device is twice that in a single-rate drive (SRD) type display device. Therefore, the number of GIP drivers in the former device is twice that in the latter. Consequently, the size of the GIP drivers in the DRD type device should be reduced to half that of the SRD type device, which leads to a further degradation in its output characteristics.

[0007] Furthermore, when double-feeding type GIP drivers are used in high pixel per inch (PPI) or DRD type display devices with narrow bezels, it is difficult to design smaller GIP drivers for small and medium-sized display panels.

[0008] Therefore, the inventors of this disclosure have invented a gating drive circuit suitable for high PPI or DRD schemes and a display device including the gating drive circuit.

[0009] The purpose of this disclosure is to provide a gating drive circuit suitable for high PPI or DRD schemes and a display device including the gating drive circuit.

[0010] Furthermore, the purpose of this disclosure is to provide a gating drive circuit that can improve image quality without degrading it even when applied to high-PPI or DRD schemes, and a display device including the gating drive circuit.

[0011] The purposes of this disclosure are not limited to those described above. Other purposes and advantages not mentioned in this disclosure may be understood based on the following description and may be more clearly understood based on embodiments according to this disclosure. Furthermore, it will be readily understood that the purposes and advantages of this disclosure can be achieved using the means set forth in the claims or a combination thereof.

[0012] A display device according to an exemplary embodiment of the present disclosure includes: a display panel including a plurality of scan lines; a first GIP (Gateway In-Panel) driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to sequentially output a scan signal; a first transmission circuit configured to selectively transmit the scan signal of the first GIP driver to a first scan line and a second scan line among the plurality of scan lines; and a second transmission circuit configured to selectively transmit the scan signal of the second GIP driver to the first scan line and the second scan line.

[0013] According to some implementations, in a first frame, the first transmission circuit is configured to transmit a scan signal output from the first GIP driver to one of the first scan line and the second scan line, and the second transmission circuit is configured to transmit a scan signal output from the second GIP driver to the other scan line of the first scan line and the second scan line. In a second frame following the first frame, the first transmission circuit is configured to transmit a scan signal output from the first GIP driver to the other scan line of the first scan line and the second scan line, and the second transmission circuit is configured to transmit a scan signal output from the second GIP driver to the other scan line of the first scan line and the second scan line.

[0014] According to some embodiments, the first GIP driver and the second GIP driver are respectively disposed on opposite sides of the display panel, the first transmission circuit is disposed between the display panel and the first GIP driver and connected to the display panel and the first GIP driver, and the second transmission circuit is disposed between the display panel and the second GIP driver and connected to the display panel and the second GIP driver.

[0015] A gating drive circuit according to an exemplary embodiment of the present disclosure includes: a first GIP driver disposed on the left side of a display panel; and a second GIP driver disposed on the right side of the display panel, wherein the scan signal of the first GIP driver is transmitted to an odd-numbered scan line among a plurality of scan lines in the nth frame and to an even-numbered scan line in the (n+1)th frame, where n is a positive integer, and the scan signal of the second GIP driver is transmitted to the even-numbered scan line in the nth frame and to the odd-numbered scan line in the (n+1)th frame.

[0016] A display device according to another exemplary embodiment of the present disclosure includes: a display panel including a plurality of scan lines and a plurality of sensing lines; a first GIP driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to sequentially output a scan signal and sequentially output a sensing signal to the display panel; a first transmission circuit configured to alternately transmit the scan signal of the first GIP driver to a first scan line and a second scan line among the plurality of scan lines, and to alternately transmit the sensing signal of the first GIP driver to a first sensing line and a second sensing line among the plurality of sensing lines; and a second transmission circuit configured to alternately transmit the scan signal of the second GIP driver to the first scan line and the second scan line, and to alternately transmit the sensing signal of the second GIP driver to the first sensing line and the second sensing line.

[0017] According to some implementations, the first GIP driver and the second GIP driver are respectively disposed on opposite sides of the display panel.

[0018] A gating drive circuit according to another exemplary embodiment of the present disclosure includes: a first GIP driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to sequentially output a scan signal and sequentially output a sensing signal; a first transmission circuit configured to alternately transmit the scan signal of the first GIP driver to a first scan line and a second scan line among a plurality of scan lines, and to alternately transmit the sensing signal of the first GIP driver to a first sensing line and a second sensing line among a plurality of sensing lines; and a second transmission circuit configured to alternately transmit the scan signal of the second GIP driver to the first scan line and the second scan line, and to alternately transmit the sensing signal of the second GIP driver to the first sensing line and the second sensing line.

[0019] According to an exemplary embodiment of this disclosure, in a display device, within the same frame, one of the scan signal output terminals of the first GIP driver and the second GIP driver is selectively connected to one of the odd-numbered and even-numbered scan lines among a plurality of scan lines, while the other of the scan signal output terminals of the first GIP driver and the second GIP driver is selectively connected to the other of the odd-numbered and even-numbered scan lines among a plurality of scan lines. Conventionally, in the edge regions of the display panel, image quality degrades due to the difference between output inputs to locations farther from the left or right GIP driver and output inputs to locations closer to the left or right GIP driver. However, using the configuration described above in this disclosure, this difference can be eliminated, allowing the brightness of the display panel to be maintained at an average brightness in the edge regions.

[0020] Furthermore, within the same frame, the display device connects one of the sensing signal output terminals of the first GIP driver and the second GIP driver to one of the odd-numbered and even-numbered sensing lines among the multiple sensing lines, and connects the other of the sensing signal output terminals of the first GIP driver and the second GIP driver to the other of the odd-numbered and even-numbered sensing lines among the multiple sensing lines. Conventionally, in the edge regions of the display panel, image quality degrades due to the difference between the output inputs to locations farther from the left or right GIP driver and those to locations closer to the left or right GIP driver. However, using the configuration described above, this difference can be eliminated, allowing the brightness of the display panel to remain at an average brightness in the edge regions.

[0021] Furthermore, the display device selectively connects the corresponding outputs of the first GIP driver 300a and the second GIP driver to the two scan lines, respectively. Therefore, it is not necessary to reduce the GIP driver size by half, thereby improving output characteristics compared to existing DRD solutions.

[0022] Furthermore, the display device selectively connects the respective outputs of the first GIP driver and the second GIP driver to two scan lines, thereby facilitating the design of GIP drivers for small and medium-sized display panels with high PPI or DRD schemes.

[0023] Furthermore, within one of the two consecutive frames, the display device outputs one of the scan signals from the first GIP driver and the second GIP driver to one of the odd-numbered and even-numbered scan lines, and outputs the other of the scan signals from the first GIP driver and the second GIP driver to the other of the odd-numbered and even-numbered scan lines. Therefore, the brightness and darkness levels of the pixels are uniform, thereby preventing defects in the shape of the column lines.

[0024] Furthermore, within one of the two consecutive frames, the display device outputs one of the scan signals from the first GIP driver 300a and the second GIP driver to one of the odd-numbered and even-numbered scan lines, and outputs the other of the scan signals from the first GIP driver and the second GIP driver to the other of the odd-numbered and even-numbered scan lines. In the other frame of the two consecutive frames, the display device outputs one of the scan signals from the first GIP driver and the second GIP driver to the other of the odd-numbered and even-numbered scan lines, and outputs the other of the scan signals from the first GIP driver and the second GIP driver to the other of the odd-numbered and even-numbered scan lines, thereby enabling the display device to improve image quality.

[0025] Furthermore, the display device selectively connects the corresponding outputs of the first and second GIP drivers to the two scan lines, respectively. Therefore, there is no need to reduce the size of the GIP drivers, and thus the display device DD can be appropriately applied to high-PPI or DRD-type display panels.

[0026] The effects of this disclosure are not limited to those described above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

[0027] In addition to the effects described above, the specific effects of this disclosure are also described along with the specific details for performing this disclosure.

[0028] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0029] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and constituting a part of this application, illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0030] Figure 1 This is a block diagram illustrating an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0031] Figure 2 This is an example diagram illustrating an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0032] Figure 3 This is a circuit diagram of an example of pixels included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0033] Figure 4 This is a circuit diagram of an example gating driver included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0034] Figure 5 This is a circuit diagram of another example of a gating driver included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0035] Figure 6 This is a circuit diagram of another example of pixels included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0036] Figure 7 This is a circuit diagram of yet another example of a gating driver included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0037] Figure 8 This is a plan view of a display panel included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0038] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The relative dimensions and depictions of these elements may be exaggerated for clarity, illustrative purposes, and convenience. Detailed Implementation

[0039] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of corresponding elements used in the following description may be chosen solely for ease of writing and therefore may differ from the names used in actual products.

[0040] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become apparent from the exemplary embodiments described below in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, these exemplary embodiments are set forth only to complete this disclosure and to fully inform those skilled in the art to which this disclosure pertains, and this disclosure is limited only by the scope of the claims.

[0041] For simplicity and clarity, the elements in the accompanying drawings are not necessarily drawn to scale. The same reference numerals in different drawings denote the same or similar elements and therefore perform similar functions. Furthermore, for the sake of simplicity, descriptions and details of well-known steps and elements have been omitted. In addition, numerous specific details are set forth in the following detailed description of this disclosure to provide a thorough understanding of the disclosure. However, it should be understood that this disclosure can be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of this disclosure. Examples of various exemplary embodiments are further shown and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. Rather, it is intended to cover substitutions, modifications, and equivalents that may be included within the technical concept and scope of this disclosure as defined by the appended claims.

[0042] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings for illustrating embodiments of this disclosure are illustrative and this disclosure is not limited thereto. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular constructions of “a” and “an” are also intended to include the plural constructions, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” “consisting of,” “made of,” “formed from,” etc., as used in this disclosure specify the presence of the stated features, integers, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term “and / or” includes any and all combinations of one or more associated listed items. Expressions such as “at least one” preceding the list of elements may modify the list of elements as a whole without modifying the individual elements of the list.

[0043] For example, the meaning of "at least one of the first element, the second element, and the third element" includes all three listed elements, any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0044] In the interpretation of numerical values, errors or tolerances may occur even without explicit description.

[0045] Furthermore, it should be understood that when a first element or layer is referred to as existing "on," "above," "above," or "over" a second element or layer, the first element may be directly disposed on the second element or may be indirectly disposed on the second element, wherein a third element or layer is disposed between the first element or layer and the second element or layer. It should be understood that when a first element or layer is referred to as being "connected to" or "attached to" a second element or layer, the first element may be directly connected to or attached to the second element or layer, or one or more intermediate elements or layers may exist between the first element or layer and the second element or layer. Furthermore, it should be understood that when an element or layer is referred to as being "between two elements or layers," it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also exist therebetween.

[0046] Furthermore, as used herein, when a layer, film, region, plate, etc., is disposed "above" or "on top of" another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc., can be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc., is directly disposed "above" or "on top of" another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc., is not disposed between the former and the latter. Furthermore, as used herein, when a layer, film, region, plate, etc., is disposed "below" or "under" another layer, film, region, plate, etc., the former can directly contact the latter, or another layer, film, region, plate, etc., can be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc., is directly disposed "below" or "under" another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc., is not disposed between the former and the latter.

[0047] In descriptions of temporal relationships, such as temporal precedence relationships between two events, like "after," "following," and "before," unless specified as "directly after," "directly following," or "directly before," another event may occur in between. When an implementation can be different, the functions or operations specified in a particular block may occur in a different order than those specified in the flowchart. For example, two consecutive blocks may actually be executed substantially simultaneously, or the two blocks may be executed in reverse order depending on the functions or operations involved.

[0048] It should be understood that although the terms “first,” “second,” “third,” “A,” “B,” “C,” “(A),” “(B),” or “(C)”, etc., may be used herein to describe various elements, components, regions, layers, and / or periods, these elements, components, regions, layers, and / or periods should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the technical concept and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0049] When exemplary implementations can be implemented differently, the functions or operations specified within a particular block can be executed in a different order than those specified in the flowchart. For example, two consecutive blocks can be executed substantially simultaneously, or blocks can be executed in reverse order based on the associated functions or operations.

[0050] Features of the various exemplary embodiments of this disclosure can be combined partially or completely with each other, and can be technically related to or operable on each other. Embodiments can be implemented independently of each other, or can be implemented together in an associated relationship.

[0051] When interpreting numerical values, the value is interpreted to include a range of error unless otherwise explicitly described. Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0052] As used herein, terms such as “implementation,” “example,” and “aspect” should not be construed as making any described aspect or design superior to or more advantageous than other aspects or designs. Furthermore, the term “or” means “inclusive or,” not “exclusive or.” That is, unless otherwise stated or clearly apparent from the context, the expression “x uses a or b” implies that one of the permutations is naturally included.

[0053] The terms used in the description below are chosen to be general and common in the relevant art. However, depending on the development and / or changes of the technology, conventions, the preferences of those skilled in the art, etc., other terms may exist besides these. Therefore, the terms used in the description set forth below should not be construed as limiting the technical concept, but should be understood as examples of terms used to describe embodiments. Furthermore, in certain cases, terms may be arbitrarily chosen by the applicant, and in such cases, their detailed meanings will be described in the corresponding description. Therefore, the terms used in the description set forth below should be understood not only based on the name of the term, but also on the meaning of the term and its content throughout the specific embodiments.

[0054] In the description of signal flow, for example, when a signal is passed from node A to node B, this may include cases where the signal is passed from node A to node B via another node, unless the phrases "immediately passed" or "directly passed" are used. Throughout this disclosure, unless otherwise stated, "A and / or B" means A, B, or A and B, and unless otherwise stated, "C to D" means including C to including D.

[0055] As used herein, the first direction, second direction, and third direction, or the X-axis direction, Y-axis direction, and Z-axis direction, should not be interpreted solely as having a geometric relationship where the first direction, second direction, and third direction are perpendicular to each other or where the X-axis direction, Y-axis direction, and Z-axis direction are perpendicular to each other. However, they can be interpreted, to the extent that the configuration of this disclosure is functionally effective, as having a geometric relationship where the first direction, second direction, and third direction intersect each other at an angle other than 90 degrees or where the X-axis direction, Y-axis direction, and Z-axis direction intersect each other at an angle other than 90 degrees. In the plan view of the display device, intersecting column directions and row directions are used to define the extension direction of components (e.g., lines).

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein. For example, the terms “component” or “unit” may be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0057] Features of the various exemplary embodiments of this disclosure can be combined with each other in part or in whole, and can be technically related to and operate on each other. Implementations can be implemented independently of each other, or they can be implemented together in an associated relationship.

[0058] Various exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0059] In the following, a gating drive circuit suitable for high PPI or DRD schemes and a display device including the gating drive circuit will be described according to embodiments of the present disclosure.

[0060] Figure 1 This is a block diagram illustrating an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0061] A display device may include a display panel and display driving circuitry as components for displaying one or more images. (See reference) Figure 1 The display device 10 includes: a display panel 100 including a plurality of pixels P; a controller 200; a gate driver 300 configured to provide a scan signal SC to the plurality of pixels P; a data driver 400 configured to provide a data voltage Vdata to the plurality of pixels P; and a power supply 500 configured to provide the voltage required to drive the plurality of pixels P.

[0062] In the display panel 100, multiple scan lines SCL and multiple data lines DL intersect each other, and each of multiple pixels P is connected to the scan lines SCL and data lines DL. Each of the multiple data lines DL can be configured to extend in a first direction. Each of the multiple scan lines SCL can be configured to extend in a second direction different from the first direction.

[0063] Specifically, a pixel P receives the scan signal SC through the scan line SCL, the data voltage Vdata through the data line DL, and the reference voltage Vref, the high-potential drive voltage ELVDD, and the low-potential drive voltage ELVSS from the power supply 500.

[0064] The scan line SCL provides the scan signal SC and the sensing signal to pixel P, and the data line DL provides the data voltage Vdata to pixel P. Furthermore, according to various exemplary embodiments, the sensing line for providing the sensing signal can be connected to the scan line SCL and can also be connected separately to pixel P.

[0065] In addition, multiple pixels P can receive high-potential driving voltage ELVDD and low-potential driving voltage ELVSS via power lines, and can receive reference voltage Vref via reference voltage line RL.

[0066] For example, power supply 500 outputs high-potential drive voltage ELVDD and low-potential drive voltage ELVSS, etc., based on an externally supplied external input voltage, to provide these voltages to multiple pixels P.

[0067] Furthermore, each pixel P includes a light-emitting element and a pixel circuit for controlling the driving of the light-emitting element. The pixel circuit includes multiple switching elements, driving elements, and capacitors. For example, the pixel circuit can be composed of 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C, etc., but is not limited to these. Each of the switching elements and driving elements can be embodied as a thin-film transistor. In the pixel circuit, the driving element controls the amount of current supplied to the light-emitting element according to the data voltage to adjust the amount of light emitted from the light-emitting element. Furthermore, multiple switching elements receive a scan signal SC provided through multiple scan lines SCL and a reference voltage Vref provided through a reference voltage line RL, and operate the pixel circuit based on the received scan signal and the received reference voltage.

[0068] Display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. Transmissive display panels can be applied to transparent display devices, where an image is displayed on the screen, and real objects in the background are visible to a viewer in front of the display device. Display panel 100 can be manufactured as a flexible display panel. Flexible display panels can be implemented as OLED panels using a plastic substrate.

[0069] Pixel P may include, but is not limited to, red, green, and blue pixels. Each pixel P may also include a white pixel. In another exemplary embodiment, pixel P may include cyan, magenta, and yellow pixels.

[0070] The touch sensor TS can be disposed on the display panel 100. Touch input can be sensed using a separate touch sensor or via a pixel P. The touch sensor can be implemented as an on-cell touch sensor or an add-on touch sensor, wherein the touch sensor is disposed on the screen of the display panel, or as an in-cell touch sensor, wherein the touch sensor is embedded in the display panel 100.

[0071] The controller 200 processes the RGB image data input from the host system to suit the size and resolution of the display panel 100, and provides the processed RGB image data to the data driver 400. The controller 200 uses synchronization signals input from an external source (e.g., clock signal CLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) to generate a gating control signal GCS and a data control signal DCS. The gating control signal GCS and the data control signal DCS are provided to the gating driver 300 and the data driver 400, respectively, to control the gating driver 300 and the data driver 400.

[0072] The voltage level of the gating control signal GCS output from controller 200 can be converted into gating on and gating off voltages by a level shifter, and can be provided to gating driver 300. The level shifter converts the low-level voltage of the gating control signal GCS to a gating low voltage VGL, and the high-level voltage of the gating control signal GCS to a gating high voltage VGH. The gating control signal GCS includes a start pulse and a shift clock.

[0073] The gating driver 300 provides the scan signal SC to the scan line SCL according to the gating control signal GCS. The gating driver 300 may be formed in the form of an integrated circuit (IC), but is not limited thereto. The gating driver 300 may be disposed on one side or each of the two opposite sides of the display panel 100 in a gating-in-panel (GIP) manner.

[0074] As another example, the gate driver 300 may be configured with at least one gate IC. As an example, the gate driver 300 may be connected to the display panel 100, for example, by tape automated bonding (TAB), chip-on-glass (COG), chip-on-board (COP), or chip-on-film (COF) methods, but is not limited thereto.

[0075] The gating driver 300 sequentially outputs scan signals SC to multiple scan lines SCL in response to a gating control signal GCS output from the controller 200. The gating driver 300 can sequentially provide the scan signals SC to the scan lines SCL by shifting the scan signals SC using a shift register. The scan signals SC may include scan signals that oscillate between a gating low voltage VGL and a gating high voltage VGH. Additionally, according to various exemplary embodiments, the gating driver 300 sequentially outputs sensing signals to multiple sensing lines SL. The sensing signals may include scan signals that oscillate between a gating low voltage VGL and a gating high voltage VGH.

[0076] The strobe driver 300 outputs a scan signal SCP in response to a start pulse and a shift clock from the controller 200, and shifts the scan signal sequentially according to the shift clock.

[0077] The data driver 400 converts image data RGB into data voltage Vdata according to the data control signal DCS output from the controller 200, and provides the converted data voltage Vdata to the pixel P through the data line DL.

[0078] although Figure 1 The diagram shows a data driver 400 disposed in a single manner on one side of the display panel 100, but the number and arrangement of the data drivers 400 are not limited thereto. For example, the data driver 400 may consist of multiple integrated circuits (ICs) that may be disposed on one side of the display panel 100. For example, the data driver 400 may be mounted in the form of integrated circuits (ICs) on the upper surface of the display panel 100, but is not limited thereto.

[0079] Power supply 500 generates the DC power required to drive the pixel array, gating driver 300, and data driver 400 of display panel 100. Power supply 500 may include a charge pump, regulator, buck converter, boost converter, etc.

[0080] Power supply 500 can receive input power from the host system and can generate DC voltages, such as a high-gated voltage VGH, a low-gated voltage VGL, a high-level drive voltage ELVDD, a low-level drive voltage ELVSS, and a reference voltage Vref. The low-gated voltage VGL and the high-gated voltage VGH can be supplied to the gated driver 300, and the high-level drive voltage ELVDD, the low-level drive voltage ELVSS, and the reference voltage Vref can be supplied to the pixel P. For example, the high-level drive voltage ELVDD can be supplied to the display panel 100 via a first power line, and the low-level drive voltage ELVSS can be supplied to the display panel 100 via a second power line, but this is not a limitation.

[0081] Figure 2 This is an example diagram illustrating an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0082] Reference Figure 2 The display device includes a display panel 100 and a first GIP driver 300a and a second GIP driver 300b respectively disposed on two opposite sides of the display panel 100. The first GIP driver 300a is disposed on the left side of the display panel 100 and the second GIP driver 300b is disposed on the right side of the display panel 100, but is not limited thereto.

[0083] Furthermore, the display device also includes a first transmission circuit 310a disposed between the display panel 100 and the first GIP driver 300a and connected to the display panel 100 and the first GIP driver 300a, and a second transmission circuit 310b disposed between the display panel 100 and the second GIP driver 300b and connected to the display panel 100 and the second GIP driver 300b. For example, the first transmission circuit 310a may be disposed on the left side of the display panel 100, and the second transmission circuit 310b may be disposed on the right side of the display panel 100, but is not limited thereto.

[0084] In this disclosure, the gating driver 300 may include a gating driving circuit, and the gating driving circuit may include a first GIP driver 300a, a second GIP driver 300b, a first transmission circuit 310a and a second transmission circuit 310b, but is not limited thereto.

[0085] Each of the first GIP driver 300a and the second GIP driver 300b can sequentially output the scan signal SC to multiple scan lines SCL1, SCL2 to SCLn by shifting the scan signal SC using a shift register comprising multiple stages.

[0086] The first transmission circuit 310a selectively connects one of the multiple outputs of the first GIP driver 300a to two of the multiple scan lines SCL1, SCL2 to SCLn. In this regard, the output of the first GIP driver 300a can be defined as the output terminal for outputting scan signals. For example, the first transmission circuit 310a may alternately connect the output of the first GIP driver 300a to the odd-numbered scan line SCL1 and the even-numbered scan line SCL2 within two consecutive frames, but is not limited thereto.

[0087] The second transmission circuit 310b selectively connects one of the multiple outputs of the second GIP driver 300b to two scan lines among the multiple scan lines SCL1, SCL2 to SCLn. In this regard, the output of the second GIP driver 300b can be defined as the output terminal for outputting scan signals. For example, the second transmission circuit 310b can alternately connect the output of the second GIP driver 300b to the even-numbered scan line SCL2 and the odd-numbered scan line SCL1 within two consecutive frames.

[0088] Alternatively, the first transmission circuit 310a can alternately output the scan signal of the first GIP driver 300a to odd-numbered scan lines and odd-numbered scan lines within consecutive frames, and can also alternately output the sensing signal of the first GIP driver 300a to odd-numbered sensing lines and odd-numbered sensing lines within consecutive frames. The second transmission circuit 310b can alternately output the scan signal of the second GIP driver 300b to odd-numbered scan lines and odd-numbered scan lines within consecutive frames, and can also alternately output the sensing signal of the second GIP driver 300b to odd-numbered sensing lines and odd-numbered sensing lines within consecutive frames.

[0089] exist Figure 2 In the figures, SDIC (not described) represents a source driver. Data driver 400 may include multiple source driver SDICs. Each source driver SDIC converts image data RGB into a data voltage and provides the converted data voltage to pixel PX via data line DL.

[0090] Figure 3 This is a circuit diagram of an example of pixels included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0091] Reference Figure 3 A pixel PX is defined by scan lines SCL, data lines DL, power lines, and reference voltage lines RL. Scan transistors SCT, drive transistors DT, light-emitting elements OLED, sensing transistors SENT, and storage capacitors Cst are disposed within a pixel, but are not limited to these. More or fewer components may be included.

[0092] The scan transistor SCT is used to select the pixel to be driven by applying a data voltage Vdata to the drive transistor DT. The scan transistor SCT is located in the region where the scan line SCL and the data line DL intersect. The scan transistor SCT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the scan line SCL. The source electrode is connected to the data line DL, and the drain electrode is connected to the drive transistor DT.

[0093] In this disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode are used interchangeably. A source electrode can be a drain electrode, and a drain electrode can be a source electrode. Furthermore, a source electrode in any aspect of this disclosure can be a drain electrode in another aspect of this disclosure, and a drain electrode in any aspect of this disclosure can be a source electrode in another aspect of this disclosure.

[0094] The driving transistor DT is used to drive the light-emitting element OLED of the pixel selected by the scanning transistor SCT. The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to the drain electrode SD of the scanning transistor SCT, a first electrode such as the source electrode is connected to a power supply line to which a high-potential driving voltage ELVDD is applied, and a second electrode such as the drain electrode is connected to the anode of the light-emitting element OLED.

[0095] The storage capacitor Cst is used to sample the data voltage Vdata. The storage capacitor Cst includes one electrode and another electrode. One electrode of the storage capacitor Cst is connected to the node between the drain electrode of the scan transistor SCT and the gate electrode of the drive transistor DT, and the other electrode of the storage capacitor Cst is connected to the node between the drain electrode of the drive transistor DT and the anode of the light-emitting element OLED. For example, the storage capacitor Cst may be disposed between the gate electrode and the drain electrode of the drive transistor DT, but is not limited thereto.

[0096] An OLED is configured to emit light by itself and to modulate the intensity of the light emitted from it according to the amount of current flowing therein. For example, an OLED can be embodied as an organic light-emitting diode (OLED). An OLED includes an anode, an emissive layer, and a cathode. The anode of the OLED is connected to the drain electrode of the driving transistor DT and the other electrode of the storage capacitor Cst, the cathode of the OLED is connected to a power line to which a low-potential driving voltage ELVSS is applied, and the emissive layer is disposed between the anode and the cathode.

[0097] For example, the light-emitting layer may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), but this disclosure is not limited thereto.

[0098] A sensing transistor (SENT) is used to initialize the anode of an OLED and the other electrode of a storage capacitor Cst with a reference voltage Vref, or to sense pixel characteristics. The sensing transistor SENT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the sensing transistor SENT is connected to the scan line SCL, and the drain electrode of the sensing transistor SENT is connected to the anode of the OLED, the drain electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst. The source electrode of the sensing transistor SENT is connected to a reference voltage line RL, which is provided with the reference voltage Vref. According to various exemplary embodiments, the gate electrode of the sensing transistor SENT may be connected to a sensing line that provides a separate sensing signal.

[0099] For example, the drain electrode of the sensing transistor SENT is connected to the node between the anode of the light-emitting element OLED, the drain electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst.

[0100] The driving transistor DT adjusts the amount of current flowing through the light-emitting element OLED based on the magnitude of the data voltage Vdata.

[0101] Furthermore, according to some embodiments, at least one of the transistors in the pixel circuit can be formed as a P-type thin-film transistor or an N-type thin-film transistor. Each transistor, including the driving transistor, can be made of, for example, LTPS, oxide, monocrystalline silicon, or organic materials. The light-emitting element OLED can be embodied as a self-emissive diode, such as an organic light-emitting element or a micro-LED. The substrate on which the pixel PX is formed can be embodied as a glass substrate, a plastic substrate, a flexible plastic substrate, a wafer, or a flexible polymer film, etc.

[0102] For example, flexible polymer films can be made from any of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), these are merely examples and are not necessarily limited thereto.

[0103] Figure 4 This is a circuit diagram of an example gating driver included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure. Figure 5 This is a circuit diagram of another example of a gating driver included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0104] exist Figure 4 and Figure 5The diagram shows a first GIP driver 300a and a second GIP driver 300b, as well as one output of each of the two scan lines. However, this is shown for illustrative purposes, and each of the first GIP driver 300a and the second GIP driver 300b includes multiple outputs, and each of the multiple outputs can be selectively connected to the two scan lines.

[0105] Reference Figure 4 The display device includes a first GIP driver 300a and a second GIP driver 300b. Each of the first GIP driver 300a and the second GIP driver 300b may include multiple stages for sequentially providing scan signals to multiple scan lines. For ease of illustration, Figure 4 One of the multiple levels is shown.

[0106] Each of the multiple stages of the first GIP driver 300a includes, but is not limited to, logic circuitry 30a, pull-up transistor T1, and pull-down transistor T2. It may include more or fewer components.

[0107] Logic circuit 30a outputs a first drive signal to node Q and a second drive signal to node QB. Pull-up transistor T1 can pull up the output of first GIP driver 300a in response to the first drive signal. Pull-down transistor T2 can pull down the output of first GIP driver 300a in response to the second drive signal.

[0108] The pull-up transistor T1 has a gate electrode connected to the Q node, a first electrode such as a source electrode connected to a line to which the global clock GCLK is applied, and a second electrode such as a drain electrode connected to the output terminal. The pull-up transistor T1 outputs a scan signal containing a scan pulse at the point in time when a first drive signal at a high logic level is applied to the Q node and the global clock GCLK at a high logic level is applied to the Q node.

[0109] The pull-down transistor T2 has a gate electrode connected to the QB node, a first electrode such as a source electrode connected to a line to which a global low potential voltage GVSS is applied, and a second electrode such as a drain electrode connected to the output terminal. For example, the pull-down transistor T2 outputs a scan signal at a low logic level while a second drive signal at a high logic level is applied to the QB node.

[0110] Similarly, each of the multiple stages of the second GIP driver 300b includes a logic circuit 30b, a pull-up transistor T1', and a pull-down transistor T2'. The logic circuit 30b outputs a first drive signal to the Q node and a second drive signal to the QB node. The pull-up transistor T1' pulls up the output of the second GIP driver 300b in response to the first drive signal. The pull-down transistor T2' pulls down the output of the second GIP driver 300b in response to the second drive signal.

[0111] For example, pull-up transistor T1' outputs a scan signal including a scan pulse at the points when a first drive signal at a high logic level is applied to the Q node and a global clock GCLK at a high logic level is applied to it. For example, pull-down transistor T2' outputs a scan signal at a low logic level, while a second drive signal at a high logic level is applied to the QB node.

[0112] Additionally, the display device DD includes a first transmission circuit 310a and a second transmission circuit 310b. The first transmission circuit 310a is disposed between and connected to the display panel DP and the first GIP driver 300a, and is configured to selectively connect the output of the first GIP driver 300a to odd-numbered scan lines and even-numbered scan lines, such as the first scan line SCL1 and the second scan line SCL2.

[0113] The second transmission circuit 310b is disposed between and connected to the display panel DP and the second GIP driver 300b, and is configured to selectively connect the output of the second GIP driver 300b to odd-numbered and even-numbered scan lines, such as a first scan line SCL1 and a second scan line SCL2 among multiple scan lines. In this respect, the first scan line SCL1 can be an odd-numbered scan line among multiple scan lines, and the second scan line SCL2 can be an even-numbered scan line among multiple scan lines.

[0114] Within the first and second frames that occur sequentially, the first transmission circuit 310a can alternately transmit the scan signal output from the first GIP driver 300a to the first scan line and the second scan line, while the second transmission circuit 310b can alternately transmit the scan signal output from the second GIP driver 300b to the first scan line and the second scan line. This is such that within the first frame, the scan signal output from the first GIP driver 300a is transmitted to one of the first and second scan lines, while the scan signal output from the second GIP driver 300b is transmitted to the other of the first and second scan lines. Similarly, within the second frame, the scan signal output from the first GIP driver 300a is transmitted to the other of the first and second scan lines, while the scan signal output from the second GIP driver 300b is transmitted to one of the first and second scan lines.

[0115] In other words, within the first frame, the first transmission circuit 310a is configured to transmit the scan signal output from the first GIP driver 300a to one of the first scan line SCL1 and the second scan line SCL2, and the second transmission circuit 310b is configured to transmit the scan signal output from the second GIP driver 300b to the other of the first scan line SCL1 and the second scan line SCL2. In the second frame following the first frame, the first transmission circuit 310a is configured to transmit the scan signal output from the first GIP driver 300a to the other of the first scan line SCL1 and the second scan line SCL2, and the second transmission circuit 310b is configured to transmit the scan signal output from the second GIP driver 300b to one of the first scan line SCL1 and the second scan line SCL2.

[0116] For example, in an odd-numbered frame, the first transmission circuit 310a can transmit the scan signal of the first GIP driver 300a to the odd-numbered scan lines among the multiple scan lines, and the second transmission circuit 310b can transmit the scan signal of the second GIP driver 300b to the even-numbered scan lines among the multiple scan lines.

[0117] For example, in odd-numbered frames, the first transmission circuit 310a can transmit the scan signal of the first GIP driver 300a to the first scan line SCL1, and the second transmission circuit 310b can transmit the scan signal of the second GIP driver 300b to the second scan line SCL2.

[0118] For example, in an even-numbered frame, the first transmission circuit 310a can transmit the scan signal of the first GIP driver 300a to the even-numbered scan lines among the multiple scan lines, and the second transmission circuit 310b can transmit the scan signal of the second GIP driver 300b to the odd-numbered scan lines among the multiple scan lines.

[0119] For example, in even-numbered frames, the first transmission circuit 310a can transmit the scan signal of the first GIP driver 300a to the second scan line SCL2, and the second transmission circuit 310b can transmit the scan signal of the second GIP driver 300b to the first scan line SCL1.

[0120] The first transmission circuit 310a includes a first transmission transistor TS1 and a second transmission transistor TS2. The first transmission transistor TS1 outputs the scan signal of the first GIP driver 300a to the first scan line SCL1 in response to a first enable signal EN1. The second transmission transistor TS2 outputs the scan signal of the first GIP driver 300a to the second scan line SCL2 in response to a second enable signal EN2.

[0121] The gate electrode of the first transmission transistor TS1 is connected to the line to which the first enable signal EN1 is applied, its drain electrode is connected to the output terminal of the first GIP driver 300a, and its source electrode is connected to the first scan line SCL1.

[0122] The gate electrode of the second transmission transistor TS2 is connected to the line to which the second enable signal EN2 is applied, its drain electrode is connected to the output terminal of the first GIP driver 300a, and its source electrode is connected to the second scan line SCL2.

[0123] The second transmission circuit 310b includes a third transmission transistor TS3 and a fourth transmission transistor TS4. The third transmission transistor TS3 outputs the scan signal of the second GIP driver 300b to the first scan line SCL1 in response to the second enable signal EN2. The fourth transmission transistor TS4 outputs the scan signal of the second GIP driver 300b to the second scan line SCL2 in response to the first enable signal EN1.

[0124] The gate electrode of the third transmission transistor TS3 is connected to the line to which the second enable signal EN2 is applied, its drain electrode is connected to the output terminal of the second GIP driver 300b, and its source electrode is connected to the first scan line SCL1.

[0125] The gate electrode of the fourth transmission transistor TS4 is connected to the line to which the first enable signal EN1 is applied, its drain electrode is connected to the output terminal of the second GIP driver 300b, and its source electrode is connected to the second scan line SCL2.

[0126] The first enable signal EN1 and the second enable signal EN2 are alternately enabled in two consecutive frames. For example, the first enable signal EN1 can be enabled in odd-numbered frames. The first transmission transistor TS1 and the fourth transmission transistor TS4 can be turned on in response to the first enable signal EN1 in odd-numbered frames. In odd-numbered frames, the first transmission transistor TS1 transmits the scan signal of the first GIP driver 300a to the first scan line SCL1 in response to the first enable signal EN1, and the fourth transmission transistor TS4 transmits the scan signal of the second GIP driver 300b to the second scan line SCL2 in response to the first enable signal EN1.

[0127] Furthermore, for example, the second enable signal EN2 can be enabled in even-numbered frames. The second transmission transistor TS2 and the third transmission transistor TS3 can be turned on in response to the second enable signal EN2 in even-numbered frames. In even-numbered frames, the second transmission transistor TS2 transmits the scan signal of the first GIP driver 300a to the second scan line SCL2 in response to the second enable signal EN2, and the third transmission transistor TS3 transmits the scan signal of the second GIP driver 300b to the first scan line SCL1 in response to the second enable signal EN2.

[0128] The first enable signal EN1 and the second enable signal EN2 may have logic levels that are inverted relative to each other, but are not limited to this. Furthermore, within two consecutive frames, the logic levels of the first enable signal EN1 and the second enable signal EN2 may be inverted relative to each other. In the example, the first enable signal EN1 and the second enable signal EN2 may be applied from the logic circuits 30a and 30b of the first GIP driver 300a and the second GIP driver 300b, respectively, as... Figure 4 As shown. For example, the first enable signal EN1 and the second enable signal EN2 applied from logic circuit 30a can be applied to the first transfer transistor TS1 and the second transfer transistor TS2, and the first enable signal EN1 and the second enable signal EN2 applied from logic circuit 30b can be applied to the fourth transfer transistor TS4 and the third transfer transistor TS3, as shown. Figure 4 As shown. In another example, the first enable signal EN1 and the second enable signal EN2 can be applied from an external source of the display panel as external clock signals CLK1 and CLK2, as shown. Figure 5 As shown.

[0129] According to various exemplary embodiments, the first transmission circuit 310a can connect the output of the first GIP driver 300a to the first scan line SCL1 in the nth frame (n is a positive integer), and can connect the output of the first GIP driver 300a to the second scan line SCL2 in the (n+1)th frame. Furthermore, the second transmission circuit 310b can connect the output of the second GIP driver 300b to the second scan line SCL2 in the nth frame, and can connect the output of the second GIP driver 300b to the first scan line SCL1 in the (n+1)th frame.

[0130] According to various exemplary embodiments, in sub-pixel SP, such as Figure 3 As shown, the scan line SCL can be connected to the gate electrode of the scan transistor SCT, which provides the data voltage Vdata to the sub-pixel SP, and can also be connected to the gate electrode of the sensing transistor SENT, which provides the reference voltage Vref to the sub-pixel SP. For example, the scan line SCL can be connected to both the gate electrode of the scan transistor SCT and the gate electrode of the sensing transistor SENT. For example, the scan line SCL can be used as a sensing line SENL to apply a sensing signal to the sensing transistor SENT.

[0131] Therefore, the first transmission circuit 310a selectively transmits the sensing signal output from the first GIP driver 300a to one of the first sensing line SENL1 ​​and the second sensing line SENL2. The second transmission circuit 310b selectively transmits the sensing signal output from the second GIP driver 300b to one of the second sensing line SENL2 and the first sensing line SENL1.

[0132] For example, in the first frame, the first transmission circuit 310a selectively transmits the sensing signal output from the first GIP driver 300a to one of the first sensing line SENL1 ​​and the second sensing line SENL2. In the second frame following the first frame, the second transmission circuit 310b selectively transmits the sensing signal output from the second GIP driver 300b to one of the second sensing line SENL2 and the first sensing line SENL1.

[0133] According to various exemplary embodiments, in a first frame, a first transmission circuit 310a is configured to transmit a scan signal output from a first GIP driver 300a to one of a first sensing line SENL1 ​​and a second sensing line SENL2, and a second transmission circuit 310b is configured to transmit a scan signal output from a second GIP driver 300b to the other of a first sensing line SENL1 ​​and a second sensing line SENL2. In a second frame following the first frame, the first transmission circuit 310a is configured to transmit a scan signal output from a first GIP driver 300a to the other of a first sensing line SENL1 ​​and a second sensing line SENL2, and the second transmission circuit 310b is configured to transmit a scan signal output from a second GIP driver 300b to one of a first sensing line SENL1 ​​and a second sensing line SENL2.

[0134] Figure 6 This is a circuit diagram of another example of pixels included in an organic light-emitting display device according to an exemplary embodiment of this disclosure. Figure 6 In the pixel circuit shown, with Figure 3 Compared to the pixel circuit shown, the scan line SCL and the sensing line SENL are set separately in it.

[0135] Specifically, the scan line SCL is connected to the gate electrode of the scan transistor SCT that provides the data voltage Vdata to the sub-pixel, and the sensing line SENL is connected to the gate electrode of the sensing transistor SENT that provides the reference voltage Vref to the sub-pixel.

[0136] The gating drive circuit applied to the pixel will be described as follows.

[0137] Figure 7 This is a circuit diagram of yet another exemplary example of a gating driver included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0138] Reference Figure 7 The gating drive circuit includes a first GIP driver 300a, a second GIP driver 300b, a first transmission circuit 310a, and a second transmission circuit 310b.

[0139] The first GIP driver 300a and the second GIP driver 300b can be respectively disposed on two opposite sides of the display panel DP. The first GIP driver 300a is disposed on the left side of the display panel DP and outputs a scan signal and a sensing signal SENSE in sequence. The second GIP driver 300b is disposed on the right side of the display panel DP and outputs a scan signal and a sensing signal SENSE in sequence.

[0140] For example, the first transmission circuit 310a can be located on the left side of the display panel DP, and the second transmission circuit 310b can be located on the right side of the display panel DP, but is not limited thereto. The first transmission circuit 310a can be located between the display panel DP and the first GIP driver 300a and connected to the display panel DP and the first GIP driver 300a, and the second transmission circuit 310b can be located between the display panel DP and the second GIP driver 300b and connected to the display panel DP and the second GIP driver 300b.

[0141] Reference Figure 7 The gating drive circuit includes a first GIP driver 300a and a second GIP driver 300b. Each of the first GIP driver 300a and the second GIP driver 300b may include multiple stages for sequentially providing scan signals to multiple scan lines. For ease of illustration, Figure 7 One of the multiple levels is shown.

[0142] Each of the multiple stages of the first GIP driver 300a includes, but is not limited to, logic circuitry 30a, a first pull-up transistor T1, a first pull-down transistor T2, a second pull-up transistor T3, and a second pull-down transistor T4. It may include more or fewer components.

[0143] Logic circuit 30a outputs a first drive signal to node Q and a second drive signal to node QB. First pull-up transistor T1, in response to the first drive signal, pulls up the scan signal output terminal of the first GIP driver 300a. First pull-down transistor T2, in response to the second drive signal, pulls down the sensing signal output terminal of the first GIP driver 300a. Second pull-up transistor T3, in response to the first drive signal, pulls up the sensing signal output terminal of the first GIP driver 300a. Second pull-down transistor T4, in response to the second drive signal, pulls down the scan signal output terminal of the first GIP driver 300a.

[0144] The first pull-up transistor T1 has a gate electrode connected to the Q node, a first electrode such as a source electrode connected to a line to which a global clock GCLK is applied, and a second electrode such as a drain electrode connected to a scan signal output terminal. At the point in time when a first drive signal at a high logic level is applied to the Q node and a global clock GCLK at a high logic level is applied to the Q node, the first pull-up transistor T1 outputs a scan signal including a scan pulse.

[0145] In the first pull-down transistor T2, the gate electrode is connected to the QB node, a first electrode, such as the source electrode, is connected to a line to which a global low potential voltage GVSS is applied, and a second electrode, such as the drain electrode, is connected to the scan signal output terminal. The first pull-down transistor T2 outputs a scan signal at a low logic level, while a second drive signal at a high logic level is applied to the QB node.

[0146] The second pull-up transistor T3 has a gate electrode connected to the Q node, a first electrode such as a source electrode connected to a line to which a global clock GCLK is applied, and a second electrode such as a drain electrode connected to a sensing signal output terminal. The second pull-up transistor T3 outputs a sensing signal containing a sensing pulse at the point in time when a first drive signal at a high logic level is applied to the Q node and a global clock GCLK at a high logic level is applied to the Q node.

[0147] The second pull-down transistor T4 has a gate electrode connected to the QB node, a first electrode such as a source electrode connected to a line to which a global low potential voltage GVSS is applied, and a second electrode such as a drain electrode connected to the sense signal output terminal. The second pull-down transistor T4 outputs a sense signal at a low logic level, while a second drive signal at a high logic level is applied to the QB node.

[0148] For example, logic circuit 30a outputs a first drive signal to Q node, first pull-up transistor T1 pulls up the scan signal output terminal of first GIP driver 300a in response to the first drive signal applied to Q node, and second pull-up transistor T3 pulls up the sensing signal output terminal of first GIP driver 300a in response to the first drive signal applied to Q node.

[0149] For example, logic circuit 30a outputs a second drive signal to the QB node, first pull-down transistor T2 pulls down the scan signal output terminal of first GIP driver 300a in response to the second drive signal applied to the QB node, and second pull-down transistor T4 pulls down the sensing signal output terminal of first GIP driver 300a in response to the second drive signal applied to the QB node.

[0150] Similarly, each of the multiple stages of the second GIP driver 300b includes a logic circuit 30b, a first pull-up transistor T1', a first pull-down transistor T2', a second pull-up transistor T3', and a second pull-down transistor T4'. The logic circuit 30b outputs a first drive signal to the Q node and a second drive signal to the QB node. The first pull-up transistor T1' can pull up the scan signal output terminal of the second GIP driver 300b in response to the first drive signal. The first pull-down transistor T2' pulls down the sense signal output terminal of the second GIP driver 300b in response to the second drive signal. The second pull-up transistor T3' pulls up the sense signal output terminal of the second GIP driver 300b in response to the first drive signal. The second pull-down transistor T4' pulls down the scan signal output terminal of the second GIP driver 300b in response to the second drive signal.

[0151] The first transmission circuit 310a selectively outputs the scan signal of the first GIP driver 300a to the first scan line SCL1 and the second scan line SCL2 among multiple scan lines, and selectively outputs the sensing signal of the first GIP driver 300a to the first sensing line SENL1 ​​and the second sensing line SENL2 among multiple sensing lines. In this embodiment, the first sensing line SENL1 ​​can be an odd-numbered sensing line among multiple sensing lines SCL1, and the second sensing line SENL2 can be an even-numbered sensing line among multiple sensing lines SCL2. In this embodiment, the first scan line SCL1 can be an odd-numbered scan line among multiple scan lines, and the second scan line SCL2 can be an even-numbered scan line among multiple scan lines.

[0152] The second transmission circuit 310b selectively outputs the scan signal of the second GIP driver 300b to the first scan line SCL1 and the second scan line SCL2 among multiple scan lines, and selectively outputs the sensing signal of the second GIP driver 300b to the first sensing line SENL1 ​​and the second sensing line SENL2 among multiple sensing lines.

[0153] For example, in the first frame, the first transmission circuit 310a is configured to transmit the scan signal output from the first GIP driver 300a to one of the first scan line SCL1 and the second scan line SCL2, and the second transmission circuit 310b is configured to transmit the scan signal output from the second GIP driver 300b to the other of the first scan line SCL1 and the second scan line SCL2. In the second frame following the first frame, the first transmission circuit 310a is configured to transmit the scan signal output from the first GIP driver 300a to the other of the first scan line SCL1 and the second scan line SCL2, and the second transmission circuit 310b is configured to transmit the scan signal output from the second GIP driver 300b to one of the first scan line SCL1 and the second scan line SCL2. Furthermore, within the first frame, the first transmission circuit 310a is configured to transmit the sensing signal output from the first GIP driver 300a to one of the first sensing line SENL1 ​​and the second sensing line SENL2, and the second transmission circuit 310b is configured to transmit the sensing signal output from the second GIP driver 300b to the other of the first sensing line SENL1 ​​and the second sensing line SENL2. In the second frame following the first frame, the first transmission circuit 310a is configured to transmit the sensing signal output from the first GIP driver 300a to the other of the first sensing line SENL1 ​​and the second sensing line SENL2, and the second transmission circuit 310b is configured to transmit the sensing signal output from the second GIP driver 300b to one of the first sensing line SENL1 ​​and the second sensing line SENL2.

[0154] According to various exemplary embodiments, the scan signal output terminal of the first GIP driver 300a can be connected to an odd-numbered scan line among multiple scan lines in the nth frame (n is a positive integer), and can be connected to an even-numbered scan line among multiple scan lines in the (n+1)th frame. Furthermore, the scan signal output terminal of the second GIP driver 300b can be connected to an even-numbered scan line SCL2 in the nth frame, and can be connected to an odd-numbered scan line in the (n+1)th frame.

[0155] The sensing signal output terminal of the first GIP driver 300a can be connected to the odd-numbered sensing line among multiple sensing lines in the nth frame (n is a positive integer), and can be connected to the even-numbered sensing line in the (n+1)th frame. Furthermore, the sensing signal output terminal of the second GIP driver 300b can be connected to the even-numbered sensing line in the nth frame, and can be connected to the odd-numbered sensing line in the (n+1)th frame.

[0156] According to various exemplary embodiments, in a display device, within the same frame, one of the scan signal output terminals of the first GIP driver 300a and the second GIP driver 300b is selectively connected to one of the odd-numbered and even-numbered scan lines among a plurality of scan lines, while the other of the scan signal output terminals of the first GIP driver 300a and the second GIP driver 300b is selectively connected to the other of the odd-numbered and even-numbered scan lines among a plurality of scan lines. Conventionally, in the edge regions of the display panel, image quality degrades due to the difference between output inputs to locations farther from the left or right GIP driver and output inputs to locations closer to the left or right GIP driver. However, using the configuration described above in this disclosure, this difference can be eliminated, allowing the brightness of the display panel to be maintained at an average brightness in the edge regions.

[0157] Furthermore, within the same frame, the display device connects one of the sensing signal output terminals of the first GIP driver 300a and the second GIP driver 300b to one of the odd-numbered and even-numbered sensing lines among the multiple sensing lines, and connects the other of the sensing signal output terminals of the first GIP driver 300a and the second GIP driver 300b to the other of the odd-numbered and even-numbered sensing lines among the multiple sensing lines. Conventionally, in the edge areas of the display panel, image quality degrades due to the difference between the output input to a location farther from the left or right GIP driver and the output input to a location closer to the left or right GIP driver. However, using the configuration described above, this difference can be eliminated, allowing the brightness of the display panel to remain at an average brightness in the edge areas.

[0158] Furthermore, the display device selectively connects the respective outputs of the first GIP driver 300a and the second GIP driver 300b to the two scan lines, respectively. Therefore, it is not necessary to reduce the GIP driver size by half, thereby improving output characteristics compared to existing DRD solutions.

[0159] Furthermore, the display device selectively connects the respective outputs of the first GIP driver 300a and the second GIP driver 300b to two scan lines, thereby facilitating the design of GIP drivers for small and medium-sized display panels with high PPI or DRD schemes.

[0160] Furthermore, within one of two consecutive frames, the display device outputs one of the scan signals from the first GIP driver 300a and the second GIP driver 300b to one of the odd-numbered and even-numbered scan lines, and outputs the other of the scan signals from the first GIP driver 300a and the second GIP driver 300b to the other of the odd-numbered and even-numbered scan lines. In the other of the two consecutive frames, the display device outputs one of the scan signals from the first GIP driver 300a and the second GIP driver 300b to the other of the odd-numbered and even-numbered scan lines, and outputs the other of the scan signals from the first GIP driver 300a and the second GIP driver 300b to one of the odd-numbered and even-numbered scan lines. Therefore, the brightness and darkness levels of the pixels are uniform, thereby preventing defects in the shape of the column lines.

[0161] For example, within the first frame, the first transmission circuit 310a can be configured to transmit a scan signal from the first GIP driver 300a to one of the first scan line SCL1 and the second scan line SCL2, and to transmit a sensing signal from the first GIP driver 300a to one of the first sensing line SENL1 ​​and the second sensing line SENL2, while the second transmission circuit 310b can be configured to transmit a scan signal from the second GIP driver 300b to the other of the first scan line SCL1 and the second scan line SCL2, and to transmit a sensing signal from the second GIP driver 300b to the other of the first sensing line SENL1 ​​and the second sensing line SENL2.

[0162] Furthermore, within one of the two consecutive frames, the display device outputs one of the scan signals of the first GIP driver 300a and the second GIP driver 300b to one of the odd-numbered and even-numbered scan lines, and outputs the other of the scan signals of the first GIP driver 300a and the second GIP driver 300b to the other of the odd-numbered and even-numbered scan lines. In the other frame of the two consecutive frames, the display device outputs one of the scan signals of the first GIP driver 300a and the second GIP driver 300b to the other of the odd-numbered and even-numbered scan lines, and outputs the other of the scan signals of the first GIP driver 300a and the second GIP driver 300b to one of the odd-numbered and even-numbered scan lines, thereby improving the image quality.

[0163] Furthermore, the display device selectively connects the corresponding outputs of the first GIP driver 300a and the second GIP driver 300b to the two scan lines, respectively. Therefore, there is no need to reduce the size of the GIP drivers, and thus the display device DD can be appropriately applied to high-PPI or DRD-type display panels.

[0164] Figure 8 This is a plan view of a display panel included in an organic light-emitting display device according to an exemplary embodiment of the present disclosure.

[0165] In response, Figure 8 This is an enlarged view of a portion of the display panel 100, to illustrate and describe the relationship between an output terminal OUTn of the GIP driver and two scan lines SCLn and SCLn+1, respectively, via a first transfer transistor TS1 and a second transfer transistor TS2.

[0166] The display panel 100 can be divided into a display area AA and a non-display area NA. Multiple pixels PX, multiple scan lines SCLn-1, SCLn, SCLn+1 and SCLn+2, multiple data lines DL, and a reference voltage line RL can be located in the display area AA. In the non-display area NA, a GIP driver, the output terminal OUTn of the GIP driver, enable lines ENL1 and ENL2, and the electrodes of the first transmission transistor TS1 and the second transmission transistor TS2 can be located.

[0167] Reference Figure 8 The output terminal OUTn of the GIP driver is connected to the drain electrode TS12D of each of the first transfer transistor TS1 and the second transfer transistor TS2. The gate electrode TS1G of the first transfer transistor TS1 is connected to the first enable line ENL1, and the first enable signal EN1 is provided to the first enable line ENL1. The source electrode TS1S of the first transfer transistor TS1 is connected to the nth scan line SCLn.

[0168] Furthermore, the gate electrode TS2G of the second transmission transistor TS2 is connected to the second enable line ENL2, and the second enable signal EN2 is provided to the second enable line ENL2. The source electrode TS2S of the second transmission transistor TS2 is connected to the (n+1)th scan line SCLn+1.

[0169] For example, an output terminal OUTn of the GIP driver is connected to either the first scan line SCLn or the second scan line SCLn+1 via each of the first transfer transistor TS1 and the second transfer transistor TS2. When the first enable signal EN1 is activated, the output terminal OUTn is connected to the first scan line SCLn via the first transfer transistor TS1. Conversely, when the second enable signal EN2 is activated, the output terminal OUTn is connected to the second scan line SCLn+1 via the second transfer transistor TS2.

[0170] For example, when designing a GIP driver that outputs four scan signals as the same number of outputs as in the SRD scheme, eight scan lines can be driven via a transmission circuit including a first transmission transistor TS1 and a second transmission transistor TS2. Alternatively, for example, four scan lines can be driven alternately in a frame.

[0171] As described above, each output terminal of the GIP driver can be selectively connected to two scan lines via a transmission circuit, thereby enabling the GIP driver design without reducing the GIP driver size. This GIP driver design can be appropriately applied to high PPI or DRD type display panels.

[0172] The display device and gating drive circuit according to various aspects and embodiments of the present disclosure as described above can be described as follows.

[0173] A first aspect of this disclosure provides a display device comprising: a display panel including a plurality of scan lines; a first GIP (Gateway In-Panel) driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to sequentially output a scan signal; a first transmission circuit configured to selectively transmit the scan signal of the first GIP driver to a first scan line and a second scan line among the plurality of scan lines; and a second transmission circuit configured to selectively transmit the scan signal of the second GIP driver to the first scan line and the second scan line.

[0174] According to some embodiments of the first aspect of this disclosure, in a first frame, the first transmission circuit is configured to transmit a scan signal output from the first GIP driver to one of the first scan line and the second scan line, and the second transmission circuit is configured to transmit a scan signal output from the second GIP driver to the other scan line of the first scan line and the second scan line. In a second frame following the first frame, the first transmission circuit is configured to transmit a scan signal output from the first GIP driver to the other scan line of the first scan line and the second scan line, and the second transmission circuit is configured to transmit a scan signal output from the second GIP driver to the other scan line of the first scan line and the second scan line.

[0175] According to some embodiments of the first aspect of this disclosure, the first transmission circuit includes: a first transmission transistor configured to transmit a scan signal of the first GIP driver to the first scan line in response to a first enable signal; and a second transmission transistor configured to transmit a scan signal of the first GIP driver to the second scan line in response to a second enable signal.

[0176] According to some embodiments of the first aspect of this disclosure, the second transmission circuit includes: a third transmission transistor configured to transmit a scan signal of the second GIP driver to the first scan line in response to the second enable signal; and a fourth transmission transistor configured to transmit the scan signal of the second GIP driver to the second scan line in response to the first enable signal.

[0177] According to some embodiments of the first aspect of this disclosure, each of the first and fourth transmission transistors is configured to be turned on in odd-numbered frames, wherein each of the second and third transmission transistors is configured to be turned on in even-numbered frames.

[0178] According to some embodiments of the first aspect of this disclosure, the logic level of the first enable signal and the logic level of the second enable signal are out of phase with respect to each other, wherein the logic level of the first enable signal and the logic level of the second enable signal are out of phase with respect to each other on a frame basis.

[0179] According to some embodiments of the first aspect of this disclosure, the first GIP driver includes a first logic circuit configured to apply the first enable signal and the second enable signal, wherein the second GIP driver includes a second logic circuit configured to apply the first enable signal and the second enable signal.

[0180] According to some embodiments of the first aspect of this disclosure, the first GIP driver further includes a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to pull up the output terminal of the first GIP driver in response to a first drive signal of the first logic circuit, and the pull-down transistor being configured to pull down the output terminal of the first GIP driver in response to a second drive signal of the first logic circuit.

[0181] According to some embodiments of the first aspect of this disclosure, the second GIP driver further includes a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to pull up the output terminal of the second GIP driver in response to a first drive signal of the second logic circuit, and the pull-down transistor being configured to pull down the output terminal of the second GIP driver in response to a second drive signal of the second logic circuit.

[0182] According to some embodiments of the first aspect of this disclosure, each of the first enable signal and the second enable signal is applied as an external clock signal from an external source of the display panel.

[0183] According to some embodiments of the first aspect of this disclosure, the first transmission circuit is configured to transmit the scan signal of the first GIP driver to the first scan line in the nth frame, and to transmit the scan signal of the first GIP driver to the second scan line in the (n+1)th frame, where n is a positive integer.

[0184] According to some embodiments of the first aspect of this disclosure, the second transmission circuit is configured to transmit the scan signal of the second GIP driver to the second scan line in the nth frame, and to transmit the scan signal of the second GIP driver to the first scan line in the (n+1)th frame.

[0185] According to some embodiments of the first aspect of this disclosure, the first scan line is an odd-numbered scan line among the plurality of scan lines, and the second scan line is an even-numbered scan line among the plurality of scan lines.

[0186] According to some embodiments of the first aspect of this disclosure, the display panel includes a plurality of sub-pixels, wherein each of the plurality of scan lines is connected to the gate electrode of a scan transistor for providing a data voltage to the sub-pixel, and is connected to the gate electrode of a sensing transistor for providing a reference voltage to the sub-pixel.

[0187] According to some embodiments of the first aspect of this disclosure, the first GIP driver and the second GIP driver are respectively disposed on opposite sides of the display panel, the first transmission circuit is disposed between the display panel and the first GIP driver and connected to the display panel and the first GIP driver, and the second transmission circuit is disposed between the display panel and the second GIP driver and connected to the display panel and the second GIP driver.

[0188] A second aspect of this disclosure provides a gating drive circuit comprising: a first GIP driver disposed on the left side of a display panel; and a second GIP driver disposed on the right side of the display panel, wherein the scan signal of the first GIP driver is transmitted to an odd-numbered scan line among a plurality of scan lines in the nth frame and to an even-numbered scan line in the (n+1)th frame, where n is a positive integer; and the scan signal of the second GIP driver is transmitted to the even-numbered scan line in the nth frame and to the odd-numbered scan line in the (n+1)th frame.

[0189] According to some embodiments of the second aspect of this disclosure, the gating drive circuit further includes: a first transmission circuit disposed between and connected to the first GIP driver and the display panel, and configured to selectively transmit the scan signal of the first GIP driver to one of the odd scan lines and the even scan lines; and a second transmission circuit disposed between and connected to the second GIP driver and the display panel, and configured to selectively transmit the scan signal of the second GIP driver to one of the odd scan lines and the even scan lines.

[0190] According to some embodiments of the second aspect of this disclosure, the first transmission circuit includes: a first transmission transistor configured to transmit a scan signal of the first GIP driver to the odd-numbered scan lines in response to a first enable signal; and a second transmission transistor configured to transmit a scan signal of the first GIP driver to the even-numbered scan lines in response to a second enable signal.

[0191] According to some embodiments of the second aspect of this disclosure, the second transmission circuit includes: a third transmission transistor configured to transmit a scan signal of the second GIP driver to the odd-numbered scan lines in response to a second enable signal; and a fourth transmission transistor configured to transmit a scan signal of the second GIP driver to the even-numbered scan lines in response to a first enable signal.

[0192] According to some embodiments of the second aspect of this disclosure, each of the first GIP driver and the second GIP driver includes a plurality of stages that sequentially provide the scan signal to the plurality of scan lines, wherein each of the plurality of stages includes: logic circuitry configured to output a first drive signal and a second drive signal; a pull-up transistor configured to pull up the output terminal of the first GIP driver or the second GIP driver in response to the first drive signal; and a pull-down transistor configured to pull down the output terminal of the first GIP driver or the second GIP driver in response to the second drive signal.

[0193] According to some embodiments of the second aspect of this disclosure, the logic circuitry of the first GIP driver is configured to provide the first enable signal and the second enable signal to the first transmission circuit, wherein the logic circuitry of the second GIP driver is configured to provide the first enable signal and the second enable signal to the second transmission circuit.

[0194] According to some embodiments of the second aspect of this disclosure, each of the first enable signal and the second enable signal is an external clock signal and is applied from an external source of the display panel.

[0195] A third aspect of this disclosure provides a display device, the display device comprising: a display panel including a plurality of scan lines and a plurality of sensing lines; a first GIP driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to sequentially output a scan signal and sequentially output a sensing signal to the display panel; a first transmission circuit configured to alternately transmit the scan signal of the first GIP driver to a first scan line and a second scan line among the plurality of scan lines, and to alternately transmit the sensing signal of the first GIP driver to a first sensing line and a second sensing line among the plurality of sensing lines; and a second transmission circuit configured to alternately transmit the scan signal of the second GIP driver to the first scan line and the second scan line, and to alternately transmit the sensing signal of the second GIP driver to the first sensing line and the second sensing line.

[0196] According to some embodiments of the third aspect of this disclosure, the first GIP driver and the second GIP driver are respectively disposed on opposite sides of the display panel. In a first frame, the first transmission circuit is configured to transmit the scan signal from the first GIP driver to one of the first scan line and the second scan line, and to transmit the sensing signal from the first GIP driver to one of the first sensing line and the second sensing line. The second transmission circuit is configured to transmit the scan signal from the second GIP driver to the other scan line of the first scan line and the second scan line, and to transmit the sensing signal from the second GIP driver to the first sensing line. And another sensing line in the second sensing line, wherein, in a second frame following the first frame, the first transmission circuit is configured to transmit the scan signal from the first GIP driver to the other scanning line of the first and second scanning lines, and to transmit the sensing signal from the first GIP driver to the other sensing line of the first and second sensing lines, while the second transmission circuit is configured to transmit the scan signal from the second GIP driver to one of the first and second scanning lines, and to transmit the sensing signal from the second GIP driver to one of the first and second sensing lines.

[0197] A fourth aspect of this disclosure provides a gating drive circuit, the gating drive circuit comprising: a first GIP driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to sequentially output a scan signal and sequentially output a sensing signal; a first transmission circuit configured to alternately transmit the scan signal of the first GIP driver to a first scan line and a second scan line among a plurality of scan lines, and to alternately transmit the sensing signal of the first GIP driver to a first sensing line and a second sensing line among a plurality of sensing lines; and a second transmission circuit configured to alternately transmit the scan signal of the second GIP driver to the first scan line and the second scan line, and to alternately transmit the sensing signal of the second GIP driver to the first sensing line and the second sensing line.

[0198] Although some embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and can be implemented in various different forms. Those skilled in the art to which this disclosure pertains will understand that the present disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not limiting but illustrative in all respects.

Claims

1. A display device, the display device comprising: The display panel includes multiple scan lines; The first panel selects a GIP driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to output a scan signal sequentially; A first transmission circuit, configured to selectively transmit the scan signal of the first GIP driver to a first scan line and a second scan line among the plurality of scan lines; and A second transmission circuit is configured to selectively transmit the scan signal of the second GIP driver to the first scan line and the second scan line.

2. The display device according to claim 1, wherein, Within the first frame, the first transmission circuit is configured to transmit a scan signal output from the first GIP driver to one of the first scan line and the second scan line, and the second transmission circuit is configured to transmit a scan signal output from the second GIP driver to the other of the first scan line and the second scan line. In the second frame following the first frame, the first transmission circuit is configured to transmit a scan signal output from the first GIP driver to the other scan line of the first scan line and the second scan line, and the second transmission circuit is configured to transmit a scan signal output from the second GIP driver to the scan line of the first scan line and the second scan line.

3. The display device according to claim 2, wherein, The first transmission circuit includes: A first transmission transistor, configured to transmit a scan signal from the first GIP driver to the first scan line in response to a first enable signal; and The second transmission transistor is configured to transmit the scan signal of the first GIP driver to the second scan line in response to a second enable signal.

4. The display device according to claim 3, wherein, The second transmission circuit includes: A third transmission transistor, configured to transmit a scan signal from the second GIP driver to the first scan line in response to the second enable signal; and A fourth transmission transistor is configured to transmit a scan signal from the second GIP driver to the second scan line in response to the first enable signal.

5. The display device according to claim 4, wherein, Each of the first and fourth transmission transistors is configured to be turned on during odd-numbered frames. Each of the second and third transmission transistors is configured to be turned on during even-numbered frames.

6. The display device according to claim 5, wherein, The logic level of the first enable signal is inversely related to the logic level of the second enable signal. The logic levels of the first enable signal and the second enable signal are inversely related to each other on a frame-by-frame basis.

7. The display device according to claim 6, wherein, The first GIP driver includes a first logic circuit configured to apply the first enable signal and the second enable signal. The second GIP driver includes a second logic circuit configured to apply the first enable signal and the second enable signal.

8. The display device according to claim 7, wherein, The first GIP driver further includes a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to pull up the output terminal of the first GIP driver in response to a first drive signal of the first logic circuit, and the pull-down transistor being configured to pull down the output terminal of the first GIP driver in response to a second drive signal of the first logic circuit.

9. The display device according to claim 7, wherein, The second GIP driver further includes a pull-up transistor and a pull-down transistor, the pull-up transistor being configured to pull up the output terminal of the second GIP driver in response to a first drive signal of the second logic circuit, and the pull-down transistor being configured to pull down the output terminal of the second GIP driver in response to a second drive signal of the second logic circuit.

10. The display device according to claim 6, wherein, Each of the first enable signal and the second enable signal is applied as an external clock signal from an external source of the display panel.

11. The display device according to claim 1, wherein, The first transmission circuit is configured to transmit the scan signal of the first GIP driver to the first scan line in the nth frame, and to transmit the scan signal of the first GIP driver to the second scan line in the (n+1)th frame, where n is a positive integer.

12. The display device according to claim 11, wherein, The second transmission circuit is configured to transmit the scan signal of the second GIP driver to the second scan line in the nth frame, and to transmit the scan signal of the second GIP driver to the first scan line in the (n+1)th frame.

13. The display device according to claim 1, wherein, The first scan line is an odd-numbered scan line among the plurality of scan lines, and the second scan line is an even-numbered scan line among the plurality of scan lines.

14. The display device according to claim 1, wherein, The display panel includes multiple sub-pixels. Each of the plurality of scan lines is connected to the gate electrode of a scan transistor for providing a data voltage to the sub-pixel, and to the gate electrode of a sensing transistor for providing a reference voltage to the sub-pixel.

15. The display device according to claim 1, wherein, The first GIP driver and the second GIP driver are respectively disposed on opposite sides of the display panel. The first transmission circuit is disposed between and connected to the display panel and the first GIP driver. The second transmission circuit is disposed between the display panel and the second GIP driver and is connected to the display panel and the second GIP driver.

16. A gating driving circuit, the gating driving circuit comprising: The first GIP driver is located on the left side of the display panel; as well as The second GIP driver is located on the right side of the display panel. In this configuration, the scan signal of the first GIP driver is transmitted to the odd-numbered scan lines among multiple scan lines in the nth frame, and to the even-numbered scan lines in the (n+1)th frame, where n is a positive integer. The scan signal of the second GIP driver is transmitted to the even-numbered scan line in the nth frame and to the odd-numbered scan line in the (n+1)th frame.

17. The gating drive circuit according to claim 16, wherein, The gating drive circuit also includes: A first transmission circuit, disposed between and connected to the first GIP driver and the display panel, is configured to selectively transmit the scan signal of the first GIP driver to one of the odd-numbered and even-numbered scan lines; and A second transmission circuit is disposed between and connected to the second GIP driver and the display panel, and is configured to selectively transmit the scan signal of the second GIP driver to one of the odd scan lines and the even scan lines.

18. The gating drive circuit according to claim 17, wherein, The first transmission circuit includes: A first transmission transistor, configured to transmit a scan signal from the first GIP driver to the odd number of scan lines in response to a first enable signal; and A second transmission transistor is configured to transmit the scan signal of the first GIP driver to the even-numbered scan lines in response to a second enable signal.

19. The gating drive circuit according to claim 18, wherein, The second transmission circuit includes: A third transmission transistor, configured to transmit a scan signal from the second GIP driver to the odd scan lines in response to the second enable signal; and A fourth transmission transistor is configured to transmit the scan signal of the second GIP driver to the even-numbered scan line in response to the first enable signal.

20. The gating drive circuit according to claim 19, wherein, Each of the first GIP driver and the second GIP driver includes multiple stages that sequentially provide the scan signal to the plurality of scan lines. Each of the plurality of levels includes: A logic circuit configured to output a first drive signal and a second drive signal; Pull-up transistor, the pull-up transistor being configured to pull up the output terminal of the first GIP driver or the second GIP driver in response to the first drive signal; and A pull-down transistor configured to pull down the output terminal of the first GIP driver or the second GIP driver in response to the second drive signal.

21. The gating drive circuit according to claim 20, wherein, The logic circuitry of the first GIP driver is configured to provide the first enable signal and the second enable signal to the first transmission circuit. The logic circuit of the second GIP driver is configured to provide the first enable signal and the second enable signal to the second transmission circuit.

22. The gating drive circuit according to claim 18 or 19, wherein, Each of the first enable signal and the second enable signal is applied as an external clock signal from an external source of the display panel.

23. A display device, the display device comprising: The display panel includes multiple scan lines and multiple sensing lines; A first GIP driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to sequentially output a scan signal and sequentially output a sensing signal to the display panel; A first transmission circuit is configured to alternately transmit the scan signal of the first GIP driver to a first scan line and a second scan line among the plurality of scan lines, and to alternately transmit the sensing signal of the first GIP driver to a first sensing line and a second sensing line among the plurality of sensing lines; and A second transmission circuit is configured to alternately transmit the scan signal of the second GIP driver to the first scan line and the second scan line, and to alternately transmit the sensing signal of the second GIP driver to the first sensing line and the second sensing line.

24. The display device according to claim 23, wherein, The first GIP driver and the second GIP driver are respectively disposed on opposite sides of the display panel. In the first frame, the first transmission circuit is configured to transmit the scan signal from the first GIP driver to one of the first scan line and the second scan line, and to transmit the sensing signal from the first GIP driver to one of the first sensing line and the second sensing line. The second transmission circuit is configured to transmit the scan signal from the second GIP driver to the other of the first scan line and the second scan line, and to transmit the sensing signal from the second GIP driver to the other of the first sensing line and the second sensing line. In a second frame following the first frame, the first transmission circuit is configured to transmit the scan signal from the first GIP driver to the other scan line of the first and second scan lines, and to transmit the sensing signal from the first GIP driver to the other sensing line of the first and second sensing lines. The second transmission circuit is configured to transmit the scan signal from the second GIP driver to one of the scan lines of the first and second scan lines, and to transmit the sensing signal from the second GIP driver to one of the sensing lines of the first and second sensing lines.

25. A gating driving circuit, the gating driving circuit comprising: A first GIP driver and a second GIP driver, wherein each of the first GIP driver and the second GIP driver is configured to output a scan signal and a sensing signal in sequence; A first transmission circuit is configured to alternately transmit the scan signal of the first GIP driver to a first scan line and a second scan line among a plurality of scan lines, and to alternately transmit the sensing signal of the first GIP driver to a first sensing line and a second sensing line among a plurality of sensing lines; and A second transmission circuit is configured to alternately transmit the scan signal of the second GIP driver to the first scan line and the second scan line, and to alternately transmit the sensing signal of the second GIP driver to the first sensing line and the second sensing line.

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