Clock pulse phase control circuit and electronic device

Abstract

The invention relates to a clock pulse phase control circuit and an electronic device. The clock pulse phase control circuit comprises a sampling circuit and a phase monitoring circuit. The sampling circuit receives a plurality of reference clock signals, and samples data read from a memory device according to the reference clock signals in response to a read instruction to obtain a plurality of sampling results. The reference clock signal is generated with a plurality of different candidate phases based on a base clock signal. The phase monitoring circuit receives the sampling result and determines an optimal phase according to the sampling result. The data read from the memory device includes data within one or more data blocks sequentially received in response to a read instruction, and in response to an end of each data block, a sampling phase of a base clock signal for sampling the data read from the memory device is adjusted according to the optimal phase.

Description

Technical Field

[0001] This invention relates to a clock phase control circuit that can effectively control the clock phase used for sampling data read from a memory device. Background Technology

[0002] With the rapid advancement of data storage technology in recent years, many data storage devices, such as those compliant with Secure Digital (SD) / Multi Media Card (MMC), Compact Flash (CF), Memory Stick (MS), Extreme Digital (XD) memory cards, Solid State Disks (SSD), embedded Multi Media Cards (eMMC), and Universal Flash Storage (UFS), have been widely used for various applications. Furthermore, with the progress in data storage technology, the data transfer rates of these data storage devices have continued to increase.

[0003] However, the increase in data transfer rates also reduces the margin for correctly latching or sampling data, which may lead to an increased error rate in latching or sampling data under certain conditions. Therefore, effectively controlling the clock phase used to latch or sample data read from the data storage device is an important issue in the field of data storage. Summary of the Invention

[0004] According to one embodiment of the present invention, a clock phase control circuit includes a sampling circuit and a phase monitoring circuit. The sampling circuit receives a plurality of reference clock signals and, in response to a read command, samples data read from a memory device based on the reference clock signals to obtain a plurality of sampling results. The reference clock signals are generated based on a base clock signal with a plurality of different candidate phases. The phase monitoring circuit receives the sampling results and determines an optimal phase based on the sampling results. The data read from the memory device includes data in one or more data blocks that are received sequentially in response to a read command, and in response to the end of each data block, a sampling phase of the base clock signal used to sample the data read from the memory device is adjusted according to the optimal phase.

[0005] According to another embodiment of the present invention, an electronic device coupled to a data storage device includes a receiving circuit and a signal processing circuit. The receiving circuit receives data read from a memory device of the data storage device. The signal processing circuit processes the data, wherein the data includes data within one or more data blocks sequentially transmitted in response to a read instruction. The signal processing circuit includes a clock signal generation circuit and a clock phase control circuit. The clock signal generation circuit generates a plurality of reference clock signals with a plurality of different candidate phases based on a base clock signal. The candidate phase includes a sampling phase of the base clock signal currently set for sampling data. The clock phase control circuit repeatedly determines an optimal phase based on a plurality of sampling results obtained based on the reference clock signals, and provides relevant information of the optimal phase to the clock signal generation circuit in response to the end of each data block to adjust the sampling phase of the base clock signal. Attached Figure Description

[0006] Figure 1 This diagram shows an example block diagram of a data storage device according to one embodiment of the present invention.

[0007] Figure 2 This diagram shows an example circuit diagram of a portion of the circuitry in the host interface and a portion of the circuitry in the device interface according to an embodiment of the present invention.

[0008] Figure 3 This diagram illustrates a data transmission timing sequence according to an embodiment of the present invention, in response to a read command issued by a host device.

[0009] Figure 4 This diagram illustrates clock phase control implemented by a clock signal generation circuit and a clock phase control circuit according to one embodiment of the present invention.

[0010] Figure 5 This diagram shows an example circuit diagram of a phase control circuit according to one embodiment of the present invention.

[0011] Figure 6 This illustrates a state machine example of performing clock phase control according to one embodiment of the present invention.

[0012] [Symbol Explanation]

[0013] 100: Data storage device

[0014] 110: Memory controller

[0015] 112: Microprocessor

[0016] 112C: Program Code

[0017] 112M: Read-Only Memory

[0018] 114: Memory Interface

[0019] 116: Buffer memory

[0020] 118, 218: Host Interface

[0021] 120: Memory device

[0022] 122: Encoder

[0023] 124: Decoder

[0024] 126, RX_Path: Signal receiving path

[0025] 128, TX_Path: Signal transmission path

[0026] 130: Main unit

[0027] 131: Processor

[0028] 132: Random Access Memory

[0029] 133: Read-only memory

[0030] 135: Power Supply Circuit

[0031] 138,238: Device interface

[0032] 211, 231: Transmission circuit

[0033] 212, 232: Receiving circuit

[0034] 213, 233: Signal processing circuits

[0035] 234: Clock signal generation circuit

[0036] 235: Clock Phase Control Circuit

[0037] 410: Clock signal generation circuit

[0038] 420: Clock Phase Control Circuit

[0039] 430, 510: Sampling circuit

[0040] 440: Phase monitoring circuit

[0041] 442,520: Comparator Circuit

[0042] 446,530: Optimal Phase Determination Circuit

[0043] 531: Temporary Register Circuit

[0044] 532: Determine the circuit

[0045] 610, 620, 630, 640, 650: Status

[0046] B_pass, F_pass: Distance

[0047] CLK: Clock signal

[0048] DATA: Data

[0049] Data_Block: Data block

[0050] EOB, SOB: Indicators

[0051] Phase[1], Phase[2], Phase[n_C], Phase[N]: Candidate phases

[0052] Read_CMD: Read command Detailed Implementation

[0053] Numerous specific details are described below to provide a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate how the invention can be practiced in the absence of one or more specific details or in reliance on other methods, elements, or materials. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring the main concepts of the invention.

[0054] Throughout this specification, references to "an embodiment" or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one of the various embodiments of the invention. Therefore, the phrases "in one embodiment of the invention," "according to one embodiment of the invention," "in an example," or "according to an example" appearing throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples.

[0055] Furthermore, to make the objectives, features, and advantages of this invention more apparent and understandable, specific embodiments of the invention are described below in detail with reference to the accompanying drawings. The purpose is to illustrate the spirit of the invention and not to limit its scope of protection. It should be understood that the following embodiments can be implemented using software, hardware, firmware, or any combination thereof.

[0056] Figure 1This diagram illustrates an example block diagram of a data storage device according to one embodiment of the present invention. The data storage device 100 may include a memory device 120 and a memory controller 110. The memory controller 110 is used to access the memory device 120 and control its operation. The memory device 120 may be a non-volatile (NV) memory device (e.g., a flash memory) and may include one or more memory elements (e.g., one or more flash memory dies, one or more flash memory chips, or other similar elements).

[0057] Data storage device 100 may be coupled to a host device 130. Host device 130 may include at least a processor 131, at least a random access memory (RAM) 132, such as at least a dynamic random access memory (DRAM) or at least a static random access memory (SRAM), at least a read only memory (ROM) 133, a power supply circuit 135, and a device interface 138.

[0058] The host device 130 can access the data storage device 100 through the device interface 138. The processor 131, device interface 138, random access memory 132, and read-only memory 133 can be interconnected through a bus and coupled to the power supply circuit 135 to obtain power. The processor 131 can control the operation of the host device 130. The read-only memory 133 can store program code. The processor 131 can execute the program code to control the operation of the host device 130.

[0059] The power supply circuit 135 can supply power to the processor 131, device interface 138, random access memory 132, and read-only memory 133 via a bus or power line, and can also supply power to the data storage device 100. For example, the power supply circuit 135 can output one or more drive voltages to the data storage device 100. The data storage device 100 can obtain the drive voltage from the host device 130 as its power source and provide storage space for the host device 130.

[0060] According to one embodiment of the present invention, the memory controller 110 may include a microprocessor 112, a read-only memory 112M, a memory interface 114, a buffer memory 116, and a host interface 118. The read-only memory 112M is used to store program code 112C. The microprocessor 112 is used to execute program code 112C to control access to the memory device 120. Program code 112C may include one or more program modules, such as boot loader program code. When the data storage device 100 receives power from the host device 130, the microprocessor 112 may execute an initialization program of the data storage device 100 by executing program code 112C. In the initialization program, the microprocessor 112 may load a set of in-system programming (ISP) program code (not shown) from the memory device 120. Figure 1 The microprocessor 112 can execute this set of in-system programming code, enabling the data storage device 100 to possess various functions. According to one embodiment of the present invention, this set of in-system programming code may include, but is not limited to: one or more program modules related to memory access (e.g., read, write, and erase), such as a read operation module, a lookup table module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, a sudden power off recovery (SPOR) module, and an uncorrectable error correction code (UECC) module, which are respectively provided to perform corresponding read, lookup table, wear leveling, read refresh, read reclaim, garbage collection, sudden power off recovery, and error handling of detected UECC errors.

[0061] The memory interface 114 may include an encoder 122 and a decoder 124. The encoder 122 may encode data to be written to the memory device 120, for example, by performing error correction code (ECC) encoding. The decoder 124 may decode data read from the memory device 120.

[0062] In a typical configuration, memory device 120 includes multiple memory elements, such as multiple flash memory dies or multiple flash memory chips, and each memory element may contain multiple memory blocks. The memory controller 110 performs data erasure operations on memory device 120 on a block-by-block basis. Additionally, a memory block may record (contain) a specific number of data pages, such as physical data pages, wherein the memory controller 110 performs write or read operations on memory device 120 on a page-by-page basis.

[0063] In practice, the memory controller 110 can utilize its internal components to perform various control operations, such as controlling the access operations of the memory device 120 (especially access operations to at least one memory block or at least one data page) using the memory interface 114, performing necessary buffering operations using the buffer memory 116, and communicating with the host device 130 using the host interface 118. The host interface 118 may include at least one signal receiving path RX_Path 126 and one signal transmitting path TX_Path 128 for processing data and signals received from the host device 130, and processing data and signals to be transmitted to the host device 130. The signal receiving path RX_Path 126 and the signal transmitting path TX_Path 128 may each include one or more signal processing circuits to perform necessary signal processing.

[0064] In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 and using a standard communication protocol. For example, the aforementioned standard communication protocol includes (but is not limited to): Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, CF interface standard, MMC interface standard, eMMC interface standard, UFS interface standard, Advanced Technology Attachment (ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PATA) standard, etc.

[0065] In one embodiment, the buffer memory 116 used to provide data buffering is implemented as random access memory. For example, the buffer memory 116 may be static random access memory, but the invention is not limited thereto. In other embodiments, the buffer memory 116 may be dynamic random access memory.

[0066] In one embodiment, the data storage device 100 may be a portable storage device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards, a USB flash drive, etc.), and the host device 130 may be an electronic device that can be connected to the data storage device, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the data storage device 100 may be a solid-state drive or an embedded storage device conforming to UFS or eMMC specifications, and may be disposed in an electronic device, such as a mobile phone, laptop, or desktop computer. In this embodiment, the host device 130 may be a processor of the electronic device.

[0067] The host device 130 may issue instructions to the data storage device 100, such as read instructions or write instructions, to access the data stored in the memory device 120, or the host device 130 may issue instructions to the data storage device 100 to further control and manage the data storage device 100.

[0068] Data storage device 100 can operate according to a clock signal CLK. In some embodiments of the present invention, the clock signal CLK can be provided by the host device 130. For example, data storage device 100 can receive the clock signal CLK from the host device 130, and the transmission of the clock signal can be unidirectional. In a write operation, data storage device 100 can receive the clock signal CLK from the host device 130 and receive data that the host device 130 wants to write or store to memory device 120 according to the clock signal CLK. In a read operation, data storage device 100 can receive the clock signal CLK from the host device 130 and output the data read from memory device 120 according to the clock signal CLK.

[0069] Figure 2 Exemplary circuit diagrams showing portions of circuitry in a host interface and a device interface according to an embodiment of the present invention illustrate the signal transmission path between a data storage device (e.g., data storage device 100) and a host device (e.g., host device 130).

[0070] Host interface 218 may be included at least in the signal transmission path (e.g., Figure 1 The transmission circuit 211 on the TX_Path 128 shown, and the signal receiving path (e.g., as shown) Figure 1The receiving circuit 212 and signal processing circuit 213 are shown on RX_Path 126. The device interface 238 may include at least a transmitting circuit 231 on the signal transmission path, a receiving circuit 232 on the signal receiving path, and a signal processing circuit 233. The transmitting circuit 211, the receiving circuit 212, and the signal processing circuit 213 are used to perform the signal processing required by the host interface 218, while the transmitting circuit 231, the receiving circuit 232, and the signal processing circuit 233 are used to perform the signal processing required by the device interface 238.

[0071] As described above, the clock signal CLK required by the data storage device can be provided by the host device. The host device can provide the clock signal CLK to the data storage device through its transmission circuit 231. The clock signal CLK provided by the host device can travel from the output pad in the transmission circuit 231 through the printed circuit board (PCB) to the input pad in the receiving circuit 212. In some implementations, the clock signal CLK can be further provided to the signal processing circuit 213 to assist the operation of the signal processing circuit 213.

[0072] The data storage device can output data DATA read from the memory device (e.g., memory device 120) to the host device via its transmission circuit 211. The host device's receiving circuit 232 can receive the data DATA read from the memory device via a printed circuit board and provide the data DATA to the signal processing circuit 233. The signal processing circuit 233 can further process the data DATA.

[0073] According to one embodiment of the present invention, the signal processing circuit 233 may include at least a clock signal generation circuit 234. The clock signal generation circuit 234 may include a delay-locked loop (DLL) circuit and may generate a predetermined reference clock signal CLK' based on the clock signal CLK (which is a base clock signal) provided to the data storage device and the phase (i.e., the sampling phase) of the data DATA currently set for latching or sampling (for simplicity, the term "sampling" is used hereinafter to represent this).

[0074] During the initialization process, the host device can first estimate the sampling phase for sampling the data DATA received from the data storage device, and apply this sampling phase to generate the aforementioned predetermined reference clock signal CLK', which is a clock signal reconstructed or regenerated by the host device based on the clock signal CLK and the sampling phase. During the read operation, the host device can sample the data DATA received from the data storage device according to its own reconstructed or regenerated predetermined reference clock signal CLK'. The predetermined reference clock signal CLK' regenerated by the host device can actually be a copy of the clock signal CLK provided by the host device to the data storage device for outputting the data DATA. For example, the clock signal CLK and the predetermined reference clock signal CLK' can have the same frequency.

[0075] However, the phase delay of the clock signal CLK used by the data storage device to output data DATA can be affected by many factors. One key factor is temperature. For example, as the temperature rises, the phase delay of the clock signal CLK also increases. As the phase delay of the clock signal CLK increases, the sampling phase previously estimated and used to recreate or regenerate the predetermined reference clock signal CLK' may no longer be aligned with the phase of the clock signal CLK used to output the data DATA read from the memory device, thus increasing the error rate of the host device's sampled data. For example, when the phase difference between the clock signal CLK and the predetermined reference clock signal CLK' exceeds the margin for correct sampled data, incorrect sampling results may be obtained.

[0076] Furthermore, as the data transfer rate between the data storage device and the host device increases, the margin for correctly sampling data decreases. Due to this reduced margin, the data error rate may further increase. To avoid obtaining erroneous sampling results on the host device due to unexpected changes in phase delay, a novel clock phase control method and a corresponding circuit structure for implementing this method are needed to control the clock phase used for sampling data read from the data storage device.

[0077] According to one embodiment of the present invention, the clock signal generation circuit 234 can generate multiple reference clock signals based on the clock signal CLK (base clock signal) with multiple different candidate phases. The candidate phases may include the sampling phase that is currently set and actually used for sampling data. Therefore, the multiple reference clock signals may include the predetermined reference clock signal CLK' that is regenerated by the host device for sampling data DATA.

[0078] According to one embodiment of the present invention, the signal processing circuit 233 may further include a clock phase control circuit 235. The clock phase control circuit 235 may repeatedly or continuously determine an optimal phase based on multiple sampling results obtained based on a reference clock signal, and provide relevant information of the optimal phase to the clock signal generation circuit 234, so as to control the actual clock phase used for sampling data by dynamically adjusting the sampling phase of the base clock signal.

[0079] According to one embodiment of the present invention, the data read from the memory device may include data in one or more data blocks that are sequentially received by the host device in response to a read instruction.

[0080] Figure 3 This diagram illustrates a data transfer timing sequence according to an embodiment of the present invention in response to a read command issued by a host device. In response to a read command (labeled Read_CMD) issued by the host device, the data storage device may read data DATA from the memory device in the form of one or more data blocks (labeled Data_Block). The index SOB can be used to indicate the start of a data block transfer, while another index EOB can be used to indicate the end of a data block transfer. The transfer of a Data_Block may begin after the index SOB and end before the index EOB.

[0081] According to one embodiment of the present invention, in response to the end of each data block (e.g., at the end of each data block or after the end of each data block), the clock phase control circuit 235 continuously provides clock signal generation circuit 234 with relevant information on the optimal phase to adjust the sampling phase of the base clock signal, such as... Figure 3 The example shows several "Update Sampling Phase Setting" operations. For instance... Figure 3 As shown, a first sampling phase setting value or sampling phase setting value A (SP_Setting_A) is applied to sample a first data block received in response to a read command Read_CMD. After updating the sampling phase setting value, it can be adjusted and changed to a second sampling phase setting value or sampling phase setting value B (SP_Setting_B). Then, the second sampling phase setting value or sampling phase setting value B is applied to sample a second data block subsequently received in response to the same read command Read_CMD, and so on. In embodiments of the present invention, the first sampling phase setting value (sampling phase setting value A) and the second sampling phase setting value (sampling phase setting value B) can be the same or different.

[0082] Figure 4This diagram illustrates clock phase control implemented by a clock signal generation circuit and a clock phase control circuit according to one embodiment of the present invention. The clock signal generation circuit 410 can generate multiple reference clock signals with different candidate phases based on the clock signal CLK (base clock signal). According to one embodiment of the present invention, there may be N candidate phases, such as... Figure 4 The candidate phases Phase[1] to Phase[N] are shown, where the values ​​1 to N represent phase index values, and N is a positive integer greater than 1.

[0083] The candidate phase may include a sampling phase, such as phase[n_C], which is the phase of the underlying clock signal currently set and actually used for sampling the data. According to one embodiment of the invention, the sampling phase of the underlying clock signal currently set for sampling the data may be the center of a margin (e.g., the center phase within a time margin or phase margin) determined in the initialization procedure for correctly sampling the data.

[0084] According to one embodiment of the present invention, the clock phase control circuit 420 may include a sampling circuit 430 and a phase monitoring circuit 440. The sampling circuit 430 may receive a reference clock signal and respond to a read command (e.g., Figure 3 The Read_CMD instruction shown samples the data DATA according to the reference clock signal to obtain the sampling result.

[0085] According to one embodiment of the present invention, the data DATA read from the memory device may include data within one or more data blocks that are sequentially transmitted in response to a read instruction, such as... Figure 3 The data blocks shown are Data_Blocks, and these one or more data blocks are received sequentially by the host device. Taking one of these data blocks as an example, according to one embodiment of the present invention, the aforementioned sampling results may include multiple predetermined sampling results obtained based on the data in the predetermined data block, and the sampling circuit 430 may continuously sample the data in the predetermined data block at multiple edges of these reference clock signals (which are generated based on the clock signal CLK) to obtain these predetermined sampling results. According to one embodiment of the present invention, the aforementioned multiple edges may be multiple consecutive edges, for example, edges that arrive one after another, sequentially, or sequentially.

[0086] According to one embodiment of the present invention, the plurality of edges may include at least one or both of a plurality of rising edges and a plurality of falling edges of a reference clock signal. According to another embodiment of the present invention, the plurality of edges may include at least one or both of a plurality of successive rising edges and a plurality of successive falling edges of a reference clock signal. Double Data Rate (DDR) type data transmission can be achieved when data is sampled at a given reference clock signal or at both the rising and falling edges of the reference clock signal.

[0087] The phase monitoring circuit 440 can receive sampling results and determine the optimal phase based on the sampling results. According to one embodiment of the present invention, the phase monitoring circuit 440 may include a comparison circuit 442 and an optimal phase determination circuit 446.

[0088] Comparator circuit 442 can receive predetermined sampling results and compare multiple predetermined sampling results corresponding to different candidate phases with those corresponding to the sampling phase (e.g., ...). Figure 4 The phase(n_C) is compared with a predetermined sample (e.g., the first predetermined sample) to produce multiple comparison results.

[0089] The optimal phase determination circuit 446 can receive the comparison result and determine the optimal phase based on the comparison result. According to one embodiment of the invention, in response to the end of a predetermined data block (e.g., at the end of a predetermined data block, or after the end of a predetermined data block), the phase monitoring circuit 440 can provide relevant information of the determined optimal phase to the clock signal generation circuit 410 to adjust the sampling phase of the base clock signal (e.g., ...). Figure 4 The phase shown is Phase[n_C]).

[0090] It should be noted that, in the embodiments of the present invention, in order to effectively control the clock phase used for sampling data, the sampling phase of the underlying clock signal actually used to sample the data read from the memory device can be dynamically adjusted according to the optimal phase determined in response to the end of each data block, such as... Figure 3 The operation involves continuously updating the sampling phase setting value. For example, after each data block ends, the phase monitoring circuit 446 can determine the optimal phase based on the latest received comparison result and provide the relevant information of the latest determined optimal phase to the clock signal generation circuit 410 to adjust the sampling phase of the base clock signal. However, it should be noted that the adjustment frequency of the sampling phase is not limited to this. In other embodiments of the invention, the sampling phase can also be updated or adjusted in response to the end of multiple data block transmissions, or periodically or non-periodically updated or adjusted based on the latest sampling result during data transmission.

[0091] According to one embodiment of the present invention, the comparison result can indicate whether the sampling result associated with the corresponding candidate phase is correct. For example, a first comparison result can be obtained by comparing the sampling result corresponding to the first candidate phase Phase[1] with the sampling result corresponding to the sampling phase Phase[n_C]. When the sampling result corresponding to the first candidate phase Phase[1] is different from the sampling result corresponding to the sampling phase Phase[n_C], the first comparison result associated with the sampling result corresponding to the first candidate phase Phase[1] can be set to a first value to indicate that the corresponding sampling result is incorrect (in Figure 4 (Represented by the cross symbol "X" in Chinese).

[0092] In another example, a second comparison result can be obtained by comparing the sampling result corresponding to the second candidate phase Phase[n_C-1] with the sampling result corresponding to the sampling phase Phase[n_C]. When the sampling result corresponding to the second candidate phase Phase[n_C-1] is the same as the sampling result corresponding to the sampling phase Phase[n_C], the second comparison result associated with the sampling result corresponding to the second candidate phase Phase[n_C-1] can be set to a second value to indicate that the corresponding sampling result is correct (in...). Figure 4 (Represented by the circle symbol "O" in Chinese).

[0093] According to one embodiment of the present invention, the optimal phase determination circuit 446 can further determine the margin of correctly sampled data within a given data block based on the comparison result, and determine the optimal phase based on the margin. The margin pattern can be derived from the comparison result. Figure 4 As shown, the range of comparison results set as the second value can depict a margin pattern of the correctly sampled data.

[0094] According to one embodiment of the present invention, the margin pattern can be defined by the index values ​​(e.g., values ​​1 to N) of the candidate phases of the correctly sampled data, and the margin edges can be defined by the minimum and maximum values ​​of the index values ​​of the candidate phases of the correctly sampled data. Furthermore, once the margin edge positions are located (e.g., by the corresponding phase index values), the distances between these edges and the currently set sampling phases for sampling data can also be obtained. For example, Figure 4 The distances F_pass and B_pass in the table show the distances between the margin edge and the sampling phase currently set for sampling data, respectively. The letter F represents the forward direction and the letter B represents the backward direction.

[0095] According to one embodiment of the present invention, the margin pattern can be updated based on the latest received comparison result, and at the end of a given data block, an intersection of multiple margins can be obtained, wherein these margins are derived from multiple sampling results obtained by sampling at multiple different clock edges (e.g., the rising edge and / or falling edge of the reference clock signal).

[0096] Figure 5 An example circuit diagram of a phase control circuit according to one embodiment of the present invention is shown. The sampling circuit 510 may include N flip-flops (abbreviated as FF). The number of flip-flops may be related to the number of candidate phases Phase[1], Phase[2], ... Phase[N]. Each flip-flop may receive a reference clock signal having a candidate phase, repeatedly sample data DATA at multiple consecutive edges of the reference clock signal, and output the corresponding sampling results sequentially.

[0097] The comparator circuit 520 may include N comparators. In one embodiment of the invention, such as Figure 5 As shown, these comparators can be implemented using a mutex OR gate (XOR gate). Assuming that the candidate phase Phase[n_C] is the sampling phase of the basic clock signal currently used for sampling data, and that the sampling result of the sampling phase Phase[n_C] is correct, each comparator will compare the sampling result corresponding to a candidate phase with the sampling result corresponding to the sampling phase Phase[n_C], and generate a corresponding comparison result.

[0098] According to one embodiment of the present invention, the optimal phase determination circuit 530 may include a register circuit 531 and a determination circuit 532. The register circuit 531 receives comparison results generated sequentially based on sampling results obtained at multiple edges of the reference clock signal, and updates the margin pattern according to the latest received comparison result.

[0099] Taking a predetermined data block from one or more data blocks as an example, according to one embodiment of the present invention, the register circuit 531 receives comparison results generated sequentially based on predetermined sampling results, which are obtained by continuously sampling data in the predetermined data block at multiple edges of a reference clock signal. The margin pattern can be defined by the index values ​​(e.g., values ​​1 to N) of candidate phases of correctly sampled data, and the register circuit 531 continuously updates the margin pattern based on sampling results obtained from sampling at different clock edges (e.g., rising edges and / or falling edges) of the reference clock signal.

[0100] For example, the register circuit 531 can continuously update the margin pattern by performing an OR operation on a previously received comparison result (or its temporarily stored data) corresponding to a candidate phase and the latest received comparison result (e.g., the latest output of the XOR gate) corresponding to the same candidate phase, and temporarily storing the result as temporary data for later use. In this way, multiple margin intersections can be obtained, where these margins are derived from comparison results associated with multiple sampling results obtained by sampling at multiple different clock edges (e.g., the rising edge and / or falling edge of the reference clock signal).

[0101] According to one embodiment of the present invention, the determining circuit 532 can locate a first edge (e.g., a left edge or a forward-direction edge) and a second edge (e.g., a right edge or a backward-direction edge) of the margin, and determine the optimal phase based on the first edge and the second edge. According to another embodiment of the present invention, the determining circuit 532 can obtain a first phase index value for the first edge, obtain a second phase index value for the second edge, and obtain a phase index value for the optimal phase based on the first phase index value and the second phase index value. According to another embodiment of the present invention, the determining circuit 532 can determine an adjustment amount of the sampling phase of the base clock signal based on the first phase index value and the second phase index value, so as to move the sampling phase to the position of the optimal phase.

[0102] According to one embodiment of the present invention, the decision circuit 532 can locate the edges or the phase index values ​​of the edges based on the margin pattern finally obtained by the register circuit 531 after each data block is completed. Furthermore, when data transmission in a given data block ends (e.g., when the EOB indicator is received), the decision circuit 532 can receive information about the final margin pattern from the register circuit 531. This information can be the intersection of multiple margins (i.e., the intersection of multiple comparison results sequentially output by the comparison circuit 520 and corresponding to each candidate phase), and locate the edges of the margins or the phase index values ​​of the edges based on the final margin pattern.

[0103] According to one embodiment of the present invention, the optimal phase can be a central phase within the final margin. Assuming that the value n_F is the phase index value of the first edge of the final margin (e.g., the left edge or the forward edge), the value n_B is the phase index value of the second edge of the final margin (e.g., the right edge or the backward edge), and the value n_C is the phase index value currently set for the sampling phase used for sampling data, the optimal phase is the central phase within the final margin, and the phase index value of the optimal phase can be determined by the following formula:

[0104] n_C-(n_F-n_B) / 2, when n_F>n_B, equation (1)

[0105] n_C+(n_B-n_F) / 2, when n_B> n_F, equation (2)

[0106] In embodiments of the present invention, the relevant information of the optimal phase may be the phase index value of the located optimal phase, or the sampling phase adjustment value used to move the sampling phase of the basic clock signal to the optimal phase.

[0107] Figure 6 This illustrates a state machine example of performing clock phase control according to one embodiment of the present invention. In state 610, the device interface awaits processing by the processor of the electronic device (e.g., ...). Figure 1 The host device 130 (processor 131) issued a read command. When the indicator EOB or other commands are received, state 610 can be entered. In response to the receipt of the read command, state 620 can be entered. In state 620, the device interface can wait for the indicator SOB. When the indicator SOB is received, state 630 is entered. In state 630, the device interface can read data provided by the data storage device in response to the read command, including the operation of sampling the data. Before receiving the indicator EOB, the device interface can jump to state 640 when the sampling result is obtained to compare the sampling result and update the phase index values ​​n_F and n_B of the two edges of the margin obtained at the latest comparison result. When the phase index values ​​of the edges are updated, the device interface can jump back to state 630 to continue sampling the data. When the indicator EOB is received, the device interface can jump to state 650 to determine the new phase index value to be set for the sampling phase of the sampled data according to the above equations (1) and (2). Figure 6 In the illustrated embodiment, the phase index value n_C, which is set for the sampling phase of the sampled data, is updated or adjusted to a new value based on the adjustment value of the sampling phase of the base clock signal, thereby moving the sampling phase to the newly determined optimal phase, i.e., as shown... Figure 6 The setting shown is [n_C = n_C - (n_F - n_B) / 2], or [n_C = n_C + (n_B - n_F) / 2].

[0108] In traditional designs, the host device estimates the sampling phase used to sample data received from the data storage device during the initialization process to obtain a sampling phase setting, which remains unchanged. However, as the temperature rises, the previously estimated sampling phase may become inconsistent with the phase actually used by the data storage device to output data, thereby increasing the error rate of the host device's sampled data.

[0109] Unlike conventional designs, in embodiments of the present invention, the sampling phase used to sample data received from the data storage device is updated or adjusted in response to the transmission of each data block, for example, after each data block transmission. Alternatively, in other embodiments of the present invention, the sampling phase used to sample data received from the data storage device is updated or adjusted after multiple data block transmissions, or periodically or non-periodically updated or adjusted based on the latest sampling result during data transmission. That is, in embodiments of the present invention, the sampling phase used to sample data received from the data storage device is continuously updated or adjusted based on the latest sampling result during data transmission. In embodiments of the present invention, the sampling phase used to sample data received from the data storage device can be repeatedly or multiple times adjusted in response to the same read instruction, such as... Figure 3 The multiple "update sampling phase setting" operations shown indicate that the host device may use different sampling phases to sample data received from the data storage device in response to the same read command.

[0110] In other words, unlike traditional designs that estimate the sampling phase setting during initialization and then leave it unchanged, and unlike traditional designs that wait until data errors are detected before re-estimating or adjusting the sampling phase, in embodiments of this invention, the host device continuously updates or adjusts the sampling phase based on the latest sampling results during data transmission, particularly during data transmission in response to a single read command. In this way, regardless of changes in the actual optimal phase for correctly sampling data (e.g., due to high temperature or other reasons), the host device can quickly and accurately lock the sampling phase to the actual optimal phase for correctly sampling data, and can avoid generating erroneous sampling results.

[0111] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A clock phase control circuit, comprising: A sampling circuit receives multiple reference clock signals and, in response to a read command, samples data read from a memory device based on these reference clock signals to obtain multiple sampling results, wherein the reference clock signals are generated based on a fundamental clock signal with multiple different candidate phases; and A phase monitoring circuit receives these sampling results and determines an optimal phase based on them. The data read from the memory device includes data within one or more data blocks that are sequentially received in response to the read command, and In response to the end of each data block, a sampling phase of the underlying clock signal used to sample the data read from the memory device is adjusted according to the optimal phase.

2. The clock phase control circuit as described in claim 1, characterized in that, These reference clock signals are generated by a clock signal generation circuit, and in response to the end of each data block, the phase monitoring circuit determines the optimal phase and provides the relevant information of the optimal phase to the clock signal generation circuit to adjust the sampling phase of the base clock signal.

3. The clock phase control circuit as described in claim 1, characterized in that, These sampling results include multiple predetermined sampling results obtained based on the data within a predetermined data block in one or more data blocks, and the sampling circuit continuously samples the data within the predetermined data block at multiple edges of these reference clock signals to obtain these predetermined sampling results.

4. The clock phase control circuit as described in claim 3, characterized in that, These edges include at least one of the multiple rising edges and multiple falling edges of these reference clock signals.

5. The clock phase control circuit as described in claim 3, characterized in that, These different candidate phases include the sampling phase of the underlying clock signal currently set for sampling the data, these predetermined sampling results include a first predetermined sampling result corresponding to the sampling phase, and the phase monitoring circuit includes: A comparison circuit receives these predetermined sampling results and compares these predetermined sampling results corresponding to these different candidate phases with the first predetermined sampling result corresponding to the sampling phase to generate multiple comparison results; and An optimal phase determination circuit receives these comparison results and determines the optimal phase based on these comparison results.

6. The clock phase control circuit as described in claim 5, characterized in that, The optimal phase determination circuit further determines a margin for correctly sampling the data within the given data block based on these comparison results, and determines the optimal phase based on this margin.

7. The clock phase control circuit as described in claim 6, characterized in that, The optimal phase determination circuit includes: A register circuit receives comparison results generated sequentially based on predetermined sampling results obtained at these edges of the reference clock signals, and updates a pattern of the margin according to the most recently received comparison results; and A determining circuit locates a first edge and a second edge of the margin based on the pattern, and locates the optimal phase based on the first edge and the second edge.

8. The clock phase control circuit as described in claim 7, characterized in that, The optimal phase is a central phase within this margin.

9. An electronic device coupled to a data storage device, comprising: A receiving circuit receives data read from a memory device of the data storage device; as well as A signal processing circuit processes the data, wherein the data includes data within one or more data blocks sequentially transmitted in response to a read instruction, and the signal processing circuit includes: A clock signal generation circuit generates multiple reference clock signals based on a base clock signal with multiple different candidate phases, wherein these different candidate phases include a sampling phase of the base clock signal currently set for sampling the data; and A clock phase control circuit repeatedly determines an optimal phase based on multiple sampling results obtained from these reference clock signals, and provides the relevant information of the optimal phase to the clock signal generation circuit in response to the end of each data block, so as to adjust the sampling phase of the base clock signal.

10. The electronic device as claimed in claim 9, characterized in that, The clock signal generation circuit includes a delay-locked loop circuit.

11. The electronic device as claimed in claim 9, characterized in that, The clock phase control circuit includes: A sampling circuit receives these reference clock signals and, in response to the read command, samples the data according to these reference clock signals to obtain the sampling results; and A phase monitoring circuit receives these sampling results and determines the optimal phase based on these sampling results.

12. The electronic device as claimed in claim 11, characterized in that, These sampling results include multiple predetermined sampling results obtained based on the data within a predetermined data block in one or more data blocks, and the sampling circuit continuously samples the data within the predetermined data block at multiple edges of these reference clock signals to obtain these predetermined sampling results.

13. The electronic device as claimed in claim 12, characterized in that, These edges include at least one of the multiple rising edges and multiple falling edges of these reference clock signals.

14. The electronic device as claimed in claim 12, characterized in that, These predetermined sampling results include a first predetermined sampling result corresponding to the sampling phase, and the phase monitoring circuit includes: A comparison circuit receives these predetermined sampling results and compares these predetermined sampling results corresponding to these different candidate phases with the first predetermined sampling result corresponding to the sampling phase to generate multiple comparison results; and An optimal phase determination circuit receives these comparison results and determines the optimal phase based on these comparison results.

15. The electronic device as claimed in claim 14, characterized in that, The optimal phase determination circuit further determines a margin for correctly sampling the data within the given data block based on these comparison results, and determines the optimal phase based on this margin.

16. The electronic device as claimed in claim 15, characterized in that, The optimal phase determination circuit includes: A register circuit receives comparison results generated sequentially based on predetermined sampling results obtained at these edges of the reference clock signals, and updates a pattern of the margin according to the most recently received comparison results; and A determining circuit locates a first edge and a second edge of the margin based on the pattern, and locates the optimal phase based on the first edge and the second edge.

17. The electronic device as claimed in claim 16, characterized in that, The optimal phase is a central phase within this margin.

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