Voltage value shifter
By introducing a boost circuit into the voltage shifter to pre-charge the input, the problems of excessive power consumption and slow signal transition speed caused by the equal driving capabilities of the pull-up and pull-down components are solved, thus achieving the effect of reducing voltage pull and improving signal transition speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2026-04-10
AI Technical Summary
In existing voltage shifters, the driving capabilities of the pull-up and pull-down components are comparable during voltage signal switching, resulting in excessive power consumption and slow signal transition speed.
By employing a voltage level shifting circuit and a boost circuit, the voltage value at the boost input terminal is increased by pre-charging the boost input terminal, thereby weakening the driving capability of the pull-up component and reducing voltage pull.
It reduces voltage pull, decreases power consumption, and increases the speed of signal transition.
Smart Images
Figure CN121838844A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to an electronic circuit, and more particularly, to a voltage level shifter. BACKGROUND
[0002] Generally, electronic products can switch between different operating voltage ranges by a voltage level shifter, so as to achieve various functions. For example, a memory device includes a voltage level shifter, and performs a shifting operation between different voltage values by the voltage level shifter.
[0003] However, since the driving capability between the pull-up component and the pull-down component in the current voltage level shifter is equivalent, the voltage pulling fight between the pull-up component and the pull-down component on the output end is intense in the operation of switching the voltage signal from the low voltage value to the high voltage value. Thus, the power consumption of the current voltage level shifter is too large, and the signal transition speed is reduced. SUMMARY
[0004] Embodiments of the present invention provide a voltage level shifter, which can reduce voltage pulling, and thus reduce power consumption and improve signal transition speed.
[0005] According to embodiments of the present invention, a voltage level shifter of embodiments of the present invention includes a voltage level shifting circuit and a boost circuit. The voltage level shifting circuit includes a first boost input end, a second boost input end, a first reference input end, and a second reference input end. The voltage level shifting circuit operates between a first voltage and a second voltage. The boost circuit is coupled to the voltage level shifting circuit. The boost circuit is used to pre-charge the first boost input end and the second boost input end to a third voltage value, and boost the third voltage value to a fourth voltage value according to a differential signal provided to the first reference input end and the second reference input end.
[0006] Based on the above, the voltage level shifter of embodiments of the present invention can improve the voltage value on the multiple boost input ends of the voltage level shifting circuit by pre-charging the multiple boost input ends by the boost circuit, and thus reduce voltage pulling. In this way, the voltage level shifter can reduce power consumption and improve signal transition speed. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 is a block diagram of a voltage level shifter according to an embodiment of the present invention;
[0008] Figure 2 is a circuit diagram of a voltage level shifter according to an embodiment of the present invention;
[0009] Figure 3 is a circuit diagram of a voltage level shifter according to an embodiment of the present invention; Figure 2An operation schematic of the voltage value shifter shown in the embodiment.
[0010] Explanation of reference numerals
[0011] 100, 200: voltage value shifter
[0012] 110, 210: voltage level shift circuit
[0013] 120, 220: boost circuit
[0014] 211: cross-coupled transistor pair
[0015] 212: differential transistor pair
[0016] 221: first boost circuit block
[0017] 222: second boost circuit block
[0018] 230: inverter
[0019] C1-C2: capacitor
[0020] IN: differential signal pair
[0021] IN1: first differential signal
[0022] IN2: second differential signal
[0023] M1-M8: transistor
[0024] N1: first boost input
[0025] N2: second boost input
[0026] N3: first reference input
[0027] N4: second reference input
[0028] N5-N6: node
[0029] O / P: output voltage
[0030] O / PN: voltage on node N5
[0031] t0-t2: time
[0032] V1: first voltage value
[0033] V2: second voltage value
[0034] V3: third voltage value
[0035] VCC: supply voltage
[0036] VH: a first voltage;
[0037] VM1: a voltage on the first boosted input;
[0038] VM2: a voltage on the second boosted input;
[0039] VSS: a second voltage. DETAILED DESCRIPTION
[0040] Referring now to the Figure 1 The voltage value shifter 100 can be, for example, a high voltage voltage value shifter. The voltage value shifter 100 is configured to perform a shift operation between a voltage value of a first voltage VH and a voltage value of a second voltage VSS. The first voltage VH can be, for example, a high supply voltage. The second voltage VSS can be, for example, a low supply voltage. The voltage value shifter 100 can be, for example, a single-ended output and differential input circuit configuration.
[0041] In Figure 1 In an embodiment, the voltage value shifter 100 includes a voltage level shifting circuit 110 and a boosting circuit 120. The voltage level shifting circuit 110 is coupled to the boosting circuit 120. In detail, the voltage level shifting circuit 110 operates between the first voltage VH and the second voltage VSS. The voltage level shifting circuit 110 includes a first boosted input N1, a second boosted input N2, a first reference input N3, and a second reference input N4. The first boosted input N1 and the second boosted input N2 are coupled to the boosting circuit 120. The first reference input N3 and the second reference input N4 are coupled to the boosting circuit 120 and receive a differential signal pair IN provided thereto.
[0042] In the shift operation, the boosting circuit 120 precharges the first boosted input N1 and the second boosted input N2 to a third voltage value. The boosting circuit 120 boosts the third voltage value on the first boosted input N1 and the second boosted input N2 to a fourth voltage value according to the differential signal pair IN. The fourth voltage value is greater than the third voltage value.
[0043] It is worth mentioning that by precharging the boosting inputs N3-N4 of the voltage level shifting circuit 110 by the boosting circuit 120, the voltage value shifter 100 is able to increase the voltage values on these boosting inputs N3-N4. Therefore, based on the increased voltage values (i.e., the third voltage value), the driving capability of the pull-up components in the voltage level shifting circuit 110 is able to be weakened, thereby reducing voltage pulling. In this way, the voltage value shifter 100 is able to reduce power consumption and increase the speed of signal transition, thereby reducing transient current.
[0044] Referring now to the Figure 2The voltage value shifter 200 includes a voltage level shifter 210 and a boost circuit 220. The voltage level shifter 210 and the boost circuit 220 can be referred to the related descriptions of the voltage value shifter 100 and be analogized.
[0045] In Figure 2 In an embodiment, the boost circuit 220 includes a first boost circuit block 221 and a second boost circuit block 222. The first boost circuit block 221 is coupled to a first boost input terminal N1 and a first reference input terminal N3 of the voltage level shifter 210. The first boost circuit block 221 receives a supply voltage VCC. In the embodiment, the supply voltage VCC has a third voltage value.
[0046] Specifically, the first boost circuit block 221 includes a first transistor M1 and a first capacitor C1. The first transistor M1 can be implemented, for example, in an n-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). In the embodiment, the first transistor M1 can be a native transistor. That is, the first transistor M1 has a threshold voltage value close to zero. In other embodiments, the transistor M1 can also be a normal transistor, and the threshold voltage value is less than the voltage value of the supply voltage VCC.
[0047] In detail, a control terminal (i.e., a gate terminal) and a first terminal (i.e., a first source / drain terminal) of the first transistor M1 are coupled together and receive the supply voltage VCC. That is, the first transistor M1 is in a diode-connected state. A second terminal (i.e., a second source / drain terminal) of the first transistor M1 is coupled to the first boost input terminal N1 and a first terminal of the first capacitor C1. A second terminal of the first capacitor C1 is coupled to the first reference input terminal N3.
[0048] In the embodiment, the second boost circuit block 222 is coupled to a second boost input terminal N2 and a second reference input terminal N4 of the voltage level shifter 210. The second boost circuit block 222 receives the supply voltage VCC.
[0049] Specifically, the second boost circuit block 222 includes a second transistor M2 and a second capacitor C2. The second transistor M2 can be implemented, for example, in an NMOSFET. In the embodiment, the second transistor M2 can be a native transistor and has a threshold voltage value close to zero. In other embodiments, the transistor M2 can also be a normal transistor, and the threshold voltage value is less than the voltage value of the supply voltage VCC. The following descriptions are made with the transistors M1 and M2 as native transistors.
[0050] In detail, the control terminal (i.e., the gate terminal) and the first terminal (i.e., the first source / drain terminal) of the second transistor M2 are coupled together and receive a supply voltage VCC. That is, the second transistor M2 is in a diode-connected state. The second terminal (i.e., the second source / drain terminal) of the second transistor M2 is coupled to the second boost input terminal N2 and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is coupled to the second reference input terminal N4.
[0051] In this embodiment, the voltage level shifter 210 includes a cross-coupled transistor pair 211 and a differential transistor pair 212. The cross-coupled transistor pair 211 is coupled to the differential transistor pair 212. The cross-coupled transistor pair 211 has a first boost input terminal N1 to couple to the first boost circuit block 221. The cross-coupled transistor pair 211 has a second boost input terminal N2 to couple to the second boost circuit block 222. The cross-coupled transistor pair 211 receives a first voltage VH.
[0052] In detail, the cross-coupled transistor pair 211 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. These transistors M3-M6 can be implemented, for example, as p-type Metal-Oxide-Semiconductor Field-Effect Transistors (PMOSFETs), respectively.
[0053] In this embodiment, the control terminal (i.e., the gate terminal) of the third transistor M3 is coupled to a node N6. The node N6 serves as an output terminal of the voltage value shifter 200. The first terminal (i.e., the first source / drain terminal) of the third transistor M3 receives the first voltage VH. The second terminal (i.e., the second source / drain terminal) of the third transistor M3 is coupled to the first terminal (i.e., the first source / drain terminal) of the fifth transistor M5. The control terminal (i.e., the gate terminal) of the fifth transistor M5 serves as the first boost input terminal N1. The second terminal (i.e., the second source / drain terminal) of the fifth transistor M5 is coupled to the node N5.
[0054] As described above, the control terminal (i.e., the gate terminal) of the fourth transistor M4 is coupled to the second terminal (i.e., the second source / drain terminal) of the fifth transistor M5 and the differential transistor pair 212 at node N5. The first terminal (i.e., the first source / drain terminal) of the fourth transistor M4 receives the first voltage VH. The second terminal (i.e., the second source / drain terminal) of the fourth transistor M4 is coupled to the first terminal (i.e., the first source / drain terminal) of the sixth transistor M6. The control terminal (i.e., the gate terminal) of the sixth transistor M6 is the second boost input terminal N2. The second terminal (i.e., the second source / drain terminal) of the sixth transistor M6 is coupled to the control terminal (i.e., the gate terminal) of the third transistor M3 and the differential transistor pair 212 at node N6.
[0055] In this embodiment, the differential transistor pair 212 has a first reference input terminal N3 to couple to the first boost circuit block 221. The differential transistor pair 212 has a second reference input terminal N4 to couple to the second boost circuit block 222. The differential transistor pair 212 receives the second voltage VSS.
[0056] In detail, the differential transistor pair 212 includes a seventh transistor M7 and an eighth transistor M8. These transistors M7-M8 can be implemented, for example, in NMOS, respectively. The control terminal (i.e., the gate terminal) of the seventh transistor M7 is the first reference input terminal N3. The first terminal (i.e., the first source / drain terminal) of the seventh transistor M7 is coupled to the second terminal (i.e., the second source / drain terminal) of the fifth transistor M5 and the control terminal (i.e., the gate terminal) of the fourth transistor M4 at node N5. The second terminal (i.e., the second source / drain terminal) of the seventh transistor M7 receives the second voltage VSS.
[0057] As described above, the control terminal (i.e., the gate terminal) of the eighth transistor M8 is the second reference input terminal N4. The first terminal (i.e., the first source / drain terminal) of the eighth transistor M8 is coupled to the control terminal (i.e., the gate terminal) of the third transistor M3 and the second terminal (i.e., the second source / drain terminal) of the sixth transistor M6 at node N6. The second terminal (i.e., the second source / drain terminal) of the eighth transistor M8 receives the second voltage VSS.
[0058] It is noted that the sizes of the first transistor M1 and the second transistor M2 are different from those of any of the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. For example, the first transistor M1 has a shorter channel length and a thinner gate oxide than the other transistors M3-M8. The first transistor M1 and the second transistor M2 can have the same size, for example. In this way, the layout area of the boost circuit 220 can be reduced.
[0059] In this embodiment, the voltage level shifter 200 further comprises an inverter 230. A first end (i.e., an input end) of the inverter 230 is coupled to the first reference input N3. A second end (i.e., an output end) of the inverter 230 is coupled to the second reference input N4. That is, the inverter 230 provides a differential signal pair IN (i.e., a first differential signal IN1 and a second differential signal IN2) with an inversion on the first reference input N3 and the second reference input N4.
[0060] Referring to FIG. 2, the voltage level shifter 200 comprises a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, and a second capacitor C2. The first transistor M1 is coupled between a first supply voltage VCC and a first boost input N1. The second transistor M2 is coupled between the first supply voltage VCC and a second boost input N2. The third transistor M3 is coupled between the first boost input N1 and a first reference input N3. The fourth transistor M4 is coupled between the second boost input N2 and a second reference input N4. The first capacitor C1 is coupled between the first boost input N1 and the first reference input N3. The second capacitor C2 is coupled between the second boost input N2 and the second reference input N4. Figure 2 Figure 3 In FIG. 2, the horizontal axis is the operation time of the voltage level shifter 200, and the vertical axis is the voltage level. In this embodiment, the first voltage VHand the second voltage VSS have the first voltage level V1 and the second voltage level V2, respectively. The supply voltage VCC has the third voltage level V3. The first voltage level V1 is greater than the third voltage level V3, and can be, for example, 10 volts (V). The third voltage level V3 is greater than the second voltage level V2, and can be, for example, 1.8 volts. The second voltage level V2 can be, for example, a reference ground voltage level. Figure 3 In the shift operation, the voltage level shifter 200 switches the output voltage O / P from the high voltage level (i.e., the first voltage level V1) to the low voltage level (i.e., the second voltage level V2), for example, at time t1.
[0061] In detail, before time t1, the fourth transistor M4 is turned on. The third transistor M3 is turned off. The first transistor M1 is turned on to pre-charge the first boost input N1 according to the supply voltage VCC. Since the first transistor M1 is a native transistor, the voltage VM1 on the first boost input N1 is pre-charged to a voltage level equal to or substantially equal to the supply voltage VCC (i.e., the third voltage level V3). Moreover, the voltage on the first reference input N3 (i.e., the first differential signal IN1 having the third voltage level V3) is also provided to the first boost input N1 through the first capacitor C1, so that the voltage VM1 has a third voltage level V3 equal to or substantially equal to twice.
[0062] Similarly, the voltage VM2 on the second boost input N2 is pre-charged to a voltage level equal to or substantially equal to the supply voltage VCC (i.e., the third voltage level V3) through the second transistor M2. Moreover, since the second reference input N4 has the second voltage level V2 (i.e., a reference ground voltage level), the voltage VM2 is maintained at the third voltage level V3.
[0063]
[0064] At time t1, the second differential signal IN2 switches from the second voltage value V2 to the third voltage value V3. The eighth transistor M8 is turned on by the second differential signal IN2 to pull down the output voltage O / P at node N6 to the voltage value of the second voltage VSS (i.e., the second voltage value V2). The third transistor M3 is turned on by the output voltage O / P at node N6.
[0065] Meanwhile, the voltage at the fourth reference input N4 (i.e., the second differential signal IN2 with the third voltage value V3) is provided through the second capacitor C2 to the second boost input N2 to pull up the voltage VM2 from the third voltage value V3 to twice the third voltage value V3. The sixth transistor M6 is reduced in the ability to be pulled up by the voltage VM2 at the second boost input N2.
[0066] Following the above description, at time t1, the first differential signal IN1 switches from the third voltage value V3 to the second voltage value V2. The seventh transistor M7 is turned off by the first differential signal IN1. The fifth transistor M5 is turned on by the voltage VM1 at the first boost input N1. The voltage O / PN at node N5 is pulled up through the third transistor M3 and the fifth transistor M5 to the voltage value of the first voltage VH (i.e., the first voltage value V1) to turn off the fourth transistor M4 and end the switching operation.
[0067] It is noted that the voltage VM2 at the second boost input N2 is pre-charged to the voltage value of the supply voltage VCC (i.e., the third voltage value V3) through the second transistor M2 and further boosted to twice the third voltage value V3 through the second capacitor C2. Therefore, in the switching operation, the voltage difference between the pull-up components (including the fourth transistor M4 and the sixth transistor M6) and the pull-down components (including the eighth transistor M8) in the voltage level shifter 210 can be adjusted to twice the third voltage value V3, thereby weakening the driving ability of the pull-up components (e.g., the sixth transistor M6) to reduce the voltage pull-up. In this way, the pull-down components can more easily and quickly pull down the output voltage O / P to the second voltage value V2 so that the corresponding voltage O / PN can be more quickly pulled up to the first voltage value V1.
[0068] In the shifting operation, the voltage value shifter 200 switches the output voltage O / P from the low voltage value (i.e., the second voltage value V2) to the high voltage value (i.e., the first voltage value V1), for example, at time t2. The operation of the voltage value shifter 200 at time t2 can be referred to the related description of the voltage value shifter 200 at time t1 and be analogized.
[0069] It should be noted that at time t2, the voltage VM1 on the first boosted input terminal N1 is pre-charged to the voltage value of the supply voltage VCC (i.e., the third voltage value V3) through the first transistor M1, and is further increased to twice the third voltage value V3 through the first capacitor C1. Therefore, in the switching operation, the control terminal of the pull-up component fifth transistor M5 in the voltage level shifter circuit 210 is adjusted to twice the third voltage value V3, thereby weakening the driving capability of the pull-up component (e.g., the fifth transistor M5), so as to reduce the voltage pull-up. In this way, the voltage pull-up can be reduced, and the pull-down component can more easily and quickly pull down the voltage O / PN to the second voltage value V2, so that the corresponding output voltage O / P can be more quickly pulled up to the first voltage value V1.
[0070] In summary, the voltage level shifter of the embodiments of the present application can increase the voltage values on the plurality of boosted input terminals of the voltage level shifter by pre-charging the boosted input terminals through the boosting circuit. Therefore, the driving capability of the pull-up component in the voltage level shifter can be weakened, thereby reducing the voltage pull-up. In this way, the voltage level shifter can reduce power consumption and increase the speed of signal transition.
[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit it; although the foregoing embodiments of the present application have been described in detail, those skilled in the art should understand that they can modify the technical solutions described in the foregoing embodiments, or make equivalent replacements to some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A voltage shifter, characterized in that, include: A voltage level shifting circuit includes a first boost input terminal, a second boost input terminal, a first reference input terminal, and a second reference input terminal, and operates between a first voltage and a second voltage; as well as A boost circuit, coupled to the voltage level shift circuit, is used to precharge the first boost input terminal and the second boost input terminal to a third voltage value, and boost the third voltage value to a fourth voltage value according to the differential signal pair provided to the first reference input terminal and the second reference input terminal.
2. The voltage shifter according to claim 1, characterized in that, The boost circuit includes: The first boost circuit block is coupled to the first boost input terminal and the first reference input terminal, and receives the supply voltage; and The second boost circuit block is coupled to the second boost input terminal and the second reference input terminal, and receives the supply voltage.
3. The voltage shifter according to claim 2, characterized in that, The power supply voltage has the third voltage value.
4. The voltage shifter according to claim 2, characterized in that, The first boost circuit block includes: A first transistor has a control terminal and a first terminal for receiving the supply voltage; and A first capacitor has a first terminal coupled to a second terminal of the first transistor and a first boost input terminal, the second terminal of the first capacitor being coupled to the first reference input terminal.
5. The voltage shifter according to claim 4, characterized in that, The second boost circuit block includes: The second transistor has a control terminal and a first terminal for receiving the supply voltage; and The second capacitor has a first terminal coupled to the second terminal of the second transistor and the second boost input terminal, and the second terminal of the second capacitor is coupled to the second reference input terminal.
6. The voltage shifter according to claim 5, characterized in that, The voltage level shifting circuit includes: A cross-coupled transistor pair, having a first boost input and a second boost input, and receiving the first voltage; and A differential transistor pair, coupled to the cross-coupled transistor pair, has a first reference input terminal and a second reference input terminal, and receives the second voltage.
7. The voltage shifter according to claim 6, characterized in that, The cross-coupled transistor pair includes: The third transistor has a first terminal that receives the first voltage; The fourth transistor has a first terminal that receives the first voltage; A fifth transistor has a control terminal serving as the first boost input terminal; a first terminal of the fifth transistor is coupled to a second terminal of the third transistor; a second terminal of the fifth transistor is coupled to the control terminal of the fourth transistor and the differential transistor pair; and The sixth transistor has a control terminal as the second boost input terminal, the first terminal of the sixth transistor is coupled to the second terminal of the fourth transistor, and the second terminal of the sixth transistor is coupled to the control terminal of the third transistor and the differential transistor pair.
8. The voltage shifter according to claim 7, characterized in that, The differential transistor pair includes: A seventh transistor has a control terminal serving as the first reference input terminal, a first terminal of the seventh transistor coupled to the second terminal of the fifth transistor and the control terminal of the fourth transistor, and the second terminal of the seventh transistor receiving the second voltage; and The eighth transistor has a control terminal as the second reference input terminal, a first terminal of the eighth transistor is coupled to the second terminal of the sixth transistor and the control terminal of the third transistor, and the second terminal of the eighth transistor receives the second voltage.
9. The voltage shifter according to claim 8, characterized in that, The dimensions of the first transistor and the second transistor are different from the dimensions of any one of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor.
10. The voltage shifter according to claim 1, characterized in that, Also includes: An inverter having a first terminal coupled to the first reference input terminal and a second terminal coupled to the second reference input terminal.