EFUSE burning yield detection method

Abstract

The invention provides an EFUSE burning yield detection method, and solves the problems of insufficient electrical verification accuracy, wafer sample waste and low test efficiency during EFUSE burning verification in the prior art by providing a method combining morphology image acquisition and electrical test. According to the method, the burning condition is controlled, the morphology image after burning is captured by adopting an imaging technology, and whether EFUSE burning succeeds or not can be more accurately judged in combination with an electrical test result, so that the detection precision of the burning yield is improved, damage and waste of a wafer sample in traditional FA slice analysis are avoided, the test efficiency is remarkably improved, and the test cost is reduced. The whole cost is reduced, meanwhile, a more efficient and more economical monitoring means is provided for the EFUSE burning and adjusting process, and therefore remarkable beneficial effects are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an EFUSE burn-in yield detection method. BACKGROUND

[0002] With the rapid development of semiconductor technology, the manufacturing process of integrated circuits (IC) becomes increasingly complex, and the requirements for device performance also increase. In this context, electrical fuse (EFUSE) as a one-time programmable non-volatile storage element plays a key role in integrated circuits. EFUSE is mainly used to permanently write or configure key information, repair defects or enhance security after chip manufacturing is completed (even after the final product is shipped).

[0003] The core function of EFUSE is to configure the chip as different models, function levels or working modes during the packaging test phase by burning out specific EFUSE. Due to the inherent small deviations in semiconductor manufacturing process, by calculating the amount of adjustment, selectively burning out some fuses in the EFUSE array to connect or disconnect the trimming resistance network or adjust the control bit, the circuit parameters are accurately calibrated to the target value.

[0004] The success of EFUSE burn-in is monitored by WAT wafer electrical test to reflect the size of the resistance by observing the change of current after burn-in, and by slice failure analysis (FA) to observe the change inside the structure to extract the best burn-in condition. However, EFUSE burn-in requires experiments of multiple voltage parameters and time, and a large number of electrical test results are needed to characterize the yield of EFUSE burn-in, so as to select the appropriate and optimal burn-in condition. In addition, due to the interference of the test environment, the accuracy of the electrical data may be affected, and FA slicing needs to be performed simultaneously to observe the state of the structure after burn-in. Each FA slicing requires more time, prolonging the overall time of burn-in, and each slicing will damage a wafer, and after slicing, the electrical test cannot be performed again, resulting in the waste of many testable samples, and the electrical test of other TSK will also be affected, causing a large cost and reducing the overall efficiency. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an EFUSE burn-in yield detection method to solve the problems of insufficient accuracy of electrical verification, waste of wafer samples by slicing analysis and low test efficiency in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides an EFUSE burn-in yield detection method, which comprises:

[0007] S1, providing several EFUSE structures, each EFUSE structure including an EFUSE fuse structure and test keys connected to both ends of the EFUSE fuse structure, the EFUSE fuse structure including, from bottom to top, a substrate, a dielectric layer, a polysilicon layer and a metal silicide layer;

[0008] S2, the same firing conditions are used to fire and adjust the EFUSE fuse structure of all the EFUSE structures, including the metal silicide layer and the polysilicon layer.

[0009] S3. Collect morphological images of the burn-in areas on the upper surface of all the EFUSE fuse structures, and perform electrical tests on the EFUSE structures using the test keys.

[0010] S4. Combine the morphological image of the burn-in area and the electrical test results to determine whether the corresponding EFUSE structure has been successfully burn-in.

[0011] S5. Calculate the burn-in yield based on the ratio of the number of successfully burn-in EFUSE structures to the total number of all EFUSE structures.

[0012] Optionally, the EFUSE fuse structure includes a fuse chain and electrical lead-out structures connected to both ends of the fuse chain. The width of the fuse chain is smaller than the width of the electrical lead-out structures, and the electrical lead-out structures are electrically connected to the test keys at the corresponding ends.

[0013] Further, in step S2, the fuse chain of the EFUSE fuse structure is heated and adjusted.

[0014] Optionally, the test key includes a conductive layer, or the test key includes multiple metal layers, and adjacent metal layers are electrically connected by conductive plugs.

[0015] Optionally, the dielectric layer comprises an oxide layer, a nitride layer, or a stack of oxide and nitride layers.

[0016] Optionally, in step S3, visible light imaging technology is used to acquire morphological images of the burn-in areas on the upper surface of all the EFUSE fuse structures.

[0017] Optionally, in step S3, deep ultraviolet or extreme ultraviolet imaging technology is used to acquire morphological images of the burn-in areas on the upper surface of all the EFUSE fuse structures.

[0018] Optionally, in step S4, the method for determining whether the corresponding EFUSE structure has been successfully fired up by combining the morphological image of the firing area and the electrical test results includes:

[0019] comparing the post-burn-in topography image with a pre-burn-in topography image or with an ideal EFUSE fuse structure image to identify whether the post-burn-in topography image has a burn-out feature;

[0020] comparing the resistance value in the electrical test result with a preset resistance threshold value;

[0021] determining whether the EFUSE structure is successfully burn-in based on the topography image analysis result and the electrical test result.

[0022] Further, the burn-out feature includes a fracture and / or a hole of the polysilicon layer.

[0023] Optionally, after step S5, the method further comprises a step of establishing a correlation model between the burn-in yield and the burn-in condition.

[0024] As described above, the EFUSE burn-in yield detection method of the present application has the following beneficial effects: by providing a method combining topography image acquisition and electrical test, the problems of insufficient electrical verification accuracy, wafer sample waste and low test efficiency in the prior art EFUSE burn-in verification are solved. The method can more accurately determine whether the EFUSE burn-in is successful by controlling the burn-in condition and using imaging technology to capture the post-burn-in topography image in combination with the electrical test result. The topography image analysis provides intuitive comparative analysis, improving the accuracy of determining whether the burn-in is successful. The electrical test provides quantitative data support, enhancing the reliability of determining whether the burn-in is successful. And through optical imaging technology, the detection can be performed without damaging the EFUSE structure, avoiding destructive section analysis, reducing material waste and test cost, thereby reducing the overall production cost. The imaging process can be performed in real time, problems occurring in the burn-in process can be found in time, and the burn-in condition can be adjusted in time. Through fast and accurate imaging technology, the burn-in and test cycle is shortened, the production efficiency is improved, a more efficient and more economical monitoring means for the EFUSE burn-in process is provided, and significant beneficial effects are obtained. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A flowchart of the EFUSE burn-in yield detection method of the present application is shown.

[0026] Figure 2 A planar structure schematic diagram of the EFUSE structure of the present application is shown.

[0027] Figure 3 A cross-sectional structure schematic diagram of the EFUSE structure of the present application along the AA' direction is shown. Figure 2

[0028] Figure 4 ​A top surface image of an EFUSE fuse structure before programming, which is an example of the present application.

[0029] Figure 5 A top surface image of an EFUSE fuse structure after programming, which is an example of the present application.

[0030] Element No. Explanation: 1 EFUSE fuse structure, 10 substrate, 101 substrate doped layer, 11 dielectric layer, 12 polysilicon layer, 121 electrical lead-out structure, 122 fuse chain, 123 electrical lead-out metal layer, 13 metal silicide layer, 14 sidewall dielectric layer, 15 insulating layer, 16 conductive via, 2 test key, 20 metal layer, 201 first metal layer, 202 second metal layer, 203 third metal layer, 204 fourth metal layer, 205 fifth metal layer, 206 sixth metal layer, 21 conductive plug, 210 first conductive plug, 211 second conductive plug, 212 third conductive plug, 213 fourth conductive plug, 214 fifth conductive plug, 22 interlayer dielectric layer, S1-S5 steps. DETAILED DESCRIPTION

[0031] The present application will be described in detail with specific embodiments hereinafter, and those skilled in the art will easily understand other advantages and effects of the present application from the contents disclosed in the specification. The present application can also be implemented or applied in other different embodiments, and various modifications or changes can be made to the details in the specification without departing from the spirit of the present application.

[0032] Please refer to Figures 1 to 5 . It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and thus the diagrams only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, number and ratio of the components in actual implementation can be arbitrarily changed, and the component layout type can also be more complex.

[0033] The present embodiment provides an EFUSE programming yield detection method, as shown in Figure 1 , the detection method comprises:

[0034] S1, providing a plurality of EFUSE structures, the EFUSE structure comprising an EFUSE fuse structure and a test key connected to both ends of the EFUSE fuse structure, the EFUSE fuse structure comprising a substrate, a dielectric layer, a polysilicon layer and a metal silicide layer from bottom to top;

[0035] S2, programming the EFUSE fuse structure of all the EFUSE structures under the same programming condition, and the programming object includes the metal silicide layer and the polysilicon layer;

[0036] S3. Collect morphological images of the burn-in areas on the upper surface of all the EFUSE fuse structures, and perform electrical tests on the EFUSE structures using the test keys.

[0037] S4. Combine the morphological image of the burn-in area and the electrical test results to determine whether the corresponding EFUSE structure has been successfully burn-in.

[0038] S5. Calculate the burn-in yield based on the ratio of the number of successfully burn-in EFUSE structures to the total number of all EFUSE structures.

[0039] This embodiment of the EFUSE burn-in yield detection method addresses the problems of insufficient accuracy in electrical verification, wafer sample waste, and low testing efficiency in existing EFUSE burn-in verification techniques by providing a method that combines morphological image acquisition and electrical testing. This method controls burn-in conditions and uses imaging technology to capture morphological images after burn-in. Combined with electrical test results, it can more accurately determine whether EFUSE burn-in was successful. Morphological image analysis provides intuitive comparative analysis, improving the accuracy of determining burn-in success, while electrical testing provides quantitative data support, enhancing the reliability of determining burn-in success. Furthermore, optical imaging technology allows for detection without damaging the EFUSE structure, avoiding destructive slicing analysis, reducing material waste and testing costs, thereby lowering overall production costs. The imaging process can be performed in real time, enabling timely detection of problems during burn-in and facilitating adjustments to burn-in conditions. Through rapid and accurate imaging technology, the burn-in and testing cycle is shortened, improving production efficiency and providing a more efficient and economical monitoring method for the EFUSE burn-in process, thus achieving significant beneficial effects.

[0040] The EFUSE burn-in yield testing method of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0041] refer to Figure 2 and Figure 3 , Figure 2 The diagram shown is a planar structural schematic of the EFUSE structure in this embodiment. Figure 3 Displayed as EFUSE structure along Figure 2 A schematic diagram of the cross-sectional structure in the AA' direction. First, step S1 is performed, providing several EFUSE structures. Each EFUSE structure includes an EFUSE fuse structure 1 and test bonds 2 connected to both ends of the EFUSE fuse structure 1. The EFUSE fuse structure 1 includes, from bottom to top, a substrate 10, a dielectric layer 11, a polysilicon layer 12, and a metal silicide layer 13.

[0042] Specifically, such asFigure 2 As shown, the EFUSE fuse structure 1 includes a fuse chain 122 and electrical lead-out structures 121 connected to both ends of the fuse chain 122, the width of the fuse chain 122 is smaller than the width of the electrical lead-out structures 121, the electrical lead-out structures 121 are electrically connected to the test key 2 of the corresponding end through an electrical lead-out metal layer 123, for example, a dielectric layer is formed on the metal silicide layer 13, the electrical lead-out metal layer 123 is electrically connected to the metal silicide layer 13 through a plurality of conductive vias 16 penetrating the dielectric layer. In the subsequent trimming process, the fuse chain 122 of the EFUSE fuse structure 1 is trimmed.

[0043] Specifically, as an example, as shown in Figure 3 As shown, the substrate 10 includes but is not limited to a silicon substrate, and the silicon substrate can further include a doped layer 101 inside to adjust the electrical properties of the silicon substrate, such as resistivity and carrier concentration, and further optimize the electrical performance of the EFUSE structure.

[0044] Specifically, as an example, as shown in Figure 3 As shown, the dielectric layer 11 and the sidewall of the polysilicon layer 12 further include a sidewall dielectric layer 14, and an insulating layer 15 can be formed on the surface of the sidewall dielectric layer 14 on the dielectric layer 11. The specific film layers of the EFUSE structure and the specific shape of the polysilicon layer 12 at both ends of the fuse chain 122 structure can be designed according to actual needs, not limited to the present embodiment.

[0045] Specifically, as an example, the test key 2 includes at least one conductive layer to realize electrical conduction through a contact probe to perform a trimming process and an electrical test after the trimming process, further, the test key 2 can only include one conductive layer, or as Figure 3As shown, the test key 2 includes multiple metal layers 20, and two adjacent metal layers 20 are electrically connected by a conductive plug 21. As a specific example, in this embodiment, the metal layers 20 include, from bottom to top, a first metal layer 201, a second metal layer 202, a third metal layer 203, a fourth metal layer 204, a fifth metal layer 205, and a sixth metal layer 206. The sixth metal layer 206 is made of aluminum, for example, and the conductive plug 21 includes, from bottom to top, a first conductive plug 210, a second conductive plug 211, a third conductive plug 212, a fourth conductive plug 213, and a fifth conductive plug 214. The fourth conductive plug 213 and the fifth conductive plug 214 have a larger pitch. In addition, each two adjacent metal layers 20 have an interlayer dielectric layer 22 therebetween, which includes an oxide layer or a nitride layer or a stack of oxide and nitride layers. The nitride layer includes, but is not limited to, SiON, SiN, and SiCN, and the oxide layer includes, but is not limited to, SiO2.

[0046] Next, step S2 is performed, in which the EFUSE fuse structures 1 of all the EFUSE structures are programmed under the same programming conditions, including the metal silicide layer 13 and the polysilicon layer 12.

[0047] Next, step S3 is performed, in which the top surface programming area of each EFUSE fuse structure 1 is imaged, and the EFUSE structure is electrically tested by the test key 2.

[0048] As an example, in step S3, the top surface programming area of each EFUSE fuse structure 1 is imaged by a visible light imaging technique, such as optical microscope observation and analysis.

[0049] As a preferred example, in step S3, the top surface programming area of each EFUSE fuse structure 1 is imaged by a deep ultraviolet (DUV) or extreme ultraviolet (EUV) imaging technique. Specifically, the following steps are included.

[0050] S31, a deep ultraviolet light or an extreme ultraviolet light is selected as a light source, i.e., a deep ultraviolet light or an extreme ultraviolet light imaging technique is used. The shorter wavelength of the deep ultraviolet light or the extreme ultraviolet light can provide higher resolution than traditional visible light, so that the small structural changes after programming can be more clearly captured and analyzed.

[0051] S32, the selected deep ultraviolet light or extreme ultraviolet light source is precisely positioned above the polysilicon layer 12, so that the light source can directly irradiate the surface of the programming area of the EFUSE fuse structure 1.

[0052] S33, a back-and-forth spatial region scan is performed above the polysilicon layer 12 to cover the entire firing area and ensure comprehensive detection.

[0053] S34, detect the deep ultraviolet or extreme ultraviolet light reflected from the upper surface of the polycrystalline silicon layer 12. The intensity and distribution of this reflected light are closely related to the structural changes of the polycrystalline silicon layer 12, because the polycrystalline silicon layer 12 in different structural states will reflect these short-wavelength lights in different ways. For example, morphological changes such as fractures and voids generated during the firing process will cause changes in the intensity and distribution of the reflected light. By capturing these changes, a morphological image of the firing area can be generated, thereby analyzing the firing effect and quality.

[0054] S35, continuously capture images of multiple polysilicon regions 12 to continuously acquire morphological images of multiple EFUSE fuse structure 1 upper surface sintering regions under the same sintering conditions.

[0055] S36 performs preprocessing on the captured image, such as noise reduction, contrast enhancement, or edge detection, to improve image quality.

[0056] Next, proceed to step S4, and determine whether the corresponding EFUSE structure has been successfully burned by combining the morphological image of the burn-in area and the electrical test results.

[0057] As a specific example, in step S4, the method for determining whether the corresponding EFUSE structure has been successfully fired up by combining the morphological image of the firing area and the electrical test results includes:

[0058] The morphology image after heat treatment is compared and analyzed with the morphology image before heat treatment or with an ideal EFUSE fuse structure image to identify whether there are burn-off features in the morphology image after heat treatment; wherein, the burn-off features include fractures and / or voids in the polysilicon layer 12. Figure 4 The image shown is an example of the morphology of the upper surface of the EFUSE fuse structure 1 before firing. It can be seen that the polysilicon layer 12 is intact, without breaks or holes. Figure 5 The image shown is an example of the morphology of the upper surface of EFUSE fuse structure 1 after heat treatment, and... Figure 4 compared to, Figure 5 It can be observed that the fuse chain 122 of the polycrystalline silicon layer 12 has undergone obvious structural changes, which allows for a direct evaluation of the effect of the firing process.

[0059] The resistance value in the electrical test results is compared with the preset resistance threshold.

[0060] The success of the burn-in of the EFUSE structure is determined based on the analysis results of the topography images and the electrical test results. For example, if the image after burn-in (such as Figure 5 ) shows the expected fracture and / or hole characteristics, and the electrical test results (such as the change in resistance value) also meet the preset threshold, it is determined that the burn-in is successful. The topography image analysis provides intuitive comparative analysis, improving the accuracy of determining whether the burn-in is successful, and the electrical test provides quantitative data support, enhancing the reliability of determining whether the burn-in is successful. Through optical imaging technology, the EFUSE structure can be detected without being damaged, avoiding destructive slicing analysis, reducing material waste and test cost, thereby reducing the overall production cost. The imaging process can be performed in real time, problems that occur during the burn-in process can be found in time, and the burn-in conditions can be adjusted in time. Through fast and accurate imaging technology, the burn-in and test cycle is shortened, and the production efficiency is improved.

[0061] Then, step S5 is performed to calculate the burn-in yield ratio based on the proportion of the number of the EFUSE structures that are successfully burned-in to the total number of the EFUSE structures.

[0062] Further, after step S5, a step of establishing a correlation model between the burn-in yield ratio and the burn-in conditions is further included. The correlation model helps to quickly identify the best burn-in parameters, improve the yield, reduce the cost, and reduce material waste, while enhancing the predictability and reliability of the production process, making the decision more data-driven, thereby improving the overall production efficiency and product quality.

[0063] In summary, the EFUSE burn-in yield detection method of the present application provides a method combining topography image acquisition and electrical testing, solving the problems of insufficient electrical verification accuracy, wafer sample waste and low testing efficiency in the prior art EFUSE burn-in verification. The method controls the burn-in conditions and uses imaging technology to capture the topography image after burn-in, combined with the electrical test results, to more accurately determine whether the EFUSE burn-in is successful. The topography image analysis provides intuitive comparative analysis, improving the accuracy of determining whether the burn-in is successful, and the electrical testing provides quantitative data support, enhancing the reliability of determining whether the burn-in is successful. And through optical imaging technology, the detection can be carried out without damaging the EFUSE structure, avoiding destructive section analysis, reducing material waste and testing cost, thereby reducing the overall production cost. The imaging process can be carried out in real time, problems that occur during the burn-in process can be found in time, and the burn-in conditions can be adjusted in time. Through fast and accurate imaging technology, the burn-in and testing cycle is shortened, the production efficiency is improved, a more efficient and more economical monitoring method is provided for the EFUSE burn-in process, thereby obtaining significant beneficial effects. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0064] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for detecting the yield of EFUSE burn-in, characterized in that, The detection method includes: S1, providing several EFUSE structures, each EFUSE structure including an EFUSE fuse structure and test keys connected to both ends of the EFUSE fuse structure, the EFUSE fuse structure including, from bottom to top, a substrate, a dielectric layer, a polysilicon layer and a metal silicide layer; S2, the same firing conditions are used to fire and adjust the EFUSE fuse structure of all the EFUSE structures, including the metal silicide layer and the polysilicon layer. S3. Collect morphological images of the burn-in areas on the upper surface of all the EFUSE fuse structures, and perform electrical tests on the EFUSE structures using the test keys. S4. Combine the morphological image of the burn-in area and the electrical test results to determine whether the corresponding EFUSE structure has been successfully burn-in. S5. Calculate the burn-in yield based on the ratio of the number of successfully burn-in EFUSE structures to the total number of all EFUSE structures.

2. The EFUSE burn-in yield testing method according to claim 1, characterized in that: The EFUSE fuse structure includes a fuse chain and electrical lead-out structures connected to both ends of the fuse chain. The width of the fuse chain is smaller than the width of the electrical lead-out structures, and the electrical lead-out structures are electrically connected to the test keys at the corresponding ends.

3. The EFUSE burn-in yield testing method according to claim 2, characterized in that: In step S2, the fuse chain of the EFUSE fuse structure is heated and adjusted.

4. The EFUSE burn-in yield testing method according to claim 1, characterized in that: The test key includes a conductive layer, or the test key includes multiple metal layers, and adjacent metal layers are electrically connected by conductive plugs.

5. The EFUSE burn-in yield testing method according to claim 1, characterized in that: The dielectric layer includes an oxide layer, a nitride layer, or a stack of oxide and nitride layers.

6. The EFUSE burn-in yield testing method according to claim 1, characterized in that: In step S3, visible light imaging technology is used to acquire morphological images of the burn-in areas on the upper surface of all the EFUSE fuse structures.

7. The EFUSE burn-in yield testing method according to claim 1, characterized in that: In step S3, deep ultraviolet or extreme ultraviolet imaging technology is used to acquire morphological images of the burn-in areas on the upper surface of all the EFUSE fuse structures.

8. The EFUSE burn-in yield testing method according to claim 1, characterized in that, In step S4, the method for determining whether the corresponding EFUSE structure has been successfully fired up by combining the morphological image of the firing area and the electrical test results includes: The morphology image after heat treatment is compared and analyzed with the morphology image before heat treatment or with the ideal EFUSE fuse structure image to identify whether there are burn-off features in the morphology image after heat treatment. The resistance value in the electrical test results is compared with a preset resistance threshold. The success of the EFUSE structure was determined by combining the results of morphological image analysis and electrical test results.

9. The EFUSE burn-in yield testing method according to claim 8, characterized in that: The burn-off features include fractures and / or voids in the polycrystalline silicon layer.

10. The EFUSE burn-in yield detection method according to claim 1, characterized in that: After step S5, the method further includes establishing a correlation model between the firing yield and the firing conditions.

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