Wafer and preparation process thereof, laser device and preparation process thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN GUANGMAO ELECTRONICS
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-23
Smart Images
Figure CN121840347B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of semiconductor devices, and more specifically, to a wafer and its fabrication process, and a laser device and its fabrication process. Background Technology
[0002] Currently, AlGaInP quaternary semiconductor chips typically use GaAs substrates. Because the bandgap of GaAs substrates is narrower than that of AlGaInP, photons emitted downwards from the active region are absorbed, significantly reducing luminous efficiency. To prevent substrate light absorption, a distributed Bragg reflector (DBR) is usually added between the substrate and the active layer to reflect light incident on the substrate and reduce GaAs absorption. However, since the DBR only effectively reflects light within a small angle (typically DBR < 20°) in the normal direction, most light rays incident far from the normal are absorbed by the GaAs substrate, thus its effect is minimal.
[0003] In order to improve luminescence efficiency, people began to study other substrates.
[0004] Transparent substrates (TS) replace GaAs substrates with GaP substrates that are transparent to visible light. This involves etching and peeling the long, thick GaP window layer die structure from the GaAs substrate and then bonding it to the GaP substrate, which can more than double the luminous efficiency. However, this process suffers from low yield and high manufacturing costs. Summary of the Invention
[0005] The technical problem to be solved by the embodiments of this application is how to design a chip wafer that has the advantages of high luminous efficiency, high yield rate and low manufacturing cost.
[0006] To address the aforementioned technical problems, this application provides a wafer employing the following technical solution:
[0007] A wafer includes a P-side electrode, a substrate, a metal reflective layer, an epitaxial layer, and an N-side electrode stacked together.
[0008] The substrate is a CuSiC alloy substrate;
[0009] The epitaxial layer is an AlGaInP epitaxial layer after the original substrate has been removed, and it is bonded to the metal reflective layer.
[0010] Furthermore, the metal reflective layer has a multi-layer metal structure, and the bottom layer of the metal reflective layer in contact with the CuSiC alloy substrate contains a metal material for forming a P-type ohmic contact.
[0011] Furthermore, the metal reflective layer is an AuBe / Au stacked structure, with the Au layer positioned closer to the epitaxial layer (4) than the AuBe layer.
[0012] Furthermore, the CuSiC alloy substrate has a single-sided polished structure, and the metal reflective layer is formed on the polished surface.
[0013] To address the aforementioned technical problems, this application also provides a wafer fabrication process for fabricating the aforementioned wafer, comprising the following fabrication steps:
[0014] S1. Prepare a metallic reflective layer on the surface of a CuSiC alloy substrate;
[0015] S2. Provide an AlGaInP / GaAs epitaxial wafer with a P-plane metal layer;
[0016] S3. The P-side metal layer of the epitaxial wafer is bonded to the metal reflective layer on the CuSiC alloy substrate using a low-temperature alloy bonding process.
[0017] S4. Remove the original GaAs substrate of the epitaxial wafer to form an AlGaInP epitaxial layer;
[0018] S5. A P-side electrode is fabricated on the side of the CuSiC alloy substrate away from the epitaxial layer, and an N-side electrode is fabricated on the surface of the AlGaInP epitaxial layer after the GaAs substrate has been removed.
[0019] Furthermore, the low-temperature alloy bonding is carried out under the protection of a N2 / H2 mixed atmosphere, the bonding temperature of the low-temperature alloy bonding is 250-350℃, and an axial pressure of 1-10MPa is applied.
[0020] Furthermore, the original GaAs substrate of the epitaxial wafer is removed by wet chemical etching; the etching solution used for the etching process is a mixed aqueous solution of NH4OH / H2O2, the volume ratio of NH4OH:H2O2:H2O is 1:(1-2):(20-50), the etching temperature is 20-30℃, and the etching time is 60-75min.
[0021] To address the aforementioned technical problems, this application also provides a laser device, including the aforementioned wafer.
[0022] To address the aforementioned technical problems, this application also provides a fabrication process for a laser device, wherein the laser device is a laser chip, and includes the following fabrication steps:
[0023] S1' Preparation of the intermediate body of the wafer: The substrate, the metal reflective layer and the epitaxial layer together constitute the intermediate body of the wafer, and the intermediate body of the wafer is prepared.
[0024] S2', Ridge waveguide formation: On the epitaxial layer of the central body of the wafer, the lateral optical waveguide and current confinement structure of the laser device are defined by photolithography and etching processes to form the ridge waveguide;
[0025] S3', P-side electrode fabrication: A P-side electrode with a specified pattern is formed on the side of the substrate away from the epitaxial layer;
[0026] S4', N-side processing and N-side electrode fabrication: The side of the epitaxial layer away from the P-side electrode is processed into a smooth and flat back surface, and an N-side electrode is formed on the back surface to obtain an epitaxial crystal plate.
[0027] S5', Bar preparation and cavity surface treatment: The obtained epitaxial wafer is diced / cleaved to divide the wafer into multiple bars, and an optical thin film is deposited on the cavity surface of the diced / cleaved bars;
[0028] S6', Die Separation: The laser strips coated with optical thin films are cleaved / sliced to separate them and obtain individual laser devices.
[0029] Furthermore, in step S2', the width of the ridge waveguide is controlled to be 2.5-5.0 μm by photolithography.
[0030] Compared with the prior art, the embodiments of this application have the following main advantages:
[0031] The CuSiC alloy substrate wafer of this application uses inexpensive and high-quality CuSiC wafers as substrates. The metal reflective layer of this application forms a mirror structure with a reflectivity of over 90% for red and yellow light and can reflect light from all incident angles, thus improving the light extraction efficiency by nearly 100%. In addition, due to the high mechanical strength and high thermal conductivity of the CuSiC substrate, the high-temperature characteristics of the product can be greatly improved, thereby increasing the product reliability.
[0032] Because the mirror structure eliminates the need for thick GaP window and DBR layers, it significantly reduces epitaxial material consumption, halving the epitaxial cost compared to ordinary GaAs substrates. It also boasts high yield and low manufacturing costs. The increased brightness expands the wafer's application range; for example, LED lighting and laser devices both require such ultra-high brightness wafers, indicating a promising future. Attached Figure Description
[0033] To more clearly illustrate the solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the wafer structure in the wafer fabrication process of this application embodiment.
[0035] Figure 2 This is a process flow diagram of the wafer fabrication process in the embodiments of this application.
[0036] Figure 3 This is a schematic diagram of the structure of the laser chip in the laser device fabrication process of this application embodiment.
[0037] Reference numerals: 1. P-side electrode; 2. Substrate; 3. Metallic reflective layer; 4. Epitaxial layer; 5. N-side electrode; 6. P-type contact layer; 7. P-type AlGaInP cladding; 8. N-type confinement layer. Detailed Implementation
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.
[0039] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0040] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
[0041] Reference Figure 1 A wafer includes a P-side electrode 1, a substrate 2, a metal reflective layer 3, an epitaxial layer 4, and an N-side electrode 5 stacked together.
[0042] The substrate 2 is a CuSiC alloy substrate;
[0043] The epitaxial layer 4 is an AlGaInP epitaxial layer 4 after the original substrate has been removed, and it is bonded to the metal reflective layer 3.
[0044] Furthermore, the metal reflective layer 3 is a multi-layer metal structure, and the bottom layer of the metal reflective layer 3 in contact with the CuSiC alloy substrate contains a metal material for forming a P-type ohmic contact.
[0045] Furthermore, the metal reflective layer 3 is an AuBe / Au stacked structure, wherein the bottom layer of the metal reflective layer 3 is AuBe, which is a P-type ohmic contact metal material; the Au phase is disposed closer to the epitaxial layer 4 than the AuBe phase.
[0046] Furthermore, in the fabrication of the aforementioned wafer, the CuSiC alloy substrate has a single-sided polished structure, and the metal reflective layer 3 is formed on the polished surface. The core function of the single-sided polished structure of the CuSiC alloy substrate is to provide an atomically smooth, clean, and defect-free substrate surface for depositing a high-performance metal reflective layer. This directly determines the reflectivity of the metal layer (optical performance), the contact resistance between the metal and the substrate or epitaxial layer (electrical performance), and the quality of subsequent bonding interfaces (mechanical and thermal reliability).
[0047] Through the above technical solution, the wafer of this application adopts a unique composite structure of "CuSiC substrate / metal reflective layer / GaAs substrate-free AlGaInP epitaxial layer", which effectively solves the core problems of traditional wafers in terms of light efficiency, heat dissipation, reliability and cost, and achieves a significant improvement in overall performance.
[0048] Firstly, it achieves ultra-high light extraction efficiency and omnidirectional reflection. The core improvement of the wafer in this application lies in completely abandoning the light-absorbing GaAs substrate and replacing it with a combination of "metal reflective layer + CuSiC alloy substrate". Traditional GaAs substrates strongly absorb photons emitted downward from the active region (wavelength 645nm and nearby red light), while commonly used distributed Bragg reflector (DBR) layers can only effectively reflect small-angle incident light (θ<20°). The metal reflective layer (such as Au / AuBe) of this invention has a reflectivity of over 90% for the target wavelength band (such as 590-650nm red light), and its reflection characteristics are close to ideal specular reflection, with a reflection angle range of nearly 90°, which can effectively reflect almost all downward-emitted photons and emit them from the front of the device. This fundamental change makes the overall light extraction efficiency nearly twice that of the traditional GaAs substrate structure, achieving a "high brightness" effect.
[0049] Secondly, it offers excellent thermal management and high-temperature reliability. Compared to traditional GaAs or GaP substrates, CuSiC alloy substrates possess extremely high thermal conductivity (typically >300 W / mK) and superior mechanical strength. During device operation, heat generated in the active region can be rapidly conducted to the CuSiC substrate and dissipated through the metallic reflective layer. This characteristic brings multiple advantages:
[0050] Lowering the operating junction temperature significantly improves the problem of heat accumulation in devices under high current drive or high temperature environments.
[0051] Improved power tolerance: Allows devices to operate stably at higher power levels, broadening their application range in high-power lighting, pumping, and other fields.
[0052] Enhanced long-term reliability: Lower operating temperature and better thermal stress distribution effectively delay material aging and performance degradation, significantly improving the lifespan and stability of the device.
[0053] Thirdly, it can significantly reduce manufacturing costs and simplify processes. This structure has significant cost advantages:
[0054] Low material cost: CuSiC substrate itself is a relatively inexpensive industrial material, far cheaper than GaP single crystal substrate of the same size.
[0055] Reduced epitaxial cost: Since the metal reflective layer can provide efficient, omnidirectional light reflection, there is no need to grow complex and expensive DBR reflective layers and thick GaP window layers in the AlGaInP epitaxial layer, which simplifies the epitaxial structure and reduces the direct cost of the epitaxial layer.
[0056] Reference Figure 1 and Figure 2 To address the aforementioned technical problems, this application also provides a wafer fabrication process for fabricating the aforementioned wafer, comprising the following fabrication steps:
[0057] S1. Prepare a metallic reflective layer 3 on the surface of a CuSiC alloy substrate;
[0058] S2. Provide an AlGaInP / GaAs epitaxial wafer with a P-plane metal layer;
[0059] S3. The P-side metal layer of the epitaxial wafer is bonded to the metal reflective layer 3 on the CuSiC alloy substrate using a low-temperature alloy bonding process.
[0060] S4. Remove the original GaAs substrate of the epitaxial wafer to form an AlGaInP epitaxial layer 4;
[0061] S5. A P-side electrode 1 is formed on the side of the CuSiC alloy substrate away from the epitaxial layer 4, and an N-side electrode 5 is formed on the surface of the AlGaInP epitaxial layer 4 after the GaAs substrate is removed.
[0062] Further, in step S3, the low-temperature alloy bonding is performed under a N2 / H2 mixed atmosphere. The bonding temperature of the low-temperature alloy bonding is 250-350℃, for example, it can be 250℃, 300℃, or 350℃, and an axial pressure of 1-10 MPa is applied. This range of axial pressure ensures that the bonding surfaces can fully contact under the influence of temperature and atmosphere, initiating atomic diffusion and alloying reactions to form a continuous bonding interface. While ensuring bonding quality, excessive pressure is avoided, which could lead to the following problems: cracks or dislocations in the AlGaInP epitaxial layer; warping or breakage of the CuSiC substrate or epitaxial wafer; and excessive compression of the metal layer at the bonding interface, causing it to flow into the non-bonded area or altering the predetermined interface structure.
[0063] Further, step S4 employs a wet chemical etching process to remove the GaAs substrate. The etching solution used in this process is a mixed aqueous solution of NH4OH / H2O2. This NH4OH / H2O2 mixed aqueous solution exhibits high selectivity for GaAs and an extremely low etching rate for AlGaInP. NH4OH provides OH- - Ions are the main components that corrode GaAs; H2O2 acts as an oxidant, reacting with GaAs to form oxides soluble in alkaline solutions; H2O regulates the corrosion rate and solution stability.
[0064] The mass fraction of NH4OH is 28%, the mass fraction of H2O2 is 30%, and the volume ratio of NH4OH:H2O2:H2O is 1:(1-2):(20-50). The corrosion rate can be finely controlled by adjusting the proportion of H2O2. As the proportion of H2O2 increases, the corrosion rate generally increases first and then decreases, and it also affects the surface morphology. The H2O2 proportion range of this application can control the effect well. The corrosion rate can be significantly changed by adjusting the proportion of H2O. The higher the proportion of H2O, the slower the corrosion rate. The H2O2 proportion range of this application can control the uniformity and selectivity well.
[0065] The etching temperature is 20-30℃. Temperature has a significant impact on the etching rate. For every 10℃ increase in temperature, the etching rate may increase by more than 2 times. Excessive temperature may lead to uneven etching or exacerbate the slight erosion of the AlGaInP epitaxial layer. The etching temperature of this application can achieve a stable and controllable process.
[0066] The corrosion treatment time is 60-75 minutes, which helps to obtain a good corrosion effect.
[0067] After etching is complete, immediately immerse the surface in a large volume of flowing deionized water to completely stop the reaction and dilute and rinse away any remaining etching solution. Then, perform a standard cleaning procedure to remove any remaining organic matter and metal ions from the surface.
[0068] The aforementioned technical solutions, employing low-temperature alloy bonding and selective wet etching processes, are compatible with existing semiconductor manufacturing infrastructure, facilitating the transition from laboratory to large-scale production and resulting in a relatively low industrialization threshold. Simultaneously, they ensure the quality and performance stability of epitaxial materials: the introduction of a "bonding" rather than "epitaxy growth" method onto the CuSiC alloy substrate, using a low-temperature (e.g., around 300℃) alloy bonding process to transfer the completed epitaxial layer structure onto the CuSiC alloy substrate, completely avoiding the extreme challenges such as lattice mismatch and high-temperature thermal stress encountered when directly epitaxially growing high-quality III-V compound semiconductors on CuSiC. This allows the epitaxial layer to grow on an optimized GaAs substrate, achieving the highest crystal quality and internal quantum efficiency, before being transferred to a high-performance CuSiC substrate in subsequent processes, thus ensuring optimal and stable performance of the light-emitting core from the source.
[0069] Furthermore, a compact and robust mechanical structure is formed: after removing the brittle and thick GaAs substrate, the main structure of the wafer consists of a robust CuSiC substrate and an AlGaInP epitaxial layer on top of it. This structure has high mechanical strength, strong resistance to bending and vibration, and reduces the risk of chip breakage due to mechanical stress during subsequent chip dicing, packaging, and end-use, thereby improving production yield and product durability.
[0070] Reference Figure 3 To address the aforementioned technical problems, this application also provides a laser device, including the aforementioned wafer, and further including an N-type confinement layer 8, a P-type AlGaInP upper cladding layer 7, and a P-type contact layer 6. The P-side electrode 1, substrate 2, metal reflective layer 3, P-type contact layer 6, P-type AlGaInP upper cladding layer 7, epitaxial layer 4, N-type confinement layer 8, and N-side electrode 5 are stacked sequentially from bottom to top.
[0071] Because wafers have the advantages of high luminous efficiency, high yield, and low manufacturing cost, laser devices containing wafers also have the same effect.
[0072] To address the aforementioned technical problems, this application also provides a fabrication process for a laser device, wherein the laser device is a laser chip, and includes the following fabrication steps:
[0073] S1' Preparation of the intermediate body of the wafer: The substrate 2, the metal reflective layer 3, and the epitaxial layer 4 together constitute the intermediate body of the wafer. The preparation of the intermediate body of the wafer specifically includes the following steps:
[0074] Using MOCVD or MBE equipment, multilayer structures are epitaxially grown on N-type original substrates (such as GaAs) to obtain AlGaInP / GaAs epitaxial wafers.
[0075] The multi-layered structure, from bottom to top, includes:
[0076] N-type substrate: GaAs raw substrate (growth substrate, which will be removed later);
[0077] N-type confinement layer 8: namely, the N-type AlGaInP lower cladding layer, which confines charge carriers and optical field;
[0078] Active layer: namely AlGaInP epitaxial layer 4 (multiple quantum wells), which serves as the core for luminescence;
[0079] 7. Cladding layer on P-type AlGaInP: confines charge carriers and optical field;
[0080] P-type contact layer 6: namely, the top layer of P-type GaP or high-aluminum AlGaInP, which serves as a window layer or contact layer to improve ohmic contact and reduce surface recombination.
[0081] A metallic reflective layer 3 is prepared on the surface of a CuSiC alloy substrate (substrate 2);
[0082] The P-side metal layer (P-type contact layer 6) of the AlGaInP / GaAs epitaxial wafer is bonded to the metal reflective layer 3 on the CuSiC alloy substrate using a low-temperature alloy bonding process.
[0083] Remove the GaAs substrate 2 of the epitaxial wafer to form an AlGaInP epitaxial layer 4;
[0084] The middle body of the wafer is obtained with a smooth surface and a complete structure.
[0085] S2', Ridge Waveguide Formation: On the epitaxial layer 4 (active layer) of the central substrate of the wafer, the lateral optical waveguide and current confinement structure of the laser device are defined by photolithography and etching processes to form the ridge waveguide. The central substrate of the wafer provides the "material" and "vertical structure" required for the laser device, while the ridge waveguide formation is based on this, and the "lateral structure" that controls light and current is created through microfabrication technology. Specifically, it includes the following steps:
[0086] (1) Pretreatment before epitaxial photolithography:
[0087] First, clean the wafer thoroughly with organic solvents (acetone, ethanol) and acid / alkali solutions to remove organic matter, particles, and metal ion contamination.
[0088] Re-dehydration baking: Removes moisture from the wafer surface and enhances the adhesion of photoresist;
[0089] (2) Ridge etching (first photolithography - defining the ridge waveguide):
[0090] Photoresist coating: Positive photoresist is spin-coated onto the surface of the central P-type contact layer 6 of the above wafer, with a thickness of about 1-2µm;
[0091] Pre-baking: allows the photoresist solvent to evaporate and cures the photoresist film;
[0092] Exposure: Using a "ridge waveguide pattern" mask, the image is aligned and exposed on a lithography machine. The pattern consists of a series of parallel bars of a specified width.
[0093] Development: Dissolve the photoresist in the exposed area with an alkaline developer to expose the semiconductor material under the strip;
[0094] Post-baking: Hardening the film (drying the adhesive) to improve the photoresist's resistance to etching;
[0095] Etching: Inductively coupled plasma (ICP) or reactive ion etching (RIE) is used with gases such as Cl2 / BCl3 to precisely etch away the P-type AlGaInP cladding layer 7 that is not protected by photoresist. The etching depth needs to be precisely controlled. For example, the etching stops at a distance of about 0.1-0.3µm from the active layer to form a "ridge".
[0096] Photoresist removal: Thoroughly remove residual photoresist using oxygen plasma ashing or a special stripping solution; at this point, a clear ridge waveguide array appears on the wafer surface;
[0097] (3) PECVD growth of passivation layer:
[0098] A layer of silicon dioxide (SiO2) or silicon nitride (Si3N4) is grown on the entire wafer surface (including the ridges and both sides) using plasma-enhanced chemical vapor deposition (PECVD); its function is:
[0099] Surface passivation: reduces surface states and lowers nonradiative recombination; Current limiting: acts as an insulating layer, forcing current to be injected only from subsequent window openings; Optical protection: prevents contamination and scratches;
[0100] (4) Photolithography 15µm window (second photolithography - defining the electrode injection window):
[0101] Coating / Exposure / Development: Use a "P-side electrode window" mask (the strip window is about 15µm wide, with a ridge slightly wider than 4µm to ensure complete coverage of the ridge top and alignment allowance) to create a window on the passivation layer.
[0102] Etching: Use buffered hydrofluoric acid wet etching or CF4-based dry etching to remove the passivation layer in the ridge region, expose the P-type contact layer, and form a current injection channel.
[0103] Remove adhesive and clean;
[0104] S3', P-side electrode fabrication: A P-side electrode 1 with a specified pattern is formed on the side of the substrate 2 away from the epitaxial layer 4, specifically including the following steps:
[0105] (5) Evaporated P-side electrode (titanium):
[0106] Metallization: The following layer structures are deposited sequentially using electron beam evaporation or magnetron sputtering:
[0107] Adhesion layer: including titanium (Ti) or chromium (Cr), approximately 20-50 nm; enhances the adhesion between metal and semiconductor;
[0108] Main conductive layer: including platinum (Pt) or gold (Au), about 100-200nm; forming good ohmic contact.
[0109] Bonding thickening layer: gold (Au), approximately 200-500nm, to facilitate subsequent wire bonding.
[0110] The overall function is to form a low-resistance, highly stable ohmic contact electrode on the P-side.
[0111] (6) Third photolithography (defining the P-side electrode pattern):
[0112] Coating / Exposure / Development: A photoresist mask is formed using a "P-side electrode pattern" mask (usually a strip wider than the window with large bonding pads at both ends);
[0113] Wet etching of metals: Using specific acid / alkali solutions (such as KI / I2 solution for etching gold, HF / HNO3 for etching titanium) to remove the metal layer not protected by photoresist and form independent electrode strips;
[0114] De-adhesive removal: to obtain patterned P-surface electrode 1;
[0115] S4', N-side processing and N-side electrode 5 fabrication: The side of the epitaxial layer 4 away from the P-side electrode 1 is processed into a smooth and flat back surface, and the N-side electrode 5 is formed on the back surface. Specifically, this includes the following steps:
[0116] (7) Thinning of N-side:
[0117] Mechanical polishing: The N-side of the wafer is polished to the target thickness (80-150µm) using a diamond grinding wheel to reduce series resistance and facilitate heat dissipation and subsequent cleaving;
[0118] Chemical mechanical polishing: polishes the abrasive surface, eliminates the damaged layer, and obtains a smooth and flat back surface;
[0119] (8) Evaporation of N-side alloy:
[0120] Metallization: Deposit N-side ohmic contact metal (such as AuGeNi / Au or Ti / Pt / Au) on the back side of the wafer.
[0121] Rapid thermal annealing: Annealing at approximately 400-450°C for 10 seconds in a nitrogen atmosphere. This alloys the metal with the N-type semiconductor, forming a low-resistance ohmic contact; resulting in an epitaxial wafer.
[0122] S5', Bar preparation and cavity surface treatment: The obtained epitaxial wafer is diced / cleaved to divide the wafer into multiple bars. An optical thin film is deposited on the cavity surface of the diced / cleaved bars. The specific steps include the following:
[0123] (9) Parseism of the Bartholomew's Law:
[0124] Dicing / cleaving: Using a precision dicing machine to scribe deep grooves along the direction perpendicular to the ridge waveguide, or using cleaving techniques to break the wafer into strips along the natural cleavage plane of the crystal;
[0125] Bar bar: Each bar contains dozens to hundreds of laser units (chips) arranged side by side, and its width is the cavity length of the final chip (250µm-2000µm).
[0126] (10) Vaporized cavity surface thin film:
[0127] Cleaning: Ultra-clean cleaning of the cut bar end face.
[0128] Coating: In a high-vacuum coating machine, electron beam evaporation is used to coat optical thin films on the two cleaving / cutting cavity surfaces of the bar.
[0129] Back end face (high reflectivity film HR): alternating SiO2 / TiO2 multilayer film, reflectivity >95%;
[0130] Front end (antireflective coating AR): reflectivity of approximately 1-10% for efficient laser output;
[0131] S6', Die Separation and Testing Packaging: The laser strips with the optical thin film deposited are cleaved / scribbled to obtain individual laser devices. The laser devices are then tested and packaged, specifically including the following steps:
[0132] (11) Core cleaving / scraping:
[0133] The coated bar strips are then diced or cleaved a second time along the direction parallel to the ridge waveguide (i.e. between each laser chip) to separate them into individual laser chips.
[0134] (12) Pile test:
[0135] On-chip testing / pin testing: Using a precision probe station, pulsed current is applied to the electrodes of each laser chip to quickly test its key parameters such as threshold current, slope efficiency, and output power, and preliminary sorting is performed based on performance;
[0136] (13) Cleaning, counting, packaging, and warehousing yield the finished laser chip:
[0137] Cleaning: Remove any remaining debris from the cutting process;
[0138] Microscopic examination: Examining external defects under a microscope;
[0139] Counting and sorting: Based on the test data, the laser chips are sorted into different boxes according to their performance level.
[0140] Vacuum packaging: Placed in anti-static, nitrogen-filled or vacuum packaging bags with clear labeling, stored in the warehouse awaiting packaging, finally yielding the finished laser chip.
[0141] Furthermore, in step S2, the specified width of the ridge waveguide is controlled to be 2.5-5.0 μm using a photolithography process. The ridge waveguide is equivalent to a "channel" for light. When this channel (width) is very narrow, it can only accommodate the stable transmission of one of the most basic light wave modes. Wider light wave modes are suppressed because they cannot form a stable light field distribution within the narrow waveguide.
[0142] The ridge waveguide width is controlled between 2.5-5.0 μm, ensuring a balance between single-mode operation and reduced loss. This results in high beam quality, with the output laser beam exhibiting a regular circular or elliptical Gaussian spot without distortion. The far-field divergence angle is small and symmetrical, the beam spreads slowly during propagation, and it has good directionality, facilitating efficient coupling with single-mode fibers, achieving coupling efficiencies exceeding 70%. It also boasts high spectral purity and a narrower spectral linewidth; the threshold current is significantly reduced, decreasing by several to tens of milliamperes compared to wide-ridge structures; and the slope efficiency is higher, resulting in greater optical power per unit current. This makes it more suitable for low-power applications, such as those consuming electronic resources (LiDAR, sensors) or devices requiring long-term operation.
[0143] If the ridge is too wide, it will allow multiple transverse modes to oscillate simultaneously, leading to degraded beam quality, beam distortion, and significant coupling loss with the fiber. If the ridge is too narrow, although it provides stronger mode confinement, it will result in excessive optical field confinement, causing some of the optical field to "overflow" into the flat plate regions on both sides, resulting in additional optical losses. It will also cause a sharp increase in series resistance, a small current channel cross-sectional area, leading to increased voltage and a decrease in electro-optical conversion efficiency.
[0144] The following specific embodiments will be used to illustrate the contents of this application in more detail and to further elaborate on this application, but these embodiments are by no means intended to limit this application.
[0145] Reference Figure 1 and Figure 2 This embodiment provides a wafer, which includes the following fabrication steps:
[0146] S1. A metal reflective layer 3 is prepared on the polished surface of a single-sided polished CuSiC alloy substrate. The metal reflective layer 3 is an AuBe / Au stacked structure, wherein the Au phase is disposed closer to the epitaxial layer 4 than the AuBe phase, and the AuBe phase is located between the CuSiC alloy substrate and the Au phase.
[0147] S2. Provide an AlGaInP / GaAs epitaxial wafer with a P-plane metal layer;
[0148] S3. The P-side metal layer of the epitaxial wafer is bonded to the metal reflective layer 3 on the CuSiC alloy substrate at 300°C using a low-temperature alloy bonding process, and an axial pressure of 5 MPa is applied.
[0149] S4. The GaAs substrate is removed by wet chemical etching to form an AlGaInP epitaxial layer 4. The etching solution used for the etching process is a mixed aqueous solution of NH4OH / H2O2, wherein the mass fraction of NH4OH is 28%, the mass fraction of H2O2 is 30%, and the volume ratio of NH4OH:H2O2:H2O is 1:1.5:30; the etching temperature is 25℃, and the etching time is 60 min.
[0150] After etching is complete, immediately immerse the surface in a large volume of flowing deionized water to completely stop the reaction and dilute and rinse away any remaining etching solution. Then, perform a standard cleaning procedure to remove any remaining organic matter and metal ions from the surface.
[0151] S5. A P-side electrode 1 is fabricated on the side of the CuSiC alloy substrate away from the epitaxial layer 4, and an N-side electrode 5 is fabricated on the surface of the AlGaInP epitaxial layer 4 after the GaAs substrate has been removed, to obtain a wafer.
[0152] Because the metallic reflective layer mirror structure does not require a thick GaP window layer and DBR layer, it significantly reduces epitaxial material consumption, lowering epitaxial costs by half compared to ordinary GaAs substrates. The increased brightness expands application range and increases product yield; the selling price of this wafer is on average 50% higher than traditional wafers, resulting in significant economic benefits.
[0153] The AlGaInP / Au / AuBe / CuSiC mirror substrate wafers were tested according to standards for wavelength, brightness, voltage, saturation current, and reverse voltage. The test results are shown in Table 1 below.
[0154]
[0155] Comparative Example 1 of Wafers
[0156] A GaAs substrate wafer, specifically an AlGaInP / GaAs substrate wafer, was selected as Comparative Example 1 in this application. The AlGaInP / GaAs substrate wafer was tested according to standards for wavelength, brightness, voltage, saturation current, and reverse voltage. The test results are shown in Table 2 below.
[0157]
[0158] As can be seen from the comparison between Table 1 and Table 2 above, the wafer of this application has excellent overall performance.
[0159] Meanwhile, the wafer of this application has the following advantages:
[0160] The use of CuSiC substrate material can improve the mechanical strength of the die, while the metal reflective layer with good thermal conductivity can provide light reflection at all angles; it improves thermal stability and can achieve high ambient temperature and high current operation; in addition, CuSiC substrate material is inexpensive, which can reduce costs; the bonding process between the substrate and AlGaInP material does not require high temperature, which can ensure the stability of the epitaxial material performance.
[0161] Reference Figure 3 This embodiment provides a laser device, which is a laser chip. The laser chip includes the following fabrication steps:
[0162] S1', Epitaxial wafer preparation: Using MOCVD equipment, a multilayer structure is epitaxially grown on N-type substrate 2 (GaAs) to obtain AlGaInP / GaAs epitaxial wafer;
[0163] The multi-layered structure, from bottom to top, includes:
[0164] N-type substrate: GaAs substrate (growth substrate, which will be removed later);
[0165] N-type confinement layer 8: namely, the N-type AlGaInP lower cladding layer, which confines charge carriers and optical field;
[0166] Active layer: namely AlGaInP epitaxial layer 4 (multiple quantum wells), which serves as the core for luminescence;
[0167] 7. Cladding layer on P-type AlGaInP: confines charge carriers and optical field;
[0168] P-type contact layer 6: namely, the top layer of P-type GaP component AlGaInP, which serves as a window layer or contact layer to improve ohmic contact and reduce surface recombination.
[0169] A metal reflective layer 3 is prepared on the polished surface of a single-sided polished CuSiC alloy substrate. The metal reflective layer 3 is an AuBe / Au stacked structure, wherein the Au phase is disposed closer to the epitaxial layer 4 than the AuBe phase, and the AuBe phase is located between the CuSiC alloy substrate and the Au phase.
[0170] The AlGaInP / GaAs epitaxial wafer is flipped over, and the P-side metal layer (P-type contact layer 6) of the AlGaInP / GaAs epitaxial wafer is alloy bonded to the metal reflective layer 3 on the CuSiC alloy substrate at a low temperature of 300°C, and an axial pressure of 5 MPa is applied.
[0171] A wet chemical etching process was used to remove the GaAs substrate and form an AlGaInP epitaxial layer. The etching solution used was a mixed aqueous solution of NH4OH / H2O2, wherein the mass fraction of NH4OH was 28%, the mass fraction of H2O2 was 30%, and the volume ratio of NH4OH:H2O2:H2O was 1:1.5:30; the etching temperature was 25°C, and the etching time was 60 min.
[0172] After etching is complete, the wafer is immediately immersed in a large volume of flowing deionized water to completely terminate the reaction and dilute and rinse away any residual etching solution. A standard cleaning process is then performed to remove any remaining organic matter and metal ions from the surface, resulting in a smooth, structurally intact epitaxial wafer.
[0173] S2', Ridge waveguide formation:
[0174] (1) Pretreatment before epitaxial photolithography:
[0175] First, clean the wafer thoroughly with organic solvents (acetone) and acid solutions to remove organic matter, particles, and metal ion contamination.
[0176] Re-dehydration baking: Removes moisture from the wafer surface and enhances the adhesion of photoresist;
[0177] (2) Etching a 4µm ridge (first photolithography - defining the ridge waveguide):
[0178] Coating: Spin-coat positive photoresist to a thickness of approximately 1-2 µm;
[0179] Pre-baking: allows the photoresist solvent to evaporate and cures the photoresist film;
[0180] Exposure: Using a "ridge waveguide pattern" mask, the image is aligned and exposed on a lithography machine. The pattern consists of a series of parallel stripes with a width of 4µm.
[0181] Development: Dissolve the photoresist in the exposed area with an alkaline developer to expose the semiconductor material under the strip;
[0182] Post-baking: Hardening the film (drying the adhesive) to improve the photoresist's resistance to etching;
[0183] Etching: Inductively coupled plasma (ICP) or reactive ion etching (RIE) is used with Cl2 gas to precisely etch away the P-type AlGaInP cladding layer that is not protected by photoresist. The etching depth needs to be precisely controlled. For example, etching stops at about 0.2µm from the active layer to form a "ridge".
[0184] Photoresist removal: Thoroughly remove residual photoresist using oxygen plasma ashing or a special stripping solution; at this point, a clear ridge waveguide array appears on the wafer surface;
[0185] (3) PECVD growth of passivation layer:
[0186] A layer of silicon dioxide (SiO2) or silicon nitride (Si3N4) is grown on the entire wafer surface (including the ridge and both sides) using plasma-enhanced chemical vapor deposition (PECVD).
[0187] (4) Photolithography 15µm window (second photolithography - defining the electrode injection window):
[0188] Coating / Exposure / Development: Use a "P-side electrode window" mask (the strip window is about 15µm wide, with a ridge slightly wider than 4µm to ensure complete coverage of the ridge top and alignment allowance) to create a window on the passivation layer.
[0189] Etching: Wet etching with buffered hydrofluoric acid is used to remove the passivation layer in the ridge area, exposing the P-type contact layer and forming a current injection channel;
[0190] Remove adhesive and clean;
[0191] Fabrication of S3' and P-side electrode 1:
[0192] (5) Evaporated P-side electrode 1 (titanium):
[0193] Metallization: Electron beam evaporation is used to sequentially deposit the following layer structures:
[0194] Adhesion layer: consisting of titanium (Ti) or chromium (Cr), approximately 30 nm;
[0195] Main conductive layer: including platinum (Pt) or gold (Au), approximately 150 nm;
[0196] Bonding thickened layer: gold (Au), approximately 350nm.
[0197] (6) Third photolithography (defining the P-side electrode pattern):
[0198] Photoresist coating / exposure / development: A photoresist mask is formed using a "P-side electrode pattern" mask;
[0199] Wet etching of metals: Using specific acid / alkali solutions (such as KI / I2 solution for etching gold, HF / HNO3 for etching titanium) to remove the metal layer not protected by photoresist and form independent electrode strips;
[0200] De-adhesive removal: to obtain patterned P-surface electrode 1;
[0201] S4', Substrate treatment and fabrication of N-face electrode 5:
[0202] (7) Thinning of N-side:
[0203] Mechanical polishing: The N-side of the wafer is polished to the target thickness of 100µm using a diamond grinding wheel;
[0204] Chemical mechanical polishing: polishes the abrasive surface, eliminates the damaged layer, and obtains a smooth and flat back surface;
[0205] (8) Evaporation of N-side alloy:
[0206] Metallization: N-side ohmic contact metal (AuGeNi / Au) is deposited on the back side of the wafer.
[0207] Rapid thermal annealing: Annealing at approximately 400°C for 10 seconds in a nitrogen atmosphere. This alloys the metal with the N-type semiconductor, forming a low-resistance ohmic contact; resulting in an epitaxial wafer.
[0208] S5', Bar strip preparation and cavity surface treatment:
[0209] (9) Parseism of the Bartholomew's Law:
[0210] Dicing / cleaving: The prepared epitaxial wafer is diced with a precision dicing machine along a direction perpendicular to the ridge waveguide, or cleaving technology is used to break the wafer into strips along the natural cleavage plane of the crystal.
[0211] Bar bar: Each bar bar contains 80 side-by-side laser units (chips), and the width is the cavity length of the final chip (1000µm).
[0212] (10) Vaporized cavity surface thin film:
[0213] Cleaning: Ultra-clean cleaning of the cut bar end face.
[0214] Coating: In a high-vacuum coating machine, electron beam evaporation is used to coat optical thin films on the two cleavage surfaces of the bar.
[0215] Back end face (high reflectivity film HR): alternating SiO2 / TiO2 multilayer film, reflectivity >95%;
[0216] Front end (antireflective coating AR): reflectivity of approximately 1-10% for efficient laser output;
[0217] S6', Die Separation and Test Packaging:
[0218] (11) Core cleaving / scraping:
[0219] The coated bar strips are then diced or cleaved a second time along the direction parallel to the ridge waveguide (i.e. between each laser chip) to separate them into individual laser chips.
[0220] (12) Pile test:
[0221] On-chip testing / pin testing: Using a precision probe station, pulsed current is applied to the electrodes of each laser chip to quickly test its key parameters such as threshold current, slope efficiency, and output power, and preliminary sorting is performed based on performance;
[0222] (13) Cleaning, counting, packaging, and warehousing yield the finished laser chip:
[0223] Cleaning: Remove any remaining debris from the cutting process;
[0224] Microscopic examination: Examining external defects under a microscope;
[0225] Counting and sorting: Based on the test data, the laser chips are sorted into different boxes according to their performance level.
[0226] Vacuum packaging: Place in an anti-static, nitrogen-filled or vacuum-sealed bag with clear labeling, store in a warehouse awaiting packaging, and finally obtain the finished 645nm laser chip with ridge waveguide structure.
[0227] The above laser chip was tested for threshold current, slope efficiency, and output power according to standards. The test results are shown in Table 3 below:
[0228]
[0229] Comparative Example 1 of Laser Devices
[0230] A laser chip with a GaAs substrate, specifically an AlGaInP / GaAs substrate laser chip, was selected as Comparative Example 1 of the laser device in this application. The threshold current, slope efficiency, and output power of the AlGaInP / GaAs substrate laser chip were tested according to standards, and the test results are shown in Table 4 below.
[0231]
[0232] As can be seen from the comparison of Tables 3 and 4 above, the laser chip of this application has excellent overall performance.
[0233] The design and manufacturing of 645nm ridge waveguide chips have very high requirements for the process. The integrity of the structure and the ability to guarantee the process are the key to making good laser chips.
[0234] In terms of the photolithography process, the 645nm laser chip with a ridge waveguide structure has very strict requirements for photolithography quality. It requires complete patterns, accurate dimensions, neat edges, and steep lines. The photolithography quality determines the shape of the ridge, affects whether the longitudinal and transverse structures of the device can meet the design requirements, and affects the electrical parameters of the device such as the threshold current. This is mainly determined by the level of photolithography.
[0235] The photolithography process involves many factors such as reagents, equipment, environment, processes, and personnel. From attaching the epitaxial wafer to coating, pre-baking, exposure, development, hardening, etching to remove the resist, and cleaning, each step should be strictly operated according to the regulations. Any mistake in any step can cause serious quality problems.
[0236] For 645nm laser chips with ridge waveguide structures, cavity surface cleavage and cavity surface coating techniques are particularly important, as a pair of perfectly formed resonant cavities are required for laser oscillation. The natural cleavage surfaces of semiconductor lasers provide resonant cavities for laser amplification. To improve output power, this application deposits high-reflectivity and anti-reflection coatings at both ends of the laser, significantly improving reflectivity.
[0237] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.
Claims
1. A wafer, characterized by, The laser device comprises a P-face electrode, a substrate, a metal reflective layer, an epitaxial layer and an N-face electrode arranged in a stack. The substrate is a CuSiC alloy substrate. The epitaxial layer is an AlGaInP epitaxial layer after removal of the original substrate and is bonded to the metal reflective layer. The metal reflective layer is a multi-layer metal structure, and a bottom layer of the metal reflective layer in contact with the CuSiC alloy substrate comprises a metal material for forming a P-type ohmic contact. The CuSiC alloy substrate is a single-side polished structure, and the metal reflective layer is formed on the polished surface.
2. The wafer of claim 1, wherein, The metal reflective layer is an AuBe / Au stack structure, and the Au is arranged closer to the epitaxial layer than the AuBe.
3. A process for producing a wafer, characterized by, A wafer for preparing the laser device of claim 1 or 2 comprises the following preparation steps: S1, preparing a metal reflective layer on the surface of a CuSiC alloy substrate; S2, providing an AlGaInP / GaAs epitaxial wafer with a P-face metal layer; S3, low-temperature alloy bonding the P-face metal layer of the epitaxial wafer to the metal reflective layer on the substrate of the CuSiC alloy substrate; S4, removing the original GaAs substrate of the epitaxial wafer to form an AlGaInP epitaxial layer; S5, forming a P-face electrode on the side of the CuSiC alloy substrate away from the epitaxial layer and forming an N-face electrode on the surface of the AlGaInP epitaxial layer after removal of the GaAs substrate.
4. The wafer manufacturing process of claim 3, wherein, The low-temperature alloy bonding is performed under protection of a N2 / H2 mixed atmosphere, the bonding temperature of the low-temperature alloy bonding is 250-350℃, and an axial pressure is applied, the axial pressure being 1-10MPa.
5. The wafer manufacturing process of claim 3, wherein, The GaAs substrate of the epitaxial wafer is removed by wet chemical etching, the etching solution used in the etching process is an NH4OH / H2O2 mixed aqueous solution, the volume ratio of NH4OH:H2O2:H2O is 1:(1-2):(20-50), the etching process is performed at a temperature of 20-30℃, and the etching process is performed for 60-75min.
6. A laser device, characterized by A wafer for preparing the laser device of claim 1 or 2.
7. A process for producing a laser device, characterized by, A laser device for preparing the laser chip of claim 6 comprises the following preparation steps: S1', preparation of the middle body of the wafer: the substrate, the metal reflective layer and the epitaxial layer together form the middle body of the wafer, and the middle body of the wafer is prepared; S2', formation of a ridge waveguide: the transverse optical waveguide and the current limiting structure of the laser device are defined on the epitaxial layer of the middle body of the wafer by a photolithography and etching process to form the ridge waveguide; S3', P-face electrode fabrication: a P-face electrode with a specified pattern is formed on the side of the substrate away from the epitaxial layer; S4', N-face processing and N-face electrode fabrication: the side of the epitaxial layer away from the P-face electrode is processed into a smooth back surface, and an N-face electrode is formed on the back surface to obtain an epitaxial wafer; S5', bar preparation and cavity surface processing: the epitaxial wafer obtained is sliced / diced to divide the epitaxial wafer into a plurality of bars, and an optical film is plated on the cavity surface of the sliced / diced bars. S6', Die Separation: The laser strips coated with optical thin films are cleaved / sliced to separate them and obtain individual laser devices.
8. The preparation process of a laser device according to claim 7, characterized in that, In step S2', the width of the ridge waveguide is controlled to be 2.5-5.0 μm by photolithography.