Inverter control method for preventing repeated fault ride-through abnormal operation

Abstract

The invention discloses an inverter control method for preventing repeated fault ride-through abnormal operation, and relates to the technical field of new energy power generation. The method is based on reactive power reference instruction duration, high / low voltage ride-through flag bit repeated transformation times in the duration, a subsynchronous current component, a super-synchronous voltage component, a negative sequence voltage component, a negative sequence current component, a three-phase voltage negative sequence unbalance degree and a flow direction of negative sequence power between an inverter and a power grid system. The method can effectively distinguish reasons causing the high-low penetration phenomenon of the inverter, provides a protection measure when the inverter inhibits power grid three-phase voltage negative sequence imbalance control instability, can avoid the risk of excitation of sub-super synchronous oscillation or causing tripping of the negative sequence protection action of the inverter, and is complete in defense function and high in reliability. The method can deal with abnormal operation conditions caused by repeated fault ride-through due to incoordination of upper and lower strategies during daily AVC reactive power regulation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of new energy power generation, in particular to an inverter control method for preventing repeated fault ride-through abnormal operation. BACKGROUND

[0002] The high-low penetration performance of the power electronic type power generation equipment of the new energy station should be aimed at when the power grid appears transient short-circuit fault, the relay protection quickly acts to remove the fault, and in this process, it can smoothly pass through without off-grid and can provide certain reactive power support. In the process of adjusting the system 220kV / 110kV bus voltage by increasing / decreasing the reactive power output of the new energy station through daily AVC, high-low penetration should not occur, and repeated high-low penetration should be avoided.

[0003] In the operation practice of the new energy station, the following typical situations often occur: Figure 2 As shown in the figure, when the AVC of the substation of the new energy station receives the voltage increase instruction from the AVC master station of the dispatching department, the AVC substation sends the reactive power regulation instruction to the station controllable platform (EMS) according to the actual value and the target value of the grid-connected voltage. The controllable platform further issues instructions according to the real-time reactive power storage of each wind turbine (or energy storage inverter) of the collection line, however, the controllable platform (EMS) usually does not collect and consider the terminal voltage of the wind turbine (or energy storage). In the case of weak grid, the wind turbine (or energy storage) only sends a small amount of capacitive reactive power, which can cause a large fluctuation of the terminal voltage, and it is very easy to reach the high-low penetration limit value, trigger the protection, and then the inverter reduces the reactive power output to restore the terminal voltage below the high-low penetration limit value. However, due to the continuous increase of the AVC / controllable instruction of the reactive power, the inverter will again enter the high-low penetration, thereby causing the inverter to repeatedly and periodically enter and exit the high-low penetration working condition.

[0004] Engineering practice shows that this kind of frequent entering and exiting high penetration process will produce obvious periodic voltage disturbance and negative sequence current component, which may cause the new energy station to occur sub-super synchronous oscillation or lead to the over-limit trip of the inverter negative sequence current protection, or lead to the action trip of the inverter negative sequence current protection, and even cause the cascading off-grid of multiple units in the station, which poses a threat to the stable operation of the power grid.

[0005] In view of the above problems, some manufacturers now take the following logic: Figure 3 As shown in the figure, on the basis of meeting the national standard for the high-low voltage penetration performance of the new energy inverter, a hysteresis zone is added between the high voltage penetration zone, the low voltage penetration zone and the normal operation zone. Assuming that the terminal voltage of the inverter is U, Figure 3When the terminal voltage U of the inverter is greater than 1.12 p.u., the inverter enters the high-voltage ride-through working condition; when the voltage is restored to below 1.1 p.u., the inverter enters the normal operation state. Similarly, when the terminal voltage U of the inverter is less than 0.85 p.u., the inverter enters the low-voltage ride-through working condition; when the voltage is restored to above 0.9 p.u., the inverter enters the normal operation state. Such an optimization scheme only prolongs the disturbance period, which can reduce the risk of inducing sub-synchronous oscillation to some extent, but does not avoid the repeated high-low ride-through phenomenon. SUMMARY

[0006] Therefore, it is necessary to provide an inverter control method for preventing abnormal operation of repeated fault ride-through in view of the above technical problems.

[0007] The specification adopts the following technical solutions: The specification provides an inverter control method for preventing abnormal operation of repeated fault ride-through, comprising: obtaining a reactive reference instruction duration of an upper machine AVC of the inverter and a repeated transformation number of high / low voltage ride-through flag bits within the duration of the reactive reference instruction of the upper machine AVC; performing Fourier decomposition on three-phase currents at the terminal of the inverter to obtain a sub-synchronous current component and a super-synchronous voltage component at the terminal of the inverter; performing positive and negative sequence decomposition on three-phase voltages and three-phase currents at the terminal of the inverter to obtain a negative sequence voltage component and a negative sequence current component at the terminal of the inverter; and determining the flow direction of the negative sequence power between the inverter and the power grid system through the negative sequence power direction comparison principle; based on the reactive reference instruction duration, the repeated transformation number of high / low voltage ride-through flag bits within the duration, the sub-synchronous current component, the super-synchronous voltage component, the negative sequence voltage component, the negative sequence current component, the three-phase voltage negative sequence unbalance degree, and the flow direction of the negative sequence power between the inverter and the power grid system, setting the inverter to shield the reactive instruction of the upper machine; based on the reactive reference instruction duration, the repeated transformation number of high / low voltage ride-through flag bits within the duration, the three-phase voltage negative sequence unbalance degree at the terminal of the inverter, and the inverter suppression compensation power grid negative sequence unbalance degree, controlling the lockout shutdown of the inverter.

[0008] Further, the setting of the inverter shielding the reactive instruction of the upper machine comprises: When the duration of the reactive power reference instruction issued by the upper computer AVC of the inverter is greater than ΔT1 seconds, the reactive power reference instruction of the upper computer AVC exists, the number of repeated transformations of the high / low voltage ride-through flag bit within the duration is not less than ΔT1 / 0.1 seconds, the machine terminal subsynchronous current component or supersynchronous voltage component is greater than 0.1 p.u, and the machine terminal negative sequence component flows from the inverter to the system, the inverter is set to shield the reactive power instruction of the upper computer for not less than 30 seconds. When the duration of the reactive power reference instruction issued by the upper computer AVC of the inverter is greater than ΔT1 seconds, the reactive power reference instruction of the upper computer AVC exists, the number of repeated transformations of the high / low voltage ride-through flag bit within the duration is not less than ΔT1 / 0.1 seconds, the machine terminal negative sequence component flows from the inverter to the system, and the negative sequence component is greater than 0.1 p.u or the three-phase voltage negative sequence unbalance degree is greater than 1%, the inverter is set to shield the reactive power instruction of the upper computer for not less than 30 seconds.

[0009] Further, the determination of the flow direction of the negative sequence power between the inverter and the power grid system through the negative sequence power direction comparison principle specifically includes: When the angle θ between the machine terminal voltage negative sequence component and the negative sequence current component satisfies -90°<θ<90°, the negative sequence power flows from the inverter to the power grid system.

[0010] Further, the machine terminal three-phase voltage negative sequence unbalance degree includes: The calculation formula of the machine terminal three-phase voltage negative sequence unbalance degree d is: ; Wherein, U1 and U2 are the machine terminal voltage negative sequence components.

[0011] Further, the control of the inverter lockout outage specifically includes: When the duration of the reactive power reference instruction issued by the upper computer AVC of the inverter is greater than ΔT1 seconds, the three-phase voltage negative sequence unbalance degree is greater than d max , the machine terminal negative sequence component flows from the inverter to the system, and the inverter suppression compensation power grid negative sequence unbalance degree function is set to 1, the inverter is locked out and stopped. Wherein, the d max is the maximum value of the power grid daily operation unbalance degree.

[0012] Further, the Fourier decomposition of the machine terminal three-phase current of the inverter includes: The machine terminal three-phase current of the inverter is independently sampled respectively; and a data analysis window with a length of 1 second is established; In the time domain processing, a Hanning window is applied to the window data to suppress frequency spectrum leakage; An overlapping sliding mechanism is adopted to process the window data to compensate for the weight attenuation of the window edge data caused by the window function, and to ensure the integrity of the continuous signal energy. Performing fast Fourier transform on the processed data, setting boundaries according to the fundamental frequency, and dividing the frequency spectrum into sub-synchronous frequency bands and super-synchronous frequency bands; Respectively solving the sub-synchronous current component and the super-synchronous current component of the three-phase current.

[0013] The above at least one technical solution adopted by the present specification can achieve the following beneficial effects: In the inverter control method for preventing abnormal operation caused by repeated fault ride-through provided by the present specification, according to the reactive power reference instruction duration issued by the upper computer AVC, the high-low ride-through phenomenon caused by the inverter is effectively distinguished due to "power grid fault" or "inappropriate daily AVC voltage regulation", and combined with the high / low voltage ride-through flag repeated number of times, whether the inverter has repeatedly high-low ride-through is determined. For the inverter that has repeatedly high-low ride-through, an anti-repeated high-low ride-through defense function is added to ensure the stable operation of the station. And protective measures are proposed when the inverter control is out of control due to the unbalanced control of three-phase voltage negative sequence of the power grid, which can avoid the risk of exciting sub-synchronous oscillation or causing the inverter negative sequence protection to trip. The strategy defense function is complete, and can cope with the abnormal operation condition caused by repeated fault ride-through due to the uncoordination of upper and lower strategies during daily AVC reactive power regulation. BRIEF DESCRIPTION OF DRAWINGS

[0014] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1 A logic diagram of the inverter control method for preventing abnormal operation caused by repeated fault ride-through provided by the present specification is shown in the figure; Figure 2 A schematic diagram of AVC regulation of the new energy station provided by the present specification is shown in the figure; Figure 3 A schematic diagram of the strategy optimization scheme based on the high-low ride-through hysteresis interval provided by the present specification is shown in the figure; Figure 4 A logic diagram of the inverter preventing sub-synchronous component out-of-limit caused by repeated high-low ride-through provided by the present specification is shown in the figure; Figure 5 A logic diagram of the inverter preventing sub-synchronous component out-of-limit caused by repeated high-low ride-through provided by the present specification is shown in the figure; Figure 6 A logic diagram of the inverter preventing sub-synchronous component out-of-limit caused by repeated high-low ride-through provided by the present specification is shown in the figure; DETAILED DESCRIPTION

[0016] For the purpose, technical solutions and advantages of the specification to be clearer, the technical solutions of the present application will be described clearly and completely below in conjunction with specific embodiments of the specification and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the specification, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0017] For the purpose, technical solutions and advantages of the specification to be clearer, the technical solutions of the present application will be described clearly and completely below in conjunction with specific embodiments of the specification and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the specification, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0018] The technical solutions provided by the embodiments of the present application will be described in detail below in conjunction with the drawings.

[0019] Figure 1 The flowchart of the control method of the inverter for defending against repeated fault ride-through abnormal operation in the specification is specifically as follows: Embodiments of the present application: assuming that the backup protection time limit overcurrent protection action time + circuit breaker action time of the new energy station collection line is ΔT1 seconds (about 0.85s), the inverter negative sequence current protection action time is ΔT2 seconds (about 6 seconds), and the field station AVC lower computer issued instruction cycle ΔT3 is 20-30 seconds.

[0020] S101: Set shielding upper computer reactive power instruction condition ①: the duration of the reactive power reference instruction issued by the upper computer AVC is greater than ΔT1 seconds. It is used to distinguish whether the high-low ride-through of the inverter is caused by power grid fault or whether the high-low ride-through of the inverter is caused by the increase of the reactive power output of the inverter by the daily AVC to adjust the system voltage.

[0021] In order to minimize the generation of sub-synchronous periodic disturbance signals (oscillation period is 0.1-0.01 seconds) by the inverter, the shielding upper computer reactive power instruction condition ② is set: the number of repeated changes of the high / low voltage ride-through flag bit is not less than ΔT1 / 0.1 seconds (about 9 times) in the presence and duration of the upper computer AVC reactive power reference instruction.

[0022] S102: If Figure 4As shown, the three-phase current at the machine end of the inverter is Fourier decomposed (FFT) to obtain the subsynchronous current component and the supersynchronous voltage component; if any of the components is greater than 0.1 p.u., and conditions ① and ② are met at the same time, it can be determined that the inverter has repeatedly entered and exited high penetration, and periodic disturbance is generated, and there is a risk of inducing oscillation.

[0023] At this time, the upper computer reactive power instruction can be shielded from the moment when the inverter recovers from the high / low voltage penetration state to normal operation, and the shielding time is set to be not less than 30 seconds.

[0024] S103: as shown, Figure 5 To determine whether the negative sequence component at the machine end flows from the system to the inverter or flows from the inverter to the system, the positive and negative sequence decomposition of the machine end voltage and the machine end current is performed to obtain the machine end voltage negative sequence component U2 and the negative sequence current component I2.

[0025] Suppose the angle between the machine end voltage negative sequence component U2 and the negative sequence current component I2 is θ, and a negative sequence voltage and negative sequence current phase difference criterion is added by using the negative sequence power direction comparison principle: when-90°< θ < 90° is met, it can be considered that the negative sequence power at the station flows from the inverter to the grid system.

[0026] Suppose the negative sequence unbalance degree of the three-phase voltage at the machine end is d, and the unit is %, and the calculation formula is: ; The "Power Quality Three-Phase Voltage Unbalance" GB / T 15543-2008 stipulates that: "When the power grid is in normal operation, the negative sequence voltage unbalance degree is not more than 2%, and the short-time is not more than 4%"; the "Rotating Machine Rating and Performance" GB / T 755-2019 stipulates that: "The three-phase AC motor should be able to run under the condition that the voltage negative sequence component of the three-phase voltage system is not more than 1% of the positive sequence component (long-term operation), or not more than 1.5% (short-term operation not more than a few minutes) and the zero sequence component is not more than 1% of the positive sequence component". Therefore, the present application takes the machine end three-phase voltage negative sequence unbalance degree d greater than 1% or the negative sequence current greater than 10% of the rated current as the criterion for shielding the upper computer reactive power instruction when the negative sequence component exceeds the limit.

[0027] When the inverter operation logic meets conditions ① and ②, the machine end negative sequence current component is large (I2 is greater than 0.1 p.u.) or the three-phase voltage unbalance degree is greater than 1%, and the negative sequence power flows from the inverter to the system, it can be determined that the inverter has repeatedly entered and exited high penetration, generates a large amount of negative sequence component, and there is a risk of inverter negative sequence protection action tripping.

[0028] At this time, the upper computer reactive power instruction can also be shielded from the moment when the inverter recovers from the high / low voltage penetration state to normal operation, and the shielding time is not less than 30 seconds.

[0029] S104: When the new energy inverter is running under the condition of "weak grid strength, and random and large fluctuation in a short time, similar to the nature of 'electrified railway train' asymmetric load", the system three-phase voltage is often low due to load fluctuation and the three-phase negative sequence unbalance degree is large. As shown in Figure 6 , it is assumed that the maximum imbalance degree of the regional power grid during daily operation is d max , the present invention prevents the increase of system three-phase negative sequence voltage imbalance caused by the disorder of inverter negative sequence suppression function, and sets the following discrimination conditions:

[0030] When the new energy inverter has the function of suppressing and compensating the negative sequence imbalance of the power grid and the function is put into operation (control word = 1). In theory, the negative sequence power at the machine end flows from the inverter to the power grid system (negative sequence voltage, phase difference θ of negative sequence current: -90° < θ < 90°), which produces a negative sequence voltage component with the same amplitude and a phase difference of 180° from the power grid, reducing the three-phase imbalance of the power grid. Under the condition of inaccurate sampling of the inverter, control program stuck, etc., the phase of the negative sequence component produced by the inverter has a serious deviation, and the three-phase voltage negative sequence imbalance does not decrease but increases. When it is greater than the maximum imbalance degree d max of the regional daily operation, it can be determined that the inverter negative sequence suppression function is disorderly, and the inverter is locked out and shut down.

[0031] It should be noted that the negative sequence component in this working condition is actively controlled by the inverter and does not belong to the abnormal working condition caused by repeated fault ride-through.

[0032] The above scheme can distinguish whether it is "inverter high-low wear caused by power grid fault" or "repeated high-low wear caused by improper adjustment of system voltage by increasing inverter reactive power output during daily AVC", and propose protection measures when the inverter suppression control of power grid three-phase voltage negative sequence imbalance is unstable, which can avoid the risk of exciting subsynchronous oscillation or causing inverter negative sequence protection trip.

[0033] The present invention proposes defense protection measures for the following three scenarios: (1) periodic disturbance component generated under repeated fault ride-through working condition, exciting sub-synchronous oscillation at the station; (2) negative sequence component generated under repeated fault ride-through working condition, leading to three-phase voltage imbalance of the power grid; (3) three-phase voltage imbalance caused by external factors, and control disorder of the inverter with negative sequence suppression function. The defense function of the proposed strategy is complete and can cope with the abnormal operating conditions caused by repeated fault ride-through due to the incoordination of upper and lower strategies during daily AVC reactive power adjustment.

[0034] The technical features of the above embodiments can be combined arbitrarily, and in order to make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present invention.

Claims

1. An inverter control method for preventing repeated fault ride-through abnormal operation, characterized in that, include: The duration of the reactive power reference command issued by the host computer AVC of the inverter and the number of times the high / low voltage crossover flag bit repeatedly changes during the duration of the reactive power reference command of the host computer AVC are present. Fourier decomposition of the three-phase current at the inverter terminal is performed to obtain the subsynchronous current component and the supersynchronous voltage component at the terminal. The three-phase voltage and three-phase current at the inverter terminal are decomposed into positive and negative sequence components to obtain the negative sequence voltage component and negative sequence current component at the terminal; and the flow direction of negative sequence power between the inverter and the grid system is determined by the negative sequence power direction comparison principle. Based on the duration of the reactive power reference command, the number of times the high / low voltage crossover flag changes during the duration, the subsynchronous current component, the supersynchronous voltage component, the negative sequence voltage component, the negative sequence current component, the three-phase voltage negative sequence imbalance, and the flow direction of negative sequence power between the inverter and the grid system, the inverter is set to shield the host computer's reactive power command. Based on the duration of the reactive power reference command, the number of times the high / low voltage ride-through flag changes during the duration, the negative sequence imbalance of the three-phase voltage at the inverter terminal, and the inverter's suppression and compensation of the grid's negative sequence imbalance, the inverter is controlled to be locked out.

2. The inverter control method for preventing repeated fault ride-through abnormal operation as described in claim 1, characterized in that, The inverter's setting to block reactive power commands from the host computer includes: When the duration of the reactive power reference command issued by the host computer AVC of the inverter is greater than ΔT1 seconds, the host computer AVC reactive power reference command exists and the number of times the high / low voltage crossover flag changes repeatedly within the duration is not less than ΔT1 / 0.1 seconds, and the subsynchronous current component or supersynchronous voltage component at the machine end is greater than 0.1pu, the inverter is set to block the host computer reactive power command for not less than 30 seconds. When the reactive power reference command issued by the inverter's host computer AVC lasts for more than ΔT1 seconds, the host computer AVC reactive power reference command exists and the high / low voltage crossover flag changes repeatedly for no less than ΔT1 / 0.1 seconds during the duration, the negative sequence current component is greater than 0.1pu or the three-phase voltage negative sequence imbalance is greater than 1% and the negative sequence component at the machine end flows from the inverter to the system, the inverter is set to block the host computer reactive power command for no less than 30 seconds. ΔT1 is the backup protection time-limited overcurrent protection operating time plus the circuit breaker operating time.

3. The inverter control method for preventing repeated fault ride-through abnormal operation as described in claim 1, characterized in that, The determination of the flow direction of negative-sequence power between the inverter and the power grid system based on the negative-sequence power direction comparison principle specifically includes: When the angle θ between the negative sequence component of the inverter terminal voltage and the negative sequence current component satisfies -90° < θ < 90°, the negative sequence power flows from the inverter to the grid system.

4. The inverter control method for preventing repeated fault ride-through abnormal operation as described in claim 1, characterized in that, The inverter terminal three-phase voltage negative sequence imbalance includes: The formula for calculating the negative sequence unbalance of the three-phase voltage at the generator terminal, d, is as follows: ； U1 and U2 are the negative sequence components of the terminal voltage, respectively.

5. The inverter control method for preventing repeated fault ride-through abnormal operation as described in claim 1, characterized in that, The control of the inverter's shutdown and lockout specifically includes: When the duration of the reactive power reference command issued by the inverter's host computer AVC is greater than ΔT1 seconds, and the three-phase voltage negative sequence imbalance is greater than d... max When the negative sequence component at the inverter terminal flows from the inverter to the system and the inverter's function of suppressing and compensating for grid negative sequence imbalance is set to 1, the inverter will be locked out. Wherein, the d max This represents the maximum value of the imbalance in the daily operation of the power grid.

6. The inverter control method for preventing repeated fault ride-through abnormal operation as described in claim 1, characterized in that, The Fourier decomposition of the three-phase current at the inverter terminals includes: The three-phase currents at the inverter terminals are sampled independently, and a data analysis window with a length of 1 second is established. In time-domain processing, a Hanning window is applied to the windowed data to suppress spectral leakage; An overlapping sliding mechanism is used to process window data to compensate for the weight decay of data at the window edges caused by the window function and to ensure the integrity of continuous signal energy. The processed data is subjected to a fast Fourier transform, and the spectrum is divided into subsynchronous and supersynchronous frequency bands based on the fundamental frequency. The subsynchronous current component and the supersynchronous current component of the three-phase current are calculated respectively.

Images