Power output double-hysteresis control circuit, electronic equipment and circuit control method

Abstract

The invention relates to the technical field of circuits, in particular to a power output double-hysteresis control circuit, electronic equipment and a circuit control method. The power output double-hysteresis control circuit comprises a reconfigurable series charge pump connected with a self-bias double-hysteresis comparator and a digital controller; the charge pump stage number output module is used for determining a target charge pump stage number and a load connection condition according to a stage number switching signal and a load switch control signal output by the digital controller, and outputting a target voltage to the self-biased double-hysteresis comparator according to the target charge pump stage number; the self-biased double-hysteresis comparator connected with the digital controller is used for comparing the target voltage with a preset circuit reference voltage to obtain a comparison result and inputting the comparison result to the digital controller; and the digital controller is used for generating a new charge pump series switching signal and a load switch control signal according to the comparison result, and outputting the new charge pump series switching signal to the reconfigurable series charge pump, so that the problems of over-high power consumption and relatively poor control stability and applicability of a power output control mode in the related technology are solved; the power supply output control efficiency is improved, and the power supply output control stability and applicability are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a power output double hysteresis control circuit, an electronic device and a circuit control method. BACKGROUND

[0002] With the development of Internet of Things technology, on the one hand, the application demand of Internet of Things in medical health, field detection, smart city and other scenes is increasing, and the edge nodes are deployed in large quantities. On the other hand, these edge nodes are often open, and the device is required to have the ability of continuous sensing and long time endurance. Finally, with the popularization of artificial intelligence technology, the computing power demand of the edge end is also increasing, and under the condition of resource limitation, more complex and massive processing tasks need to be faced. These development characteristics put forward the requirements of small size, low cost, long life and multi-task for Internet of Things edge device, among which the energy requirement of the device is particularly harsh. In recent years, more and more Internet of Things devices introduce environmental energy collection and low power supply management technology to realize self-powered devices and make up for the shortcomings of low power density and insufficient endurance of traditional batteries.

[0003] In the related art, in the self-powered scene, the power output control needs to solve two core demands: first, the energy collection voltage is unstable, and the edge load task is sensitive to the power supply stability, which needs to ensure the stable operation of the power supply under the complex conditions of input and load change; second, the peak conversion efficiency of the power management circuit exists but is difficult to maintain in practice, which needs to maintain this high efficient condition through the output control circuit to realize the high efficient operation of the system. The main implementation methods are as follows, (1) the power management circuit structure based on energy collection, which adopts the form of simple LDO for output control, (2) the energy collection power management circuit structure with interleaved hysteresis control, which discards the output control method of LDO and introduces two hysteresis comparators to generate control signals based on the change of the output circuit and alternately charge two super capacitors at the output end, (3) directly using the task driven power output control method.

[0004] However, in the related art, scheme (1) has poor anti-interference ability due to the simple amplifier structure and a gain of only 35 dB, needs to provide an additional fine current bias, introduces large power consumption, and does not consider the driving problem of a load task, when the load current exceeds the LDO bearing range, the power supply is directly disconnected, which may cause task failure or information loss, scheme (2) has a long circuit startup time, and also does not consider the driving problem of a load task, when the load current exceeds the maximum power range of energy collection, alternately charging the super capacitor cannot solve the problem, and when the power supply is directly disconnected, information loss may also occur, and scheme (3) only controls the output power without controlling the output voltage, can drive the task but cannot guarantee the execution effect of the task, and when supplying power to a subsequent processing circuit, cannot guarantee the conversion efficiency, which leads to high power consumption and poor stability of the power supply output control mode, and urgently needs to be solved. SUMMARY

[0005] The application provides a power supply output double hysteresis control circuit, an electronic device and a circuit control method, to solve the problems of high power consumption, poor control stability and applicability of the power supply output control mode in the related art, improve the efficiency of power supply output control, and improve the stability and applicability of power supply output control.

[0006] To achieve the above-mentioned purpose, the first aspect of the application provides a power supply output double hysteresis control circuit, comprising: a reconfigurable stage number charge pump, a self-bias double hysteresis comparator and a digital controller, wherein the reconfigurable stage number charge pump is connected with the self-bias double hysteresis comparator and the digital controller, respectively, is used for determining a target charge pump stage number and a load connection condition according to a charge pump stage number switching signal and a load switch control signal output by the digital controller, and outputting a target voltage to the self-bias double hysteresis comparator according to the target charge pump stage number; the self-bias double hysteresis comparator is connected with the digital controller, is used for comparing the target voltage and a preset circuit reference voltage to obtain a comparison result, and inputting the comparison result to the digital controller; and the digital controller is used for generating a new charge pump stage number switching signal and a load switch control signal according to the comparison result, and outputting the new charge pump stage number switching signal to the reconfigurable stage number charge pump.

[0007] Further, in some embodiments, further comprising: a load circuit connected with the reconfigurable stage number charge pump through a load control switch, and used for executing a load driving task according to the target voltage output by the reconfigurable stage number charge pump.

[0008] Further, in some embodiments, the self-biased dual-hysteresis comparator includes: a first comparator circuit and a second comparator circuit, both of which are composed of first to eleventh transistors. The gate of the first transistor is connected to a power supply access node, the source of the first transistor is connected to a ground node, and the drain of the first transistor is connected to the source of the second transistor and the source of the third transistor. The gate of the second transistor is connected to the voltage output terminal of the reconfigurable stage charge pump, and the drain of the second transistor is connected to the gates of the fourth transistor, the fifth transistor, the sixth transistor, and the ninth transistor, respectively. The gate of the third transistor is connected to a preset circuit reference voltage output terminal, and the drain of the third transistor is connected to the drain of the fourth transistor, the gate of the fifth transistor, the gate of the seventh transistor, and the gate of the tenth transistor, respectively. The gate of the fourth transistor is connected to the gate of the sixth transistor. The source of the fourth transistor is connected to the source of the fifth transistor, the source of the sixth transistor, and the source of the seventh transistor. The gate of the fifth transistor is connected to the gate of the seventh transistor, and the source of the fifth transistor is connected to the source of the seventh transistor. The drain of the sixth transistor is connected to the drain of the second transistor and the gate of the ninth transistor. The drain of the seventh transistor is connected to the drain of the third transistor and the gate of the tenth transistor. The gate of the eighth transistor is connected to the gate of the eleventh transistor, the source of the eighth transistor is connected to the ground node, and the drain of the eighth transistor is connected to the gate of the eighth transistor and the drain of the ninth transistor. The drain of the tenth transistor is connected to the channel output terminal of the corresponding comparator circuit. The source of the eleventh transistor is connected to the ground node, and the drain of the eleventh transistor is connected to the channel output terminal of the corresponding comparator circuit.

[0009] Furthermore, in some embodiments, the first comparator circuit outputs a first positive hysteresis voltage and a first negative hysteresis voltage, and the second comparator circuit outputs a second positive hysteresis voltage and a second negative hysteresis voltage, wherein the absolute value of the first positive hysteresis voltage is higher than the absolute value of the second positive hysteresis voltage, and the absolute value of the second negative hysteresis voltage is higher than the absolute value of the first negative hysteresis voltage.

[0010] Furthermore, in some embodiments, the first positive hysteresis voltage and the first negative hysteresis voltage are determined by a first width-to-length ratio between the fourth and sixth transistors corresponding to the first comparator circuit and a second width-to-length ratio between the fifth and seventh transistors corresponding to the first comparator circuit; the second positive hysteresis voltage and the second negative hysteresis voltage are determined by a third width-to-length ratio between the fourth and sixth transistors corresponding to the second comparator circuit and a fourth width-to-length ratio between the fifth and seventh transistors corresponding to the second comparator circuit.

[0011] Furthermore, in some embodiments, it further includes: an auxiliary circuit, which is connected to the reconfigurable stage charge pump, the self-biased dual hysteresis comparator, the digital controller and the load circuit respectively, for providing the reconfigurable stage charge pump, the self-biased dual hysteresis comparator, the digital controller and the load circuit with the original circuit voltage and the original control signal.

[0012] The power output dual-hysteresis control circuit provided by the present invention includes a reconfigurable stage charge pump connected to a self-biased dual-hysteresis comparator and a digital controller, respectively. The reconfigurable stage charge pump determines the target charge pump stage based on the stage switching signal output by the digital controller and outputs a target voltage to the self-biased dual-hysteresis comparator based on the target charge pump stage. The self-biased dual-hysteresis comparator, connected to the digital controller, compares the target voltage with a preset circuit reference voltage to obtain a comparison result and inputs the comparison result to the digital controller. The digital controller generates a new charge pump stage switching signal based on the comparison result and outputs the new charge pump stage switching signal to the reconfigurable stage charge pump. This solves the problems of excessive power consumption, poor control stability, and poor applicability in related technologies, improves the efficiency of power output control, and enhances the stability and applicability of power output control.

[0013] To achieve the above objectives, a second aspect of the present invention provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to be applied to a power output dual hysteresis control circuit as described in the above embodiments.

[0014] To achieve the above objectives, a third aspect of the present invention provides a control method for a power output dual-hysteresis control circuit, comprising the following steps: determining a target charge pump stage and load connection status based on a charge pump stage switching signal and a load switch control signal output by the digital controller, and outputting a target voltage to the self-biased dual-hysteresis comparator based on the target charge pump stage; comparing the target voltage with a preset circuit reference voltage based on the self-biased dual-hysteresis comparator to obtain a comparison result, and inputting the comparison result to the digital controller; generating a new charge pump stage switching signal and a load switch control signal by the digital controller based on the comparison result, and outputting the new charge pump stage switching signal to the reconfigurable stage charge pump.

[0015] Furthermore, in some embodiments, a load driving task is performed based on the target voltage output by the reconfigurable stage charge pump.

[0016] Furthermore, in some embodiments, the self-biased dual hysteresis comparator includes: a first comparator circuit and a second comparator circuit, both of which are composed of first to eleventh transistors.

[0017] According to the control method of the power output dual-hysteresis control circuit provided by the embodiments of the present invention, a reconfigurable stage charge pump connected to a self-biased dual-hysteresis comparator and a digital controller is used to determine the target charge pump stage and load connection status based on the stage switching signal and load switch control signal output by the digital controller, and outputs a target voltage to the self-biased dual-hysteresis comparator according to the target charge pump stage. The self-biased dual-hysteresis comparator connected to the digital controller is used to compare the target voltage with a preset circuit reference voltage to obtain a comparison result, and inputs the comparison result to the digital controller. The digital controller is used to generate a new charge pump stage switching signal and a load switch control signal based on the comparison result, and outputs the new charge pump stage switching signal to the reconfigurable stage charge pump. This solves the problems of excessive power consumption, poor control stability and applicability in the power output control method in related technologies, improves the efficiency of power output control, and enhances the stability and applicability of power output control.

[0018] Therefore, the present invention has the following beneficial effects: (1) The circuit structure of the dual hysteresis control circuit of the present invention is simple, without the need to introduce a high power amplifier and additional bias circuit. It has strong PVT robustness due to the relative relationship of hysteresis voltage based on transistor size ratio, and is suitable for power management schemes with limited energy.

[0019] (2) The present invention can adjust the number of stages of the reconfigurable charge pump according to different load scenarios, avoiding information confusion and loss.

[0020] (3) By controlling the output voltage and output current, the present invention limits the output power to a specific operating range, ensuring that the circuit always meets the load conditions of high conversion efficiency when the load changes, thereby improving the applicability of the circuit. Attached Figure Description

[0021] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A block diagram of a power output dual hysteresis control circuit provided according to an embodiment of the present invention; Figure 2 A schematic diagram of a power output dual hysteresis control circuit according to a specific embodiment of the present invention; Figure 3 A schematic diagram of the operating timing of a power output dual hysteresis control circuit according to a specific embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present invention; Figure 5 This is a flowchart illustrating the control method of the power output dual hysteresis control circuit provided in an embodiment of the present invention. Detailed Implementation

[0022] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0023] The following description, with reference to the accompanying drawings, describes the power output dual hysteresis control circuit, electronic device, and circuit control method provided according to embodiments of the present invention. First, the power output dual hysteresis control circuit provided according to embodiments of the present invention will be described with reference to the accompanying drawings.

[0024] Figure 1 This is a block diagram of a power output dual hysteresis control circuit provided according to an embodiment of the present invention.

[0025] like Figure 1 As shown, the power output dual hysteresis control circuit 10 includes: a reconfigurable stage charge pump 100, a self-biased dual hysteresis comparator 200, and a digital controller 300. The reconfigurable stage charge pump 100 is connected to a self-biased dual hysteresis comparator 200 and a digital controller 300, respectively. It is used to determine the target charge pump stage and load connection status based on the charge pump stage switching signal and load switch control signal output by the digital controller 300, and outputs a target voltage to the self-biased dual hysteresis comparator 200 based on the target charge pump stage. The self-biased dual hysteresis comparator 200 is connected to the digital controller 300 and is used to compare the target voltage with a preset circuit reference voltage to obtain a comparison result, and inputs the comparison result to the digital controller 300. The digital controller 300 is used to generate a new charge pump stage switching signal and a load switch control signal based on the comparison result, and outputs the new charge pump stage switching signal to the reconfigurable stage charge pump 100.

[0026] Among them, a reconfigurable stage charge pump refers to a voltage conversion circuit that dynamically switches the number of effective charge and discharge branches (i.e., stages) of the charge pump by controlling the switch state; a self-biased dual hysteresis comparator refers to a hysteresis threshold comparator that includes two independent channels, each configured with a different hysteresis threshold; and a digital controller refers to a driving device that processes signals based on digital logic.

[0027] Furthermore, in some embodiments, a load circuit 400 is also included, which is connected to the reconfigurable stage charge pump 100 via a load control switch, for performing a load driving task according to the target voltage output by the reconfigurable stage charge pump 100.

[0028] Specifically, in this embodiment of the invention, the load scenario of the power output dual hysteresis control circuit 10 can be determined based on the load current of the load circuit 400. For example, in this embodiment of the invention, a critical current is set, and the circuit load scenario is determined based on the relationship between the load current and the critical current.

[0029] As one possible approach, let's assume the load current at which the power supply output dual-hysteresis control circuit reaches the target output voltage is denoted as I. load_max The load current is I load If the load current I load Less than the critical current I load_max This indicates that the load circuit has low power consumption and low power requirements, which can easily lead to an increase in the output voltage of the reconfigurable stage charge pump, indicating a light load scenario; if the load current I load Greater than the critical current I load_max This indicates that the load circuit has high power consumption requirements and consumes a lot of power, which will easily lead to a decrease in the output voltage of the reconfigurable stage charge pump, indicating that this is a heavy load scenario. It should be noted that the load circuit in this embodiment of the invention refers to a functional circuit that can stably output voltage to complete a preset working task and can adjust its own operating state according to a control signal.

[0030] further, Figure 2 This is a schematic diagram of a power output dual hysteresis control circuit structure according to a specific embodiment of the present invention, wherein, in some embodiments, such as Figure 2 As shown, the self-biased dual hysteresis comparator 200 includes: a first comparator circuit 201 and a second comparator circuit 202. Both the first comparator circuit 201 and the second comparator circuit 202 are composed of transistors 1 to 11. The gate of the first transistor 203 is connected to a power supply access node, the source of the first transistor 203 is connected to a ground node, and the drain of the first transistor 203 is connected to the source of the second transistor 204 and the source of the third transistor 205. The gate of the second transistor 204 is connected to the voltage output terminal of the reconfigurable stage charge pump 100, and the drain of the second transistor 204 is connected to the gates of the fourth transistor 206, the fifth transistor 207, the sixth transistor 208, and the ninth transistor 211. The gate of the third transistor 205 is connected to a preset circuit reference voltage output terminal, and the drain of the third transistor 205 is connected to the drain of the fourth transistor 206, the gate of the fifth transistor 207, the gate of the seventh transistor 209, and the gate of the tenth transistor 212. The gate of the fourth transistor 206 is connected to the gate of the sixth transistor 208. The gate of transistor 208 is connected to the source of transistor 206. The source of transistor 206 is connected to the source of transistor 207, the source of transistor 208, and the source of transistor 209. The gate of transistor 207 is connected to the gate of transistor 209, and the source of transistor 207 is connected to the source of transistor 209. The drain of transistor 208 is connected to the drain of transistor 204 and the gate of transistor 211. The drain of transistor 209 is connected to the drain of transistor 205 and... The gate of the tenth transistor 212 is connected; the gate of the eighth transistor 210 is connected to the gate of the eleventh transistor 213; the source of the eighth transistor 210 is connected to the ground node; the drain of the eighth transistor 210 is connected to the gate of the eighth transistor 210 and the drain of the ninth transistor 211, respectively; the drain of the tenth transistor 212 is connected to the channel output terminal of the corresponding comparator circuit; the source of the eleventh transistor 213 is connected to the ground node; and the drain of the eleventh transistor 213 is connected to the channel output terminal of the corresponding comparator circuit.

[0031] Furthermore, in some embodiments, the first comparator circuit 201 outputs a first positive hysteresis voltage and a first negative hysteresis voltage, and the second comparator circuit 202 outputs a second positive hysteresis voltage and a second negative hysteresis voltage, wherein the absolute value of the first positive hysteresis voltage is higher than the absolute value of the second positive hysteresis voltage, and the absolute value of the second negative hysteresis voltage is higher than the absolute value of the first negative hysteresis voltage.

[0032] Furthermore, in some embodiments, the first positive hysteresis voltage and the first negative hysteresis voltage are determined by the first width-to-length ratio between the fourth transistor 206 and the sixth transistor 208 corresponding to the first comparator circuit 201 and the second width-to-length ratio between the fifth transistor 207 and the seventh transistor 209 corresponding to the first comparator circuit 201; the second positive hysteresis voltage and the second negative hysteresis voltage are determined by the third width-to-length ratio between the fourth transistor 206 and the sixth transistor 208 corresponding to the second comparator circuit 202 and the fourth width-to-length ratio between the fifth transistor 207 and the seventh transistor 209 corresponding to the second comparator circuit 202.

[0033] In one possible implementation, in this embodiment of the invention, the output of the first comparator circuit 201 is COM1, the output of the second comparator circuit 202 is COM2, and the power supply access node voltage is V. EH The voltage output of the reconfigurable stage charge pump 100 is divided by a voltage divider network to obtain the output voltage of the reconfigurable stage charge pump 100 as V. FB The voltage divider network can be a resistor voltage divider network, a capacitor voltage divider network, or any type of voltage divider network; no specific restrictions are imposed here. The preset circuit reference voltage is V. REF First, transistor M1 (i.e., the first transistor 203) generates a bias current to supply M2 (i.e., the second transistor 204) and M3 (the third transistor 205), and the output voltage V at the voltage output terminal... FB With the preset circuit reference voltage V REF The signals are input to the gates of M2 and M3 respectively, converted into current signals, and then transmitted to the cross-coupled structure of M4 (i.e., the fourth transistor 206) - M7 (i.e., the seventh transistor 209). The left and right comparison channels (i.e., COM1 and COM2) are configured with high positive hysteresis, low negative hysteresis, and low positive hysteresis, high negative hysteresis thresholds respectively through the width-to-length ratio differences of M4 (i.e., the fourth transistor 206) / M6 (i.e., the sixth transistor 208) and M5 (i.e., the fifth transistor 207) / M7 (i.e., the seventh transistor 209). The left channel with high positive hysteresis and low negative hysteresis has a ratio of 1:A and B:1, which is suitable for light load scenarios; the right channel with low positive hysteresis and high negative hysteresis has a ratio of 1:B and A:1, which is suitable for heavy load scenarios. The output signals of COM1 and COM2 are flipped and transmitted to the digital controller 300 to drive the reconfigurable stage charge pump 100 to switch stages or adjust the state of the load circuit 400.

[0034] Furthermore, the charge pump stage switching signal output by the digital controller 300 is S. cp The inverse signal of the charge pump stage switching signal is S. cpnThe charge pump stage switching signal and its inverse signal are used to control the reconfigurable stage charge pump switching capacitor. The load switch control signal is EN, which is used to control the on / off state of the load circuit or the switching of the operating mode. When the load current exceeds the critical range, the digital controller uses this signal to switch the load circuit to a low-power state to retain the task and avoid power failure.

[0035] As one possible way to achieve this, let S be... cp and S cpn These are mutually exclusive digital signals, typically 0 / 1 level signals. The reconfigurable stage charge pump 100 contains multiple parallel capacitor-switch branches. cp and S cpn The switches directly connected to these branches control the reconfigurable stage charge pump 100 based on the current operating scenario and the load switch control signal. For example, if the current operating scenario is a light load scenario, i.e., S... cp S is high level. cpn When the level is low, the load switch is always on. The choice between high and low conversion ratios depends on the output. For example, if the output voltage is too high, the circuit is switched to a low conversion ratio (i.e., reducing the number of charge pump stages) to avoid wasting energy due to excessive voltage. Conversely, if the output voltage is too low, the circuit is switched to a high conversion ratio to maintain the output voltage within the target range. If the current operating scenario is a heavy load scenario, i.e., S... cp S is low level. cpn When the signal is high, the system defaults to high conversion ratio operation. In this state, the load connection is controlled based on the output conditions. For example, if the output voltage is consistently lower than a preset voltage threshold, the load switch control signal EN controls the load to retain core tasks and suspend unnecessary tasks to reduce power consumption. When the load is at a critical point (i.e., the load current is close to the critical current), the load switch state remains unchanged, and the charge pump stage state also remains unchanged, ensuring that the load power consumption matches the peak conversion efficiency. Therefore, through S... cp and S cpn The complementary level and the load switch control signal EN ensure both the accuracy of stage switching and avoid branch conflicts.

[0036] It should be understood that the embodiments of the present invention realize the control of a charge pump stage switching signal consisting of one signal (where Scp and Scpn are always complementary and are essentially one signal) and a load switch control signal consisting of one signal through a self-biased dual hysteresis comparator.

[0037] It should be noted that the number of self-biased hysteresis comparators in the embodiments of the present invention can be two, three or more. When there are multiple self-biased hysteresis comparators, multiple charge pump stage switching signals and one load switch control signal can be controlled. Here, the number of self-biased hysteresis comparators is not specifically limited.

[0038] For example, embodiments of the present invention can also output three signals through three self-biased hysteresis comparators, thereby controlling a charge pump stage switching signal consisting of two signals and a load switch control signal consisting of one signal, to achieve efficient control of the circuit.

[0039] further, Figure 3 This is a timing diagram of a power output dual hysteresis control circuit according to a specific embodiment of the present invention, as shown below. Figure 3 As shown, the load current when the power supply output dual hysteresis control circuit reaches the target output voltage is denoted as I. load_max The load current is denoted as I. load , when I load load_max When the output voltage reaches the target output voltage, charging continues until it exceeds the hysteresis comparator threshold. At this point, the control signal Scp flips, controlling the output voltage within the range of [target voltage + high positive hysteresis voltage, target voltage - low negative hysteresis voltage] by controlling the number of stages of the reconfigurable charge pump; when I load >I load_max When the output voltage cannot be maintained at the target voltage and falls below a certain threshold, the control signal EN flips, controlling the output voltage within the range of [target voltage + low positive hysteresis voltage, target voltage - high negative hysteresis voltage] by controlling the operating state of the load circuit; when I load = I load_max When the power supply output power is exactly equal to the power required by the load, the comparator does not perform any additional switching.

[0040] Furthermore, in some embodiments, an auxiliary circuit 500 is also included, which is connected to the reconfigurable stage charge pump 100, the self-biased dual hysteresis comparator 200, the digital controller 300, and the load circuit 400, respectively, for providing the reconfigurable stage charge pump 100, the self-biased dual hysteresis comparator 200, the digital controller 300, and the load circuit 400 with the original circuit voltage and the original control signal.

[0041] ​The power output dual-hysteresis control circuit provided by the present invention includes a reconfigurable stage charge pump connected to a self-biased dual-hysteresis comparator and a digital controller, respectively. The reconfigurable stage charge pump determines the target charge pump stage and load connection based on the stage switching signal and load control switch signal output by the digital controller, and outputs a target voltage to the self-biased dual-hysteresis comparator based on the target charge pump stage. The self-biased dual-hysteresis comparator connected to the digital controller compares the target voltage with a preset circuit reference voltage to obtain a comparison result, and inputs the comparison result to the digital controller. The digital controller generates a new charge pump stage switching signal and a load switch control signal based on the comparison result, and outputs the new charge pump stage switching signal to the reconfigurable stage charge pump. This solves the problems of excessive power consumption, poor control stability, and poor applicability in related technologies, improves the efficiency of power output control, and enhances the stability and applicability of power output control.

[0042] Figure 4 This is a schematic diagram of an electronic device provided according to an embodiment of the present invention. The electronic device may include: The memory 401, the processor 402, and the computer program stored on the memory 401 and capable of running on the processor 402.

[0043] When the processor 402 executes the program, it implements the control method of the power output dual hysteresis control circuit provided in the above embodiments.

[0044] Furthermore, electronic devices also include: Communication interface 403 is used for communication between memory 401 and processor 402.

[0045] The memory 401 is used to store computer programs that can run on the processor 402.

[0046] The memory 401 may include high-speed RAM (Random Access Memory) memory, and may also include non-volatile memory, such as at least one disk storage.

[0047] If the memory 401, processor 402, and communication interface 403 are implemented independently, then the communication interface 403, memory 401, and processor 402 can be interconnected via a bus to complete communication between them. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0048] Optionally, in a specific implementation, if the memory 401, processor 402, and communication interface 403 are integrated on a single chip, then the memory 401, processor 402, and communication interface 403 can communicate with each other through an internal interface.

[0049] Processor 402 may be a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present invention.

[0050] Next, the control method of the power output dual hysteresis control circuit provided according to an embodiment of the present invention is described with reference to the accompanying drawings.

[0051] Figure 5 This is a flowchart illustrating the control method of the power output dual hysteresis control circuit provided in an embodiment of the present invention.

[0052] like Figure 5 As shown, the control method of this power output dual hysteresis control circuit includes the following steps: In step S501, the target charge pump stage number is determined according to the charge pump stage number switching signal output by the digital controller, and the target voltage is output to the self-biased dual hysteresis comparator according to the target charge pump stage number.

[0053] In step S502, the target voltage and the preset circuit reference voltage are compared based on the self-biased dual hysteresis comparator to obtain the comparison result, and the comparison result is input to the digital controller.

[0054] In step S503, the digital controller generates a new charge pump stage switching signal and a load switch control signal based on the comparison result, and outputs the new charge pump stage switching signal to the reconfigurable stage charge pump.

[0055] Furthermore, in some embodiments, the load driving task is performed based on the target voltage output by the reconfigurable stage charge pump.

[0056] Furthermore, in some embodiments, the self-biased dual hysteresis comparator includes: a first comparator circuit and a second comparator circuit, both of which are composed of first to eleventh transistors.

[0057] It should be noted that the foregoing explanation of the power output dual hysteresis control circuit embodiment also applies to the power output dual hysteresis control circuit of this embodiment, and will not be repeated here.

[0058] According to the control method of the power output dual-hysteresis control circuit provided by the present invention, a reconfigurable stage charge pump connected to a self-biased dual-hysteresis comparator and a digital controller is used to determine the target charge pump stage and load connection status based on the stage switching signal and load control switch signal output by the digital controller, and outputs a target voltage to the self-biased dual-hysteresis comparator according to the target charge pump stage. The self-biased dual-hysteresis comparator connected to the digital controller is used to compare the target voltage and a preset circuit reference voltage to obtain a comparison result, and inputs the comparison result to the digital controller. The digital controller is used to generate a new charge pump stage switching signal and a load switch control signal based on the comparison result, and outputs the new charge pump stage switching signal to the reconfigurable stage charge pump. This solves the problems of excessive power consumption, poor control stability and applicability in the power output control method in related technologies, improves the efficiency of power output control, and enhances the stability and applicability of power output control.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0061] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A power output dual hysteresis control circuit, characterized in that, include: A reconfigurable series charge pump, a self-biased dual hysteresis comparator, and a digital controller, wherein, The reconfigurable stage charge pump is connected to the self-biased dual hysteresis comparator and the digital controller, respectively, and is used to determine the target charge pump stage and load connection status according to the charge pump stage switching signal and load switch control signal output by the digital controller, and output the target voltage to the self-biased dual hysteresis comparator according to the target charge pump stage. The self-biased dual hysteresis comparator is connected to the digital controller and is used to compare the target voltage with a preset circuit reference voltage to obtain a comparison result, and input the comparison result to the digital controller. The digital controller is used to generate a new charge pump stage switching signal and a load switch control signal based on the comparison result, and outputs the new charge pump stage switching signal to the reconfigurable stage charge pump.

2. The circuit according to claim 1, characterized in that, Also includes: A load circuit, which is connected to the reconfigurable stage charge pump via a load control switch, is used to perform a load driving task based on the target voltage output by the reconfigurable stage charge pump.

3. The circuit according to claim 1, characterized in that, The self-biased dual-hysteresis comparator includes: a first comparator circuit and a second comparator circuit, both of which are composed of transistors one through eleventh. The gate of the first transistor is connected to the power supply node, the source of the first transistor is connected to the ground node, and the drain of the first transistor is connected to the source of the second transistor and the source of the third transistor. The gate of the second transistor is connected to the voltage output terminal of the reconfigurable stage charge pump, and the drain of the second transistor is connected to the gate of the fourth transistor, the drain of the fifth transistor, the gate of the sixth transistor, and the gate of the ninth transistor, respectively. The gate of the third transistor is connected to a preset circuit reference voltage output terminal, and the drain of the third transistor is connected to the drain of the fourth transistor, the gate of the fifth transistor, the gate of the seventh transistor, and the gate of the tenth transistor, respectively. The gate of the fourth transistor is connected to the gate of the sixth transistor, and the source of the fourth transistor is connected to the source of the fifth transistor, the source of the sixth transistor, and the source of the seventh transistor, respectively. The gate of the fifth transistor is connected to the gate of the seventh transistor, and the source of the fifth transistor is connected to the source of the seventh transistor. The drain of the sixth transistor is connected to the drain of the second transistor and the gate of the ninth transistor. The drain of the seventh transistor is connected to the drain of the third transistor and the gate of the tenth transistor; The gate of the eighth transistor is connected to the gate of the eleventh transistor, the source of the eighth transistor is connected to the ground node, and the drain of the eighth transistor is connected to the gate of the eighth transistor and the drain of the ninth transistor. The drain of the tenth transistor is connected to the channel output terminal of the corresponding comparator circuit. The source of the eleventh transistor is connected to the ground node, and the drain of the eleventh transistor is connected to the channel output terminal of the corresponding comparator circuit.

4. The circuit according to claim 3, characterized in that, The first comparator circuit outputs a first positive hysteresis voltage and a first negative hysteresis voltage, and the second comparator circuit outputs a second positive hysteresis voltage and a second negative hysteresis voltage. Wherein, the absolute value of the first positive hysteresis voltage is higher than the absolute value of the second positive hysteresis voltage, and the absolute value of the second negative hysteresis voltage is higher than the absolute value of the first negative hysteresis voltage.

5. The circuit according to claim 4, characterized in that, The first positive hysteresis voltage and the first negative hysteresis voltage are determined by the first width-to-length ratio between the fourth and sixth transistors corresponding to the first comparator circuit and the second width-to-length ratio between the fifth and seventh transistors corresponding to the first comparator circuit. The second positive hysteresis voltage and the second negative hysteresis voltage are determined by the third width-to-length ratio between the fourth and sixth transistors corresponding to the second comparator circuit and the fourth width-to-length ratio between the fifth and seventh transistors corresponding to the second comparator circuit.

6. The circuit according to claim 1, characterized in that, Also includes: Auxiliary circuit, The auxiliary circuit is connected to the reconfigurable stage charge pump, the self-biased dual hysteresis comparator, the digital controller, and the load circuit, respectively, and is used to provide the reconfigurable stage charge pump, the self-biased dual hysteresis comparator, the digital controller, and the load circuit with the original circuit voltage and the original control signal.

7. An electronic device, characterized in that, include: The power output dual hysteresis control circuit as described in any one of claims 1-6.

8. A control method for a power output dual hysteresis control circuit, characterized in that, The power output dual-hysteresis control circuit includes a reconfigurable stage charge pump, a self-biased dual-hysteresis comparator, and a digital controller, comprising the following steps: The target charge pump stage and load connection status are determined based on the charge pump stage switching signal and load switch control signal output by the digital controller, and the target voltage is output to the self-biased dual hysteresis comparator based on the target charge pump stage. The target voltage is compared with a preset circuit reference voltage using a self-biased dual hysteresis comparator to obtain a comparison result, and the comparison result is input to the digital controller. The digital controller generates a new charge pump stage switching signal and a load switch control signal based on the comparison result, and outputs the new charge pump stage switching signal to the reconfigurable stage charge pump.

9. The method according to claim 8, characterized in that, The load driving task is performed based on the target voltage output by the reconfigurable stage charge pump.

10. The method according to claim 8, characterized in that, The self-biased dual hysteresis comparator includes: a first comparator circuit and a second comparator circuit, both of which are composed of first to eleventh transistors.

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