Multi-phase switching power supply and current sharing circuit thereof

Abstract

The invention discloses a multiphase switching power supply and a current sharing circuit thereof. The current sharing circuit comprises a processing unit used for providing a difference current between a master phase sampling current and a slave phase sampling current; the adjusting unit is connected with the processing unit and is used for providing average current according to the difference current and the reference current; the output unit is connected with the adjusting unit through the first current path and is used for outputting average current under the conduction state of the first current path; the clamping unit is connected with a first node, the first node is a common node of the adjusting unit and the first current path, the clamping unit clamps the first node according to the first voltage in an off state of the first current path, the multi-phase switching power supply comprises a master phase and a slave phase, and when an enable signal of the slave phase is an active level, the first node is a common node of the adjusting unit and the first current path. The first current path is conducted. And when the slave phase is not started, the voltage clamping of the first node is realized through the clamping module, so that the anti-interference performance of the multi-phase switching power supply is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a multi-phase switching power supply and a current sharing circuit thereof. BACKGROUND

[0002] In the current situation of increasingly urgent demand for high power and large current applications, multi-phase switching power supplies, through multi-channel parallel operation and power sharing, have lower current ripple, better heat dissipation, higher efficiency and power density compared with single-phase switching converters, and are widely used in server power supplies, communication power supplies, new energy inverter front stages, high-power LED drivers, electric vehicle on-board chargers and other scenarios.

[0003] In a multi-phase switching power supply, it is crucial to maintain current balance between phases to ensure the stability and reliability of the entire system. In the prior art, a master-slave current sharing scheme is usually used to achieve current balance between phases. Specifically, the master phase controls its own current through feedback adjustment to stabilize the output voltage, and the slave phase detects the difference between the master phase current and its own current through a current sharing circuit to realize current tracking.

[0004] During the operation of a multi-phase switching power supply, the number of operating phases is adaptively adjusted according to the changes in load. When the number of operating phases increases, the master phase current has been established, but the slave phase current is zero, and the transient deviation between the two is large, which can cause excessive adjustment of the slave phase current and even system oscillation or failure. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a multi-phase switching power supply and a current sharing circuit thereof, which can improve the anti-interference and stability of the current sharing circuit.

[0006] According to an aspect of the present application, a current sharing circuit applied to a multi-phase switching power supply is provided, which includes: a processing unit configured to provide a difference current between a master phase sampling current and a slave phase sampling current; an adjusting unit connected to the processing unit and configured to provide an average current according to the difference current and a reference current; an output unit connected to the adjusting unit through a first current path and configured to output the average current in a conduction state of the first current path; and a clamping unit connected to a first node, the first node being a common node of the adjusting unit and the first current path, and the clamping unit being configured to clamp the first node according to a first voltage in a disconnection state of the first current path, wherein the multi-phase switching power supply includes a master phase and a slave phase, and the first current path is turned on when an enable signal of the slave phase is at an active level.

[0007] Optionally, the current sharing circuit further comprises a voltage generating unit connected to the output unit via a second current path, wherein the voltage generating unit and the second current path are connected to a second node, the second node is connected to the clamping unit, the second current path is turned on when the first current path is disconnected, and the second node provides the first voltage.

[0008] Optionally, the processing unit comprises a first filtering module configured to filter the main phase sampling current to obtain a first filtered current, a second filtering module configured to filter the slave phase sampling current to obtain a second filtered current, and a difference calculating module configured to provide the difference current according to the first filtered current and the second filtered current.

[0009] Optionally, the first filtering module comprises a first filter, a first transistor having a first end and a control end connected to the main phase sampling current and a second end connected to ground, and a second transistor having a second end connected to ground and a control end connected to the control end of the first transistor via the first filter, the second filtering module comprises a second filter, a third transistor having a first end and a control end connected to the slave phase sampling current and a second end connected to ground, and a fourth transistor having a second end connected to ground and a control end connected to the control end of the third transistor via the second filter, and the difference calculating module comprises a thirteenth transistor having a second end and a control end connected to the first end of the second transistor, and a fourteenth transistor having a first end connected to the first end of the thirteenth transistor, a control end connected to the control end of the thirteenth transistor, and a second end connected to the first end of the fourth transistor and configured to provide the difference current.

[0010] Optionally, the first filter and / or the second filter is an RC filter.

[0011] Optionally, the adjusting unit comprises a fifth transistor having a first end and a control end connected to the difference current and the reference current and a second end connected to ground, and a sixth transistor having a control end connected to the control end of the fifth transistor, a second end connected to ground, and a first end configured to provide the average current.

[0012] Optionally, the clamping unit comprises an operational amplifier having a non-inverting input end connected to the first voltage and an inverting input end connected to the first node, and a clamping transistor having a first end connected to a power voltage, a second end connected to the first node, and a control end connected to an output end of the operational amplifier.

[0013] Optionally, the voltage generating unit comprises a ninth transistor having a first end and a control end connected to a mirror current of the slave phase sampling current and a second end connected to ground, and a tenth transistor having a control end connected to the control end of the ninth transistor, a second end connected to ground, and a first end connected to the second node.

[0014] Optionally, the first current path comprises a seventh transistor and an eighth transistor connected in series, the first end of the seventh transistor is connected to the output unit, the control end is connected to the enable signal, the second end of the eighth transistor is connected to the first node, the control end is connected to the inverse signal of the enable signal, the second current path comprises an eleventh transistor and a twelfth transistor connected in series, the first end of the eleventh transistor is connected to the output unit, the control end is connected to the inverse signal of the enable signal, the second end of the twelfth transistor is connected to the second node, the control end is connected to the enable signal, wherein the first end and the second end of the eighth transistor are shorted, and the first end and the second end of the twelfth transistor are shorted.

[0015] Optionally, the output unit comprises a fifteenth transistor, the control end and the second end of which are shorted and connected to the first current path and the second current path, and a sixteenth transistor, the first end of which is connected to the first end of the fifteenth transistor, the control end of which is connected to the control end of the fifteenth transistor, and the second end of which outputs the average current when the first current path is turned on.

[0016] Optionally, the first voltage is greater than zero.

[0017] According to still another aspect of the present application, there is provided a multi-phase switching power supply, comprising: a main phase; and a slave phase comprising the current sharing circuit according to any one of the above, the slave phase providing its own output current according to the average current.

[0018] Optionally, the multi-phase switching power supply further comprises: a sampling circuit for providing a feedback voltage representing an output voltage of the multi-phase switching power supply; an error amplifier for providing an error amplified signal of the feedback voltage and a reference voltage; and a conversion circuit for converting the error amplified signal of the voltage type to provide the reference current, wherein the main phase provides its own output current according to the reference current.

[0019] Optionally, the slave phase further comprises: an enable circuit for providing the enable signal of the slave phase according to an output current of the multi-phase switching power supply and a soft start signal, wherein the enable signal provides an effective level after the output current of the multi-phase switching power supply falls into a set range and a soft start stage ends.

[0020] According to the multiphase switching power supply and its current sharing circuit provided in this application, when the slave phase is not started, the voltage of the first node is clamped by the clamping unit, thereby reducing the voltage change amplitude of the first node at the moment of slave phase start-up. Since the transient magnitude of the current sharing current is related to the voltage change amplitude, the overshoot of the current sharing current at the moment of slave phase start-up can be avoided, thereby avoiding excessive adjustment at the moment of slave phase start-up, which is beneficial to improving the immunity, start-up stability and dynamic response performance of the slave phase. Attached Figure Description

[0021] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic structural diagram of a multiphase switching power supply is shown.

[0023] Figure 2 A schematic structural diagram of the control circuitry in some embodiments of this application is shown;

[0024] Figure 3 Show Figure 2 A schematic diagram of the current sharing circuit.

[0025] Figure 4 Show Figure 3 A schematic circuit diagram of the processing unit;

[0026] Figure 5 Show Figure 3 A schematic circuit diagram of the parts other than the processing unit;

[0027] Figure 6 A schematic structural diagram of the control circuitry in some other embodiments of this application is shown;

[0028] Figure 7 Show Figure 6 A schematic diagram of the current sharing circuit;

[0029] Figure 8 A schematic structural diagram of the control circuitry is shown in some of the embodiments of this application. Detailed Implementation

[0030] Various embodiments of the present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0031] Meanwhile, certain terms used in the description and example will be understood to refer to certain components by their name regardless of multiple instances or iterations of such components, unless otherwise indicated. Further, terms including technical and scientific terms used in the description have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined.

[0032] It should be understood that, in the following description, "circuitry" can include a single or multiple components, or combinations thereof, that are collectively capable of performing the functions described herein. When the term "circuit" or "circuitry" is used, it is understood that the circuitry can include a single component or multiple components, or combinations thereof, that are collectively capable of performing the functions described herein. When an element or circuit is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or it can have intervening components coupled or connected thereto, and the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that the two are connected without any intervening elements.

[0033] In addition, it should also be noted that, in the present context, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an indefinite article "a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the defined element.

[0034] Figure 1 A schematic diagram of a multi-phase switching power supply is shown. As Figure 1As shown, the multiphase switching power supply includes a plurality of power phases connected in parallel between the control circuit 100 and the output capacitor 10. Each power phase includes a driving unit 210 and a power unit 220. The driving unit 210 is configured to drive a power tube in the power unit 220 according to a pulse width modulation signal PWM provided by the control circuit 100, so as to adjust the total output current Iout of the multiphase switching power supply by adjusting the output current of each power phase, and thus to achieve dynamic adjustment and stabilization of the output voltage Vout. The structure and working principle of the driving unit 210 and the power unit 220 should be well known to those skilled in the art. For example, the power unit 220 can be a boost architecture, a buck architecture, a buck-boost architecture, etc. In addition, for any type of power unit architecture, in some embodiments, it can be a double-tube structure with a main power tube and a freewheeling power tube to achieve synchronous rectification, or a single-tube structure with a main power tube and a freewheeling diode to achieve non-synchronous rectification.

[0035] In Figure 1 , a two-phase switching power supply is taken as an example. The power phase 200a is the master phase, and the power phase 200b is the slave phase. The control circuit 100 provides a first pulse width modulation signal PWM1 to the master phase 200a and a second pulse width modulation signal PWM2 to the slave phase 200b.

[0036] In order to ensure the stability and reliability of the multiphase switching power supply, the current balance of each power phase can be achieved by a master-slave scheme. Specifically, the control circuit 100 further includes a sub-control circuit corresponding to each power phase (not shown in the figure). The sub-control circuit corresponding to the master phase 200a controls its own current through feedback adjustment, and the sub-control circuit corresponding to the slave phase 200b includes a current sharing circuit, which achieves the tracking of the slave phase current to the master phase current by detecting the difference between the master phase sampling current Isen1 and the slave phase sampling current Isen2. Figure 1

[0037] Figure 2 A schematic structural diagram of the control circuit in some embodiments of the present application is shown. As Figure 2 shown, in some embodiments of the present application, the control circuit 100 specifically includes a sampling circuit, an error amplifier 120, a conversion circuit 130, a current sharing circuit 140a, a comparator 150, a PWM generation circuit 160, an enable circuit 170, and a mirror circuit 180.

[0038] The sampling circuit includes a first sampling resistor 111 and a second sampling resistor 112 connected in series between the output voltage Vout and the ground terminal GND, and the intermediate node of the two provides a feedback voltage Vfb representing the output voltage Vout. The error amplifier 120 is configured to compare the feedback voltage Vfb with a reference voltage Vref and provide an error amplification signal Vcomp of the two. In Figure 2 ​In the embodiment shown in FIG. 1, the non-inverting input of the error amplifier 120 is connected to the feedback voltage Vfb, the inverting input is connected to the reference voltage Vref, and the output outputs an error amplification signal Vcomp. The conversion circuit 130 converts the error amplification signal Vcomp of the voltage type into a reference current Icomp. It should be understood that in the control circuit 100, the sub-control circuits of each power phase can share the reference current Icomp to regulate their own output currents. That is, each sub-control circuit shares the sampling circuit, the error amplifier 120, and the conversion circuit 130 described above.

[0039] The sub-control circuit of the main phase and the corresponding control principle should be well known to those skilled in the art, for example, the regulation of its own current can be achieved by a peak current control mode and / or a valley current mode. Therefore, in the embodiment shown in FIG. 1, the sub-control circuit of the main phase is not described in detail. Figure 2 In the embodiment shown in FIG. 1, the sub-control circuit of the main phase is not described in detail. That is, each sub-control circuit of the main phase has its own current sharing circuit 140a, comparator 150, PWM generation circuit 160, enable circuit 170, and mirror circuit 180.

[0040] In the embodiment shown in FIG. 1, the sub-control circuit of the main phase is not described in detail. That is, each sub-control circuit of the main phase has its own current sharing circuit 140a, comparator 150, PWM generation circuit 160, enable circuit 170, and mirror circuit 180. Figure 2 In the embodiment shown in FIG. 1, the sub-control circuit of the main phase is not described in detail. That is, each sub-control circuit of the main phase has its own current sharing circuit 140a, comparator 150, PWM generation circuit 160, enable circuit 170, and mirror circuit 180.

[0041] The enable circuit 170 is configured to determine the current load state according to the total output current Iout of the multiphase switching power supply, and generate the slave phase enable signal En and the inverse of the enable signal En_b. In some embodiments, the multiphase switching power supply can include multiple slave phases, and thus the enable signal En of each slave phase can be generated independently. For example, when the total output current Iout is in the first interval, only the enable signal of the first slave phase has a valid level, i.e., only the main phase and the first slave phase are enabled; when the total output current Iout is in the second interval, the enable signals of the first slave phase and the second slave phase both have a valid level, i.e., the main phase, the first slave phase and the second slave phase are enabled, and so on. The enable signal En can be used to control the working state of the corresponding slave phase by controlling the working state of the PWM generation circuit 160. When the enable signal En has a valid level, the PWM generation circuit 160 works normally and outputs the corresponding pulse width modulation signal PWM; when the enable signal En has an invalid level, the pulse width modulation signal PWM provided by the PWM generation circuit 160 always remains at its invalid level, so that the power unit 220 remains off. The mirror circuit 180 is configured to generate the mirror current Isen2' of the slave phase sampling current Isen2 for use by the current sharing circuit 140a.

[0042] Figure 3 A schematic structural diagram of the current sharing circuit of some embodiments of the present application is shown. Figure 4 A schematic circuit diagram of the processing unit is shown. Figure 3 A schematic circuit diagram of the processing unit is shown. Figure 5 A schematic circuit diagram of the processing unit is shown. Figure 3 A schematic circuit diagram of the processing unit is shown. The specific structure of the current sharing circuit 140a of the present application is described below. Figures 3 to 5 A schematic circuit diagram of the processing unit is shown.

[0043] Reference is made to Figure 3 In some embodiments, the current sharing circuit 140a includes a processing unit 141, a regulating unit 142, a first current path 143, an output unit 144, a clamping unit 145, a voltage generation unit 146, and a second current path 147.

[0044] The processing unit 141 is configured to receive the main phase sampling current Isen1 and the slave phase sampling current Isen2, and provide a difference current Ierr therebetween.

[0045] Reference is made to Figure 4In a preferred embodiment, the processing unit 141 comprises a first filtering module 141a, a second filtering module 141b and a difference calculation module 141c. The first filtering module 141a filters the main phase sampling current Isenl to obtain a first filtered current Ifl, the second filtering module 141b filters the slave phase sampling current Isen2 to obtain a second filtered current If2, and the difference calculation module 141c provides a difference current Ierr according to the first filtered current Ifl and the second filtered current If2. Before obtaining the difference current Ierr, the main phase sampling current Isenl and the slave phase sampling current Isen2 are respectively subjected to low-pass filtering, so that the influence of high-frequency noise on the current sharing regulation accuracy can be suppressed.

[0046] Specifically, the first filter module 141a includes a first filter 1411, a first transistor MN1 and a second transistor MN2. The first end and the control end of the first transistor MN1 are shorted and connected with the main phase sampling current Isen1, and the second end is grounded GND. The first end of the second transistor MN2 provides the first filter current If1, the second end is grounded GND, and the control end is connected with the control end of the first transistor MN1 through the first filter 1411. The second filter module 141b includes a second filter 1412, a third transistor MN3 and a fourth transistor MN4. The first end and the control end of the third transistor MN3 are shorted and connected with the slave phase sampling current Isen2, and the second end is grounded GND. The first end of the fourth transistor MN4 provides the second filter current If2, the second end is grounded GND, and the control end is connected with the control end of the third transistor MN3 through the second filter 1412. The first filter 1411 and the second filter 1412 are, for example, RC filters. Among them, the first filter 1411 includes a first resistor R1 connected between the control end of the first transistor MN1 and the control end of the second transistor MN2, and a first capacitor C1 connected between the control end of the second transistor MN2 and the ground GND, and the second filter 1412 includes a second resistor R2 connected between the control end of the third transistor MN3 and the control end of the fourth transistor MN4, and a second capacitor C2 connected between the control end of the fourth transistor MN4 and the ground GND. It should be understood that the first filter 1411 and the second filter 1412 can also have other filter structures, which are not limited in the present application. The difference calculation module 141c includes a thirteenth transistor MP1 and a fourteenth transistor MP2. The control end and the second end of the thirteenth transistor MP1 are shorted and connected with the first filter current If1, specifically connected with the first end of the second transistor MN2. The control end of the fourteenth transistor MP2 is connected with the control end of the thirteenth transistor MP1, the first end is connected with the first end of the thirteenth transistor MP1, the second end is connected with the second filter current If2, specifically connected with the first end of the fourth transistor MN4, and provides a difference current Ierr, which is also the shunt result of the second filter current If2 to the first filter current If1. Figure 4 In the example, the first ends of the thirteenth transistor MP1 and the fourteenth transistor MP2 are connected with the supply voltage VDD.

[0047] The adjusting unit 142 is connected with the processing unit 141, and is configured to provide an average current Iavg according to the difference current Ierr and a reference current Icomp. Specifically, the adjusting unit 142 includes a fifth transistor MN5 and a sixth transistor MN6. The first end and the control end of the fifth transistor MN5 are shorted and connected with the reference current Icomp and the difference current Ierr, and the second end is grounded GND. The first end of the sixth transistor MN6 provides the average current Iavg, the second end is grounded GND, and the control end is connected with the control end of the fifth transistor MN5.

[0048] The output unit 144 is connected to the adjusting unit 142 via the first current path 143 for outputting the average current Iavg when the first current path 143 is turned on. Wherein, the first current path 143 is turned on when the enable signal En is at an effective level.

[0049] The output unit 144 includes a fifteenth transistor MP3 and a sixteenth transistor MP4. The control terminal and the second terminal of the fifteenth transistor MP3 are shorted, and the average current Iavg is connected via the first current path 143, specifically, the first terminal of the sixth transistor MN6. The control terminal of the sixteenth transistor MP4 is connected to the control terminal of the fifteenth transistor MP3, the first terminal is connected to the first terminal of the fifteenth transistor MP3, and the second terminal outputs the average current Iavg when the first current path 143 is turned on. In Figure 5 For example, the first terminals of the fifteenth transistor MP3 and the sixteenth transistor MP4 are connected to the power supply voltage VDD.

[0050] In some embodiments, the first current path 143 includes a seventh transistor MN7. The control terminal of the seventh transistor MN7 receives the enable signal En, the first terminal is connected to the output unit 144, specifically, the second terminal of the fifteenth transistor MP3, and the second terminal is connected to the first terminal of the sixth transistor MN6. The seventh transistor MN7 is turned on when the enable signal En is at an effective level to realize the transmission of the average current Iavg. In a preferred embodiment, the first current path 143 further includes an eighth transistor MN8 connected in series with the seventh transistor MN7. The first terminal of the eighth transistor MN8 is connected to the second terminal of the seventh transistor MN7, the second terminal is connected to the first terminal of the sixth transistor MN6, and the control terminal receives the inverse signal En_b of the enable signal En. Wherein, the first terminal and the second terminal of the eighth transistor MN8 are shorted, when the phase is started, the seventh transistor MN7 is turned on, the eighth transistor MN8 is turned off, and the seventh transistor MN7 can fully absorb the channel charge of the eighth transistor MN8 to establish its own channel, which is more conducive to reducing the interference caused by the current mutation at the starting moment.

[0051] The clamping unit 145 is connected with the first node A. As shown, the first node A is specifically a common node of the regulating unit 142 and the first current path 143. The clamping unit 145 is configured to clamp the voltage of the first node A according to the first voltage Vcla when the first current path 143 is disconnected. In some embodiments, the clamping unit 145 includes an operational amplifier AMP and a clamping transistor MC1. The non-inverting input terminal of the operational amplifier AMP is connected with the first voltage Vcla, the inverting input terminal is connected with the first node A, and the output terminal is connected with the control terminal of the clamping transistor MC1; the first end of the clamping transistor MC1 is connected with the power supply voltage VDD, and the second end is connected with the first node A. The operational amplifier AMP can be specifically a five-tube structure, a nine-tube structure, etc., which is not limited in the present application. Through the clamping unit 145, the voltage of the first node A can be stabilized at the first voltage Vcla when the phase is not started, and when the phase is started, the first current path 143 is turned on, and the voltage of the first node A is continued to be established by the first voltage Vcla, so that the voltage fluctuation of the first node A can be effectively reduced, the current impact caused by the voltage mutation can be avoided, and the over-regulation of the phase caused by the excessive average current Iavg when the phase is started can be avoided, which is more conducive to improving the system stability.

[0052] The voltage generating unit 146 is configured to generate the first voltage Vcla described above. In some embodiments, the first voltage Vcla can be generated according to the mirror current Isen2' of the phase sampling current Isen2. Specifically, the voltage generating unit 146 includes a ninth transistor MN9 and a tenth transistor MN10. The control terminal and the first end of the ninth transistor MN9 are short-circuited and connected with the mirror current Isen2', and the second end is grounded GND. The control terminal of the tenth transistor MN10 is connected with the control terminal of the ninth transistor MN9, the first end is connected with the output unit 144 through the second current path 147, and the second end is grounded GND. The tenth transistor MN10 is connected with the second node B through the second current path 147, and the clamping unit 145 is connected with the second node B to connect the first voltage Vcla. The mirror current Isen2' of the phase sampling current Isen2 is provided through the mirror circuit 180, so that the first voltage Vcla generated is closely related to the current of the phase itself, which is more conducive to improving the system anti-interference. It should be noted that, in an ideal state, the phase sampling current Isen2 and the mirror current Isen2' are completely equal. However, in actual working conditions, due to the process deviation of devices and other reasons, the phase sampling current Isen2 and the mirror current Isen2' may have a slight deviation, i.e., they are approximately equal.

[0053] In some embodiments, the second current path 147 includes an eleventh transistor MN11, with its first terminal connected to the output unit 144, specifically to the second terminal of the fifteenth transistor MP3. The second terminal is connected to the second node B, and the control terminal receives an inverting signal En_b, thus interlocking the on / off states of the second current path 147 and the first current path 143 to prevent both from conducting simultaneously and creating a DC path. In a preferred embodiment, the second current path 147 further includes a twelfth transistor MN12 connected in series with the eleventh transistor MN11. The first terminal of the twelfth transistor is connected to the second terminal of the eleventh transistor MN11, and the second terminal is connected to the second node B. The control terminal receives an enable signal En. The first and second terminals of the twelfth transistor MN12 are shorted, which also allows full utilization of the channel charge during the level switching of the enable signal En to improve the output immunity of the current sharing circuit 140a. It should be understood that when the enable signal En has an invalid level, the second current path 147 is on, and thus the aforementioned first voltage Vcla can be provided at the second node B. At the same time, the output unit 144 will also provide output current according to the current of the second current path 147, but since the PWM generation circuit is not enabled at this time, the output current of the output unit 144 will not affect the slave phase.

[0054] According to the multiphase switching power supply and its current sharing circuit provided in this application, when the slave phase is not started, the voltage of the first node is clamped by the clamping unit, thereby reducing the voltage change amplitude of the first node at the moment of slave phase start-up. Since the transient magnitude of the current sharing current is related to the voltage change amplitude, the overshoot of the current sharing current at the moment of slave phase start-up can be avoided, thereby avoiding excessive adjustment at the moment of slave phase start-up, which is beneficial to improving the immunity, start-up stability and dynamic response performance of the slave phase.

[0055] Furthermore, according to the current sharing circuit provided in this application, at the instant of level switching of the enable signal, the channel charge of the eighth or twelfth transistor can be fully utilized to establish the channel of the seventh or eleventh transistor, thereby effectively suppressing the current disturbance caused by switching and improving the stability of the current sharing circuit in the dynamic response process.

[0056] Furthermore, by generating a first voltage based on the mirror current of the sampled current of the slave phase, the first voltage can be dynamically synchronized with the sampled current of the slave phase itself. Compared with using a fixed first voltage, it can more accurately adapt to the current situation and further improve the clamping effect.

[0057] Figure 6 The following are schematic structural diagrams of the control circuitry in some embodiments of this application. Figure 7 Show Figure 6 A schematic diagram of the current sharing circuit.

[0058] like Figure 6The control circuit 100b shown also includes a sampling circuit having a first sampling resistor 111 and a second sampling resistor 112, an error amplifier 120, a conversion circuit 130, a comparator 150, a PWM generation circuit 160, and an enabling circuit 170.

[0059] The control circuit 100b shown is different from the control circuit 100a shown in Figure 2 The control circuit 100b shown is different from the control circuit 100a shown in Figure 6 The control circuit 100b shown is different from the control circuit 100a shown in Figure 7 The control circuit 100b shown is different from the control circuit 100a shown in Figure 7 The control circuit 100b shown is different from the control circuit 100a shown in Figures 3 to 5 The control circuit 100b shown is different from the control circuit 100a shown in

[0060] It should be noted that in the embodiment shown in Figures 2 to 5 The control circuit 100b shown is different from the control circuit 100a shown in Figures 6 to 7 The control circuit 100b shown is different from the control circuit 100a shown in

[0061] Figure 8 A schematic structural diagram of a control circuit 100c in some embodiments of the present application is shown. The control circuit 100c also includes a sampling circuit having a first sampling resistor 111 and a second sampling resistor 112, an error amplifier 120, a conversion circuit 130, a current sharing circuit 140a, a comparator 150, a PWM generation circuit 160, and a mirror circuit 180. The control circuit 100c shown is different from the control circuit 100a shown in Figure 2 The control circuit 100b shown is different from the control circuit 100a shown in Figure 8The enable circuit 170' in the control circuit 100c shown is configured to generate an enable signal En and an inverse enable signal En_b according to the total output current Iout and the soft start signal SSdone. That is, the enable unit 170' is configured to provide an active level of the enable signal En after the total output current Iout falls into a set range and the soft start stage ends. In the soft start stage of the slave phase, since the enable signal En also has an inactive level, the current sharing circuit 140a also does not output the current sharing current Iavg, and the current sharing disturbance caused by the fact that the phase currents are not stable during the soft start process can be avoided, and the reliability and stability of the slave phase start process are further improved.

[0062] According to the current sharing circuit and the multi-phase switching power supply provided in the present application, when the slave phase is not working, the first node is voltage clamped by the clamping module, so that the voltage variation range of the first node is reduced at the slave phase start moment, and over-regulation at the slave phase start moment is avoided, and the start stability and dynamic response performance of the multi-phase switching power supply are improved.

[0063] In accordance with the embodiments of the present application as described above, the embodiments do not describe all the details, and the present application is not limited to the specific embodiments. Obviously, according to the above description, many modifications and changes can be made. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The scope of protection of the present application should be subject to the scope defined by the claims of the present application.

Claims

1. A current sharing circuit for use in a multiphase switching power supply, wherein, The current sharing circuit comprises: a processing unit configured to provide a difference current of a main phase sampling current and a slave phase sampling current; an adjusting unit connected to the processing unit and configured to provide an average current according to the difference current and a reference current; an output unit connected to the adjusting unit via a first current path and configured to output the average current in a conducting state of the first current path; and a clamping unit connected to a first node which is a common node of the adjusting unit and the first current path, and configured to clamp the first node according to a first voltage in a non-conducting state of the first current path, wherein the multi-phase switching power supply comprises a main phase and a slave phase, and the first current path is conducted when an enable signal of the slave phase is at a valid level. The current sharing circuit further comprises:

2. The current sharing circuit of claim 1, wherein, a voltage generating unit connected to the output unit via a second current path, wherein the voltage generating unit and the second current path are connected to a second node which is connected to the clamping unit, the second current path is conducted when the first current path is non-conducted, and the second node provides the first voltage. The processing unit comprises:

3. The current sharing circuit of claim 1, wherein, a first filtering module configured to filter the main phase sampling current to obtain a first filtered current; a second filtering module configured to filter the slave phase sampling current to obtain a second filtered current; and a difference calculating module configured to provide the difference current according to the first filtered current and the second filtered current.

4. The current sharing circuit of claim 3, wherein the first filtering module comprises: a first filter, a first transistor having a first end and a control end shorted and connected to the main phase sampling current, and a second end grounded; and a second transistor having a second end grounded, and a control end connected to the control end of the first transistor via the first filter, the second filtering module comprises: a second filter, a third transistor having a first end and a control end shorted and connected to the slave phase sampling current, and a second end grounded; and a fourth transistor having a second end grounded, and a control end connected to the control end of the third transistor via the second filter, the difference calculating module comprises: a thirteenth transistor having a second end and a control end shorted and connected to the first end of the second transistor; and a fourteenth transistor having a first end connected to the first end of the thirteenth transistor, a control end connected to the control end of the thirteenth transistor, and a second end connected to the first end of the fourth transistor and configured to provide the difference current. The first filter and / or the second filter is an RC filter.

5. The current sharing circuit of claim 4, wherein, The adjusting unit comprises:

6. The current sharing circuit of claim 1, wherein, a fifth transistor having a first end and a control end shorted and connected to the difference current and the reference current, and a second end grounded; and a sixth transistor having a control end connected to the control end of the fifth transistor, a second end grounded, and a first end configured to provide the average current. The clamping unit comprises:

7. The current sharing circuit of claim 1, wherein, an operational amplifier having a non-inverting input end connected to the first voltage, and an inverting input end connected to the first node; and a clamping transistor having a first end connected to a power voltage, a second end connected to the first node, and a control end connected to an output end of the operational amplifier. The voltage generating unit comprises:

8. The current sharing circuit of claim 2, wherein, ​ a ninth transistor having a first end and a control end shorted and connected to a mirror current of the sampling current of the slave phase, and a second end connected to ground; and a tenth transistor having a control end connected to the control end of the ninth transistor, a second end connected to ground, and a first end connected to the second node.

9. The current sharing circuit of claim 2, wherein, the first current path comprises a seventh transistor and an eighth transistor connected in series, the seventh transistor has a first end connected to the output unit, and a control end connected to the enable signal, the eighth transistor has a second end connected to the first node, and a control end connected to an inverted signal of the enable signal, the second current path comprises an eleventh transistor and a twelfth transistor connected in series, the eleventh transistor has a first end connected to the output unit, and a control end connected to the inverted signal of the enable signal, the twelfth transistor has a second end connected to the second node, and a control end connected to the enable signal, wherein the first end and the second end of the eighth transistor are shorted, and the first end and the second end of the twelfth transistor are shorted.

10. The current sharing circuit of claim 2, wherein, the output unit comprises: a fifteenth transistor having a control end and a second end shorted and connected to the first current path and the second current path; and a sixteenth transistor having a first end connected to the first end of the fifteenth transistor, a control end connected to the control end of the fifteenth transistor, and a second end outputting the average current when the first current path is turned on.

11. The current sharing circuit of any of claims 1-10, wherein, the first voltage is greater than zero.

12. A multiphase switching power supply wherein, comprises: a main phase; and a slave phase comprising the current sharing circuit according to any one of claims 1-11, the slave phase providing an output current of the slave phase according to the average current.

13. The multiphase switching power supply of claim 12 wherein, The multi-phase switching power supply further comprises: a sampling circuit configured to provide a feedback voltage, the feedback voltage representing an output voltage of the multi-phase switching power supply; an error amplifier configured to provide an error amplified signal of the feedback voltage and a reference voltage; and a conversion circuit configured to convert the error amplified signal of the voltage type to provide the reference current, wherein the main phase provides an output current of the main phase according to the reference current.

14. The multiphase switching power supply of claim 12 wherein, The slave phase further comprises: an enable circuit configured to provide an enable signal of the slave phase according to an output current of the multi-phase switching power supply and a soft start signal, wherein the enable signal provides an active level after the output current of the multi-phase switching power supply falls into a set range and a soft start stage ends.

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