Coupler and chip

Abstract

A coupler and a chip are provided. The coupler includes: a plurality of unit circuits connected to a plurality of differential line pairs and a single-ended line; and a plurality of isolation resistors connected between the plurality of differential line pairs, in which each of the plurality of unit circuits includes: a transformer including a primary side and a secondary side, the primary side being connected to one of the plurality of differential line pairs, the secondary side being connected to a single-ended line; and a secondary side capacitor connected in parallel to the secondary side.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0136902, filed on October 8, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to N-way couplers and chips including N-way couplers. Background Technology

[0003] With the commercialization of 5G (5G) New Radio (NR) communications, development is underway for radio frequency integrated circuits (RFICs) used in millimeter-wave bands (such as FR2 (frequency range 2)). In high-frequency bands (such as millimeter waves), supply voltages also decrease as transistor performance deteriorates due to factors such as parasitic components, and the complementary metal-oxide-semiconductor (CMOS) process used in RFIC designs is being scaled down. The degradation of transistor performance and the reduction in supply voltage quickly lead to a decrease in the output power of the power amplifier. Summary of the Invention

[0004] Embodiments of this disclosure provide an N-way coupler and a chip including the N-way coupler.

[0005] According to one aspect of the embodiments, a coupler includes: a plurality of unit circuits connected to a plurality of differential pairs and a single-ended line; and a plurality of isolation resistors connected between the plurality of differential pairs, wherein each of the plurality of unit circuits includes: a transformer including a primary side and a secondary side, the primary side being connected to one of the plurality of differential pairs and the secondary side being connected to the single-ended line; and a secondary-side capacitor connected in parallel to the secondary side.

[0006] According to one aspect of an embodiment, a chip includes: a plurality of amplifiers configured to output a plurality of amplified signals via a plurality of differential line pairs; and a coupler connected to the plurality of differential line pairs and configured to combine the plurality of amplified signals and output a combined signal via a single-ended line, wherein the coupler includes: a plurality of unit circuits connected to the plurality of differential line pairs and the single-ended line, and a plurality of isolation resistors connected between the plurality of unit circuits and the plurality of differential line pairs, and each of the plurality of unit circuits includes: a transformer including a primary side and a secondary side, the primary side being connected to one of the plurality of differential line pairs and the secondary side being connected to the single-ended line; and a secondary-side capacitor connected in parallel to the secondary side.

[0007] According to one aspect of an embodiment, a chip includes: a coupler connected between a plurality of differential line pairs and a single-ended line, and configured to distribute a signal applied through the single-ended line into a plurality of signals; and a plurality of amplifiers connected to the plurality of differential line pairs and configured to amplify the plurality of signals, wherein the coupler includes: a plurality of unit circuits connected to the plurality of differential line pairs and the single-ended line, and a plurality of isolation resistors connected between the plurality of unit circuits and the plurality of differential line pairs, and each of the plurality of unit circuits includes: a transformer including a primary side and a secondary side, the primary side being connected to one of the plurality of differential line pairs and the secondary side being connected to the single-ended line; and a secondary-side capacitor connected in parallel to the secondary side. Attached Figure Description

[0008] The above and other objects and features of this disclosure will become clear from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0009] Figure 1 A chip according to some embodiments is shown.

[0010] Figures 2 to 6 This is a circuit diagram illustrating the conversion process of the unit circuit according to some embodiments.

[0011] Figure 7 It is based on Figures 2 to 6 The circuit diagram of the conversion unit circuit.

[0012] Figure 8 This is a circuit diagram of a unit circuit according to some embodiments.

[0013] Figure 9 This is a circuit diagram of an N-way coupler according to some embodiments.

[0014] Figure 10 This is a circuit diagram of an N-channel chip according to some embodiments.

[0015] Figure 11 This is a circuit diagram of a 2-way coupler according to some embodiments.

[0016] Figure 12 This is a circuit diagram of a 2-way chip according to some embodiments.

[0017] Figure 13 This is a circuit diagram of an N-channel chip according to some embodiments.

[0018] Figure 14 This is a circuit diagram of an N-channel chip according to some embodiments.

[0019] Figures 15 to 18 The diagram shows a simulated waveform of a coupler according to some embodiments.

[0020] Figure 19 An array of transformers included in a coupler is shown according to some embodiments.

[0021] Figure 20 A wireless communication device according to some embodiments is shown. Detailed Implementation

[0022] In the following description, embodiments of the present disclosure will be described in such detail and clarity that those skilled in the art can readily implement the present disclosure.

[0023] Figure 1 A chip according to some embodiments is shown.

[0024] Reference Figure 1 According to some embodiments, chip 100 may include a plurality of amplifiers AMP1 to AMPN and coupler 110.

[0025] Multiple amplifiers AMP1 to AMPN can be configured to output multiple amplified signals through multiple differential line pairs DL1, DL2, ..., DLN. Specifically, each amplifier can be connected to a corresponding differential line pair and output an amplified signal by amplifying the signal applied to the differential line pair. Therefore, the amplified signal output through the differential line pair is a differential signal. Multiple amplifiers AMP1 to AMPN are connected to coupler 110 through multiple differential line pairs DL1 to DLN. That is, multiple amplified signals are applied to coupler 110 through multiple differential line pairs DL1 to DLN.

[0026] In some embodiments, a plurality of amplifiers AMP1 to AMPN can amplify the signal applied to the differential line pair and output the amplified signal (or amplified signal) in a first direction D1, which is the direction of the single-ended line SEL. For example, each of the plurality of amplifiers AMP1 to AMPN can be a power amplifier.

[0027] Optionally, in some embodiments, a plurality of amplifiers AMP1 to AMPN can amplify the signal applied to the differential line pair via a single-ended line SEL and a plurality of unit circuits UC1, UC2, ..., UCN, and can output the amplified signal in a second direction D2. For example, the second direction D2 may be opposite to the first direction D1. For example, each of the plurality of amplifiers AMP1 to AMPN may be a low-noise amplifier (LNA).

[0028] In some embodiments, the number of differential line pairs DL1 to DLN can be configured as N (where N is a natural number greater than or equal to 2). Similarly, the number of amplifiers AMP1 to AMPN can also be configured as N to correspond to the number of differential line pairs DL1 to DLN.

[0029] Coupler 110 is connected between a single-ended line SEL and multiple differential line pairs DL1 to DLN.

[0030] In some embodiments, coupler 110 may be configured to couple (or combine) multiple amplified signals from multiple amplifiers AMP1 to AMPN, and output the combined signal to a single-ended line SEL. In this case... Figure 1 Coupler 110 can be defined as a combiner. When the number of amplifiers AMP1 to AMPN is N, coupler 110 can operate as an N-way coupler 110 that combines N amplified signals.

[0031] Optionally, coupler 110 can be configured to distribute the signal applied via single-ended line SEL into multiple signals (e.g., N signals) through multiple unit circuits UC1 to UCN, and output the N signals to multiple amplifiers AMP1 to AMPN. In this case, Figure 1 Coupler 110 can be defined as a distributor. When the number of amplifiers AMP1 to AMPN is N, coupler 110 can operate as an N-way distributor that distributes one signal into N signals. In this case, multiple amplifiers AMP1 to AMPN can amplify multiple distributed signals.

[0032] In some embodiments, the coupler 110 may include multiple unit circuits UC1 to UCN and multiple isolation resistors R. ISO11 To R ISO1N and R ISO21 To R ISO2N .

[0033] The number of unit circuits UC1 to UCN is N, where N is the number of differential line pairs DL1 to DLN or the number of amplifiers AMP1 to AMPN.

[0034] Differential line pairs are connected to one side of a corresponding unit circuit among the multiple unit circuits UC1 to UCN, and single-ended line SEL is connected to the other side of that corresponding unit circuit. Here, this side may correspond to the output terminal of each of the multiple amplifiers AMP1 to AMPN. Furthermore, in this application, differential line pairs may correspond to differential ports, and single-ended line SEL may correspond to single-ended ports.

[0035] In some embodiments, each of the plurality of unit circuits UC1 to UCN may be configured to operate as a differential single-ended transmission line having a characteristic impedance having a first value (or magnitude) and a phase having a second value (or magnitude). In this disclosure, a differential single-ended transmission line may be defined as a transmission line in which one end is connected to a differential pair and the other end is connected to a single-ended line SEL.

[0036] In some embodiments, each of the plurality of unit circuits UC1 to UCN can be configured to provide signal conversion and impedance matching between the differential line pair and the single-ended line SEL. Specifically, this is equivalently defined as each of the plurality of unit circuits UC1 to UCN having a differential characteristic impedance as a characteristic impedance defined in the differential line pair and a single-ended characteristic impedance as a characteristic impedance defined in the single-ended line SEL. The differential characteristic impedance or the single-ended characteristic impedance may have a value that allows each of the plurality of unit circuits UC1 to UCN to provide impedance matching between the differential line pair and the single-ended line SEL.

[0037] When impedance matching is provided through each of the multiple unit circuits UC1 to UCN, the impedance (or the load impedance of the amplifier) ​​defined at the output terminal of each of the multiple amplifiers AMP1 to AMPN can correspond to a reference impedance. Here, the reference impedance can be defined as the impedance that "allows the output power on the load side of the amplified power of each of the multiple amplifiers AMP1 to AMPN to have a maximum value". In other words, the output power can be maximized through impedance matching.

[0038] Furthermore, signals transmitted via multiple differential lines DL1 to DLN (e.g., output signals of multiple amplifiers AMP1 to AMPN) and signals transmitted via single-ended lines SEL can be converted to each other via multiple unit circuits UC1 to UCN.

[0039] In some embodiments, the second value of the differential single-ended transmission line equivalent to each of the plurality of unit circuits UC1 to UCN can be 90 degrees. That is, each of the plurality of unit circuits UC1 to UCN can be configured to be equivalent to a differential single-ended transmission line having a length of λ / 4 (where "λ / 4" is the wavelength of the signal).

[0040] Multiple isolation resistors R ISO11 To R ISO1N and R ISO21 To R ISO2N It can be connected between multiple differential pairs DL1 to DLN (and / or multiple unit circuits UC1 to UCN) and can provide isolation between differential pairs (and signals transmitted through differential pairs).

[0041] In some embodiments, multiple isolation resistors R ISO11 To R ISO1N and R ISO21 To R ISO2N It may include multiple first isolation resistors R ISO11 To R ISO1N and multiple second isolation resistors R ISO21 To R ISO2N Multiple first isolation resistors R ISO11 To RISO1N Connected to the first differential line in a differential line pair, and multiple second isolation resistors R ISO21 To R ISO2N Connect to the second differential line in this differential line pair. Specifically, multiple first isolation resistors R... ISO11 To R ISO1N One end of each of them is connected to the first differential line, and multiple first isolation resistors R ISO11 To R ISO1N The other ends of each of them are connected to the first node N1. In addition, multiple second isolation resistors R ISO21 To R ISO2N One end of each of them is connected to the second differential line, and multiple second isolation resistors R ISO21 To R ISO2N The other ends of each of them are connected to the second node N2.

[0042] Here, the first differential line can be called a positive line, differential signal line, high signal line, etc., and the second differential line can be called a negative line, inverted differential signal line, low signal line, etc.

[0043] In some embodiments, when N is greater than 2, the plurality of first isolation resistors R ISO11 To R ISO1N It may include N first isolation resistors and multiple second isolation resistors R ISO21 To R ISO2N It may include N second isolation resistors. Optionally, when N is 2, one first isolation resistor and one second isolation resistor may be included in the coupler 110. Multiple isolation resistors R ISO11 To R ISO1N and R ISO21 To R ISO2N Provides isolation between differential lines (or signals passing through differential lines).

[0044] According to some of the embodiments described above, the chip 100 can include multiple unit circuits UC1 to UCN and multiple isolation resistors R. ISO11 To R ISO1N and R ISO21 To R ISO2N The coupler 110 couples the amplified signal to provide high output power, provides isolation between amplified signals, and provides signal conversion and impedance matching between differential lines and single-ended lines.

[0045] Figures 2 to 6 This is a circuit diagram illustrating the conversion process of the unit circuit according to some embodiments. Figure 7 It is based on Figures 2 to 6 The circuit diagram of the conversion unit circuit.

[0046] First, refer to Figure 2 The unit circuit UCa may include a first transformer TF1 and a transmission line TL. The impedance connected to each side of the first transformer TF1 is the target of impedance transformation (or matching). Multiple impedances at opposite ends (or both ends) of the primary side of the first transformer TF1 are defined as a first impedance Z1, and the transmission line TL is connected to the secondary side of the first transformer TF1. Furthermore, the impedances at both ends of the secondary side of the first transformer TF1 are defined as a second impedance Z2, and the transmission line TL is connected in series with the second impedance Z2. Additionally, one end of the secondary side of the first transformer TF1 is grounded. Therefore, the signal on the primary side of the first transformer TF1 is a differential signal, and the signal on the secondary side is a single-ended signal.

[0047] The first transformer TF1 can be configured as a matching network to provide a transition between a first impedance Z1 and a second impedance Z2. The turns ratio of the first transformer TF1 can be set according to the relationship between the first impedance Z1 and the second impedance Z2. In some embodiments, when the first impedance Z1 is 2 × Z2, the turns ratio of the first transformer TF1 can be set to... Optionally, when the first impedance Z1 is k×Z2 (where k is a non-zero positive real number), the turns ratio of the first transformer TF1 can be set to... .

[0048] For example, when the turns ratio of the first transformer TF1 is 2:1, the unit circuit can match the impedance observed from the primary side of the first transformer TF1 (i.e., the first impedance Z1) to four times the second impedance Z2.

[0049] A transmission line TL can be configured to have a phase difference and characteristic impedance based on its length. In some embodiments, the transmission line TL can be configured to have a specific characteristic impedance and a 90-degree phase difference. For example, the transmission line TL may have... The length of the transmission line TL. The characteristic impedance of the transmission line TL can have various values ​​depending on the number of amplifiers combined into the unit circuit.

[0050] Differential signals and single-ended signals can be converted to each other through the unit circuit UCa, and the first impedance Z1 and the second impedance Z2 can be converted to each other.

[0051] exist Figure 3 In the unit circuit UCb, Figure 2 The transmission line TL can be equivalently converted into a capacitor-inductor-capacitor (CLC) circuit (e.g., a low-pass filter). The CLC circuit may include a first inductor L1, a first capacitor C1, and a second capacitor C2, with the first inductor L1, first capacitor C1, and second capacitor C2 positioned at opposite ends of the secondary side of the first transformer TF1 at a distance of pi (or...). The shape is realized. In this case, the inductance L of the first inductor L1 is... Q Can be set to And the capacitance C of each of the first capacitor C1 and the second capacitor C2 Q Can be set to .here, It is the angular velocity of the signal.

[0052] exist Figure 4 In the unit circuit UCc, including Figure 3 In a CLC circuit, the first capacitor C1 can be implemented using a third capacitor C3 and a second inductor L2 connected in parallel, which are equivalent to each other. The second capacitor C2 can be implemented using a fourth capacitor C4 and a third inductor L3 connected in parallel, which are equivalent to each other. In this case, the capacitance of each of the third capacitor C3 and the fourth capacitor C4 is C. P Furthermore, the inductance of each of the second inductor L2 and the third inductor L3 is L. P hour, It can be created.

[0053] exist Figure 5 In the unit circuit UCd, in Figure 4 The first inductor L1, the second inductor L2, and the third inductor L3, implemented in a pi shape, can be equivalently implemented as a second transformer TF2 with a 1:1 turns ratio. The second transformer TF2 includes a fourth inductor L4 located on the primary side of the second transformer TF2 and a fifth inductor L5 located on the secondary side of the second transformer TF2. In this case, the inductance of each of the fourth inductor L4 and the fifth inductor L5 is L. X Inductor L X Can be used with inductor L Q have The relationship is as follows. In this case, "M" is the mutual inductance of the second transformer TF2. Furthermore, the inductance L... X Can be used with inductor L P have The relationship.

[0054] exist Figure 6 In the unit circuit UCE, Figure 5 The third capacitor C3, connected in parallel with the fourth inductor L4, can be implemented as the fifth capacitor C5 when transferred to the primary side of the first transformer TF1. In this case, the fifth capacitor C5 can have a capacitance that is (1 / k) times the capacitance of the fourth capacitor C4. For example, when k is 2, the capacitance of the fifth capacitor C5 is C. P / 2.

[0055] exist Figure 7In the unit circuit UCf, Figure 6 The first transformer TF1 and the second transformer TF2 can be implemented using a third transformer TF3, which is equivalent to them. The third transformer TF3 may include a sixth inductor L6 on the primary side and a fifth inductor L5 on the secondary side. In this case, the inductance of the sixth inductor L6 may have the same inductance as the fifth inductor L5. X The inductance is k times the value of the inductor. For example, when k is 2, the inductance of the sixth inductor L6 is 2L. X .

[0056] As described above, Figures 2 to 7 The unit circuits are equivalent to each other. In other words, through Figure 7 The unit circuit UCf, Figure 2 Transformers for impedance matching and transmission lines (TL) with specific characteristic impedances and phase differences can be implemented. Figure 7 In the unit circuit UCf, the transformer and transmission line TL are equivalently implemented as a transformer and two capacitors connected to both sides of the transformer. Therefore, with Figure 2 The first transformer TF1 is similar. Figure 7 The unit circuit UCf provides impedance matching between the impedance at one end of the transmission line TL and the impedance at the other ends of the transmission line TL, while reducing power loss and area due to the multi-stage structure (transformer and transmission line TL). Furthermore, Figure 7 The unit circuit UCf can be used as a differential single-ended transmission line TL that can convert the differential signal at one end of the transmission line TL to the single-ended signal at the other end of the transmission line TL while reducing power loss and area.

[0057] Figure 8 This is a circuit diagram of a unit circuit according to some embodiments.

[0058] Reference Figure 8 According to some embodiments, the unit circuit UCg can be configured, and from Figure 7 The fifth capacitor in the unit circuit is omitted. Specifically, the unit circuit UCg may include the transformer TF and the secondary-side capacitor C_S.

[0059] The primary side of transformer TF is connected to a differential pair (DL), and the secondary side of transformer TF is connected to a single-ended line SEL. Transformer TF may have a turns ratio of k:1. For example, the turns ratio may be 2:1.

[0060] The secondary-side capacitor C_S is connected in parallel to the secondary side of the transformer TF. When the capacitor is additionally connected to the primary side of the transformer TF (i.e., the differential line pair DL), the unit circuit can operate as a differential single-ended transmission line capable of providing impedance matching.

[0061] Figure 9 This is a circuit diagram of an N-way coupler according to some embodiments.

[0062] Reference Figure 9 In some embodiments, coupler 110a may include multiple unit circuits UC1 to UCN and multiple isolation resistors R. ISO11 To R ISO1N and R ISO21 To R ISO2N .

[0063] Multiple unit circuits UC1 to UCN can be connected between N differential line pairs DL1 to DLN and a single-ended line SEL, and can be implemented according to the above embodiments (e.g., Figures 2 to 8 The configuration can be configured as follows: Each unit circuit may include a transformer whose primary side is connected to one of a plurality of differential line pairs DL1 to DLN and whose secondary side is connected to a single-ended line SEL, as well as a secondary-side capacitor C_S connected in parallel to the secondary side.

[0064] In some embodiments, each of the plurality of unit circuits UC1 to UCN may further include a primary-side capacitor C_F connected in parallel to the primary side of the transformer. For example, the primary-side capacitor C_F (e.g., primary-side capacitors C_F1 to C_FN) may have a capacitance that is (1 / k) times the capacitance of the secondary-side capacitors C_S (e.g., secondary-side capacitors C_S1 to C_SN). The primary-side capacitor C_F may be omitted.

[0065] According to the above embodiments, and Figure 2 The unit circuits are equivalently configured with multiple unit circuits UC1 to UCN, and thus impedance matching and signal conversion between differential lines and single-ended lines can be provided with less power loss and area.

[0066] Since each unit circuit is equivalently configured to include Figure 2 The first transformer can be provided with matching for the differential characteristic impedance defined as the impedance in the differential line pair. For example, when k is 2 and the single-ended characteristic impedance defined in the single-ended line SEL is "R". OPT When / 2”, the differential characteristic impedance can be matched to R OPT Here, R OPT It corresponds to the reference impedance mentioned above.

[0067] In some embodiments, each transformer may be configured such that the bias current (e.g., I0) is applied. DC The bias current flows in the center tap. The bias current can be supplied via the power supply voltage V connected to the center tap of each transformer. DDThis is generated and can be supplied to transistors included in an amplifier that can be connected to coupler 110a. In this case, the center tap of each transformer is grounded to AC, and therefore the bias current can be supplied without an RF choke to AC ground. Specifically, because each transformer is connected in parallel to the corresponding differential pair, the differential signal flowing through the corresponding differential pair is combined at the center tap of each transformer. Therefore, the center tap can be grounded to AC.

[0068] Multiple isolation resistors R ISO11 To R ISO1N and R ISO21 To R ISO2N It can be connected between multiple differential pairs DL1 to DLN and provides isolation between the differential pairs connected to coupler 110a (and signals transmitted through the differential pairs). Multiple first isolation resistors R ISO11 To R ISO1N Connected to the first node N1 and the first differential line in a differential line pair, and multiple second isolation resistors R ISO21 To R ISO2N Connect the second node N2 and the second differential line in the differential line pair.

[0069] According to some embodiments, multiple isolation resistors R ISO11 to RISO1N and R ISO21 To R ISO2N It can be configured such that the corresponding impedance has the same magnitude as the differential characteristic impedance (e.g., R). OPT ).

[0070] Coupler 110a may have multiple unit circuits UC1 to UCN, which are equivalent to transmission lines, and multiple isolation resistors R. ISO11 To R ISO1N and R ISO21 To R ISO2N Therefore, it retains the characteristics of a Wilkinson coupler. Thus, coupler 110a can provide high isolation between multiple differential port pairs and maintain matched impedances over a wide bandwidth (e.g., differential characteristic impedance is R). OPT And the single-ended characteristic impedance is R OPT / k). Furthermore, as mentioned above, coupler 110a provides signal conversion and impedance matching between differential pairs and single-ended lines (SEL). Additionally, coupler 110a can be implemented using only transformers and capacitors instead of matching networks and transmission lines, thereby reducing power loss area.

[0071] Figure 10 This is a circuit diagram of an N-channel chip according to some embodiments.

[0072] See Figure 10 According to some embodiments, chip 100a may include a coupler comprising multiple unit circuits UC1 to UCN connected to multiple differential line pairs DL1 to DLN and a single-ended line SEL for combining amplified signals, and multiple isolation resistors R connected between the multiple differential line pairs DL1 to DLN. ISO11 To R ISO1N and R ISO21 To R ISO2N And the output terminal circuit OS connected to multiple differential line pairs DL1 to DLN.

[0073] The output terminal circuit OS includes multiple current sources IS1 to ISN, each corresponding to an amplifier's output terminal and connected to a differential pair. These current sources IS1 to ISN can be voltage-controlled current sources and can equivalently correspond to a transistor included in the output terminal of one of the multiple amplifiers. The capacitor connected in parallel to each current source is a parasitic capacitance (or a parasitic capacitance assembly). Each of the multiple parasitic capacitors C_par1 to C_parN can perform the function of the primary-side capacitor C_F according to the above embodiment in the corresponding unit circuit, or can replace the primary-side capacitor C_F.

[0074] According to some embodiments, the primary-side capacitor C_F can be omitted when the capacitance of each of the plurality of parasitic capacitance components C_par1 to C_parN is (1 / k) times the capacitance of the secondary-side capacitor C_S. For example, the primary-side capacitor C_F can be omitted when the parasitic capacitance is half the capacitance of the secondary-side capacitor C_S when k is 2.

[0075] Optionally, when the primary-side capacitor C_F is configured according to some embodiments, the secondary-side capacitor C_S can be configured to have a capacitance that is k times the sum of the capacitance of the primary-side capacitor C_F and the parasitic capacitance of one of the plurality of amplifiers. For example, when k is 2, the capacitance of the secondary-side capacitor C_S is twice the sum of the parasitic capacitance and the capacitance of the primary-side capacitor C_F.

[0076] According to the above embodiment, the transformer and secondary-side capacitor C_S (or, additionally, primary-side capacitor C_F) included in each unit circuit of the chip 100a, as well as the parasitic capacitance, can be connected with having Differential characteristic impedance and The single-ended characteristic impedance of the 90-degree transmission line and the transformer used for impedance matching operate equivalently. For example, when k is 2, the single-ended characteristic impedance is... In other words, each unit circuit and parasitic capacitance can be equivalent to the transmission line of a Wilkinson coupler. Therefore, chip 100a can provide high isolation between multiple differential port pairs and maintain matched impedance over a wide bandwidth.

[0077] In some embodiments, the bias current can be configured to be the supply voltage V connected to the center tap of each transformer. DD The current flows to the corresponding current source included in the output terminal circuit OS.

[0078] While achieving low power loss and small area, the chip 100a according to the above embodiment can couple amplified signals using the characteristics of a Wilkinson coupler. Furthermore, by using parasitic capacitance and a transformer as the transmission line of the Wilkinson coupler, the chip 100a does not require an additional inductor for resonance of the parasitic capacitance.

[0079] Figure 11 This is a circuit diagram of a 2-way coupler according to some embodiments.

[0080] Reference Figure 11 According to some embodiments, coupler 110b may include a first unit circuit UC1 connected to a first differential pair DL1 and a single-ended line SEL, a second unit circuit UC2 connected to a second differential pair DL2 and a single-ended line SEL, and a first isolation resistor R. ISO1 Second isolation resistor R ISO2 Here, the first isolation resistor R ISO1 Second isolation resistor R ISO2 It can be connected between the first differential line pair DL1 and the second differential line pair DL2.

[0081] The first unit circuit UC1 includes a first transformer TF1 whose primary side is connected to the first differential line pair DL1 and whose secondary side is connected to the single-ended line SEL, and a secondary capacitor C_S1 connected in parallel to the secondary side of the first transformer TF1.

[0082] Used to transfer bias current I DC The power supply voltage V provided to the transistor that can be connected to the first differential line pair DL1 DD It can be connected to the center tap of the first transformer TF1. The center tap of the first transformer TF1 is AC grounded, and therefore the bias current can be provided without affecting AC operation.

[0083] In some embodiments, the first unit circuit UC1 may further include a primary-side capacitor C_F1 connected in parallel to the primary side of the first transformer TF1.

[0084] The second unit circuit UC2 includes a second transformer TF2 whose primary side is connected to the second differential line pair DL2 and whose secondary side is connected to the single-ended line SEL, and a secondary capacitor C_S2 connected in parallel to the secondary side of the second transformer TF2.

[0085] Used to transfer bias current I DC The power supply voltage V provided to the transistor that can be connected to the second differential line pair DL2 DD It can be connected to the center tap of the second transformer TF2. The center tap of the second transformer TF2 is AC grounded, so bias current can be provided without affecting AC operation.

[0086] In some embodiments, the second unit circuit UC2 may further include a primary-side capacitor C_F2 connected in parallel to the primary side of the second transformer TF2.

[0087] According to the embodiments described above, the first unit circuit UC1 and the second unit circuit UC2 can provide signal conversion and impedance matching between the differential line pairs and the single-ended line SEL.

[0088] The first isolation resistor is connected to the third node N3 and the fifth node N5. The third node N3 is connected to the first differential pair DL1, and the fifth node N5 is connected to the second differential pair DL2. The second isolation resistor is connected to the fourth node N4 and the sixth node N6. The fourth node N4 is connected to the first differential pair DL1, and the sixth node N6 is connected to the second differential pair DL2. Each isolation resistor provides isolation between the differential lines of the differential pair.

[0089] Coupler 110b according to the above embodiment provides the characteristics of a Wilkinson coupler with low power loss and area. Furthermore, coupler 110b provides signal conversion and impedance matching between differential pairs and single-ended lines SEL.

[0090] Figure 12 This is a circuit diagram of a 2-way chip according to some embodiments.

[0091] Reference Figure 12 According to some embodiments, chip 100b may include a coupler and an output terminal circuit OS. The coupler includes a first unit circuit UC1, a second unit circuit UC2, and a first isolation resistor R for coupling amplified signals. ISO1 Second isolation resistor R ISO2 The output terminal circuit OS is connected to the first differential pair DL1 and the second differential pair DL2.

[0092] The output terminal circuit includes a first current source IS1 connected to the first differential line pair DL1 and a second current source IS2 connected to the second differential line pair DL2. Each of the plurality of parasitic capacitors C_par1 and C_par2 connected in parallel to the current sources IS1 and IS2 respectively can perform the function of the primary-side capacitor C_F according to the above embodiment in the corresponding unit circuit, or can replace the primary-side capacitor C_F.

[0093] According to the above embodiment, the primary-side capacitor C_F can be omitted depending on the capacitance of each of the parasitic capacitance components C_par1 and C_par2.

[0094] The first and second isolation resistors provide isolation between the differential line pairs. In some embodiments, the respective impedances can be configured to have the same magnitude as the differential characteristic impedance (e.g., R0). OPT ).

[0095] The first transformer TF1, the first capacitor C_F1, and the second capacitor C_S1 of the first unit circuit UC1 can be used as having Differential characteristic impedance and The single-ended characteristic impedance of the 90-degree transmission line and the transformer used for impedance matching operate equivalently.

[0096] Similarly, the second transformer TF2, the first capacitor C_F2, and the second capacitor C_S2 of the second unit circuit UC2 can be used as having Differential characteristic impedance and The single-ended characteristic impedance of the 90-degree transmission line and the transformer used for impedance matching operate equivalently.

[0097] In some embodiments, the bias current I DC It can be configured to supply voltage V connected to the center tap of the first transformer TF1. DD The current flows to the first current source IS1, and the bias current I... DC It can be configured to supply voltage V connected to the center tap of the second transformer TF2. DD It flows to the second current source IS2.

[0098] While achieving low power loss and small area, the chip 100b according to the above embodiment can couple amplified signals using the characteristics of a Wilkinson coupler. Furthermore, by using parasitic capacitance and a transformer as the transmission line of the Wilkinson coupler, the chip 100b does not require an additional inductor for resonance of the parasitic capacitance.

[0099] Figure 13 This is a circuit diagram of an N-channel chip according to some embodiments.

[0100] Reference Figure 13 According to some embodiments, chip 100c may include a coupler and a receive amplifier circuit RSC. The coupler includes multiple unit circuits UC1 to UCN and multiple isolation resistors R. ISO11 To R ISO1N and R ISO21 To R ISO2N The receiver amplifier circuit RSC is connected to multiple differential line pairs DL1 to DLN.

[0101] Multiple unit circuits UC1 to UCN can distribute a single signal provided from the single-ended line SEL into N signals, and can provide the N distributed signals to the receiving amplifier circuit RSC. In this case, a single-ended signal can be converted into N differential signals by multiple unit circuits UC1 to UCN.

[0102] According to the above embodiment, the transformer and secondary-side capacitor C_S (or, additionally, primary-side capacitor C_F) included in each unit circuit of chip 100c, as well as the parasitic capacitance included in the receiving amplifier circuit RSC, can operate equivalently to the transmission lines of the transformer and Wilkinson coupler used for impedance matching. Therefore, chip 100c can provide high isolation between multiple differential port pairs and maintain matched impedance over a wide bandwidth.

[0103] In some embodiments, the bias current can be configured to be the supply voltage V connected to the center tap of each transformer. DD The current flows to the corresponding current source included in the output terminal circuit.

[0104] The receiving amplifier circuit RSC is configured to amplify N assigned signals and includes multiple current sources IS1 to ISN respectively connected to multiple differential line pairs DLI to DLN. The multiple current sources IS1 to ISN can be voltage-controlled current sources and can equivalently correspond to transistors included in the output terminals of multiple amplifiers. Each of the multiple parasitic capacitors C_par1 to C_parN can perform the function of the primary-side capacitor C_F according to the above embodiment in the corresponding unit circuit, or can replace the primary-side capacitor C_F.

[0105] While possessing low power loss and area, as well as the characteristics of a Wilkinson coupler, the chip 100c according to the above embodiment can distribute single-ended signals. Furthermore, by using parasitic capacitance and a transformer as the transmission line of the Wilkinson coupler, the chip 100c does not require an additional inductor for resonance of the parasitic capacitance.

[0106] Figure 14 This is a circuit diagram of an N-way chip according to some embodiments. Detailed descriptions of portions identical to those described above may be omitted below.

[0107] Reference Figure 14 In some embodiments, in addition to the coupler 110 connected between the multiple differential line pairs DL1 to DLN and the single-ended line SEL, the chip 200 may also include multiple attenuators ATT1 to ATTN connected to the multiple differential line pairs DL1 to DLN.

[0108] Multiple attenuators ATT1 to ATTN can be configured to attenuate the magnitude of signals transmitted through multiple differential line pairs DL1 to DLN. For example, the multiple attenuators ATT1 to ATTN may include fixed attenuators with a fixed attenuation, variable attenuators with a variable attenuation, etc. For example, each of the multiple attenuators ATT1 to ATTN may be implemented as a T-type, pi-type, bridged T-type, O-type, etc., including multiple impedances and / or multiple variable impedances.

[0109] Coupler 110 can be connected to multiple isolation resistors R ISO11 To R ISO1N and R ISO21 To R ISO2N Multiple attenuators ATT1 to ATTN provide isolation for the attenuated signal. Coupler 110 can combine the attenuated signal through multiple unit circuits UC1 to UCN, and can output the combined signal to a single-ended line SEL.

[0110] Figure 15 , Figure 16 , Figure 17 and Figure 18 Simulated waveforms of the coupler according to some embodiments are shown.

[0111] Reference Figure 15 The diagram shows the waveforms or curves of the S-parameters S11, S22, and S33 corresponding to the return loss at each frequency. It can be seen that the S-parameters indicate the maximum values ​​near the center frequency (fcenter) across all ports. In other words, it shows that the differential characteristic impedance and single-ended characteristic impedance of each port are matched to each other.

[0112] Reference Figure 16 The waveforms of S31 and S32 for each frequency are shown. It can be seen that high isolation is ensured between ports because S31 and S32 are approximately -3dB.

[0113] Reference Figure 17 The waveform or curve of S21 for each frequency is shown. It can be seen that S21 shows the maximum value near the center frequency. It can also be seen that high isolation is ensured between the ports.

[0114] Reference Figure 18 This shows what happens when power is input to a 2-way coupler (e.g., in...). Figure 18 The power (input power pin) is coupled in a single-ended line. It can be seen that, compared to the case where the power is not coupled (case 1), when the power is coupled due to the two couplers (case 2), the output power of port 12 (e.g., ...) is significantly higher. Figure 18 The Pout value increased by approximately 3 dB.

[0115] Figure 19 An array of transformers included in a coupler is shown according to some embodiments.

[0116] Reference Figure 19 In some embodiments, the array of transformers may further include multiple transformers TF1 to TFN connected between multiple differential pairs DL1 to DLN and a single-ended line SEL. Each transformer may include a primary winding FC and a secondary winding SC.

[0117] Each primary-side coil FC can be connected to a corresponding differential pair. For example, the primary-side coil FC can be configured with a turns ratio of k:1. Figure 19 In this case, the turns ratio of the primary coil FC is 2:1. The primary coil FC can form k loops according to the turns ratio. As shown, when the turns ratio of the primary coil FC is 2:1, the primary coil FC may include an outer loop that overlaps with the secondary coil SC and an inner loop that does not overlap with the outer loop. In this case, the outer loop may be formed in a layer different from the layer of the secondary coil SC.

[0118] The two ends of the outer loop of the primary side coil FC can be connected to each differential line pair.

[0119] Each of the secondary-side coils SC can be connected together to a single-ended line SEL. The secondary-side coils SC can be configured to have a 1:1 turns ratio. The secondary-side coils SC may include a loop that overlaps with the primary-side coil FC and forms a loop in a different layer.

[0120] One end of a loop can be connected to a single-ended line SEL, and the other end of the loop can be grounded.

[0121] The transformer array according to the above embodiment is included in the coupler. In other words, the coupler can use a single transformer instead of the transformer and transmission line used for impedance matching, thereby reducing power loss and area.

[0122] Figure 20 A wireless communication device according to some embodiments is shown.

[0123] Reference Figure 20 The wireless communication device 300 may include a modem 310, an RF integrated circuit (RFIC) 320, a duplexer 330, a power modulator 340, and an antenna ANT.

[0124] Modem 310 may include digital processing circuitry (DPC) 311, a first digital-to-analog converter (DAC) 312, a second DAC 313, an analog-to-digital converter (ADC) 314, and a Mobile Industry Processor Interface (MIPI). Modem 310 may process baseband signal BB_T (e.g., including I and Q signals) including information to be transmitted via digital processing circuitry 311, according to various communication schemes. Modem 310 may process received baseband signal BB_R via digital processing circuitry 311, according to various communication schemes.

[0125] For example, modem 310 can process the transmitted or received signal according to a communication scheme (such as OFDM (Orthogonal Frequency Division Multiplexing), OFDMA (Orthogonal Frequency Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), or HSPA+ (High-Speed ​​Packet Access+)). Furthermore, modem 310 can process the baseband signal BB_T or BB_R according to various communication schemes (i.e., various communication schemes that apply techniques for modulating or demodulating the amplitude and frequency of the baseband signal BB_T or BB_R).

[0126] According to some embodiments, the modem 310 can extract the envelope of the baseband signal BB_T through the digital processing circuit 311, and can generate a digital envelope signal D_ENV based on the extracted envelope.

[0127] According to some embodiments, modem 310 can generate an average power signal D_REF based on an average power tracking (APT) table (i.e., an APT table) stored in memory. The APT table stores information about the necessary power supply voltage of power amplifier PA and the average power signal D_REF corresponding to the necessary power supply voltage of power amplifier PA, based on the expected output power (or transmit power) of antenna ANT. Therefore, when the expected output power of antenna ANT is determined, modem 310 can generate the average power signal D_REF using the APT table and can provide the generated average power signal D_REF as a reference voltage signal to power modulator 340.

[0128] The digital processing circuit 311 can perform various processing operations on the baseband signal in the digital domain.

[0129] For example, the digital processing circuit 311 can perform tasks such as generating an average power signal, extracting the envelope, generating a digital envelope signal, peak factor reduction (CFR), shaping function (SF), digital predistortion (DPD), and delay correction.

[0130] CFR can reduce the peak-to-average power ratio (PAPR) of communication signals (e.g., baseband signal BB_T). SF can modify the digital envelope signal D_ENV, thereby improving the efficiency and linearity of the power amplifier PA. DPD can compensate for the distortion of the power amplifier PA in the digital domain so that it can be linearized. In addition, delay correction tasks can correct the delay of the digital envelope signal D_ENV or the baseband signal BB_T.

[0131] The digital processing circuit 311 can output a digital envelope signal D_ENV and a baseband signal BB_T. The digital envelope signal D_ENV can be converted into an analog envelope signal A_ENV by the first DAC 312, and the analog envelope signal A_ENV can be provided to the power modulator 340; the baseband signal BB_T can be converted into a transmit signal TX by the second DAC 313, and the transmit signal TX can be provided to the transmit circuit TXC.

[0132] The digital processing circuit 311 may also include internal components to handle the above operations (i.e., baseband signal processing, envelope extraction, and digital envelope signal generation).

[0133] At least one or more second DACs 313 and ADCs 314 may be provided. The modem 310 can generate a transmit signal TX by performing digital-to-analog conversion on the baseband signal BB_T using the second DAC 313. Furthermore, the modem 310 may be provided with a receive signal RX as an analog signal from the RFIC 320. The modem 310 can perform analog-to-digital conversion on the receive signal RX using the ADC 314 included therein, and can extract the baseband signal BB_R as a digital signal. For example, the receive signal RX can be implemented using a differential signal comprising positive and negative signals.

[0134] RFIC 320 can generate an RF input signal RF_IN by performing frequency up-conversion on the transmitted signal TX, or can generate a received signal RX by performing frequency down-conversion on the RF received signal RF_R. Specifically, RFIC 320 may include a transmitted circuit TXC for frequency up-conversion, a received circuit RXC for frequency down-conversion, a local oscillator LO, a power amplifier PA, and a coupler 323.

[0135] Here, the transmitting circuit TXC may include a first analog baseband filter ABF1, a first mixer MX1, and a driver amplifier 321. For example, the first analog baseband filter ABF1 may include a low-pass filter.

[0136] The first analog baseband filter ABF1 filters the transmit signal TX received from the modem 310 so that it can be provided to the first mixer MX1. That is, the first analog baseband filter ABF1 filters the baseband signal. The first mixer MX1 ​​performs frequency up-conversion using a frequency signal provided by the local oscillator LO to convert the frequency of the transmit signal TX from baseband to a higher frequency band. The transmit signal TX, after such frequency up-conversion, is provided to the driver amplifier 321 as the RF input signal RF_IN, and the driver amplifier 321 primarily amplifies the power of the RF input signal RF_IN so that it can be provided to the power amplifier PA.

[0137] The power amplifier PA can be supplied with a direct current (DC) voltage or a power supply voltage (i.e., a dynamically variable output voltage), and can amplify the power of the RF input signal RF_IN based on the supplied power supply voltage, and can generate an RF output signal RF_OUT. The power amplifier PA can provide the thus generated RF output signal RF_OUT to the duplexer 330 through coupler 323.

[0138] The receiver circuit RXC may include a second analog baseband filter ABF2, a second mixer MX2, and a low-noise amplifier (LNA) 322. For example, the second analog baseband filter ABF2 may include a low-pass filter.

[0139] LNA 322 amplifies the RF received signal RF_R provided from duplexer 330 via coupler 323 so that it can be provided to second mixer MX2. Second mixer MX2 performs frequency down-conversion using a frequency signal provided by local oscillator LO to convert the frequency of the RF received signal RF_R from high-frequency band to baseband. In other words, second mixer MX2 can convert the RF received signal RF_R into a baseband signal using the LO signal.

[0140] The RF received signal RF_R corresponding to the baseband signal can be provided to the second analog baseband filter ABF2 as the received signal RX through the above frequency down-conversion, and the second analog baseband filter ABF2 can filter the received signal RX corresponding to the baseband signal so that it can be provided to the modem 310.

[0141] Coupler 323 can combine amplified signals output from power amplifier PA and provide the combined signals to duplexer 330. Optionally, coupler 323 can distribute signals received from duplexer 330 into multiple signals and provide the multiple signals to LNA 322.

[0142] According to the above embodiments (for example, Figures 1 to 14 , Figure 19The coupler 323 implemented according to the above embodiments may include multiple unit circuits and multiple isolation resistors.

[0143] The power amplifier PA and / or LNA 322 and coupler 323 can be connected via multiple differential pairs, and the coupler 323 and duplexer 330 can be connected via single-ended lines. Coupler 323 provides signal conversion and impedance matching between differential pairs and single-ended lines.

[0144] Coupler 323 can be implemented as N-channel depending on the number of power amplifiers PA and / or LNA 322.

[0145] In one embodiment, the wireless communication device 300 can transmit signals via multiple frequency bands using carrier aggregation (CA). Furthermore, for this purpose, the wireless communication device 300 may include multiple power amplifiers PA for amplifying the power of multiple RF input signals RF_IN, each corresponding to a multiple carrier. However, in embodiments of this disclosure, for ease of description, a description will be given for one power amplifier PA.

[0146] The duplexer 330 can be connected to the antenna ANT and can separate the transmit frequency from the receive frequency. Specifically, the duplexer 330 can separate the RF output signal RF_OUT provided from the power amplifier PA for each frequency band so that it can be provided to the corresponding antenna ANT. Furthermore, the duplexer 330 can provide external signals provided from the antenna ANT to the LNA 322 of the receiver circuit RXC of the RFIC 320. For example, the duplexer 330 may include a front-end module (FEMiD) with an integrated duplexer.

[0147] In one embodiment, the wireless communication device 300 may include a switching structure capable of separating the transmit and receive frequencies instead of the duplexer 330. Alternatively, the wireless communication device 300 may include a structure implemented using the duplexer 330 and a switch for separating the transmit and receive frequencies. However, for ease of description, in embodiments of this disclosure, the description will be given as including the duplexer 330 capable of separating the transmit and receive frequencies in the wireless communication device 300.

[0148] The power modulator 340 can generate a modulated output voltage with dynamically changing levels based on the analog envelope signal A_ENV and the average power signal D_REF, and can provide the output voltage as the power supply voltage for the power amplifier PA.

[0149] Specifically, the power modulator 340 may be provided with an average power signal D_REF and an analog envelope signal A_ENV from the modem 310. The power modulator 340 may be driven in a tracking mode corresponding to either an envelope tracking (ET) mode or an APT mode based on the thus provided average power signal D_REF and analog envelope signal A_ENV, and may generate a dynamically variable output voltage. Furthermore, the power modulator 340 may provide the generated output voltage as a power supply voltage to the power amplifier PA.

[0150] In one embodiment, the power efficiency of the power amplifier PA may decrease when a fixed-level supply voltage is applied to it. Therefore, in order to efficiently manage the power of the power amplifier PA, the power modulator 340 may modulate the input voltage (i.e., the power supplied from the battery) based on at least one of the analog envelope signal A_ENV and the average power signal D_REF, and may provide the modulated voltage as the supply voltage to the power amplifier PA.

[0151] The antenna ANT can send the RF output signal RF_OUT, which is frequency-separated by the duplexer 330, to the outside, or it can provide the RF received signal RF_R received from the outside to the duplexer 330. For example, the antenna ANT may include, but is not limited to, an array antenna.

[0152] For reference, each of the modem 310, RFIC 320, power amplifier PA, duplexer 330, and power modulator 340 may be implemented individually as an IC, chip, or module. Furthermore, the modem 310, RFIC 320, power amplifier PA, duplexer 330, and power modulator 340 may be mounted together on a printed circuit board (PCB). However, embodiments of this disclosure are not limited thereto. In some embodiments, at least a portion of the modem 310, RFIC 320, duplexer 330, and power modulator 340 may be implemented using a single communication chip.

[0153] In addition, Figure 20 The wireless communication device 300 shown can be included in a wireless communication system using cellular networks (such as 5G, LTE), and can also be included in a wireless local area network (WLAN) system or any other wireless communication system. The configuration of the wireless communication device 300 is not limited to... Figure 1 The embodiments shown are different and can be configured differently according to communication protocols or communication schemes.

[0154] The foregoing description illustrates detailed embodiments for carrying out this disclosure. Embodiments in which the design is simply altered or easily modified, as well as the embodiments described above, may be included. Furthermore, techniques easily modified and implemented using the foregoing embodiments may be included in this disclosure. Therefore, it will be apparent to those skilled in the art that various changes and modifications can be made to the foregoing embodiments without departing from the spirit and scope of this disclosure as set forth in the appended claims.

[0155] According to embodiments of this disclosure, an N-way coupler and a chip including the N-way coupler can be provided.

[0156] Although this disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A coupler, comprising: Multiple unit circuits are connected to multiple differential pairs and single-ended lines; as well as Multiple isolation resistors are connected between the multiple differential pairs. Each of the plurality of unit circuits includes: The transformer includes a primary side and a secondary side. The primary side is connected to one of the plurality of differential line pairs, and the secondary side is connected to a single-ended line. The secondary capacitor is connected in parallel to the secondary side.

2. The coupler as claimed in claim 1, wherein, The number of the plurality of difference line pairs is N, and N is a natural number greater than or equal to 2.

3. The coupler as claimed in claim 2, wherein, The number of the multiple unit circuits is N.

4. The coupler according to any one of claims 1 to 3, wherein, Each of the plurality of unit circuits further includes a primary-side capacitor connected in parallel to the primary side.

5. The coupler as claimed in any one of claims 1 to 3, wherein, Each of the plurality of isolation resistors has an impedance of the same magnitude as the differential characteristic impedance, which is defined in the differential line pair.

6. The coupler according to any one of claims 1 to 3, wherein, The plurality of isolation resistors include: Multiple first isolation resistors are connected to the first differential line in the differential line pair; and Multiple second isolation resistors are connected to the second differential line in the differential line pair.

7. The coupler according to any one of claims 1 to 3, wherein, The transformer has a turns ratio of 2:

1.

8. The coupler according to any one of claims 1 to 3, wherein, The transformer is configured such that bias current flows through the center tap.

9. A chip, comprising: Multiple amplifiers are configured to output multiple amplified signals through multiple differential line pairs; as well as A coupler, connected to the plurality of differential line pairs, is configured to combine the plurality of amplified signals and output the combined signal through a single-ended line. The coupler includes: multiple unit circuits connected to the multiple differential pairs and single-ended lines; and multiple isolation resistors connected between the multiple unit circuits and / or between the multiple differential pairs. Each of the plurality of unit circuits includes: The transformer includes a primary side and a secondary side. The primary side is connected to one of the plurality of differential line pairs, and the secondary side is connected to a single-ended line. The secondary capacitor is connected in parallel to the secondary side.

10. The chip as claimed in claim 9, wherein, The number of the plurality of amplifiers is N, and N is a natural number greater than or equal to 2.

11. The chip as claimed in claim 10, wherein, The number of the multiple unit circuits is N.

12. The chip according to any one of claims 9 to 11, wherein, Each of the plurality of unit circuits further includes a primary-side capacitor connected in parallel to the primary side.

13. The chip as claimed in claim 12, wherein, The secondary-side capacitor has a capacitance that is twice the sum of the capacitance of the primary-side capacitor and the parasitic capacitance of one of the plurality of amplifiers.

14. The chip according to any one of claims 9 to 11, wherein, Each of the plurality of isolation resistors has an impedance of the same magnitude as the differential characteristic impedance, which is defined in the differential line pair.

15. The chip according to any one of claims 9 to 11, wherein, The plurality of isolation resistors include: Multiple first isolation resistors are connected to the first differential line in the differential line pair; and Multiple second isolation resistors are connected to the second differential line in the differential line pair.

16. The chip according to any one of claims 9 to 11, wherein, The transformer is configured such that a bias current flows through the center tap, and the bias current is configured to bias the plurality of amplifiers.

17. A chip, comprising: A coupler is connected between multiple differential line pairs and a single-ended line, and is configured to distribute a signal applied through the single-ended line into multiple signals; as well as Multiple amplifiers are connected to the multiple differential line pairs and configured to amplify the multiple signals. The coupler includes: multiple unit circuits connected to the multiple differential pairs and single-ended lines; and multiple isolation resistors connected between the multiple unit circuits and / or between the multiple differential pairs. Each of the plurality of unit circuits includes: The transformer includes a primary side and a secondary side. The primary side is connected to one of the plurality of differential line pairs, and the secondary side is connected to a single-ended line. The secondary capacitor is connected in parallel to the secondary side.

18. The chip of claim 17, wherein, The number of the plurality of amplifiers is N, and N is a natural number greater than or equal to 2.

19. The chip as claimed in claim 17 or 18, wherein, Each of the plurality of unit circuits further includes a primary-side capacitor connected in parallel to the primary side.

20. The chip as claimed in claim 17 or 18, wherein, The plurality of isolation resistors include: Multiple first isolation resistors are connected to the first differential line in the differential line pair; and Multiple second isolation resistors are connected to the second differential line in the differential line pair.

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