Data verification method and device, electronic equipment, storage medium and program product

Abstract

The embodiment of the invention provides a data verification method and device, electronic equipment, a storage medium and a program product. Comprising the steps that state message information currently sent by a sending end is received and stored, a first verification data packet currently sent by the sending end is received, and the first verification data packet comprises transmission data, first verification data and target data; the target data comprises first low-order data of a first preset digit in the first counting data and second low-order data of a second preset digit in the second counting data. And determining target step data according to the first low-order data and stored first counting data, and determining second verification data according to the target step data, the first counting data, the second counting data and the first verification data packet. And if the second verification data is the same as the first verification data, the verification of the state message information is passed. According to the invention, the data processing amount in the verification calculation process is reduced, so that the communication resources occupied in the verification process are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data communication, and in particular to a data verification method and device, an electronic device, a storage medium, and a program product. BACKGROUND

[0002] With the rapid development of communication technology, the sending end and the receiving end need to frequently interact information, and the security and integrity in the data transmission process will directly affect the stable operation of the sending end and the receiving end business.

[0003] To ensure the security and reliability of data transmission between the sending end and the receiving end, a verification mechanism is usually added in the transmission process in related technologies. The sending end combines the data with the counter in the complete state, and the complete state means that the counter is transmitted in the complete number of bits. A check value is generated by an encryption algorithm and sent to the receiving end. The receiving end verifies the transmitted data by comparing the check value.

[0004] However, the above-mentioned method occupies more communication resources. SUMMARY

[0005] The embodiments of the present application provide a data verification method and device, an electronic device, a storage medium, and a program product to reduce the occupied communication resources.

[0006] In a first aspect, the embodiments of the present application provide a data verification method, comprising:

[0007] Receiving the state message information currently sent by the sending end and storing the state message information in a preset storage area, wherein the state message information includes first count data of a state counter and second count data of a message counter;

[0008] Receiving the first check data packet currently sent by the sending end, wherein the first check data packet includes transmission data, first check data, and target data, and the target data includes first low bit data of a first preset number of bits in the first count data and second low bit data of a second preset number of bits in the second count data;

[0009] Determining target step difference data according to the first low bit data and the stored first count data;

[0010] Determining second check data according to the target step difference data, the first count data, the second count data, and the first check data packet;

[0011] If the second check data is the same as the first check data, the verification of the state message information is passed.

[0012] In one possible implementation, determining the target step difference data according to the first low bit data and the stored first count data comprises:

[0013] determining third low bit data of the first count data according to the stored first count data, the third low bit data being the first count data at a third preset bit position;

[0014] determining target step difference data from a preconfigured mapping relationship between low bit data and step difference data according to the first low bit data and the third low bit data.

[0015] In a possible implementation, the second check data is determined according to the target step difference data, the first count data, the second count data and the first check data packet, and the determining the second check data includes:

[0016] obtaining third count data of a state counter and fourth count data of a message counter, the third count data and the fourth count data being count data after a state packet information sent by a sending end last time passes a check;

[0017] determining first target count data of the state counter and second target count data of the message counter according to the third count data, the fourth count data, the target step difference data, the first count data and the second count data;

[0018] determining the second check data according to the first target count data, the second target count data and the first check data packet.

[0019] In a possible implementation, the first target count data of the state counter and the second target count data of the message counter are determined according to the third count data, the fourth count data, the target step difference data, the first count data and the second count data, and the determining the first target count data of the state counter and the second target count data of the message counter includes:

[0020] adding the first count data and the target step difference data to obtain first data after addition;

[0021] if the first data is greater than the third count data, determining the first data as the first target count data of the state counter, setting high bit data of a third preset bit number in the message counter to 0, setting low bit data of a second preset bit number in the message counter to the second low bit data, and obtaining the second target count data of the message counter;

[0022] if the first data is equal to the third count data, determining the first target count data of the state counter and the second target count data of the message counter according to a size relationship between the fourth count data and the second count data.

[0023] In a possible implementation, the first target count data of the state counter and the second target count data of the message counter are determined according to the size relationship between the fourth count data and the second count data, and the determining the first target count data of the state counter and the second target count data of the message counter includes:

[0024] If the fourth count data is less than the second count data, the first count data is determined as the first target count data of the state counter, high bit data of the third preset bit number in the message counter is set as high bit data corresponding to the third preset bit number in the fourth count data, low bit data of the second preset bit number in the message counter is set as the second low bit data, and the second target count data of the message counter is obtained;

[0025] If the fourth count data is greater than or equal to the second count data, the first count data is determined as the first target count data of the state counter, high bit data of the third preset bit number in the message counter is set as data obtained by adding 1 to high bit data corresponding to the third preset bit number in the fourth count data, low bit data of the second preset bit number in the message counter is set as the second low bit data, and the second target count data of the message counter is obtained.

[0026] In a possible implementation, the second check data is determined according to the first target count data, the second target count data and the first check data packet, and the method comprises the following steps.

[0027] The transmission data in the first check data packet, the first target count data and the second target count data are spliced into a data block based on a preset order.

[0028] The data block is calculated by using a preset encryption algorithm to determine the second check data.

[0029] In a second aspect, an embodiment of the present application provides a data check device, which comprises:

[0030] A receiving module is configured to receive a state message information currently sent by a sending end and store the state message information in a preset storage area, wherein the state message information comprises first count data of a state counter and second count data of a message counter.

[0031] The receiving module is further configured to receive a first check data packet currently sent by the sending end, wherein the first check data packet comprises transmission data, first check data and target data, and the target data comprises first low bit data of a first preset bit number in the first count data and second low bit data of a second preset bit number in the second count data.

[0032] A determining module is configured to determine target step difference data according to the first low bit data and the stored first count data.

[0033] The determining module is further configured to determine second check data according to the target step difference data, the first count data, the second count data and the first check data packet.

[0034] A check module is configured to check the state message information as passed if the second check data is the same as the first check data.

[0035] In a third aspect, an electronic device is provided, comprising: a memory, a processor;

[0036] The memory stores computer-executable instructions.

[0037] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the first aspect and / or various possible implementation manners of the first aspect.

[0038] In a fourth aspect, a computer-readable storage medium is provided, and the computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by a processor, the computer-executable instructions are used to implement the first aspect and / or various possible implementation manners of the first aspect.

[0039] In a fifth aspect, a computer program product is provided, and the computer program product comprises a computer program. When the computer program is executed by a processor, the computer program implements the first aspect and / or various possible implementation manners of the first aspect.

[0040] The data verification method and device, electronic device, storage medium, and program product provided in the embodiments of the present application receive a state message information currently sent by a sending end and store the state message information, and receive a first verification data packet currently sent by the sending end. The first verification data packet comprises transmission data, first verification data, and target data. The target data comprises first low bit data of a first preset number of bits in first count data and second low bit data of a second preset number of bits in second count data. Target step difference data is determined according to the first low bit data and the stored first count data. Second verification data is determined according to the target step difference data, the first count data, the second count data, and the first verification data packet. If the second verification data is the same as the first verification data, the verification of the state message information is passed. In the method, only the first low bit data of the first preset number of bits in the first count data of the state counter and the second low bit data of the second preset number of bits in the second count data of the message counter are carried in the target data of the first verification data packet, instead of the transmission of the complete-bit count data, thereby reducing the redundant information transmitted additionally. When the second verification data is calculated based on the first verification data packet, the complete-bit count data does not need to be processed, thereby further reducing the data processing amount in the verification calculation process, and thereby reducing the communication resources occupied in the verification process. BRIEF DESCRIPTION OF DRAWINGS

[0041] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the present application.

[0042] Figure 1 An exemplary application scenario provided in the present application is shown in the following schematic diagram.

[0043] Figure 2 A flowchart of a data verification method provided by an embodiment of the present application is shown in FIG. 1.

[0044] Figure 3 A flowchart of a method for determining second verification data provided by an embodiment of the present application is shown in FIG. 2.

[0045] Figure 4 A flowchart of a method for determining target count data provided by an embodiment of the present application is shown in FIG. 3.

[0046] Figure 5 A structural diagram of a data verification device provided by an embodiment of the present application is shown in FIG. 4.

[0047] Figure 6 A structural diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 5.

[0048] The specific embodiments of the present application have been shown in the above-described drawings, and will be described in more detail hereinafter. These drawings and the written description are not intended to restrict the scope of the present application by any means, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0049] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, the same numbers are used to indicate the same elements in different drawings, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] In the present application, the receiving end and the sending end are illustrated by taking a vehicle (referred to as a vehicle end) and a cloud server (referred to as a cloud end) as examples. With the rapid development of big data, cloud platform and other technologies, the deep integration of these technologies and the battery management system (BMS) has become a core development trend of the next generation of BMS. Under this technical background, the cloud-based BMS needs to perform high-frequency and large-scale data interaction transmission with the vehicle end BMS. These interaction data are directly related to the accuracy of battery operation monitoring, state evaluation and control strategy execution, and therefore the security and integrity of the transmission process are crucial.

[0051] In order to prevent data from being tampered with or forged during transmission, the receiving end usually needs to verify the state message information sent by the sending end, wherein the state message information includes the key information preset by the sending end, as well as the count data of the state counter and the complete number of bits of the message counter.

[0052] In related technologies, when verifying transmitted status message information, the sending end first sends a verification data packet to the receiving end. This verification data packet may include the count data of a full-length status counter T1 (e.g., 16 bits) and the count data of a message counter T2 (e.g., 32 bits). The sending end generates a checksum by combining the transmitted data, the full-length count data of status counter T1, and the full-length count data of message counter T2. The receiving end verifies the status message information by comparing the checksum. The count data of status counter T1 and message counter T2 are represented by binary data 0 and 1.

[0053] However, in the above method, the sending end needs to transmit the count data of the status counter and message counter with complete bit width, i.e., 16 bits + 32 bits, which results in 48 bits of data needing to be transmitted per frame, occupying a large amount of communication bandwidth and thus consuming a lot of communication resources.

[0054] Therefore, to address the issue of excessive communication resource consumption in related technologies, this application proposes a data verification method. Specifically, the receiving end receives and stores a first counting data containing the full number of bits of the status counter and a second counting data containing the full number of bits of the message counter, transmitted by the sending end. It also receives a first verification data packet sent by the sending end. The target data of this first verification data packet only carries the first low-order bits of the first counting data (a first preset number of bits) and the second low-order bits of the second counting data (a second preset number of bits), i.e., partial bit data, rather than the full-number counting data as in related technologies. The receiving end can determine the target step difference data based on the stored full-number first counting data and the received first low-order bits. It then calculates the second verification data by combining the target step difference data, the stored full-number first and second counting data, and the first verification data packet. Finally, verification is completed by comparing the second verification data with the first verification data. This significantly reduces the number of bits transmitted for the counter data while ensuring verification accuracy, thereby reducing communication bandwidth consumption and communication resource consumption.

[0055] To facilitate understanding of the methods in this application, an exemplary application scenario is provided below. Please refer to [link / reference]. Figure 1 , Figure 1 This application provides an exemplary application scenario diagram, which includes a vehicle terminal 01 and a cloud server 02. The vehicle terminal 01 and the cloud server 02 can interact with each other via a wireless network.

[0056] In this scenario, the sending end is vehicle terminal 01, and the receiving end is cloud server 02. Vehicle terminal 01 sends status message information and a verification data packet to cloud server 02. The verification data packet includes first verification data. Cloud server 02 receives and stores the status message information sent by vehicle terminal 01, and determines second verification data based on the received verification data packet and status message information. It then performs a consistency check between the second verification data and the first verification data. If they match, the status message information sent by vehicle terminal 01 is deemed to have passed verification.

[0057] It is understood that this application does not limit the type, function, or number of the sending and receiving ends. The above examples are for illustrative purposes only, and the specific details can be determined based on the actual application.

[0058] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0059] Please see Figure 2 , Figure 2 This is a flowchart illustrating a data verification method provided in an embodiment of this application. The execution entity of this method can be a data verification device. This data verification device can be implemented through a computer program, or through a medium storing the relevant computer program, such as a USB flash drive and / or optical disc, or through a physical device integrating or installing the relevant computer program, such as a chip or electronic device. The electronic device can be a server, server cluster, smart terminal, vehicle terminal, etc. Figure 2 As shown, the method may include:

[0060] S201. Receive the status message information currently sent by the sending end and store the status message information in a preset storage area.

[0061] The receiving end receives a frame of status message information currently sent by the sending end. This status message information may include the first count data of the status counter and the second count data of the message counter, and may also include key information preset by the sending end. The key information may be control information, detection information, and operation information, etc.

[0062] The status counter is used to indicate the synchronization status of the operating cycle of the transmitting electronic control unit (ECU). It increments by a preset data after each operating cycle, for example, +1 after each operating cycle.

[0063] The message counter is used to indicate the message count status sent by the sending ECU. It increments by a preset data for each frame of status message information sent, for example, +1 for each frame of status message information sent.

[0064] The receiving end stores the current status message information sent by the sending end in non-volatile memory (NVM). The NVM storage mechanism can restore the stored historical state even after the ECU loses power, reducing the risk of data loss.

[0065] S202. Receive the first verification data packet currently sent by the sending end. The first verification data packet includes transmission data, first verification data, and target data. The target data includes the first low-order bit data of the first preset number of bits in the first counting data and the second low-order bit data of the second preset number of bits in the second counting data.

[0066] The receiving end receives the first verification data packet currently sent by the sending end.

[0067] The first verification data can be determined based on the transmission data, the first count data of the status counter, and the second count data of the message counter.

[0068] Optionally, the transmitted data, the first counting data, and the second counting data can be concatenated into a data block based on a preset order, and the data block can be encrypted and calculated according to a preset encryption algorithm to determine the first verification data V_mac.

[0069] For example, the preset encryption algorithm can be the 128-bit Advanced Encryption Standard - Cipher-based Message Authentication Code (AES-128-CMAC) algorithm.

[0070] In this algorithm, the initial data block is constructed by concatenating the first counting data, the second counting data, and the transmitted data in that order. This data is then padded to a length that is a multiple of 128 bits. The padded 128-bit data block is encrypted with a key to obtain an intermediate key. This intermediate key is then generated by left-shifting and XORing the padded data block to produce subkeys K1 and K2. The padded data block is then divided into 128-bit groups. Chain encryption is initiated with an all-zero initialization vector. Each group is XORed with the previous encryption result and then encrypted with the key. The final group is XORed with its corresponding subkey, combined with the result of the second-to-last group, and then XORed again. Finally, the result is encrypted with the key to obtain V_mac.

[0071] It is understood that the above encryption algorithms are for illustrative purposes only and do not limit this application.

[0072] The target data includes the first low-order bit data of the first preset number of bits in the first counting data. For example, if the total number of bits in the first counting data is 16, then the first low-order bit data of the first preset number of bits can be the lower 2 bits.

[0073] Accordingly, in the second counting data, assuming the complete number of bits is 32 bits, the second low-order bit data of the second preset number of bits can be the lower 6 bits of data.

[0074] In this embodiment, the transmitting end only needs to transmit 8 bits (2 bits + 6 bits) at a time, which is about 83% less than the 48 bits (16 bits + 32 bits) transmitted at a time in related technologies (1-8 / 48≈83%).

[0075] S203. Determine the target step difference data based on the first low-order data and the stored first count data.

[0076] Based on the stored first count data, the third least significant bit of the first count data is determined at the first preset number of bits, and based on the first least significant bit and the third least significant bit, the target step difference data is determined from the pre-configured mapping relationship between the least significant bit data and the step difference data.

[0077] Since the first count data stored is the count data of the complete number of bits of the state counter, the first preset number of bits is taken, such as the preset lower two bits, to obtain the third lower bit data.

[0078] In this embodiment, the mapping relationship between low-order data and step difference data is pre-configured, as shown in Table 1. In Table 1, the first row represents the first low-order data, assuming it is represented by A, and the first column represents the third low-order data, assuming it is represented by B.

[0079] Table 1

[0080]

[0081] Assuming the first least significant digit is "00" and the third least significant digit is "01", then according to Table 1, the target step difference is "1". Assuming the first least significant digit is "10" and the third least significant digit is "01", then the target step difference is "-1".

[0082] S204. Determine the second verification data based on the target step difference data, the first count data, the second count data, and the first verification data packet.

[0083] According to S201 in this embodiment, the receiving end stores historical count data of the state counter and message counter in the NVM.

[0084] In this step, the receiving end determines the second verification data based on the target step difference data, the first count data, the second count data, the first verification data packet, and the historical count data. The specific implementation process will be described in detail in the following embodiments. Please refer to the following embodiments.

[0085] S205. If the second verification data is the same as the first verification data, then the verification of the status message information is successful.

[0086] The receiving end compares the second verification data with the first verification data. If the second verification data and the first verification data are the same, the verification of the current status message information passes; if the second verification data and the first verification data are different, the verification of the current status message information fails.

[0087] It is understandable that when the sending end is the cloud and the receiving end is the vehicle, the vehicle's data verification method is similar to that in this application, and will not be repeated here to avoid redundancy.

[0088] In the above embodiments of this application, the method receives and stores the status message information currently sent by the sending end, and receives the first verification data packet currently sent by the sending end. The first verification data packet includes transmission data, first verification data, and target data. The target data includes the first low-order data of the first preset number of bits in the first count data and the second low-order data of the second preset number of bits in the second count data. Based on the first low-order data and the stored first count data, target step difference data is determined. Based on the target step difference data, the first count data, the second count data, and the first verification data packet, second verification data is determined. If the second verification data is the same as the first verification data, the verification of the status message information passes. The method of this application only carries the first preset number of bits of low-order data from the first count data of the status counter and the second preset number of bits of low-order data from the second count data of the message counter in the target data of the first verification data packet, instead of transmitting the complete bit count data, thereby reducing redundant information transmitted. Furthermore, when the receiving end calculates the second verification data based on the first verification data packet, since it does not need to process the complete bit count data, the amount of data processing during the verification calculation process is further reduced, thereby reducing the communication resources occupied during the verification process.

[0089] Furthermore, based on the above embodiments, the following embodiments illustrate the process of determining the second verification data based on the target step difference data, the first count data, the second count data, and the first verification data packet.

[0090] Please see Figure 3 , Figure 3 A flowchart illustrating a method for determining second verification data provided in this application embodiment, the method may include the following steps:

[0091] S301. Obtain the third count data of the stored state counter and the fourth count data of the message counter.

[0092] As can be seen from the above embodiments, the receiving end stores historical count data of the state counter and message counter in the NVM. Therefore, the receiving end can obtain the third and fourth count data after the status message information sent by the sending end has been verified.

[0093] The third counting data is the counting data of the status counter after the previous status message information sent by the sending end has been verified, and the fourth counting data is the counting data of the message counter after the previous verification has been passed.

[0094] S302. Based on the third count data, the fourth count data, the target step difference data, the first count data, and the second count data, determine the first target count data of the state counter and the second target count data of the message counter.

[0095] The following will combine Figure 4 For further explanation, please refer to [link / reference]. Figure 4 , Figure 4 A flowchart illustrating a method for determining target count data provided in this application embodiment may include:

[0096] S401. Add the first count data to the target step difference data to obtain the first data after addition.

[0097] Assuming the target step difference data is X, the result of adding X to the first count data is determined as the first data.

[0098] S402. Determine whether the first data is greater than the third count data.

[0099] S403. If the first data is greater than the third count data, then the first data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set to 0, and the low-order data of the second preset bit in the message counter is set to the second low-order data, so as to obtain the second target count data of the message counter.

[0100] For example,

[0101] The first target count data of the state counter: the first data.

[0102] The second target count data of the message counter: the high bit of the third preset bit is 0, and the low bit of the second preset bit is the second low bit.

[0103] S404. If the first data is less than the third count data, an early warning message is output. This early warning message indicates that the first target count data and the second target count data cannot be determined, and the operation has failed.

[0104] S405. If the first data is equal to the third count data, then determine the first target count data of the state counter and the second target count data of the message counter according to the size relationship between the fourth count data and the second count data.

[0105] S406. Determine whether the fourth count data is less than the second count data.

[0106] S407. If the fourth count data is less than the second count data, then the first count data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set as the high-order data corresponding to the third preset bit in the fourth count data, and the low-order data of the second preset bit in the message counter is set as the second low-order data, so as to obtain the second target count data of the message counter.

[0107] For example,

[0108] The first target count data of the state counter: the first count data.

[0109] The second target count data of the message counter: the high-order data of the third preset bit is the high-order data corresponding to the third preset bit in the fourth count data, and the low-order data of the second preset bit is the second low-order data.

[0110] S408. If the fourth count data is greater than or equal to the second count data, then the first count data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set to the data after adding 1 to the high-order data corresponding to the third preset bit in the fourth count data, and the low-order data of the second preset bit in the message counter is set to the second low-order data, so as to obtain the second target count data of the message counter.

[0111] For example,

[0112] The first target count data of the state counter: the first count data.

[0113] The second target count data of the message counter: the high-order data of the third preset bit is the high-order data corresponding to the third preset bit in the fourth count data +1, and the low-order data of the second preset bit is the second low-order data.

[0114] S303. Determine the second verification data based on the first target count data, the second target count data, and the first verification data packet.

[0115] Based on a preset order, the transmission data, the first target count data, and the second target count data in the first verification data packet are concatenated into a data block. The data block is then encrypted using a preset encryption algorithm to determine the second verification data.

[0116] The preset encryption algorithm can be the AES-128-CMAC algorithm. The specific implementation process is similar to the encryption process in the above embodiments. To avoid repetition, it will not be described again.

[0117] It is important to note that the encryption algorithm used at the receiving end must be consistent with the encryption algorithm used at the sending end.

[0118] In the above embodiments of this application, the third count data of the state counter and the fourth count data of the message counter, stored after the last successful verification of the sender's status message, are retrieved and combined with the current target step difference data, the first count data, and the second count data to determine the first target count data of the state counter and the second target count data of the message counter. This allows for the establishment of a continuous correlation link of counting information based on reliable count data that has passed historical verification, effectively correcting potential deviations or interference in single count data transmission and ensuring that the target count data accurately matches the sender's current true counting state. The second verification data is generated based on this accurate target count data and the first verification data packet, improving the reliability of the verification data and the accuracy of the final verification result. This eliminates the need for additional redundant information transmission, reducing communication bandwidth and resource consumption while ensuring verification quality.

[0119] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a data verification device provided in an embodiment of this application, as shown below. Figure 5 As shown,

[0120] The receiving module 501 is used to receive the status message information currently sent by the sending end and store the status message information in a preset storage area. The status message information includes the first count data of the status counter and the second count data of the message counter.

[0121] The receiving module 501 is also used to receive the first verification data packet currently sent by the sending end. The first verification data packet includes transmission data, first verification data and target data. The target data includes the first low-order data of the first preset number of bits in the first counting data and the second low-order data of the second preset number of bits in the second counting data.

[0122] The determination module 502 is used to determine the target step difference data based on the first low-order data and the stored first count data.

[0123] The determining module 502 is also used to determine the second verification data based on the target step difference data, the first count data, the second count data, and the first verification data packet.

[0124] The verification module 503 is used to verify the status message information if the second verification data is the same as the first verification data.

[0125] In one possible implementation, module 502 is specifically used for:

[0126] Based on the stored first count data, determine the third least significant bit of the first count data at the first preset number of bits.

[0127] Based on the first and third low-order data, the target step difference data is determined from the pre-configured mapping relationship between low-order data and step difference data.

[0128] In one possible implementation, module 502 is specifically used for:

[0129] Retrieve the third count data of the stored status counter and the fourth count data of the message counter. The third count data and the fourth count data are the count data after the status message information sent by the sending end has been verified.

[0130] Based on the third count data, the fourth count data, the target step difference data, the first count data, and the second count data, determine the first target count data of the state counter and the second target count data of the message counter.

[0131] The second verification data is determined based on the first target count data, the second target count data, and the first verification data packet.

[0132] In one possible implementation, module 502 is specifically used for:

[0133] Add the first count data to the target step difference data to obtain the summed first data.

[0134] If the first data is greater than the third count data, then the first data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set to 0, and the low-order data of the second preset bit in the message counter is set to the second low-order data, so as to obtain the second target count data of the message counter.

[0135] If the first data is equal to the third count data, then the first target count data of the state counter and the second target count data of the message counter are determined according to the relationship between the fourth count data and the second count data.

[0136] In one possible implementation, module 502 is specifically used for:

[0137] If the fourth count data is less than the second count data, then the first count data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set as the high-order data corresponding to the third preset bit in the fourth count data, and the low-order data of the second preset bit in the message counter is set as the second low-order data, so as to obtain the second target count data of the message counter.

[0138] If the fourth count data is greater than or equal to the second count data, then the first count data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set to the data after adding 1 to the high-order data corresponding to the third preset bit in the fourth count data, and the low-order data of the second preset bit in the message counter is set to the second low-order data, so as to obtain the second target count data of the message counter.

[0139] In one possible implementation, module 502 is specifically used for:

[0140] Based on a preset order, the transmission data, the first target count data, and the second target count data in the first verification data packet are concatenated into a data block.

[0141] The data block is encrypted using a preset encryption algorithm to determine the second verification data.

[0142] The data verification device provided in this embodiment can execute the data verification method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0143] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device provided in this embodiment includes at least one processor 601 and a memory 602. Optionally, the device further includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus 604.

[0144] In a specific implementation, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to perform the above-described method.

[0145] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0146] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0147] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0148] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0149] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0150] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0151] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory, electrically erasable programmable read-only memory, erasable programmable read-only memory, programmable read-only memory, read-only memory, magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0152] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0153] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0154] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0155] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0156] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0157] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0158] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A data verification method, characterized in that, include: Receive the status message information currently sent by the sending end, and store the status message information in a preset storage area. The status message information includes the first count data of the status counter and the second count data of the message counter. Receive the first verification data packet currently sent by the sending end. The first verification data packet includes transmission data, first verification data, and target data. The target data includes the first low-order data of the first preset number of bits in the first counting data and the second low-order data of the second preset number of bits in the second counting data. Based on the first low-order data and the stored first count data, the target step difference data is determined; The second verification data is determined based on the target step difference data, the first count data, the second count data, and the first verification data packet; If the second verification data is the same as the first verification data, then the verification of the status message information is successful.

2. The method according to claim 1, characterized in that, The step of determining the target step difference data based on the first low-order data and the stored first count data includes: Based on the stored first count data, determine the third least significant bit of the first count data at the first preset bit position; Based on the first low-order data and the third low-order data, the target step difference data is determined from the pre-configured mapping relationship between low-order data and step difference data.

3. The method according to claim 1, characterized in that, The step of determining the second verification data based on the target step difference data, the first count data, the second count data, and the first verification data packet includes: Obtain the third count data of the stored status counter and the fourth count data of the message counter, wherein the third count data and the fourth count data are respectively the count data after the status message information sent by the sending end in the last time has been verified. Based on the third count data, the fourth count data, the target step difference data, the first count data, and the second count data, determine the first target count data of the state counter and the second target count data of the message counter; The second verification data is determined based on the first target count data, the second target count data, and the first verification data packet.

4. The method according to claim 3, characterized in that, The step of determining the first target count data of the state counter and the second target count data of the message counter based on the third count data, the fourth count data, the target step difference data, the first count data, and the second count data includes: Add the first count data to the target step difference data to obtain the first data after addition; If the first data is greater than the third count data, then the first data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set to 0, and the low-order data of the second preset bit in the message counter is set to the second low-order data, so as to obtain the second target count data of the message counter. If the first data is equal to the third count data, then the first target count data of the state counter and the second target count data of the message counter are determined according to the size relationship between the fourth count data and the second count data.

5. The method according to claim 4, characterized in that, The step of determining the first target count data of the state counter and the second target count data of the message counter based on the size relationship between the fourth count data and the second count data includes: If the fourth count data is less than the second count data, then the first count data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set as the high-order data corresponding to the third preset bit in the fourth count data, and the low-order data of the second preset bit in the message counter is set as the second low-order data, so as to obtain the second target count data of the message counter. If the fourth count data is greater than or equal to the second count data, then the first count data is determined as the first target count data of the state counter, and the high-order data of the third preset bit in the message counter is set to the data after adding 1 to the high-order data corresponding to the third preset bit in the fourth count data, and the low-order data of the second preset bit in the message counter is set to the second low-order data, so as to obtain the second target count data of the message counter.

6. The method according to claim 5, characterized in that, The step of determining the second verification data based on the first target count data, the second target count data, and the first verification data packet includes: Based on a preset order, the transmitted data, the first target count data, and the second target count data in the first verification data packet are concatenated into a data block; The data block is encrypted using a preset encryption algorithm to determine the second verification data.

7. A data verification device, characterized in that, include: The receiving module is used to receive the status message information currently sent by the sending end and store the status message information in a preset storage area. The status message information includes the first count data of the status counter and the second count data of the message counter. The receiving module is further configured to receive the first verification data packet currently sent by the sending end. The first verification data packet includes transmission data, first verification data, and target data. The target data includes the first low-order data of the first preset number of bits in the first counting data and the second low-order data of the second preset number of bits in the second counting data. The determining module is used to determine the target step difference data based on the first low-order data and the stored first count data; The determining module is further configured to determine the second verification data based on the target step difference data, the first count data, the second count data, and the first verification data packet; The verification module is used to verify the status message information if the second verification data is the same as the first verification data.

8. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-6.

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