Low-power-consumption label detection system and method for wireless communication chip

Abstract

The invention discloses a low-power-consumption tag detection system for a wireless communication chip, and the system comprises a state control module which is provided with a low-frequency timer, and is used for controlling the chip to be switched among three state stages of dormancy, preparation and detection through reading a configuration value of a chip register; the input end of the adaptive ADC acquisition module is connected with the antenna end of the chip and the reference current source, and the adaptive ADC acquisition module is used for comparing the antenna voltage with the reference voltage and outputting a comparison pulse signal; and the input end of the digital logic control module is connected with the output end of the adaptive ADC acquisition module, and the digital logic control module is used for comparing the pulse signals, performing shaping, counting and logic judgment, outputting a quantized value, comparing the quantized value with a preset voltage threshold interval, outputting a label approach judgment result, and judging whether the dormancy stage is interrupted or not based on the label approach judgment result. According to the invention, the environmental noise and the real tag signal can be effectively distinguished, the false triggering rate is obviously reduced, and low-power-consumption operation of the chip is realized.

Description

Technical Field

[0001] This invention relates to wireless communication chips, and more particularly to a low-power tag detection system and method for wireless communication chips. Background Technology

[0002] Existing wireless communication chips typically employ a continuous radio frequency (RF) signal transmission mode to detect tag arrival. Because the RF power amplifier continuously consumes a large current, the chip's average power consumption remains high, severely limiting its application in battery-powered portable devices.

[0003] To reduce power consumption, some existing technologies employ an intermittent operating mode, i.e., periodically waking up for probing. However, this approach still faces the following significant technical problems in practical applications: Environmental noise leads to low detection accuracy and a high false trigger rate. The induced voltage at both ends of the wireless communication chip antenna is highly susceptible to ambient temperature drift, metallic interference, or the proximity of non-tag objects. Traditional detection methods typically rely on fixed voltage thresholds for decision-making, failing to distinguish between voltage fluctuations caused by the environment and signal changes caused by the actual tag's arrival. This results in frequent misjudgments and constant wake-ups of the main control circuit, ultimately increasing unnecessary power consumption. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, which rely on fixed voltage thresholds for judgment and cannot distinguish between voltage fluctuations caused by the environment and signal changes caused by the arrival of actual tags, leading to frequent misjudgments and frequent wake-ups of the main control circuit, thus increasing unnecessary power consumption.

[0005] In a first aspect, the present invention provides a low-power tag detection system for a wireless communication chip, comprising: The state control module is equipped with a low-frequency timer and a crystal clock. The state control module is used to control the chip to switch between three state stages: sleep, preparation, and detection by reading the configuration value of the chip register. The adaptive ADC acquisition module connects the antenna terminal of the chip and the reference current source at its input terminal. It is used to compare the antenna voltage with the reference voltage and output a comparison pulse signal. The digital logic control module has its input end connected to the output end of the adaptive ADC acquisition module. It is used to compare pulse signals for shaping, counting, and logic decision output of quantized values. The quantized values ​​are compared with a preset voltage threshold range to output the tag entry determination result. Based on the tag entry determination result, the sleep phase is interrupted.

[0006] Optionally, the adaptive ADC acquisition module includes a linear voltage regulator circuit, a pulse generation circuit, a resistor divider network, and a voltage comparator.

[0007] Optionally, the resistor divider network consists of a transmission gate array controlled by several bit control signals.

[0008] Optionally, the transmission gate array of the resistor divider network adopts a cascaded structure.

[0009] Optionally, the digital logic control module includes a pulse shaping circuit, a pulse counting circuit, a voltage decision circuit, and upper and lower threshold registers. The pulse shaping circuit is connected to the pulse counting circuit, and the pulse counting circuit is connected to the voltage decision circuit.

[0010] Optionally, a threshold counter is provided in the pulse counting circuit.

[0011] Optionally, the voltage decision circuit includes a detection count counter, a reference voltage adjustment circuit, and a reference voltage register.

[0012] This invention provides a low-power tag detection method for wireless communication chips, comprising the following steps: The state control module has a preset low-frequency timer and crystal clock. The low-frequency timer is used for counting. When the low-frequency timer counts out of a predetermined value, the chip enters the preparation stage from the sleep stage. During the preparation phase, the crystal oscillator clock is used. Once the crystal oscillator clock stabilizes, the testing phase begins. During the detection phase, the antenna voltage is acquired by the adaptive ADC acquisition module and compared with the preset reference voltage to output a comparison pulse signal; The digital logic control module shapes, counts, and makes logical decisions on the comparison pulse signal to output a quantized value. It then compares the quantized value with a preset voltage threshold range to output a tag arrival determination result. Based on the tag arrival determination result, it determines whether to interrupt the sleep phase.

[0013] Optionally, if the quantization value is not within the voltage threshold range, it is determined that the tag has entered the field and an interrupt signal is triggered to end the sleep stage; if the quantization value is within the voltage threshold range, it is determined that the tag has not entered the field and a reset signal is triggered to return to the sleep stage.

[0014] Optionally, the adaptive ADC acquisition circuit acquires the antenna amplitude and uses binary search logic to control the resistor voltage transmission network to adjust the reference voltage bit by bit within a preset number of comparisons.

[0015] The beneficial effects of this invention are: through the dynamic management of the state control module, the voltage comparison of the adaptive ADC acquisition module, and the fine decision of the digital logic control module, this invention can effectively distinguish between environmental noise and real tag signals, significantly reduce the false trigger rate, and achieve low power consumption operation of the chip, thereby improving the reliability and energy efficiency of tag detection in battery-powered portable devices. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] Figure 1 These are system block diagrams from some embodiments; Figure 2 These are detection circuit diagrams of the adaptive ADC acquisition module in some embodiments; Figure 3 These are circuit diagrams of resistor divider networks in some embodiments; Figure 4 This is a schematic diagram comparing voltage threshold ranges in some embodiments; Figure 5 This is a schematic diagram of the three-stage low-power tag detection in some embodiments; Figure 6 This is a flowchart of a low-power tag detection method in some embodiments. Detailed Implementation

[0018] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0019] This invention provides a low-power tag detection system for wireless communication chips, comprising: The state control module is equipped with a low-frequency timer and a crystal clock, which is used to control the chip to switch between three state stages: sleep, ready, and detection by reading the configuration value of the chip register; The adaptive ADC acquisition module connects the antenna terminal of the chip and the reference current source at its input terminal. It is used to compare the antenna voltage with the reference voltage and output a comparison pulse signal. The digital logic control module has its input end connected to the output end of the adaptive ADC acquisition module. It is used to compare pulse signals for shaping, counting, and logic decision output of quantized values. The quantized values ​​are compared with a preset voltage threshold range to output the tag entry determination result. Based on the tag entry determination result, the sleep phase is interrupted.

[0020] The chip operates in several phases: The sleep phase, where the chip operates at extremely low power, is characterized by most internal functions being disabled to conserve energy; the preparation phase, where the chip awakens from sleep and performs necessary initialization and preparatory work, such as starting the internal crystal clock and waiting for it to reach a stable operating state; and the detection phase, where the chip is active and dedicated to tag detection, performing signal acquisition and processing. Antenna voltage is the voltage induced at the chip's antenna when it receives an external electromagnetic signal. Reference voltage is the voltage value used as a benchmark during voltage comparison. The comparison pulse signal is the digital pulse signal generated after comparing the antenna voltage with the reference voltage. The quantized value is the value obtained after the digital logic control module shapes, counts, and performs logical decisions on the comparison pulse signal; this value reflects the specific characteristics of the antenna voltage. The tag entry determination result is the conclusion made based on comparing the quantized value with a preset voltage threshold range, indicating whether a tag has entered the detection range.

[0021] Specifically, the state control module is configured to manage the chip's transitions between three state phases: sleep, ready, and detection. For example, this module can be implemented using a simple sequential logic circuit, driving the state machine transitions via an internal counter or an external trigger signal. In one implementation, the duration of state transitions can be preset to a fixed value; for example, the sleep phase lasts a fixed duration, followed by an automatic transition to the ready phase, and then to the detection phase. This fixed-timing control method may not be able to flexibly respond to changes in the external environment or system requirements in certain application scenarios.

[0022] The input of the adaptive ADC acquisition module is connected to the chip's antenna and a reference current source. The module's function is to compare the antenna voltage with a reference voltage and output a comparison pulse signal.

[0023] The input of the digital logic control module is connected to the output of the adaptive ADC acquisition module. This module's function is to shape, count, and logically determine the received comparison pulse signal, and output a quantized value. Subsequently, this quantized value is compared with a preset voltage threshold range to output a tag arrival determination result. Based on this determination result, the module decides whether to interrupt the chip's sleep phase.

[0024] This system effectively distinguishes between environmental noise and real tag signals through dynamic management of the state control module, voltage comparison of the adaptive ADC acquisition module, and precise decision-making of the digital logic control module. This significantly reduces the false trigger rate and enables low-power operation of the chip, thereby improving the reliability and energy efficiency of tag detection in battery-powered portable devices.

[0025] Furthermore, during the sleep phase, the high-frequency clock tree and RF transmission module are shut down, and only the low-frequency oscillator and low-dropout linear regulator are maintained to keep the standby current below 2μA; during the preparation phase, the 27MHz high-frequency crystal oscillator and bandgap reference circuit are started, and a preset stabilization time window is provided; during the detection phase, the RF carrier transmission is turned on to trigger the ADC acquisition process.

[0026] like Figure 1 As shown, in some embodiments, the adaptive ADC acquisition module includes a linear voltage regulator circuit, a pulse generation circuit, a resistor divider network, and a voltage comparator.

[0027] The linear regulator circuit is a power management circuit whose main function is to convert an unstable input voltage into a stable output DC voltage. Its role is to provide a clean and stable power environment for other circuits within the adaptive ADC acquisition module (such as voltage comparators and resistor divider networks), thereby effectively suppressing power fluctuations and noise interference with antenna voltage sampling, ensuring the accuracy and reliability of the comparison process, and addressing the nonlinearity problem of traditional resistor networks at low voltages. The linear regulator circuit can employ a series regulator structure based on BJTs or MOSFETs, maintaining output voltage stability through a negative feedback mechanism; or it can use a low-dropout linear regulator (LDO), characterized by a small input-output voltage difference, low noise, and high power supply rejection ratio (PSRR).

[0028] A pulse generation circuit is used to convert the output level signal of a voltage comparator into a pulse signal with a specific width and / or frequency. Its function is to digitize the analog comparison result, facilitating subsequent counting, shaping, and logic decision-making by the digital logic control module. The pulse generation circuit can be based on a Schmitt trigger and an RC delay circuit to convert the edge of the comparator output into a pulse of fixed width; or it can utilize a monostable multivibrator to generate a pulse of a preset duration upon receiving a trigger signal from the comparator output.

[0029] like Figure 3 As shown, the resistor divider network consists of multiple resistors connected in series, used to proportionally distribute the input voltage to generate multiple lower reference voltage points. Its function is to provide an adjustable reference voltage, enabling the adaptive ADC acquisition module to dynamically adjust the comparison reference according to the actual range of the antenna voltage or environmental changes, thereby improving the flexibility and accuracy of detection. The resistor divider network is driven by a 10-bit control word, with an auxiliary transmission gate cascaded between every two main transmission gates to suppress sudden changes in on-impedance and nonlinear fluctuations during reference voltage switching.

[0030] A voltage comparator is an electronic circuit used to compare the magnitudes of two input voltages and output a high-level or low-level signal based on the comparison result. Its function is to accurately compare the antenna voltage with a reference voltage provided by a resistor divider network, generating a digital signal indicating the relationship between the two, which serves as the input to a pulse generation circuit. Voltage comparators can employ a differential amplifier-based structure, using high gain to amplify minute differences in the input voltage into a full-swing digital signal; or they can use a hysteresis comparator, introducing positive feedback to prevent output jitter caused by input noise and improve anti-interference capability.

[0031] Through the above technical solution, the linear voltage regulator circuit provides a stable operating voltage for the entire adaptive ADC acquisition module, effectively isolating the influence of power supply noise on signal sampling. The voltage comparator can accurately compare the antenna voltage with the reference voltage provided by the resistor divider network, which allows the reference voltage to be dynamically adjusted according to the actual environment and signal characteristics, making the comparison process more adaptive. The pulse generation circuit converts the analog output of the comparator into a standard digital pulse signal, facilitating subsequent processing by the digital logic control module. These components work together to enable the adaptive ADC acquisition module to more accurately distinguish between the actual tag arrival signal and voltage fluctuations caused by environmental noise, significantly enhancing the system's noise immunity, reducing the risk of misjudgment and false triggering, thereby improving the accuracy and reliability of tag detection and avoiding increased power consumption due to invalid wake-ups.

[0032] Traditional reference voltage generation circuits suffer from nonlinear errors. In on-chip integrated ADC designs, when transmission gate resistor networks are commonly used as voltage dividers, the on-resistance of the transmission gates exhibits nonlinear characteristics with voltage changes, leading to a decrease in the accuracy of the generated reference voltage and consequently affecting the quantization accuracy of weak tag signals.

[0033] In some embodiments, the resistor divider network is composed of a transmission gate array controlled by several bit control signals.

[0034] Specifically, a resistor divider network is a circuit structure used to divide an input voltage in a certain proportion to produce a lower output voltage. Its core function is to provide an adjustable reference voltage for subsequent voltage comparison or sampling. Implementation methods can include, but are not limited to, a series of series resistors, with the voltage division ratio changed by selecting different tap points; or a parallel resistor group, with different resistor branches connected and disconnected via switches. Several control signals are digital or analog signals used to control the state of variable components in the resistor divider network. Their function is to precisely adjust the output voltage of the resistor divider network according to system requirements or external commands. A transmission gate array (GGA) is a switching network composed of multiple transmission gates (usually composed of CMOS transistors). Each transmission gate can act as a controlled switch, turning on or off according to the logic state of the control signal. In a resistor divider network, the GGA's function is to dynamically connect or disconnect different resistor units according to the commands of several control signals, thereby changing the equivalent resistance value and voltage division ratio of the entire voltage divider network, and thus achieving flexible adjustment of the reference voltage.

[0035] By constructing a resistor voltage divider network using a transmission gate array controlled by several control signals, this application effectively solves the problems of insufficient accuracy and inability to adapt to changes in environmental noise when providing a reference voltage in traditional fixed-structure resistor voltage dividers. Specifically, the transmission gate array, as a programmable switching network, can dynamically configure the structure of the resistor voltage divider network according to the instructions of several control signals, thereby achieving fine-grained and adaptive adjustment of the reference voltage. This dynamically adjustable reference voltage enables the adaptive ADC acquisition module to more accurately reflect the signal changes caused by the arrival of actual tags when comparing the antenna voltage with the reference voltage, effectively distinguishing between environmental noise interference and actual tag signals. Therefore, the system can significantly reduce the false judgment rate caused by inaccurate reference voltage, avoid unnecessary chip wake-ups and wasted power consumption, thereby improving the overall performance and reliability of the low-power tag detection system.

[0036] Furthermore, the resistor divider network is driven by a 10-bit control word, with an auxiliary transmission gate cascaded between every two main transmission gates to suppress sudden changes in on-resistance and nonlinear fluctuations during reference voltage switching. The voltage comparator is used to compare the reference voltage output by the resistor divider network with the antenna voltage and outputs the corresponding signal to the pulse generation circuit. If the reference voltage is less than the antenna voltage at this time, the pulse generation circuit will output the corresponding analog signal pulse to the digital logic control module.

[0037] The resistor voltage divider network consists of a series voltage divider link composed of resistors R0 to R9 and a transmission gate selection array composed of TG0 to TG9. Its working principle is as follows: The input voltage Vin is applied to the left side of the series resistor chain. Through the voltage division effect of each resistor, a series of gradient voltage levels are generated at each node of the resistor chain. The signals Vref[0] to Vref[9] at the top come from the output of the reference voltage register in Figure 2. They are connected to the corresponding transmission gate as gating control signals. When one of the control signals is valid, the corresponding transmission gate is turned on, which selects the voltage of the corresponding node on the resistor chain and transmits it to the output terminal Vout. Vout is then output to the input of the voltage comparator and compared with the antenna voltage, thereby realizing the extraction of a specific voltage divider value or the output of the reference voltage.

[0038] In some embodiments, the transmission gate array of the resistor divider network adopts a cascaded structure.

[0039] Specifically, a cascaded structure refers to a configuration in which multiple components or stages are connected in series, with the output of one stage serving as the input to the next. In resistor divider networks, the transmission gate array employs a cascaded structure, meaning that the transmission gates are not simply arranged in parallel for selection, but rather connected in a sequential or hierarchical manner. This connection method allows for finer and more stable control over the voltage division ratio.

[0040] Through the above technical solution, the transmission gate array of the resistor voltage divider network adopts a cascaded structure, enabling multi-stage connections and effectively solving the problem of insufficient voltage division accuracy. This multi-stage connection method allows for more precise and stable adjustment of the reference voltage, reduces transient noise and voltage fluctuations that may be introduced by a single switching operation, and lowers mutual interference between different voltage division paths. Consequently, the stability of the resistor voltage divider network is significantly optimized, allowing the adaptive ADC acquisition module to more accurately compare the antenna voltage with the reference voltage. This directly helps distinguish between voltage fluctuations caused by environmental factors (such as ambient temperature drift, metallic interference, or the proximity of non-tag objects) and signal changes caused by the actual arrival of tags, thereby reducing the risk of system misjudgment, improving the accuracy of tag arrival detection, and avoiding unnecessary power consumption caused by frequent false wake-ups of the main control circuit.

[0041] In some embodiments, the digital logic control module includes a pulse shaping circuit, a pulse counting circuit, a voltage decision circuit, and upper and lower threshold registers. The pulse shaping circuit is connected to the pulse counting circuit, and the pulse counting circuit is connected to the voltage decision circuit.

[0042] Specifically, the pulse shaping circuit uses a high-frequency clock to oversample the pulse output of the analog comparator, converting unstable edge transitions into stable digital levels. This eliminates noise, glitches, and distortion, making the waveform regular and clear, providing a reliable basis for subsequent accurate counting and decision-making. If the count value is greater than or equal to the expected set count value, the current antenna voltage is considered stable. The purpose of counting pulses is to eliminate pulses caused by accidental triggering or noise. The pulse counting circuit can use a synchronous counter, such as a binary counter or BCD counter, to count the input pulses at the rising or falling edge of each clock pulse; alternatively, it can use an asynchronous counter, implementing the counting function through cascaded flip-flops. The voltage decision circuit has built-in hardware-based binary search logic, locking the quantization value within a finite number of clock cycles through a successive approximation algorithm. The voltage decision circuit is used to make logical decisions based on the count value output by the pulse counting circuit and compare it with the preset voltage thresholds stored in the upper and lower threshold registers to determine whether the tag has entered the field. The upper and lower threshold registers are used to store the preset voltage threshold ranges.

[0043] The pulse shaping circuit is connected to the pulse counting circuit, which in turn is connected to the voltage decision circuit. This series connection ensures the sequentiality and integrity of the signal processing flow, enabling the shaped signal to be accurately counted and the counting result to be correctly determined. This connection can be implemented directly through digital signal lines to ensure real-time signal transmission and processing; alternatively, it can be connected through a bus interface or buffer to accommodate the level or timing matching requirements between different modules.

[0044] Through the above technical solution, this application addresses the accuracy and stability issues in signal processing by specifying the circuit composition and connection relationships of the digital logic control module, thereby reducing the false judgment rate. The pulse shaping circuit first shapes the comparison pulse signal, eliminating noise and distortion, ensuring a regular signal waveform, and providing a reliable foundation for subsequent processing. Secondly, the pulse counting circuit is directly connected to the pulse shaping circuit, counting the shaped pulses, quantizing the signal strength, avoiding misreading caused by environmental fluctuations, and providing objective measurement data. Finally, the voltage decision circuit is connected to the pulse counting circuit, performing logical decisions based on the count value, outputting the quantized result, and comparing it with a threshold to achieve accurate tag entry judgment and reduce false wake-ups caused by noise interference. The series connection of the entire module ensures the efficiency and continuity of the signal processing flow, avoids delays or distortions in intermediate links, and improves the system's anti-interference capability and power consumption control.

[0045] In some embodiments, the pulse counting circuit includes a threshold counter.

[0046] Specifically, this threshold counter is a counter that introduces a judgment mechanism during the counting process. Its core function is to filter the received pulse signals, ensuring that only valid pulses that meet specific conditions are counted. Furthermore, the threshold counter can be designed in various implementation methods.

[0047] By introducing a threshold counter into the pulse counting circuit of the digital logic control module, the counting of comparison pulse signals output by the adaptive ADC acquisition module is no longer a simple accumulation of all pulses. Instead, the threshold counter filters the received pulses according to preset threshold conditions. Only pulses that meet these threshold conditions are counted. This filtering mechanism effectively identifies and filters out false or low-intensity pulses caused by environmental noise, interference, or the proximity of non-tag objects. These noise pulses, not meeting the preset threshold conditions, are not counted, thus avoiding interference with the counting of valid signals. By ensuring that the data provided by the pulse counting circuit is more accurate and reliable, the voltage decision circuit can more accurately distinguish between signal changes caused by the arrival of real tags and environmental noise during subsequent logic decisions. This significantly reduces the probability of the system frequently waking up the main control circuit due to noise misjudgments, thereby reducing unnecessary power consumption and improving the overall reliability and low-power performance of the tag detection system.

[0048] In some embodiments, the voltage decision circuit includes a detection count counter, a reference voltage adjustment circuit, and a reference voltage register.

[0049] The detection count counter is used to record the number of times a specific event or operation occurs. In this application, its main function is to record the number of attempts for tag detection or voltage decision, so as to ensure that there is sufficient data accumulation before adjusting the reference voltage or making a final decision, and to avoid misjudgment caused by a single instantaneous environmental fluctuation.

[0050] The reference voltage adjustment circuit can dynamically change its output reference voltage value according to external control signals or internal logic. Its function is to dynamically adjust the reference voltage used for comparison to improve the accuracy and robustness of the decision in response to antenna voltage fluctuations caused by environmental noise (such as temperature drift and metallic interference).

[0051] The reference voltage register is used to store digital values. In this application, it is mainly used to store the reference voltage value (usually in digital form) adjusted by the reference voltage adjustment circuit, so that the adaptively adjusted reference voltage can be continuously used in subsequent voltage comparison processes, ensuring the continuity and accuracy of the decision. This register can be integrated inside the digital logic control module as a general-purpose register or a special-purpose register for temporarily storing the currently valid reference voltage digital value; alternatively, it can also be a specific storage area in an external EEPROM or flash memory to retain the adjusted reference voltage value after power failure for loading upon the next startup.

[0052] Through the above technical solution, the voltage decision circuit of this application no longer relies on a fixed voltage threshold for decision-making. Instead, it achieves dynamic adaptive adjustment of the reference voltage by introducing a detection count counter, a reference voltage adjustment circuit, and a reference voltage register. The detection count counter ensures the stability of the decision and effectively avoids misjudgments caused by single instantaneous environmental fluctuations. The reference voltage adjustment circuit can dynamically adjust the reference voltage based on multiple detection results to adapt to environmental changes, thereby effectively filtering out the influence of environmental noise (such as temperature drift and metal interference) on the antenna voltage. The reference voltage register ensures that the adjusted reference voltage can be continuously and accurately applied to subsequent comparisons, maintaining the continuity and accuracy of the decision. These features work together to enable the digital logic control module to perform more intelligent and robust tag arrival judgment after receiving the comparison pulse signal output by the adaptive ADC acquisition module and processing it through the pulse shaping circuit and pulse counting circuit. This significantly improves the accuracy of tag detection, reduces the false trigger rate and invalid wake-up caused by environmental noise, and thus effectively reduces the average power consumption of the chip while maintaining a low-power sleep mode.

[0053] Furthermore, the detection count counter limits the number of detections to 10. When a detection completion signal arrives, the detection count is incremented by 1. The reference voltage adjustment circuit controls the reference voltage register to increase or decrease by half based on each detection. If the valid detection signal is 0, it indicates that the reference voltage is greater than the antenna voltage, and the reference voltage is reduced to half its original value. If the valid detection signal is 1, it indicates that the reference voltage is less than the antenna voltage, and the reference voltage is increased to half its original value. After 10 comparisons, an accurate reference voltage value is obtained for a 10-bit precision reference voltage; this reference voltage value is the antenna voltage value. After 10 detections, the current reference voltage value (i.e., the antenna voltage value) is compared with the voltage threshold range in the voltage threshold configuration module. The reference voltage register then outputs a 10-bit reference voltage control signal to the resistor divider network in the adaptive ADC acquisition circuit, achieving adaptive adjustment of the reference voltage.

[0054] This invention provides a low-power tag detection method for wireless communication chips, comprising the following steps: The state control module has a preset low-frequency timer and crystal clock. The low-frequency timer is used for counting. When the low-frequency timer counts out of a predetermined value, the chip enters the preparation stage from the sleep stage. During the preparation phase, the crystal oscillator clock is used. Once the crystal oscillator clock stabilizes, the testing phase begins. During the detection phase, the antenna voltage is acquired by the adaptive ADC acquisition module and compared with the preset reference voltage to output a comparison pulse signal; The digital logic control module shapes, counts, and makes logical decisions on the comparison pulse signal to output a quantized value. It compares the quantized value with the voltage threshold range stored in the voltage threshold configuration module to output the tag entry determination result. Based on the tag entry determination result, it determines whether to interrupt the sleep phase.

[0055] The core innovation of this embodiment lies in combining phased state control with adaptive ADC sampling and digital signal processing to dynamically adjust the detection process to adapt to environmental changes, thereby effectively distinguishing environmental noise from genuine tag signals. Specifically, the state control module precisely controls the chip's state transition timing by pre-setting a low-frequency timer. When the count overflows a predetermined value, it triggers a switch from the sleep phase to the preparation phase, avoiding continuous power consumption. During the preparation phase, the crystal oscillator clock is started and stabilized before entering the detection phase, ensuring the reliability of the clock signal and providing an accurate time reference for subsequent detection. In the detection phase, the adaptive ADC acquisition module acquires the antenna voltage in real time and dynamically compares it with a reference voltage, outputting a comparison pulse signal. This module can adaptively adjust the reference voltage according to environmental conditions, effectively dealing with fluctuations caused by temperature drift and metal interference. The digital logic control module further performs shaping operations on the comparison pulse signal to eliminate instantaneous noise interference, quantizes the signal strength characteristics through counting operations, and outputs a quantized value based on logical decisions. This quantized value is intelligently compared with the voltage threshold range stored in the voltage threshold configuration module, outputting a reliable tag arrival determination result. The sleep phase is interrupted only when a genuine tag is confirmed to have arrived, avoiding false wake-ups caused by environmental noise.

[0056] Through the above technical solution, this application achieves accurate differentiation between environmental noise and real tag signals, significantly reducing the false trigger rate. Because the state control module precisely manages the chip's operating phases, activating high-power modules only when necessary, and the collaborative action of the adaptive ADC acquisition module and digital logic control module ensures the robustness of the detection process, thereby significantly reducing average power consumption while maintaining high detection accuracy. Overall, this method effectively solves the problems of low detection accuracy and high false trigger rate caused by environmental noise interference, while achieving the goal of low-power operation, significantly improving the applicability and energy efficiency of wireless communication chips in battery-powered portable devices.

[0057] In some embodiments, if the quantization value is not within the voltage threshold range, it is determined that the tag has entered the field and an interrupt signal is triggered to end the sleep stage; if the quantization value is within the voltage threshold range, it is determined that the tag has not entered the field and a reset signal is triggered to return to the sleep stage.

[0058] like Figure 4 As shown, the voltage threshold range includes an upper threshold and a lower threshold (the upper threshold corresponds to the upper threshold in the figure, and the lower threshold corresponds to the lower threshold in the figure). When the quantized value of the induced voltage (corresponding to the "antenna voltage" in the figure) exceeds the preset voltage threshold range, it indicates that the signal strength or characteristics received by the antenna has changed significantly, which is usually caused by the tag entering the detection range. In specific implementation, the voltage decision circuit inside the digital logic control module can be configured to trigger tag entry determination when the received quantized value is higher than the preset upper threshold or lower than the preset lower threshold.

[0059] Furthermore, the technical feature of "triggering an interrupt signal to end the sleep phase" is used to immediately send an interrupt signal to the system's main control unit after confirming the tag's arrival, forcing the chip to switch from a low-power sleep phase to an operating phase, thereby quickly responding to tag events. This prevents the system from missing important events while in sleep mode, ensuring real-time performance.

[0060] Meanwhile, the technical feature of "determining that the tag has not entered the field if the quantized value is within the voltage threshold range" aims to determine that no tag has entered the field when the quantized value is within the preset voltage threshold range. This helps to distinguish between minor fluctuations caused by environmental noise or interference and real tag signals, avoiding misjudgments and thus reducing unnecessary system wake-ups.

[0061] Building upon this, the technical feature of "triggering a reset signal to return to the sleep phase" ensures that the system can promptly and effectively return to a low-power sleep phase after determining that no tag has entered the field. This is crucial for maintaining the overall low-power operation of the chip, avoiding prolonged high-power states due to misjudgments or uncertainties. For example, when the tag absence determination logic outputs a valid signal, this signal can be directly connected to the reset input or sleep enable input of the state control module. Upon receiving this signal, the state control module immediately terminates the current detection or preparation phase and restarts the sleep phase timer, causing the chip to enter a low-power state. Furthermore, after determining that no tag has entered the field, the digital logic control module can also notify the state control module to perform a sleep recovery operation by sending specific control commands or setting the status register. The control logic of the state control module will respond to this command, shutting down unnecessary clock and power domains and entering a preset sleep mode.

[0062] Through the above technical solution, this application introduces a more refined bidirectional decision mechanism into the decision logic based on the comparison of quantized values ​​and voltage threshold ranges. Specifically, when the quantized value output by the digital logic control module exceeds the preset voltage threshold range, the system can accurately determine that a tag has entered the field and immediately trigger an interrupt signal, thereby quickly ending the sleep phase and ensuring a rapid response to real tag events, avoiding missing tags due to delayed wake-up. Conversely, when the quantized value is within the preset voltage threshold range, the system determines that a tag has not entered the field and triggers a reset signal, allowing the chip to promptly return to the low-power sleep phase. This mechanism effectively distinguishes between real tag signals and voltage fluctuations caused by environmental noise or interference, significantly reducing the false judgment rate. Therefore, the system can avoid unnecessary frequent wake-ups of the main control circuit, thereby significantly reducing ineffective power consumption and improving the battery life and overall energy efficiency of the wireless communication chip in battery-powered portable devices.

[0063] High-precision sampling and low power consumption are difficult to achieve simultaneously. To improve detection accuracy, some existing solutions introduce high-speed ADCs to sample antenna signals. However, high-speed ADCs require high-frequency clock support and have high static power consumption, making it difficult to meet the stringent requirements of microamp-level standby current in battery-powered scenarios when continuously running the ADC for monitoring.

[0064] In some implementations, the adaptive ADC acquisition circuit acquires the antenna amplitude and uses binary search logic to control the resistor-based voltage transmission network to adjust the reference voltage bit by bit within a preset number of comparisons.

[0065] Specifically, "adaptive ADC acquisition circuit acquiring antenna amplitude" refers to the adaptive ADC acquisition circuit acquiring signal strength information sensed by the antenna in real time through the chip's antenna terminal connected to its input terminal. Antenna amplitude is typically expressed as the magnitude of the antenna voltage, which directly reflects the signal received by the wireless communication chip (such as tag signals). Acquiring the antenna amplitude is the basis for subsequent comparisons and adjustments, providing the system with signal strength data for the current environment. Possible implementation methods include: 1. The sample-and-hold circuit inside the adaptive ADC acquisition circuit samples the antenna voltage instantaneously and converts it into a digital quantity to represent the antenna amplitude.

[0066] 2. The adaptive ADC acquisition circuit captures the peak value of the antenna voltage through a peak detection circuit and quantizes it as the antenna amplitude.

[0067] "Using binary search logic" refers to a highly efficient search algorithm employed during reference voltage adjustment. Binary search logic rapidly approximates the target reference voltage value by continuously halving the search range. For example, if the target reference voltage is between 0V and 1V, binary search will first attempt 0.5V, then determine whether the target is between 0V and 0.5V or between 0.5V and 1V based on the comparison result. It then continues to perform binary search within the narrowed range until it finds the closest or most suitable reference voltage. This method significantly improves the efficiency and speed of reference voltage adjustment. Possible implementations include: 1. A binary search algorithm unit is integrated into the digital logic control module. This unit iteratively generates a new reference voltage control word based on the comparison results of the adaptive ADC acquisition module.

[0068] 2. The binary search logic is implemented through a finite state machine (FSM). The FSM controls the digital input of the resistor divider network according to the output state of the comparator, gradually converging to a suitable reference voltage.

[0069] "Controlling within a preset number of comparisons" refers to setting a maximum number of iterations for the reference voltage adjustment process. This means that the binary search logic will not perform infinite comparisons and adjustments, but will stop after reaching the preset number of comparisons and adopt the current optimal reference voltage value. This aims to ensure that the reference voltage adjustment process is completed within a finite time, avoiding prolonged search due to environmental fluctuations or signal instability, thereby effectively controlling the system's power consumption and response time. Possible implementation methods include: 1. Set a counter in the digital logic control module. The counter increments by one each time the reference voltage is adjusted. When the counter reaches the preset value, the adjustment process stops.

[0070] 2. Limit the adjustment time using a hardware timer or software timer. Once the preset time is reached, lock the current reference voltage value.

[0071] "Resistor voltage divider network step-by-step adjustment of reference voltage" refers to using a network of multiple resistors to change the output reference voltage value in discrete steps under the action of a digital control signal. This adjustment method allows the system to accurately generate a series of reference voltages as needed.

[0072] Through the above technical solution, the adaptive ADC acquisition circuit can acquire antenna amplitude in real time and efficiently adjust the reference voltage bit by bit within a preset number of comparisons using a resistor voltage divider network. This method enables the reference voltage to quickly and accurately track changes in antenna voltage, ensuring comparison accuracy even in complex environments such as ambient noise, temperature drift, or metallic interference. Compared to traditional fixed threshold or simple linear adjustment, the binary search logic significantly reduces the number of iterations required to find the optimal reference voltage, thereby reducing power consumption during the adjustment process. Simultaneously, completing the adjustment within the preset number of comparisons ensures timely system response and avoids ineffective long-term searches. This refined and efficient reference voltage adjustment mechanism greatly improves the accuracy and anti-interference capability of tag detection, effectively reduces the false trigger rate, thereby reducing unnecessary chip wake-up and power consumption, further optimizing the low-power performance of the wireless communication chip. The use of binary successive approximation technology to replace continuous sampling significantly shortens the ADC turn-on time; and combined with an anti-interference pulse counting circuit and a cascaded transmission gate compensation structure, it effectively suppresses errors caused by environmental noise and device nonlinearity, thus achieving highly robust, non-intrusive tag arrival detection at ultra-low power consumption.

[0073] like Figure 5 As shown, the first stage is the sleep stage. In this stage, only an ultra-low power low-dropout linear regulator (LDO) and an ultra-low power ring oscillator are working in the wireless communication chip. The duration of this stage is configurable, with a default value of 500ms, and the operating current is on the order of μA. The second stage is the preparation stage. Based on the first stage, the crystal oscillator is enabled, allowing it to start oscillating. After the crystal clock stabilizes, the register for detecting the card is configured. At the same time, the low-power bias circuit and ADC operate normally. The duration of this stage is configurable, with a default value of 200us, and the operating current is close to the order of mA. The third stage is the card picking stage. Based on the second stage, the radio frequency signal transmission is enabled, using the lowest power carrier transmission. The ADC automatically detects the antenna amplitude and compares it to determine if a card has entered the field. If a card has entered the field, an interrupt is generated, exiting the low-power mode and entering normal card searching. If no card has entered the field, the cycle of detection returns to the first stage. The duration of this stage is configurable, with a default value of 50us, and the operating current is on the order of mA.

[0074] Further, Figure 6 shows the overall flowchart of the Low Power Card Picking Mode (LPCD). Before entering the LPCD, the external microcontroller first configures the relevant registers of the wireless communication chip via the bus, such as the lengths of the three stages T1, T2, and T3, the transmit carrier power, and the upper and lower threshold voltages. Finally, it enters the LPCD by writing to the control register. After entering the LPCD, it first enters the first stage T1. The low-frequency clock is responsible for storing the register values ​​in the wireless communication chip and counting the duration of the stage. When the count value is full, it enters the second stage. In the second stage, the low power state machine turns on the high-frequency clock. During the duration of T2, the high-frequency clock gradually starts oscillating. When the count value is full, it enters the third stage. In the third stage, there is a certain delay before counting the number of output pulses of the voltage comparator to reduce the impact of noise. After 10 antenna voltage detections, the antenna voltage magnitude is judged. If the condition of a card entering the field is met, an interrupt is generated to notify the MCU, exiting the low power card picking mode and performing card search in normal mode to obtain the corresponding unique identifier (UID). If the condition of no card entering the field is met, it returns to the first stage and repeats the low power card picking process.

[0075] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A low-power tag detection system for wireless communication chips, characterized in that, include: The state control module is equipped with a low-frequency timer and a crystal clock. The state control module is used to control the chip to switch between three state stages: sleep, preparation, and detection by reading the configuration value of the chip register. The adaptive ADC acquisition module connects the antenna terminal of the chip and the reference current source at its input terminal. It is used to compare the antenna voltage with the reference voltage and output a comparison pulse signal. The digital logic control module has its input end connected to the output end of the adaptive ADC acquisition module. It is used to compare pulse signals for shaping, counting, and logic decision output of quantized values. The quantized values ​​are compared with a preset voltage threshold range to output the tag entry determination result. Based on the tag entry determination result, the sleep phase is interrupted.

2. The low-power tag detection system for wireless communication chips according to claim 1, characterized in that, The adaptive ADC acquisition module includes a linear voltage regulator circuit, a pulse generation circuit, a resistor divider network, and a voltage comparator.

3. The low-power tag detection system for wireless communication chips according to claim 2, characterized in that, The resistor divider network consists of a transmission gate array controlled by several control signals.

4. The low-power tag detection system for wireless communication chips according to claim 3, characterized in that, The transmission gate array of the resistor divider network adopts a cascaded structure.

5. The low-power tag detection system for wireless communication chips according to claim 1, characterized in that, The digital logic control module includes a pulse shaping circuit, a pulse counting circuit, a voltage decision circuit, and upper and lower threshold registers. The pulse shaping circuit is connected to the pulse counting circuit, and the pulse counting circuit is connected to the voltage decision circuit.

6. The low-power tag detection system for wireless communication chips according to claim 5, characterized in that, The pulse counting circuit includes a threshold counter.

7. The low-power tag detection system for wireless communication chips according to claim 5, characterized in that, The voltage decision circuit includes a detection count counter, a reference voltage adjustment circuit, and a reference voltage register.

8. A method for detecting low-power tags for wireless communication chips, used in the low-power tag detection system for wireless communication chips as described in any one of claims 1-7, characterized in that, Includes the following steps: The state control module has a preset low-frequency timer and crystal clock. The low-frequency timer is used for counting. When the low-frequency timer counts out of a predetermined value, the chip enters the preparation stage from the sleep stage. The crystal oscillator clock is started during the preparation phase. After the crystal oscillator clock stabilizes, the testing phase begins. During the detection phase, the antenna voltage is acquired by the adaptive ADC acquisition module and compared with the preset reference voltage to output a comparison pulse signal; The digital logic control module shapes, counts, and makes logical decisions on the comparison pulse signal to output a quantized value. It then compares the quantized value with a preset voltage threshold range to output a tag arrival determination result. Based on the tag arrival determination result, it determines whether to interrupt the sleep phase.

9. The low-power tag detection method for wireless communication chips according to claim 8, characterized in that, If the quantization value is not within the voltage threshold range, it is determined that the tag has entered the field and an interrupt signal is triggered to end the sleep stage. If the quantization value is within the voltage threshold range, it is determined that the tag has not entered the field and a reset signal is triggered to return to the sleep stage.

10. The low-power tag detection method for wireless communication chips according to claim 8, characterized in that, The adaptive ADC acquisition circuit acquires the antenna amplitude and uses binary search logic to control the resistor voltage transmission network to adjust the reference voltage bit by bit within a preset number of comparisons.

Images