Device preparation method based on double-pattern photoetching process, device and chip

Abstract

The invention belongs to the technical field of power devices, and provides a device preparation method, a device and a chip based on a double-pattern photoetching process, and the preparation method comprises the steps: forming a P-type shielding region at the bottom of a groove of an N-type drift region, and arranging a corner dielectric layer at the corner region of the groove of the N-type drift region, thereby reducing the high electric field of a central oxide layer at the bottom of a grid electrode, and improving the reliability of the device; the field intensity extends downwards, the breakdown voltage of the device is improved, the contact area of the drift region and the grid electrode is reduced, the Qg of the device is reduced, the width of the bottom P-type shielding region is reduced, the current path is wider, and the on-resistance is reduced. A plurality of P-type floating ring regions with the same width are arranged in the central region of an N-type drift region and are sequentially arranged from a P-type shielding region to a drain layer, so that the distribution range of a high electric field in the drift region is expanded, the area of a space charge region is increased, the saturation current of the device is effectively reduced, the endurance capability of the device under a short-circuit test is improved, and the reliability of the device is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power devices, and particularly relates to a device preparation method based on a double-pattern photolithography process, a device, and a chip. BACKGROUND

[0002] A silicon carbide (SiC) trench gate metal oxide semiconductor field effect transistor (TG-MOSFET) has a very high gate density and is not limited by the parasitic JFET channel in a planar SiC MOSFET, thus reducing the contribution of channel resistance to the total on-resistance, due to its excellent material properties, including a wide band gap, a high critical electric field, and good thermal conductivity. Compared with a conventional planar SiC MOSFET, a TG-MOSFET can significantly reduce the specific on-resistance by accommodating more channels on a given chip area and completely eliminating the JFET effect.

[0003] However, in the current SiC trench MOSFET device, the breakdown voltage of the device is limited by the collapse of the gate oxide layer, and during reverse operation, it may not pass the reliability test, affecting the application scenarios of the device. SUMMARY

[0004] To solve the above technical problems, the embodiments of the application provide a device preparation method based on a double-pattern photolithography process, a device, and a chip, which aims to improve the endurance of the SiC trench MOSFET device and improve the reliability of the device.

[0005] The first aspect of the embodiments of the application provides a device preparation method based on a double-pattern photolithography process, which comprises: providing a silicon carbide substrate, sequentially forming a buffer layer and an N-type drift region on the front surface of the silicon carbide substrate, and forming a plurality of P-type floating ring regions with the same width in the central region of the N-type drift region through repeated oxide deposition, etching, ion implantation, and epitaxy; continuing to epitaxial the N-type drift region, and forming a current spreading material layer, a P-type doped layer, an N-type heavily doped layer, and a P-type heavily doped region through N-type ion implantation and P-type ion implantation; the N-type heavily doped layer is provided with the P-type heavily doped region on both sides; the doping concentration of the N-type drift region increases in the direction from the silicon carbide substrate to the current spreading material layer; etching along a partial region of the N-type heavily doped layer to form an ion implantation trench reaching the N-type drift region; the ion implantation trench divides the current spreading material layer into a first current spreading layer and a second current spreading layer, divides the P-type doped layer into a first P-type well region and a second P-type well region, and divides the N-type heavily doped layer into a first N-type heavily doped region and a second N-type heavily doped region; depositing a first sacrificial dielectric material to form a first sacrificial dielectric layer in the ion implantation trench, forming a first photoresist mask on the first sacrificial dielectric layer, and then selectively etching the first sacrificial dielectric layer, and then removing the first photoresist mask and etching again to form a first corner protection layer and a second corner protection layer on both sides of the bottom of the ion implantation trench; forming a protection layer along the inner surface of the ion implantation trench, forming a second photoresist mask on the protection layer, and etching the first region exposed by the protection layer under the protection of the second photoresist mask; after removing the second photoresist mask, implanting P-type doped ions along the first region, and then removing the protection layer, the first corner protection layer, and the second corner protection layer, and then annealing to form a P-type shielding region at the bottom of the ion implantation trench; the spacing distance between the P-type floating ring region and the P-type shielding region is greater than the thickness of the P-type shielding region; depositing a second sacrificial dielectric material to form a second sacrificial dielectric layer, forming a third photoresist mask on the second sacrificial dielectric layer, and then selectively etching the second sacrificial dielectric layer, and then removing the third photoresist mask and etching again to form a gate trench, and then forming a first corner dielectric layer and a second corner dielectric layer on both sides of the bottom of the gate trench; forming a concave gate dielectric layer along the inner surface of the gate trench, forming a gate layer in the recess of the gate dielectric layer, and forming a field oxide layer on the gate layer; wherein the gate dielectric layer and the field oxide layer form a closed structure enclosing the gate layer; etching the field oxide layer, then forming a source layer in contact with both sides of the gate dielectric layer, the P-type well region, the N-type heavily doped region, the P-type heavily doped region, and the field oxide layer, and then forming a drain layer on the back of the silicon carbide substrate.

[0006] In some embodiments, after removing the second photoresist mask, implanting P-type doped ions along the first region, and then removing the protection layer, the first corner protection layer, and the second corner protection layer, and then annealing to form a P-type shielding region, includes: after removing the second photoresist mask, implanting P-type doped ions from the first region at the bottom of the ion implantation trench to the N-type drift region to form a P-type shielding region, with the first corner protection layer and the second corner protection layer as masks.

[0007] In some embodiments, the method further comprises: implanting P-type doping ions into the N-type drift region at the first region at the bottom of the trench to form a P-type shielding region by taking the first corner protection layer and the second corner protection layer as a mask, including: implanting P-type doping ions into the N-type drift region at the first region at the bottom of the trench for multiple times by taking the first corner protection layer and the second corner protection layer as a mask, so that the doping concentration of the P-type shielding region is trapezoidal.

[0008] In some embodiments, the interval distance between adjacent P-type floating ring regions in the plurality of P-type floating ring regions gradually decreases from the drain layer to the source layer.

[0009] In some embodiments, the interval distance between adjacent P-type floating ring regions in the plurality of P-type floating ring regions is the same.

[0010] In some embodiments, the doping concentration of adjacent P-type floating ring regions in the plurality of P-type floating ring regions gradually increases from the drain layer to the source layer.

[0011] In some embodiments, the interface between the gate layer and the field oxide layer is arc-shaped.

[0012] In some embodiments, the contact surface between the gate layer and the gate dielectric layer is step-shaped; and the top step of the gate dielectric layer is formed on the upper surface of the N-type heavily doped region.

[0013] The second aspect of the embodiments of the present application further provides a silicon carbide power device, which is prepared by the device preparation method of any one of the above embodiments.

[0014] The third aspect of the embodiments of the present application further provides a chip comprising a silicon carbide power device prepared by the device preparation method of any one of the above embodiments.

[0015] The beneficial effects of this application's embodiments are as follows: By forming a P-type shielding region at the bottom of the groove in the N-type drift region and setting corner protection layers (i.e., a first corner protection layer and a second corner protection layer) in the corner region of the groove in the N-type drift region, the high electric field of the central oxide layer at the bottom of the gate is reduced, causing the field strength to extend downward, improving the breakdown voltage of the device, and also helping to reduce the contact area between the drift region and the gate, reducing the gate charge Qg of the device, and reducing the width of the bottom P-type shielding region (the P-type shielding region needs to completely cover the bottom of the gate dielectric layer, therefore, setting the first corner protection layer and the second corner protection layer results in a smaller width of the P-type shielding region than not setting the first corner protection layer and the second corner protection layer), making the current path wider, reducing the on-resistance, and multiple P-type floating ring regions of the same width are arranged sequentially along the P-type shielding region towards the drain layer, which can expand the distribution range of the high electric field in the drift region, increase the area of ​​the space charge region, effectively reduce the saturation current of the device, improve the device's withstand capability under short-circuit testing, and improve the reliability of the device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the silicon carbide power device provided in the embodiments of this application; Figure 2 This is a schematic flowchart of a preparation method provided in an embodiment of this application; Figure 3 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application; Figure 4 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application; Figure 5 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application; Figure 6 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application; Figure 7 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application; Figure 8 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application; Figure 9 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application; Figure 10 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application; Figure 11 This is a schematic diagram of a portion of the preparation process of the preparation method provided in the embodiments of this application. Detailed Implementation

[0017] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0018] To address the aforementioned technical problems, embodiments of this application provide a device fabrication method based on a dual-pattern photolithography process. This device fabrication method is used to fabricate devices such as… Figure 1 The silicon carbide power device shown is described in the following document. Figure 2 As shown, the device fabrication method in this embodiment includes steps S100 to S900.

[0019] In step S100, a silicon carbide substrate 210 is provided, and a buffer layer 220 and an N-type drift region 230 are sequentially formed on the front side of the silicon carbide substrate 210. Multiple P-type floating ring regions 260 with the same width are formed in the central region of the N-type drift region 230 through repeated oxide deposition, etching, ion implantation and epitaxy.

[0020] In this embodiment, a buffer layer 220 and an N-type drift region 230 can be sequentially formed on a silicon carbide substrate 210 using an epitaxial process. The doping concentration of the N-type drift region 230 is greater than that of the buffer layer 220. Figure 3 The schematic structure (a) is shown in the figure. A deposited oxide hard film 240, as... Figure 3 The schematic structure (b) is shown in the diagram. Photoresist 251 is formed on the oxide hard film 20, as shown in the diagram. Figure 3 As shown in the schematic structure (c), the oxide hard film 240 is then etched according to the pattern of the photoresist 251, as follows. Figure 3 The schematic structure (d) is shown in the figure.

[0021] Combination Figure 4 After removing photoresist 251, as Figure 4 The schematic structure (a) is shown in the diagram. Under the protection of the oxide hard film 240, implanting P-type dopant ions can form a P-type floating ring region 260, as shown in the diagram. Figure 4 The schematic structure (b) is shown in the diagram. Then, the oxide hard film 240 is removed, as shown in the diagram. Figure 4 The schematic structure (c) is shown in the diagram. An epitaxial N-type drift region 230 is formed, which covers a P-type floating ring region 260. Then, through repeated oxide deposition, etching, ion implantation, and epitaxy, multiple P-type floating ring regions 260 of equal width are formed in the central region of the N-type drift region 230, as shown in the diagram. Figure 4 The schematic structure (d) is shown in the figure.

[0022] In this embodiment, since the widths of the multiple P-type floating ring regions are the same, the same mask can be used for etching when forming multiple P-type floating ring regions, which reduces the number of mask alignments and improves the device fabrication efficiency and accuracy.

[0023] In step S200, the N-type drift region 230 is further epitaxially extended, and a current-extending material layer 310, a P-type doped layer 320, an N-type heavily doped layer 340, and a P-type heavily doped region (first P-type heavily doped region 331 and second P-type heavily doped region 332) are formed by N-type ion implantation and P-type ion implantation.

[0024] In this embodiment, the N-type drift region 230 is further extended, such as... Figure 5 The schematic structure (a) is shown in the diagram. A current-spreading material layer 310, a P-type doped layer 320, an N-type heavily doped layer 340, and a P-type heavily doped region are formed by N-type ion implantation and P-type ion implantation. The P-type heavily doped region includes a first P-type heavily doped region 331 and a second P-type heavily doped region 332 respectively disposed on both sides of the N-type heavily doped layer 340, as shown in the diagram. Figure 5 The schematic structure (b) is shown in the figure. In this structure, the doping concentration of the N-type drift region increases sequentially from the silicon carbide substrate toward the current spreading material layer.

[0025] In this embodiment, by setting a higher doping concentration in the N-type drift region near the bottom of the gate dielectric layer, the carrier density in the N-type drift region can be increased, directly reducing the specific on-resistance of the device and improving the switching efficiency of the device. Furthermore, by setting a P-type floating ring region to share the electric field borne by the gate dielectric layer, the electric field shielding effect at the bottom of the gate dielectric layer can be enhanced, reducing the risk of gate oxide breakdown.

[0026] In step S300, etching is performed along a portion of the N-type heavily doped layer 340 to form an ion implantation trench extending into the N-type drift region 230.

[0027] In this embodiment, ion implantation trenches are formed by photolithography under the protection of the first photoresist 252. The ion implantation trenches divide the current spreading material layer 310 into a first current spreading layer 311 and a second current spreading layer 312, divide the P-type doped layer 320 into a first P-type well region 321 and a second P-type well region 322, and divide the N-type heavily doped layer 340 into a first N-type heavily doped region 341 and a second N-type heavily doped region 342, as shown below. Figure 5 The schematic structure (c) is shown in the figure. The first P-type well region 321 and the second P-type well region 322 are L-shaped structures. The first N-type heavily doped region 341 and the first P-type heavily doped region 331 are located on the horizontal part of the first P-type well region 321, and the second N-type heavily doped region 342 and the second P-type heavily doped region 332 are located on the horizontal part of the second P-type well region 322.

[0028] In step S400, a first sacrificial dielectric layer 360 is formed by depositing a first sacrificial dielectric material in the ion implantation trench, such as... Figure 5 The schematic structure (d) is shown in the figure. After forming the first photomask 253 on the first sacrificial dielectric layer 360, the first sacrificial dielectric layer 360 is selectively etched, and then the first photomask 253 is removed and etched again to form a first corner protection layer 361 and a second corner protection layer 362 on both sides of the bottom of the ion implantation trench, respectively.

[0029] In this embodiment, a first sacrificial dielectric layer 360 is formed by depositing a first sacrificial dielectric material in an ion implantation trench, such as... Figure 6 The schematic structure (a) is shown in the diagram. After forming the first photomask 253 on the first sacrificial dielectric layer 360, the first sacrificial dielectric layer 360 is selectively etched, as shown in the diagram. Figure 6 The schematic structure (b) is shown in the diagram. Then the first photomask 253 is removed, as shown in the diagram. Figure 6 The schematic structure (c) is shown in the diagram. Further etching is performed to form a first corner protection layer 361 and a second corner protection layer 362 on both sides of the bottom of the ion implantation trench, as shown in the diagram. Figure 6 The schematic structure (d) is shown in the figure.

[0030] In step S500, a protective layer 410 is formed along the inner surface of the ion implantation trench, such as... Figure 7 The schematic structure (a) is shown in the diagram. A second photomask 254 is formed on the protective layer 410, as shown in the diagram. Figure 7 The schematic structure (b) is shown in the diagram. Under the protection of the second photolithography mask 254, the protective layer 410 is etched to expose the first region, resulting in a new first protective layer 411 and a second protective layer 412, as shown in the diagram. Figure 7 The schematic structure (c) is shown in the figure.

[0031] In some embodiments, the first region is located at the bottom of the ion implantation trench.

[0032] In step S600, the second photolithography mask 254 is removed, as follows: Figure 7 The schematic structure (d) is shown in the diagram. P-type doped ions are implanted along the first region under the protection of the first protective layer 411 and the second protective layer 412, as shown in the diagram. Figure 8 The schematic structure (a) is shown in the diagram. After removing the first protective layer 411, the second protective layer 412, the first corner protective layer 361, and the second corner protective layer 362, annealing is performed to form a P-type shielding area 370, as shown in the diagram. Figure 8 The schematic structure (b) is shown in the figure.

[0033] In some embodiments, in step S600, P-type dopant ions are implanted to inject P-type dopant ions into the N-type drift region 230 through the first region, and after removing the protective layers (first protective layer 411, second protective layer 412), first corner protective layer 361 and second corner protective layer 362, the region is annealed at an environment of 1650-1800°C to form a P-type shielding region 370 at the bottom of the first region.

[0034] In this embodiment, using the first corner protection layer 361 and the second corner protection layer 362 as masks, P-type doped ions can be injected into the N-type drift region 230 through the first region at the bottom of the ion implantation trench to form a P-type shielding region 370. With the first corner protection layer 361 and the second corner protection layer 362 as masks, the P-type doped ion implantation process can be carried out in multiple stages, so that the doping concentration of the P-type shielding region 370 gradually changes in a trapezoidal shape.

[0035] In some embodiments, the p-type doped ion may include aluminum ions.

[0036] In some embodiments, the location of the first region is defined by the initial gate structure of the device, and a first corner protection layer 361 and a second corner protection layer 362 are formed on both sides of the first region, respectively.

[0037] In some embodiments, the location of the first region is defined by the initial gate structure of the device. Depositing silicon nitride as an etch stop layer can ensure high-precision pattern transfer, control critical dimensions, and reduce process defects. Specifically, in the photolithography pattern transfer process, the etch stop layer utilizes the difference in etching rate with adjacent materials (such as silicon oxide or polysilicon) to precisely stop etching during pattern transfer, avoiding over-etching of the underlying structure. Furthermore, the etch stop layer can also prevent the loss of stop layer height inside and outside the sidewalls, ensuring the uniformity of subsequent pattern transfer.

[0038] In some embodiments, the etching selectivity ratio between the etch stop layer and the adjacent material is greater than or equal to 10:1.

[0039] In some embodiments, by adjusting the nitrogen content in the silicon nitride material, the etch stop layer can include a multi-layer structure. Adjusting the etching rate of the etch stop layer can also facilitate the adjustment of the shape and size of the first region.

[0040] In step S700, a second sacrificial medium material is deposited to form a second sacrificial medium layer 380, such as... Figure 8 The schematic structure (c) is shown in the diagram. A third photomask 255 is formed on the second sacrificial dielectric layer 380, as shown in the diagram. Figure 8 The schematic structure (d) shows the selective etching of the second sacrificial dielectric layer 380, as shown in the diagram. Figure 9The schematic structure (a) is shown in the diagram. Then, the third photomask is removed, as shown in the diagram. Figure 9 The schematic structure (b) is shown in the diagram. The second sacrificial dielectric layer is etched again to form a gate trench, and a first corner dielectric layer 381 and a second corner dielectric layer 382 are formed on both sides of the bottom of the gate trench, as shown in the diagram. Figure 9 The schematic structure (c) is shown in the figure.

[0041] In this embodiment, the design pattern is split into two sets of photomasks according to odd / even lines or spatial positions using a dual-pattern photolithography process. This ensures that the spacing between each set of photomasks is greater than the photolithographic resolution limit. During the photolithography stage, a marker layer is added to ensure that the patterns from the two exposures are accurately superimposed, with an error control of <3nm. In the deposition stage, the core is first deposited, then etched to form the initial lines. Then, a sacrificial dielectric material (such as silicon oxide or silicon nitride) can be deposited using ALD or CVD to form the sidewall material. The sidewalls are etched to form double the lines, and then the core is removed to obtain the final pattern.

[0042] In some embodiments, during the deposition of sidewall material, spacers can be selectively etched to retain them. Using the spacers as a mask, the underlying material can be selectively etched to form new gate trenches. By utilizing material properties (such as etching selectivity and surface energy differences) or the physical properties of the deposition / etching process, the pattern can be automatically aligned without multiple photolithography alignments, thereby improving etching accuracy, increasing yield, and reducing the complexity of the photolithography process.

[0043] In some embodiments, in step S700, the etching selectivity ratio of silicon oxide and silicon nitride in the second sacrificial dielectric material is adjusted to regulate the morphology of the gate trench.

[0044] In this embodiment, selective removal is achieved by utilizing the difference in etching rates of different materials (such as silicon oxynitride and silicon). By utilizing material properties (such as etching selectivity and surface energy differences) or the physical properties of the deposition / etching process, the pattern can be automatically aligned without the need for multiple photolithographic alignments.

[0045] In step S800, a concave gate dielectric layer 431 is formed along the inner surface of the gate trench, such as... Figure 9 The schematic structure (d) is shown in the diagram. The gate material is deposited, such as... Figure 10 The schematic structure (a) is shown in the diagram. A gate layer 441 is formed within a recess in the gate dielectric layer 431, as shown in the diagram. Figure 10 The schematic structure is shown in (b). A field oxide layer 451 is formed on the gate layer 441, as shown in the diagram. Figure 10 As shown in the schematic structure (c), the gate dielectric layer 431 and the field oxide layer 451 form a closed structure that encloses the gate layer 441.

[0046] In some embodiments, the gate layer 441 can be a metal material. By providing a metal gate, the phenomenon of unstable threshold voltage during reliable operation of the device can be improved.

[0047] In some embodiments, the dielectric constant of the gate dielectric layer 431 is greater than that of the first corner dielectric layer 381 and the second corner dielectric layer 382, ​​and the gate dielectric layer 431 may be composed of a high-k dielectric material. During device conduction, the channel resistance accounts for the largest proportion of the specific on-resistance, and the channel size, device bias voltage, oxide layer capacitance, channel electron mobility, and threshold voltage play an important role in reducing the specific on-resistance. By using high-k dielectric materials and metal gate materials, the capacitance value of the oxide layer can be greatly increased with the same dielectric layer thickness, which is beneficial to the reduction of the threshold voltage, and also enhances the oxide layer collapse electric field, reduces the leakage current of the device, and improves the reliability of the device.

[0048] In some embodiments, the gate dielectric layer 431 may be a composite dielectric layer of silicon oxide and silicon nitride, which may be formed by alternating layers of silicon oxide and silicon nitride.

[0049] Within the same reaction chamber, by adjusting the reaction gas at alternating time intervals, for example, by gradually increasing nitrogen and decreasing oxygen, silicon nitride is gradually deposited in that stage; if oxygen is gradually increased and nitrogen is gradually decreased, silicon oxide is gradually deposited in that stage. At the same time, silicon-containing gas needs to be introduced. By adjusting the content of various gases in the mixed gas, the oxygen and nitrogen content in the thin film can be controlled, thereby achieving the alternating deposition of silicon oxide and silicon nitride layers within the same reaction chamber to form the gate dielectric layer 431.

[0050] In step S900, a second photoresist 256 is formed on the field oxide layer 451, such as... Figure 10 As shown in the schematic structure (d), the field oxide layer 451 is then etched according to the pattern of the second photoresist 256 until the first P-type well region 321, the second P-type well region 322, the first heavily doped N-type region 341, the second heavily doped N-type region 342, the first heavily doped P-type region 331, and the second heavily doped P-type region 332 are exposed, as shown in the schematic structure (d). Figure 11 The schematic structure (a) is shown in the diagram. The second photoresist 256 is removed, as shown in the diagram. Figure 11 The schematic structure is shown in (b). A source layer 460 is formed in contact with both sides of the gate dielectric layer 431, the P-type well region, the N-type heavily doped region, the P-type heavily doped region, and the field oxide layer 451, as shown in the diagram. Figure 11 The schematic structure (c) is shown in the diagram. A drain layer 110 is formed on the back side of the silicon carbide substrate 210, as shown in the diagram. Figure 1 As shown.

[0051] In this embodiment, source electrode material is deposited after etching the field oxide layer 451 to form a source layer 460 that contacts both sides of the gate dielectric layer 431, the first N-type heavily doped region 341, the second N-type heavily doped region 342, the first P-type heavily doped region 331 and the second P-type heavily doped region 332, the first P-type well region 321, the second P-type well region 322, and the field oxide layer 451. During this process, the regions of the gate dielectric layer 431 located on the first P-type well region 321, the second P-type well region 322, the first N-type heavily doped region 341, the second N-type heavily doped region 342, the first P-type heavily doped region 331, and the second P-type heavily doped region 332 are also etched.

[0052] In some embodiments, photoresist is used to define the coverage area of ​​the field oxide layer 451, and silicon oxide material is etched under the photoresist coverage until the first P-type well region 321, the second P-type well region 322, the first heavily doped N-type region 341, the second heavily doped N-type region 342, the first heavily doped P-type region 331, and the second heavily doped P-type region 332 are exposed. By etching the field oxide layer 451, the width of the field oxide layer 451 is set to be greater than the width of the gate layer 441, so that the subsequent electrode deposition material can contact the first heavily doped N-type region 341, the second heavily doped N-type region 342, the first heavily doped P-type region 331, the second heavily doped P-type region 332, and both sides of the gate dielectric layer 431.

[0053] Combination Figure 11 As shown in the schematic structure (a), a second photoresist 256 is formed on the field oxide layer 451 to define the source electrode region. Then, under the cover of the second photoresist 256, the field oxide layer 451 is etched to expose the first P-type well region 321, the second P-type well region 322, the first heavily doped N-type region 341, the second heavily doped N-type region 342, the first heavily doped P-type region 331, and the second heavily doped P-type region 332. After removing the photoresist 305, the source electrode material is deposited to form the source layer 460, as shown in the schematic structure (a). Figure 11 The schematic structures shown in (b) and (c) are illustrated. Drain electrode material is deposited to form a drain layer 210 on the back side of the silicon carbide substrate 210.

[0054] In the dual-patterning photolithography process of this embodiment, aluminum ions are implanted at the center of the trench bottom of the SiC trench gate MOSFET using the first patterning photolithography and high-concentration aluminum ion implantation to form a P-type shielding region 370. This shields and reduces the high electric field of the central oxide layer at the bottom of the trench gate, preventing high-field collapse and reducing gate leakage current, thereby improving device operational reliability. In the second patterning photolithography process, a first corner dielectric layer 381 and a second corner dielectric layer 382 are formed at the bottom corners of both sides of the trench of the SiC trench gate MOSFET using photolithography. This reduces the electric field concentration effect at the bottom corners of the trench gate, reduces gate leakage current, and improves device reliability. In some embodiments, the position of the P-type shielding region 370 is defined by the initial gate structure of the device, and the position of the first region is also defined by the initial gate structure of the device. A first corner protection layer 361 and a second corner protection layer 362 are formed on both sides of the first region, respectively. In the second photolithography pattern transfer process, a mandrel is first determined, an initial linear pattern is established, and silicon nitride material is deposited as an etch stop layer. The mandrel provides a geometric reference for subsequent sidewall deposition, and the sidewall thickness of the etch stop layer is determined, which can ensure high-precision pattern transfer, control critical dimensions, and reduce process defects. Then, an interlayer dielectric layer is deposited, and an etchant is used to etch the bottom of the gate trench to retain the silicon nitride material on both sides of the P-type shielding region 370 as the first corner dielectric layer 381 and the second corner dielectric layer 382.

[0055] In the photolithography pattern transfer process, the etch stop layer utilizes the difference in etching rate with adjacent materials (such as silicon oxide and polysilicon) to precisely stop etching during the pattern transfer process, avoiding over-etching of the underlying structure. Furthermore, the etch stop layer can also prevent the loss of height of the stop layer inside and outside the sidewalls, ensuring the uniformity of subsequent pattern transfer.

[0056] In this embodiment, by forming a P-type shielding region at the bottom of the groove in the N-type drift region and setting corner protection layers (i.e., the first corner protection layer and the second corner protection layer) at the corners of the groove in the N-type drift region, the high electric field of the central oxide layer at the bottom of the gate is reduced, causing the field strength to extend downward, improving the breakdown voltage of the device, and also helping to reduce the contact area between the drift region and the gate, reducing the gate charge Qg of the device, and reducing the width of the bottom P-type shielding region (the width of the P-type shielding region is greater than the width of the contact surface between the P-type shielding region and the gate dielectric layer, and less than the maximum width between the first corner dielectric layer and the second corner dielectric layer, i.e., the P-type shielding region completely covers the bottom of the gate dielectric layer), making the current path wider, reducing the on-resistance, and multiple P-type floating ring regions of the same width are arranged sequentially along the P-type shielding region towards the drain layer, which can expand the distribution range of the high electric field in the drift region, increase the area of ​​the space charge region, effectively reduce the saturation current of the device, improve the device's withstand capability under short-circuit testing, and improve the reliability of the device.

[0057] In this embodiment, the distance between the plurality of P-type floating ring regions and the P-type shielding region is greater than the thickness of the P-type shielding region.

[0058] In this embodiment, by setting multiple P-type floating ring regions 260 with uniform width within the N-type drift region 230, multiple floating P-ring regions (multiple P-type floating ring regions 260) with a spacing greater than the thickness of the P-type shielding region are set in the central region of the N-type drift region 230. This extends the electric field at the bottom of the gate downwards (i.e., towards the silicon carbide substrate), effectively reducing the electric field intensity on the oxide surface at the bottom of the device trench gate and improving the reliability of device operation. On the other hand, the presence of the floating P-ring regions expands the high electric field distribution range within the drift region, increases the space charge area to improve the device's withstand voltage capability, and increases the breakdown voltage. Although the presence of the floating P-ring regions will increase the on-resistance, combined with the increase in the device's effective BV, it is beneficial to optimize its static quality factor. Due to the introduction of the floating P-ring regions, the saturation current of the device is effectively reduced, improving the device's dynamic short-circuit withstand time (tsc) under short-circuit testing, enhancing the device's withstand capability under short-circuit testing, and improving the device's reliability.

[0059] In some embodiments, a P-type shielding region 370 is formed at the bottom of the groove in the N-type drift region 230. A grounded P-type shielding region 370 electrode is used to reduce the Qgd of the device and optimize the device structure. The device structure can also be optimized by changing the vertical position of the P-type floating ring region 260 in the N-type drift region 230, the width and density of the P-type floating ring region 260, and the number of P-type floating ring regions 260, thereby increasing the device's breakdown voltage BV. Adding a first current spreading layer 311 and a second current spreading layer 312 to the epitaxial layer further optimizes the device structure and reduces the device's on-resistance Ron,sp.

[0060] In this embodiment, a P-type shielding region 370 is formed at the bottom of the groove in the N-type drift region 230. The width of the P-type shielding region 370 is greater than or equal to the width of the gate dielectric layer 431. The P-type shielding region 370 surrounds the bottom of the gate dielectric layer 431, and the gate dielectric layer 431 is formed on the inner wall of the groove in the P-type shielding region 370. By injecting P-type doped ions at the center of the bottom of the trench of the SiC trench gate MOSFET to form the P-type shielding region 370, the high electric field of the central oxide layer at the bottom of the trench gate is reduced, thereby preventing high electric field collapse inside the device and reducing gate leakage current, thus improving the operational reliability of the device.

[0061] In some embodiments, the doping concentration of the P-type shielding region 370 is gradient-distributed, gradually increasing from the drain layer to the source layer.

[0062] In this embodiment, the P-type shielding region 370 can be formed by multiple aluminum ion implantations, with different energies for each implantation, resulting in a gradient distribution of doping concentration in the P-type shielding region 370.

[0063] In some embodiments, an innovative structure can be created by implanting N-type doped ions into the P-type shielding region 370 to form an N-type doped region, thereby forming at least two new PN junctions on both sides of the P-type shielding region 370. A PN junction is formed between the P-type shielding region 370 and the N-type drift region 230, and between the P-type shielding region 370 and the N-type doped region. During the turn-on process of the linear floating P-ring silicon carbide trench device with a forward bias applied to the gate, this novel structure implanted by N-type doped ions within the P-type shielding region 370 does not affect the JFET region or the N-type drift region in the original device structure. Therefore, it does not cause any impact degradation to the device's on-resistance or the gate charge Qg generated during high-frequency operation. During the turn-off process of the linear floating P-ring silicon carbide trench device in this embodiment, the reverse bias caused by the positive voltage applied to the drain, due to the PN junction generated within the P-type shielding region 370, provides more depletion region area to increase the device's withstand voltage field, thus improving the device's breakdown voltage capability and reliability.

[0064] In some embodiments, an N-type doped region is formed in the central region inside the P-type shielding region 370, and the number of N-type doped regions is the same as the number of P-type floating ring regions 260.

[0065] In some embodiments, the width of the N-type doped region in the central region inside the P-type shielding region 370 is the same.

[0066] In some embodiments, the doping concentration of the N-type drift region increases sequentially from the silicon carbide substrate toward the current spreading material layer.

[0067] In this embodiment, by setting a higher doping concentration in the N-type drift region near the bottom of the gate dielectric layer, the carrier density in the N-type drift region can be increased, directly reducing the specific on-resistance of the device and improving the switching efficiency of the device. Furthermore, by setting a P-type floating ring region to share the electric field borne by the gate dielectric layer, the electric field shielding effect at the bottom of the gate dielectric layer can be enhanced, reducing the risk of gate oxide breakdown.

[0068] In some embodiments, the width of the plurality of P-type floating ring regions 260 is smaller than the width of the P-type shielding region 370.

[0069] In some embodiments, the doping concentration of the P-type floating ring regions 260 in the plurality of P-type floating ring regions 260 gradually increases from the drain layer 110 to the source layer 460.

[0070] In some embodiments, the spacing between adjacent P-type floating ring regions 260 in the plurality of P-type floating ring regions 260 is the same.

[0071] In some embodiments, the silicon carbide trench gate power device in this embodiment further includes a plurality of first P-type floating ring regions and second P-type floating ring regions disposed on both sides of the N-type drift region 230, so as to further extend the electric field downward and to both sides.

[0072] In this embodiment, a plurality of first P-type floating ring regions are disposed on the first side region of the N-type drift region 230 and are disposed opposite to the first current extension layer 311, and a plurality of second P-type floating ring regions are disposed on the second side region of the N-type drift region 230 and are disposed opposite to the second current extension layer 312.

[0073] In some embodiments, the doping concentration of the plurality of first P-type floating ring regions gradually increases from the drain layer 110 to the source layer 460.

[0074] In some embodiments, the doping concentration of the plurality of second P-type floating ring regions gradually increases from the drain layer 110 to the source layer 460.

[0075] In some embodiments, a plurality of first P-type floating ring regions are configured in a one-to-one correspondence with a plurality of second P-type floating ring regions.

[0076] In some embodiments, the interface between the gate layer 441 and the field oxide layer 451 is arc-shaped.

[0077] In some embodiments, the contact surface between the gate layer 441 and the gate dielectric layer 431 is arc-shaped, and the apex of the arc is in contact with the P-type shielding region 370.

[0078] In some embodiments, the contact surface between the gate layer 441 and the gate dielectric layer 431 is stepped; the top of the step on the first side of the gate dielectric layer 431 is formed on the upper surface of the first heavily doped N-type region 341; the top of the step on the second side of the gate dielectric layer 431 is formed on the upper surface of the second heavily doped N-type region 342.

[0079] In some embodiments, the contact interface between the P-type shielding region 370 and the gate dielectric layer 431 is located between the first corner dielectric layer 381 and the second corner dielectric layer 382.

[0080] In some embodiments, the width of the first N-type heavily doped region 341 is greater than the width of the first P-type heavily doped region 331; the width of the second N-type heavily doped region 342 is greater than the width of the second P-type heavily doped region 332.

[0081] In some embodiments, the width of the first P-type heavily doped region is greater than the width of the vertical portion of the first P-type well region L-shaped structure.

[0082] In some embodiments, the width of the field oxide layer 451 is greater than the width of the gate layer 441.

[0083] In some embodiments, the depth of the first P-type heavily doped region is the same as the depth of the first N-type heavily doped region. The depth of the first current spreading layer 311 is less than the depth of the first P-type well region 321, and the depth of the second current spreading layer 312 is less than the depth of the second P-type well region 322.

[0084] This application also provides a silicon carbide power device, which can employ the above-described... Figures 2 to 11 The device was fabricated using the dual-pattern photolithography process described above. See also... Figure 1As shown, the silicon carbide power device in this embodiment includes: a silicon carbide substrate 210, a buffer layer 220, an N-type drift region 230, a current spreading layer (first current spreading layer 311, second current spreading layer 312), a P-type well region (first P-type well region 321, second P-type well region 322), corner dielectric layers (first corner dielectric layer 381, second corner dielectric layer 382), a gate dielectric layer 431, a gate layer 441, a P-type shielding region 370, and a field oxide layer 451. The silicon carbide substrate 210, buffer layer 220, and N-type drift region 230 are stacked, and the N-type drift region 230 has a concave structure. The first current spreading layer 311, the second current spreading layer 312, the buffer layer 220, the N-type drift region 230, the first current spreading layer 311, the second current spreading layer 312 ... A spread layer 312 is formed on the side of the N-type drift region 230. A first P-type well region 321 is formed on the first current spread layer 311. A second P-type well region 322 is formed on the second current spread layer 312. A first corner dielectric layer 381 and a second corner dielectric layer 382 are disposed in the corner region of the groove of the N-type drift region 230. A P-type shielding region 370 is formed at the bottom of the groove of the N-type drift region 230. A gate dielectric layer 431 is formed on the inner wall of the groove of the P-type shielding region 370. The gate dielectric layer 431 is a concave structure in which the groove width gradually increases from the bottom to the opening. The gate dielectric layer 431 and the field oxide layer 451 form a closed structure that encloses the gate layer 441.

[0085] In this embodiment, the P-type shielding region 370 is formed at the bottom of the groove of the N-type drift region 230. The gate dielectric layer 431 is formed on the inner wall of the groove on the P-type shielding region 370. By setting the first corner dielectric layer 381 and the second corner dielectric layer 382 in the corner region of the groove of the N-type drift region 230, the high electric field of the central oxide layer at the bottom of the gate is reduced, so that the field strength extends downward, thereby increasing the breakdown voltage of the device. It also helps to reduce the contact area between the drift region and the gate, reduce the Qg of the device, and reduce the width of the bottom P-type shielding region 370, making the current path wider and reducing the on-resistance.

[0086] In some embodiments, the width of the P-type shielding area 370 is greater than the width of the contact surface between the P-type shielding area 370 and the gate dielectric layer 431, and less than the width between the first corner dielectric layer 381 and the second corner dielectric layer 382.

[0087] In some embodiments, the doping concentration of the P-type shielding region 370 exhibits a gradient distribution.

[0088] In this embodiment, the P-type shielding region 370 can be formed by multiple aluminum ion implantations, with different energies for each implantation, resulting in a gradient distribution of doping concentration in the P-type shielding region 370.

[0089] In some embodiments, the first corner dielectric layer 381 contacts the bottom of the first side step of the first current spreading layer 311 and the gate dielectric layer 431; the second corner dielectric layer 382 contacts the bottom of the second side step of the second current spreading layer 312 and the gate dielectric layer 431.

[0090] In this embodiment, the P-type shielding region 370 and the first corner dielectric layer 381 and the second corner dielectric layer 382 on both sides of the gate oxide at the bottom of the trench can further reduce the electric field concentration effect in the bottom corner region of the gate, avoid high electric field collapse, reduce the gate leakage current phenomenon of the device, and improve the reliability of the device.

[0091] In some embodiments, combined with Figure 1 As shown, the silicon carbide power device in this embodiment further includes: an N-type heavily doped region (first N-type heavily doped region 341, second N-type heavily doped region 342), a P-type heavily doped region (first P-type heavily doped region 331, second P-type heavily doped region 332), multiple P-type floating ring regions 260, a source layer 460, and a drain layer 110. The first N-type heavily doped region 341 and the first P-type heavily doped region 331 are formed on the first P-type well region 321. Two heavily doped N-type regions 342 and two heavily doped P-type regions 332 are formed on the second P-type well region 322. The first heavily doped N-type region 341 and the second heavily doped N-type region 342 are in contact with both ends of the gate dielectric layer 431, respectively. A plurality of floating P-type ring regions 260 are located within the N-type drift region 230, and the plurality of floating P-type ring regions 260 are arranged sequentially along the P-type shielding region 370 toward the drain layer 110. The plurality of floating P-type ring regions 260 have the same width. The source layer 460 is in contact with the first P-type well region 321, the second P-type well region 322, the first heavily doped N-type region 341, the second heavily doped N-type region 342, the first heavily doped P-type region 331, the second heavily doped P-type region 332, both sides of the gate dielectric layer 431, and the field oxide layer 451. The drain layer 110 is formed on the back side of the silicon carbide substrate 210.

[0092] In this embodiment, multiple P-type floating ring regions 260 of the same width are arranged sequentially along the P-type shielding region 370 toward the drain layer, which can expand the distribution range of high electric field in the drift region, increase the area of ​​space charge region, effectively reduce the saturation current of the device, improve the device's withstand capability under short-circuit test, and enhance the device's reliability.

[0093] In some embodiments, the width of the plurality of P-type floating ring regions 260 is the same as the width of the P-type shielding region 370.

[0094] In some embodiments, the spacing between adjacent P-type floating ring regions 260 in a plurality of P-type floating ring regions 260 gradually decreases from the drain layer to the source layer.

[0095] In some embodiments, the spacing between adjacent P-type floating ring regions 260 in the plurality of P-type floating ring regions 260 is the same.

[0096] In some embodiments, the doping concentration of adjacent P-type floating ring regions 260 in a plurality of P-type floating ring regions 260 gradually increases from the drain layer to the source layer.

[0097] In some embodiments, the P-type floating ring region 260 is also disposed on both sides of the N-type drift region 230 and is disposed opposite to the current spreading layer.

[0098] In some embodiments, a grounded P-type shielded electrode configuration can be used to reduce the Qgd of the device, thereby optimizing the device structure design. The device structure can be further optimized and its breakdown voltage improved by altering the vertical position of the linear P-type floating ring region within the N-type drift region 230, the width and density of the linear P-type floating ring region, and the number of linear P-type floating ring regions. Adding a current spreading layer structure to the N-type drift region 230 helps reduce the specific on-resistance Ron,sp of the device.

[0099] In some embodiments, an innovative structure is formed by implanting N-type doped ions into the P-type shielding region 370 at the bottom center of the trench of a SiC trench gate MOSFET device to form an N-type doped region, thereby forming at least two new PN junctions on both sides of the P-type shielding region 370. A PN junction is formed between the P-type shielding region 370 and the N-type drift region 230, and a PN junction is formed between the P-type shielding region 370 and the N-type doped region. During the conduction process of the linear floating P-ring silicon carbide trench device with a forward bias voltage applied to the gate, the novel structure of the N-type doped ions implanted in the region of the P-type shielding region 370 does not have any effect on the JFET region and the N-type drift region in the original device structure. Therefore, it does not have any impact on the on-resistance of the device or the gate charge Qg generated by the device during high-frequency operation. During the shutdown process of the linear floating P-ring silicon carbide trench device with the novel structure in this embodiment, the reverse bias voltage caused by the positive voltage applied to the drain is increased by the PN junction generated in the region of the P-type shielding region 370, which provides more depletion region area to improve the breakdown electric field that the device can withstand, thereby improving the breakdown voltage capability and reliability of the device.

[0100] In some embodiments, an N-type doped region is formed in the central region inside the P-type shielding region 370, and the number of N-type doped regions is the same as the number of P-type floating ring regions 260.

[0101] In some embodiments, the width of the N-type doped region in the central region inside the P-type shielding region 370 is the same.

[0102] In some embodiments, the vertical cross-section of the outer side surface of the gate dielectric layer 431 is stepped or arc-shaped.

[0103] In some embodiments, the interface between the gate dielectric layer 431 and the gate layer 441 is stepped or arc-shaped.

[0104] In some embodiments, the interface between the gate dielectric layer 431 and the corner dielectric layers (first corner dielectric layer 381, second corner dielectric layer 382) is arc-shaped or stepped.

[0105] In some embodiments, the first corner dielectric layer 381 and the second corner dielectric layer 382 are in contact with the bottom of the first step of the gate dielectric layer 431.

[0106] In some embodiments, the first current spreading layer 311 and the second current spreading layer 312 are in contact with the bottom of the first step of the gate dielectric layer 431.

[0107] In some embodiments, the top step of the gate dielectric layer 431 is formed on the upper surface of the N-type heavily doped region.

[0108] In some embodiments, a first current spreading layer 311 and a first P-type well region 321 are formed on a first side of an N-type drift region 230, and a second current spreading layer 312 and a second P-type well region 322 are formed on a second side of an N-type drift region 230. A P-type shielding region 370 is formed at the bottom of a recess in the N-type drift region 230, and a gate dielectric layer 431 is formed on the P-type shielding region 370. The gate dielectric layer 431 has a concave structure, and the gate dielectric layer 431 and the field oxide layer 451 form a closed structure that encloses the gate layer 441. A first heavily doped N-type region 341 is formed between a first side of the gate dielectric layer 431 and a first P-type well region 321, and a second heavily doped N-type region 342 is formed between a second side of the gate dielectric layer 431 and a second P-type well region 322. The spacing between the two sides of the gate dielectric layer 431 gradually increases from the bottom to the opening, and the height of the gate dielectric layer 431 is greater than the sum of the heights of the first current spreading layer 311 and the first P-type well region 321. The first corner dielectric layer 381 and the second corner dielectric layer 382 are located on both sides of the gate dielectric layer 431, and the bottoms of the first corner dielectric layer 381 and the second corner dielectric layer 382 are flush with the bottom of the gate dielectric layer 431. The source layer 460 is in contact with the first P-type well region 321, the second P-type well region 322, the first heavily doped N-type region 341, the second heavily doped N-type region 342, both sides of the gate dielectric layer 431, and the field oxide layer 451. The top portion of the gate dielectric layer 431 covers the first heavily doped N-type region 341 and the second heavily doped N-type region 342.

[0109] In some embodiments, a first N-type heavily doped region 341 is formed between a first side of the gate dielectric layer 431 and a first P-type well region 321, and a second N-type heavily doped region 342 is formed between a second side of the gate dielectric layer 431 and a second P-type well region 322. The spacing between the two sides of the gate dielectric layer 431 gradually increases from the bottom to the opening. The height of the gate dielectric layer 431 is greater than the sum of the heights of the first current extension layer 311 and the first P-type well region 321. The first corner dielectric layer 381 and the second corner dielectric layer 382 are located on both sides of the gate dielectric layer 431, and the bottoms of the first corner dielectric layer 381 and the second corner dielectric layer 382 are flush with the bottom of the gate dielectric layer 431. The source layer 460 is in contact with the first P-type well region 321, the second P-type well region 322, the first N-type heavily doped region 341, the second N-type heavily doped region 342, the two sides of the gate dielectric layer 431, and the field oxide layer 451.

[0110] In some embodiments, such as Figure 1 As shown, the gate dielectric layer 431 has a concave structure and the bottom of the gate dielectric layer 431 is arc-shaped. The first corner dielectric layer 381 and the second corner dielectric layer 382 are respectively attached to the bottom two sides of the gate dielectric layer 431, and the first corner dielectric layer 381 and the second corner dielectric layer 382 are arc-shaped.

[0111] In some embodiments, the first corner dielectric layer 381 and the second corner dielectric layer 382 may be silicon oxide layers.

[0112] In some embodiments, the gate dielectric layer 431 has a symmetrical structure.

[0113] In some embodiments, such as Figure 1 As shown, the inner wall of the groove in the gate dielectric layer 431 has a stepped structure.

[0114] In this embodiment, the inner diameter of the groove in the gate dielectric layer 431 gradually decreases from the source layer 460 to the drain layer 210, and the inner wall of the groove in the gate dielectric layer 431 has a stepped structure.

[0115] In some embodiments, the two sides of the gate dielectric layer 431 have a stepped structure.

[0116] In this embodiment, the inner wall of the groove of the gate dielectric layer 431 is a stepped structure, and the outer surfaces of both sides of the gate dielectric layer 431 are also stepped structures.

[0117] like Figure 1As shown, in some embodiments, the top portion of the gate dielectric layer 431 covers the first heavily doped N-type region 341 and the second heavily doped N-type region 342. The first P-type well region 321 and the second P-type well region 322 have an L-shaped structure. The first heavily doped N-type region 341 and the first heavily doped P-type region 331 are located on the horizontal portion of the first P-type well region 321, and the second heavily doped N-type region 342 and the second heavily doped P-type region 332 are located on the horizontal portion of the second P-type well region 322. The source layer 460 has a bald cap structure. The first vertical portion of the bald cap structure covers the area of ​​the first heavily doped N-type region 341 not covered by the gate dielectric layer, the vertical portion of the first P-type well region 321, and the first heavily doped P-type region 331. The second vertical portion of the bald cap structure covers the area of ​​the second heavily doped N-type region 342 not covered by the gate dielectric layer, the vertical portion of the second P-type well region 322, and the second heavily doped P-type region 332.

[0118] In TG-MOS devices, during reverse operation and high-voltage drain operation, an electric field concentration effect exists at the gate oxide corners at the bottom of the trench gate, causing gate oxide collapse and leakage current, which may prevent the device from passing reliability tests. In this application, a P-type shielding region 370 is formed at the bottom of the trench in the N-type drift region 230. A concave gate dielectric layer 431 is formed on the P-type shielding region 370. The gate dielectric layer 431 and the field oxide layer 451 form a closed structure enclosing the gate layer 441, thereby reducing the electric field of the central oxide layer at the bottom of the trench gate. Furthermore, the P-type shielding region 370 and the first corner dielectric layers 381 and 382 on both sides of the gate oxide at the bottom of the trench can further reduce the electric field concentration effect in the corner region at the bottom of the gate, avoiding high-field collapse, reducing gate leakage current, and improving device reliability.

[0119] This application also provides a chip, including a silicon carbide power device fabricated by the device fabrication method described in any of the above embodiments.

[0120] In this embodiment, the chip includes a chip substrate, on which one or more silicon carbide power devices fabricated using a device fabrication method based on a dual-pattern photolithography process are disposed.

[0121] In one specific application embodiment, other related semiconductor devices may also be integrated on the chip substrate to form an integrated circuit as described in any of the above embodiments.

[0122] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0123] In this embodiment, a P-type shielding region 370 is formed at the bottom of the groove of the N-type drift region 230, and a gate dielectric layer 431 is formed on the inner wall of the groove on the P-type shielding region 370. By setting a corner protection layer in the corner region of the groove of the N-type drift region 230, the high electric field of the central oxide layer at the bottom of the gate is reduced, so that the field strength extends downward, improving the breakdown voltage of the device. It also helps to reduce the contact area between the drift region and the gate, reduce the Qg of the device, and reduce the width of the bottom P-type shielding region 370, making the current path wider and reducing the on-resistance. In addition, multiple P-type floating ring regions 260 of the same width are arranged sequentially along the P-type shielding region 370 toward the drain layer 110, which can expand the distribution range of the high electric field in the drift region, increase the area of ​​the space charge region, effectively reduce the saturation current of the device, improve the device's withstand capability under short-circuit testing, and improve the reliability of the device.

[0124] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0125] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0126] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0127] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0128] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A device fabrication method based on a dual-pattern photolithography process, characterized in that, The device fabrication method includes: A silicon carbide substrate is provided, and a buffer layer and an N-type drift region are sequentially formed on the front side of the silicon carbide substrate. Multiple P-type floating ring regions of the same width are formed in the central region of the N-type drift region by repeated oxide deposition, etching, ion implantation and epitaxy. The N-type drift region is further epitaxially extended, and a current spreading material layer, a P-type doped layer, an N-type heavily doped layer, and a P-type heavily doped region are formed by N-type ion implantation and P-type ion implantation; the P-type heavily doped regions are provided on both sides of the N-type heavily doped layer; the doping concentration of the N-type drift region increases sequentially from the silicon carbide substrate toward the current spreading material layer. An ion implantation trench is formed by etching along a portion of the heavily doped N-type layer, extending into the N-type drift region. The ion implantation trench divides the current spreading material layer into a first current spreading layer and a second current spreading layer, divides the P-type doped layer into a first P-type well region and a second P-type well region, and divides the heavily doped N-type layer into a first heavily doped N-type region and a second heavily doped N-type region. After depositing a first sacrificial dielectric material in the ion implantation trench to form a first sacrificial dielectric layer, and forming a first photomask on the first sacrificial dielectric layer, the first sacrificial dielectric layer is selectively etched. Then, the first photomask is removed and etched again to form a first corner protection layer and a second corner protection layer on both sides of the bottom of the ion implantation trench, respectively. After forming a protective layer along the inner surface of the ion implantation trench, a second photomask is formed on the protective layer, and the first area exposed by the protective layer is etched under the protection of the second photomask. After removing the second photomask, P-type doped ions are implanted along the first region, and after removing the protective layer, the first corner protective layer and the second corner protective layer, annealing is performed to form a P-type shielding region at the bottom of the ion implantation trench; the spacing between the P-type floating ring region and the P-type shielding region is greater than the thickness of the P-type shielding region; A second sacrificial dielectric material is deposited to form a second sacrificial dielectric layer, and a third photomask is formed on the second sacrificial dielectric layer to selectively etch the second sacrificial dielectric layer. Then, the third photomask is removed, and the second sacrificial dielectric layer is etched again to form a gate trench. A first corner dielectric layer and a second corner dielectric layer are formed on both sides of the bottom of the gate trench, respectively. After forming a concave gate dielectric layer along the inner surface of the gate trench, a gate layer is formed in the groove of the gate dielectric layer, and a field oxide layer is formed on the gate layer; wherein, the gate dielectric layer and the field oxide layer form a closed structure that encloses the gate layer; The field oxide layer is etched to form a source layer that contacts both sides of the gate dielectric layer, the P-type well region, the N-type heavily doped region, the P-type heavily doped region, and the field oxide layer, and a drain layer is formed on the back side of the silicon carbide substrate.

2. The device fabrication method according to claim 1, characterized in that, The process of removing the second photolithographic mask, implanting P-type doped ions along the first region, and then annealing after removing the protective layer, the first corner protective layer, and the second corner protective layer to form a P-type shielding region includes: After removing the second photolithography mask, using the first corner protective layer and the second corner protective layer as masks, P-type doped ions are injected into the N-type drift region through the first region at the bottom of the ion implantation trench to form a P-type shielding region.

3. The device fabrication method according to claim 2, characterized in that, The step of using the first corner protective layer and the second corner protective layer as masks to implant P-type doped ions into the N-type drift region through the first region at the bottom of the ion implantation trench to form a P-type shielding region includes: Using the first corner protective layer and the second corner protective layer as masks, P-type doped ions are injected multiple times into the N-type drift zone through the first region at the bottom of the ion implantation trench, so that the doping concentration of the P-type shielding region changes in a trapezoidal manner.

4. The device fabrication method according to claim 1, characterized in that, The spacing between adjacent P-type floating ring regions in the plurality of P-type floating ring regions gradually decreases from the drain layer to the source layer.

5. The device fabrication method according to claim 1, characterized in that, The spacing between adjacent P-type floating ring zones in the plurality of P-type floating ring zones is the same.

6. The device fabrication method according to claim 1, characterized in that, The doping concentration of adjacent P-type floating ring regions in the plurality of P-type floating ring regions gradually increases from the drain layer to the source layer.

7. The device fabrication method according to claim 1, characterized in that, The interface between the gate layer and the field oxide layer is arc-shaped.

8. The device fabrication method according to claim 1, characterized in that, The contact surface between the gate layer and the gate dielectric layer is stepped; the top step of the gate dielectric layer is formed on the upper surface of the N-type heavily doped region.

9. A silicon carbide power device, characterized in that, The silicon carbide power device is prepared by the device preparation method according to any one of claims 1-8.

10. A chip, characterized in that, Including silicon carbide power devices prepared by the device preparation method according to any one of claims 1-8.

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