Two-dimensional Bi2MoO6 single crystal gate dielectric material, preparation method and application of two-dimensional Bi2MoO6 single crystal gate dielectric material in field effect transistor

Abstract

The invention discloses a two-dimensional Bi2MoO6 single-crystal gate dielectric material, a preparation method and application of the two-dimensional Bi2MoO6 single-crystal gate dielectric material in a field effect transistor, the two-dimensional Bi2MoO6 single-crystal gate dielectric material is in an ultrathin nanosheet shape, the thickness is 7.5-70 nm, the crystal structure is an orthorhombic system, [MoO4] 2-layers and [Bi2O2] 2 + layers are alternately arranged along a c axis, a Pca21 space group is adopted, lattice constants a = b = 5.53, c = 16.30, Bi2O3, MoO3 and BiOCl are used as precursors, fluorophlogopite is used as a substrate, and the two-dimensional Bi2MoO6 single-crystal gate dielectric material is prepared through a hydrothermal method. The material is prepared through a BiOCl-assisted chemical vapor deposition method, and has the advantages of high crystal quality, high dielectric constant, wide band gap and excellent high-temperature stability and air stability. According to the field effect transistor, by constructing the Bi2MoO6 / MoS2 Van der Waals heterojunction, the problems that an existing field effect transistor has many gate dielectric interface defects, large hysteresis and high-temperature performance degradation are solved, the switching ratio which is still larger than 104 at the high temperature of 500 K is obtained, the hysteresis voltage is smaller than 10 mV, and the field effect transistor is suitable for a next-generation low-power-consumption and high-temperature-resistant electronic device.

Description

Technical Field

[0001] This invention belongs to the field of low-dimensional semiconductor materials and devices, specifically relating to a two-dimensional Bi2MoO6 single-crystal gate dielectric material, its preparation method, and its application in field-effect transistor devices. Background Technology

[0002] With the rapid development of semiconductor devices towards miniaturization and low power consumption, traditional silicon-based field-effect transistors (FETs) are increasingly unable to meet the performance requirements of next-generation electronic devices due to limitations such as short-channel effects and carrier mobility. Two-dimensional (2D) semiconductor materials (such as transition metal chalcogenides like MoS2), with their atomically thin layered structure, high carrier mobility, and excellent electrostatic control capabilities, have become core candidate materials for constructing novel low-power 2D field-effect transistors (2D-FETs) and are considered a key direction for overcoming the size limitations of silicon-based technology.

[0003] In 2D-FETs, the gate dielectric is a core component, and its performance directly determines the device's switching characteristics, leakage current, stability, and operating temperature range. An ideal gate dielectric must simultaneously possess a high dielectric constant (high κ), a wide bandgap (low leakage), excellent thermal stability, and interface characteristics compatible with 2D semiconductors (low defects, low hysteresis). However, the development of current gate dielectric materials still faces many technical bottlenecks: traditional high-κ dielectrics (such as HfO2 and Al2O3) widely used in existing silicon-based devices, while exhibiting certain reliability at high temperatures, are prone to crystalline phase transitions from stable to metastable phases when scaled down to the nanoscale required for 2D-FETs. This leads to a large number of defects (such as oxygen vacancies and grain boundaries) within the dielectric layer. These defects significantly increase gate leakage current, increase hysteresis voltage, exacerbate carrier scattering, and severely reduce the on / off ratio of 2D-FETs. I on / I off ), subthreshold swing ( SS Key electrical properties such as dielectric properties are also a concern. To address the interface compatibility issues between traditional dielectrics and 2D semiconductors, researchers have developed various ultrathin two-dimensional gate dielectrics (including layered and non-layered crystal structures). While these materials can reduce interface scattering and hysteresis through van der Waals assembly, only a very few can maintain stable dielectric properties at high temperatures (such as above 300 K). Most materials undergo crystal transformation, a sharp drop in dielectric constant, or a surge in leakage current at high temperatures, failing to meet the requirements of high-reliability applications.

[0004] Among known functional materials, Bi₂MoO₆, as a high-kb dielectric material with ceramic-like properties, has been widely studied in fields such as catalysis and microwave dielectric communications, possessing unique advantages. On one hand, Bi₂MoO₆ has a theoretical dielectric constant above 30 and can stably maintain its crystal structure and high dielectric properties even at high temperatures, avoiding the performance degradation problem of traditional dielectrics at high temperatures. On the other hand, its large bandgap (>3 eV) can effectively suppress gate leakage current. These properties theoretically give Bi₂MoO₆ the potential to be used as a gate dielectric for constructing high-performance 2D-FETs. However, to date, no research has developed Bi₂MoO₆ as a gate dielectric material for 2D-FETs—existing research has neither solved the problem of controllable preparation of ultrathin Bi₂MoO₆ single crystals (such as achieving nanoscale thickness control and ensuring the quality of large-area single crystals), nor explored its interface compatibility mechanism with 2D semiconductors (such as MoS₂) and device integration processes. This prevents the advantages of Bi₂MoO₆, such as its high kb, wide bandgap, and high-temperature stability, from being fully utilized in 2D-FETs.

[0005] Therefore, developing a method for controllably preparing high-quality Bi2MoO6 ultrathin single crystals and integrating them into 2D-FETs as gate dielectrics, fully leveraging their combined advantages of high κ, wide bandgap, low leakage, and high-temperature stability, and solving the interface compatibility problem with 2D semiconductors, is of great significance for overcoming the performance limitations of existing 2D-FETs and promoting their application in the field of high-temperature electronics. Summary of the Invention

[0006] The purpose of this invention is to overcome the technical shortcomings of existing 2D-FETs gate dielectric materials, such as the difficulty in balancing high dielectric constant and wide bandgap, insufficient high-temperature stability, and significant hysteresis due to numerous interface defects. This invention provides a two-dimensional Bi2MoO6 single-crystal gate dielectric material and its preparation method, aiming to achieve efficient integration of this gate dielectric with MoS2, and to construct 2D-FETs with low subthreshold sway, high current on / off ratio, low hysteresis, and high-temperature stability, thereby meeting the application requirements of next-generation low-power and high-reliability electronic devices.

[0007] To achieve the above objectives, the two-dimensional Bi₂MoO₆ single-crystal grating dielectric material provided by this invention is an ultrathin nanosheet with a thickness of 7.5–70 nm and a lateral dimension of 5–30 μm. Its crystal structure is orthorhombic, with [MoO₄] alternating along the c-axis. 2- Layers and [Bi2O2] 2+ Layer, space group Pca21, lattice constants a=b=5.53 Å, c=16.30 Å, α=β=γ=90°.

[0008] The preparation method of the above-mentioned two-dimensional Bi2MoO6 single-crystal gate dielectric material is as follows: Bi2O3 powder, MoO3 powder, and BiOCl powder are ground and mixed uniformly at a molar ratio of 1.5-2:1:0.3-0.8 to obtain precursor powder; the precursor powder is placed at the bottom of a quartz boat, and fluorophlogopite is placed on top of the precursor powder. Then, the quartz boat is placed in the central heating zone of a tube furnace, and two-dimensional Bi2MoO6 single-crystal gate dielectric material is grown on the fluorophlogopite using argon gas as a carrier through chemical vapor deposition. This preparation method is BiOCl-assisted chemical vapor deposition (CVD), in which grinding and mixing are used to improve the particle size of the precursor and achieve uniform dispersion of the precursor; BiOCl acts as an auxiliary agent to lower the volatilization temperature of the precursor and also provides a bismuth source for the precursor; fluorophlogopite serves as a growth substrate to induce the epitaxial growth of Bi2MoO6 single crystals; and argon gas is used to remove air from the growth system and carry the precursor vapor, ensuring that the saturated vapor pressure of the precursor is suitable for single crystal growth.

[0009] Furthermore, in the above-mentioned method for preparing two-dimensional Bi2MoO6 single-crystal gate dielectric material, the purity of both Bi2O3 powder and MoO3 powder is above 99.9%, and the purity of BiOCl powder is above 99.5%; the fluorophlogopite is placed 3-5 mm directly above the precursor powder.

[0010] Furthermore, in the above-mentioned method for preparing two-dimensional Bi2MoO6 single-crystal gate dielectric material, the flow rate of argon gas is 50-200 sccm, the temperature of chemical vapor deposition is 560-700 ℃, the time is 5-30 minutes, and the heating rate is 10-40 ℃ / min.

[0011] The present invention also provides a MoS2 field-effect transistor, which comprises, from bottom to top, a substrate, a MoS2 channel layer, a gate dielectric layer, a source electrode, a gate electrode, and a drain electrode; the gate dielectric layer is formed of the two-dimensional Bi2MoO6 single crystal gate dielectric material of the present invention.

[0012] In the above-mentioned MoS2 field-effect transistors, the MoS2 channel layer has 1 to 5 layers with a total thickness of 0.6 to 6 nm. This number of MoS2 layers has both high carrier mobility and good electrical stability.

[0013] In the above-mentioned MoS2 field-effect transistor, the substrate is any one of SiO2 / Si, sapphire, quartz, gallium nitride, and aluminum nitride; the MoS2 channel layer has 1 to 5 layers with a total thickness of 0.6 to 6 nm; the source electrode, gate electrode, and drain electrode are any one of In / Au and Cr / Au, with In or Cr thickness of 5 to 15 nm and Au thickness of 20 to 100 nm.

[0014] The method for fabricating a MoS2 field-effect transistor provided by this invention includes the following steps: Step 1: Obtain 1 to 5 layers of MoS2 nanosheets by mechanical exfoliation and transfer them onto a substrate to form a MoS2 channel layer.

[0015] Step 2: Transfer the two-dimensional Bi2MoO6 single crystal gate dielectric material onto the MoS2 channel layer to form the gate dielectric layer.

[0016] Step 3: Photolithography is used to lithographically pattern the source electrode and drain electrode at both ends of the MoS2 channel layer, and to lithographically pattern the gate electrode at the center of the gate dielectric layer.

[0017] Step 4: Thermally evaporate and deposit the source electrode, gate electrode, and drain electrode onto the source electrode pattern, gate electrode pattern, and drain electrode pattern.

[0018] Step 5: Immerse the device deposited in step 4 in acetone, peel off the photoresist, and dry it with nitrogen to fabricate a MoS2 field-effect transistor.

[0019] In step 2 above, a polystyrene solution is spin-coated onto the surface of the two-dimensional Bi2MoO6 single-crystal gate dielectric material grown on the fluorophlogopite, and baked at 100-200 °C for 20-40 minutes to form a polystyrene film. Then, the fluorophlogopite is immersed in ultrapure water to remove the fluorophlogopite, resulting in a polystyrene / Bi2MoO6 composite film. The polystyrene / Bi2MoO6 composite film is retrieved from the substrate in step 1 where the MoS2 channel layer was formed, baked at 100-200 °C for 10-30 minutes, and then immersed in acetone to remove the polystyrene film, forming a gate dielectric layer on the surface of the MoS2 channel layer.

[0020] The beneficial effects of this invention are as follows: 1. This invention utilizes BiOCl-assisted CVD, selecting uniformly ground and mixed Bi₂O₃, MoO₃, and BiOCl as precursors, and fluorophlogopite as a substrate, to prepare a two-dimensional Bi₂MoO₆ single-crystal gate dielectric material with high crystallinity, uniform size and orientation, and adjustable thickness. The two-dimensional Bi₂MoO₆ single-crystal gate dielectric material of this invention exhibits high crystallinity, high dielectric constant (20–75), wide bandgap (3.85 eV), and excellent high-temperature and air stability, with a breakdown current density below 10. -3 A / cm 2 Furthermore, its crystal structure and dielectric properties remain stable even after being exposed to air for one year and within a temperature range of 300–650 K.

[0021] 2. This invention utilizes Bi2MoO6 single-crystal gate dielectric material as the gate dielectric layer to construct a high-dielectric, high-temperature stable, and low-hysteresis MoS2 field-effect transistor, solving the technical pain points of existing FETs such as numerous gate dielectric interface defects, large hysteresis, and high-temperature performance degradation. Specifically, the MoS2 channel layer and the two-dimensional Bi2MoO6 single-crystal gate dielectric material form a heterojunction interface through van der Waals forces, effectively reducing interface defects and carrier scattering. The offsets of the conduction band bottom and valence band top of both are greater than 1 eV, further suppressing gate leakage current and providing key technical support for the development of next-generation 2D electronic devices.

[0022] 3. The on / off ratio of the MoS2 field-effect transistor of the present invention ( I on / I off (Higher than 10) 6 Subthreshold swing ( SS The voltage is as low as 61 mV / dec (close to the thermal limit of 60 mV / dec at 300 K), with a hysteresis voltage of less than 10 mV at 300 K; and it can operate stably in the temperature range of 80–500 K, still greater than 10 mV at 500 K. 4 The switching ratio meets the requirements of high-temperature and high-reliability applications. Attached Figure Description

[0023] Figure 1 This is an orthorhombic phase structure diagram of the two-dimensional Bi2MoO6 single-crystal gate dielectric material of the present invention, wherein the left figure is a schematic diagram of the (0l0) plane structure and the right figure is a schematic diagram of the (l00) plane structure.

[0024] Figure 2 The image shown is an optical microscope (OM) image of the two-dimensional Bi2MoO6 single-crystal grating dielectric material prepared in Example 1, and the inset is an atomic force microscope (AFM) image.

[0025] Figure 3 The image shows the Raman spectrum of the two-dimensional Bi2MoO6 single-crystal grating dielectric material transferred to the SiO2 / Si substrate in Example 1.

[0026] Figure 4 These are the X-ray diffraction (XRD) spectra and simulated XRD spectra of the two-dimensional Bi2MoO6 single-crystal grating dielectric material in Example 1.

[0027] Figure 5 The image is an in-plane high-angle annular dark-field-scanning transmission electron microscope (HAADF-STEM) image of the two-dimensional Bi2MoO6 single-crystal grating dielectric material in Example 1, with the inset being a simulated atomic structure diagram.

[0028] Figure 6It is the selected area electron diffraction (SAED) pattern along the zone axis of the two-dimensional Bi2MoO6 single crystal gate dielectric material

[010] in Example 1.

[0029] Figure 7 This is the micro-area energy dispersive X-ray photoelectron spectroscopy (EDS) spectrum of the two-dimensional Bi2MoO6 single-crystal grating dielectric material in Example 1.

[0030] Figure 8 The image shows the UV-Vis absorption spectrum of the two-dimensional Bi2MoO6 single-crystal grating dielectric material in Example 1. The inset shows the bandgap fitting results.

[0031] Figure 9 This is the band alignment diagram between the two-dimensional Bi2MoO6 single-crystal gate dielectric material and MoS2 in Example 1.

[0032] Figure 10 This is an AFM image of the two-dimensional Bi2MoO6 single-crystal gate dielectric material prepared at 560 °C in Example 2.

[0033] Figure 11 This is an AFM image of the two-dimensional Bi2MoO6 single-crystal gate dielectric material prepared at 590 °C in Example 3.

[0034] Figure 12 This is an AFM image of the two-dimensional Bi2MoO6 single-crystal gate dielectric material prepared at 620 °C in Example 4.

[0035] Figure 13 This document presents schematic diagrams of the structure and dielectric performance test results of metal-insulator-metal (MIM) capacitors based on the two-dimensional Bi2MoO6 single-crystal gate dielectric material in Examples 1-4. Specifically, a) is a schematic diagram of a metal-insulator-metal (MIM) capacitor based on the 37.6 nm thick two-dimensional Bi2MoO6 single-crystal gate dielectric material in Example 3, along with its frequency-dielectric constant curve; b) compares the dielectric constants of two-dimensional Bi2MoO6 single-crystal gate dielectric materials of different thicknesses in Examples 1-4; and c) shows the leakage current density-electric field curve of the 21 nm thick two-dimensional Bi2MoO6 single-crystal gate dielectric material in Example 1.

[0036] Figure 14 This is a schematic diagram and electrical performance diagram of the MoS2 FET with a two-dimensional Bi2MoO6 single crystal gate dielectric material as the top gate in Example 5, where a is a schematic diagram of the MoS2 FET structure; b is the output characteristic ( I ds - V ds ) curve; c is the dual-scan transfer characteristic ( I ds - V g) curve; d is the relationship between subthreshold swing and source / drain current ( SS - I ds )curve.

[0037] Figure 15 This is a stability test graph of the MoS2 FET with a two-dimensional Bi2MoO6 single-crystal gate dielectric material as the top gate in Example 5, where a represents the value at 80–500 K. I ds - V g The curves are shown in the inset, with a) showing the hysteresis voltage at each temperature; b) showing the transfer curve after 500 cycles; and c) showing a comparison of the transfer curves at the initial stage of preparation and after 30 days of storage. Detailed Implementation

[0038] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments, but the scope of protection of the present invention is not limited to these embodiments. Example 1

[0039] Bi₂O₃ powder and MoO₃ powder with a purity ≥99.9% were selected as bismuth source and molybdenum source, respectively. BiOCl powder with a purity ≥99.5% was used as both bismuth source and auxiliary reagent. The three were uniformly mixed in a molar ratio of 1.5:1:0.5 to obtain precursor powder. The precursor powder was placed at the bottom of a quartz boat, and freshly peeled fluorophlogopite was selected as the growth substrate and placed 3-5 mm directly above the precursor powder. The quartz boat was then placed in the central heating zone of a single-temperature zone tube furnace. The entire growth process was carried out under atmospheric pressure. First, high-purity argon gas at a flow rate of 300 sccm was purged for 10 minutes to completely remove residual air from the furnace. Then, the argon gas flow rate was adjusted to 100 sccm as the carrier gas, and the furnace temperature was raised to 570℃ at a heating rate of 30℃ / min and held for 20 minutes to grow a two-dimensional Bi₂MoO₆ single-crystal grating dielectric material on the fluorophlogopite.

[0040] In this embodiment, the crystal structure of the two-dimensional Bi₂MoO₆ single-crystal grating dielectric material grown on fluorophlogopite is orthorhombic, with [MoO₄] alternating along the c-axis. 2- Layers and [Bi2O2] 2+ Layer, space group Pca21. Lattice constants a=b=5.53 Å, c=16.30 Å, α=β=γ=90°. Figure 1 As shown, the atomic arrangement along the b-axis (left image) and a-axis (right image) are illustrated respectively. Figure 2 As shown, the two-dimensional Bi2MoO6 single-crystal grating dielectric material grown on fluorophlogopite has an ultrathin nanosheet morphology with a thickness of 10–30 nm.

[0041] A polystyrene-assisted transfer method was used to transfer two-dimensional Bi₂MoO₆ single-crystal grating dielectric material from fluorophlogopite to a SiO₂ / Si substrate. Specifically, a 13% (w / w) polystyrene solution (toluene as solvent) was spin-coated onto the surface of the two-dimensional Bi₂MoO₆ single-crystal grating dielectric material grown on the fluorophlogopite. The mixture was then baked at 180°C for 30 minutes to form a polystyrene film. The fluorophlogopite was then immersed in ultrapure water to exfoliate it, yielding a polystyrene / Bi₂MoO₆ composite film. The polystyrene / Bi₂MoO₆ composite film was retrieved from the SiO₂ / Si substrate, baked at 110°C for 15 minutes, and then immersed in acetone to remove the polystyrene film. Raman spectroscopy was performed on the transferred sample, and the results are as follows: Figure 3 As shown, at 282, 328, 354, 406, 710, 796 and 847 cm -1 A characteristic vibrational peak appeared at the [specific location], consistent with the standard Raman spectrum of orthorhombic Bi₂MoO₆. The crystal structure was also verified by XRD analysis. Figure 4 The measured and simulated XRD spectra are compared with the (020), (060), and (080) diffraction planes of orthorhombic Bi₂MoO₆. Figure 1 This further confirmed the accuracy of the crystal structure. The microstructure and composition of the transferred Bi₂MoO₆ single crystal were characterized. Figure 5 The image shows its in-plane HAADF-STEM image, with the inset showing a simulated atomic structure. The image shows a clear and orderly arrangement of atoms, and two sets of lattice fringes with a spacing of 0.28 nm and an angle of 90°. These fringes correspond to the (002) and (200) crystal planes of Bi2MoO6, respectively. This result is in high agreement with the in-plane STEM simulation image (inset). Figure 6 The SAED pattern along the (010) zone axis is used to prove its single crystal form and orthorhombic crystal system structure. Figure 7 The EDS surface scan image shows a uniform distribution of Bi, Mo, and O elements. Furthermore, Figure 8 The test curves for analyzing its optical performance by UV-Vis absorption spectroscopy are shown in the inset, which shows the band gap fitting results, indicating a band gap of 3.85 eV. Figure 9 The diagram shows the band alignment between the two-dimensional Bi₂MoO₆ single-crystal gate dielectric material and MoS₂, revealing that the offsets of its conduction band bottom and valence band top are both greater than 1 eV. This band alignment can simultaneously suppress the Schottky emission process of holes and electrons, thereby suppressing gate leakage current. In this embodiment, the dielectric constant of the two-dimensional Bi₂MoO₆ single-crystal gate dielectric material is 20–50, and its crystal quality and dielectric properties do not change significantly after exposure to air for one year in the temperature range of 300–650 K. Example 2

[0042] In this embodiment, the growth temperature was changed to 560 °C, and the other steps were the same as in Example 1. The thickness of the two-dimensional Bi₂MoO₆ single-crystal gate dielectric material grown on fluorophlogopite was 7.5–20 nm, and the dielectric constant was 20–40. Figure 10 This is an AFM image of the two-dimensional Bi2MoO6 single-crystal gate dielectric material in this embodiment. Example 3

[0043] In this embodiment, the growth temperature was changed to 590 °C, and the other steps were the same as in Example 1. The thickness of the two-dimensional Bi₂MoO₆ single-crystal gate dielectric material grown on fluorophlogopite was 25–45 nm, and the dielectric constant was 25–55. Figure 11 This is an AFM image of the two-dimensional Bi2MoO6 single-crystal gate dielectric material in this embodiment. Example 4

[0044] In this embodiment, the growth temperature was changed to 620 °C, and the other steps were the same as in Example 1. The thickness of the two-dimensional Bi₂MoO₆ single-crystal gate dielectric material grown on fluorophlogopite was 40–70 nm, and the dielectric constant was 30–75. Figure 12 This is an AFM image of the two-dimensional Bi2MoO6 single-crystal gate dielectric material in this embodiment.

[0045] A quartz substrate with a surface roughness ≤0.5 nm was selected. Graphene was deposited on the substrate as the bottom electrode using a transfer method (1-2 graphene layers, size ≥50 μm × 50 μm). Then, single crystals of two-dimensional Bi₂MoO₆ single-crystal gate dielectric materials of different thicknesses from Examples 1-4 were transferred onto the graphene bottom electrode to form an insulating layer. Finally, a 50 nm thick Au electrode was transferred onto the Bi₂MoO₆ surface as the top electrode to fabricate a MIM capacitor. Its dielectric properties were tested, and the results are shown in [Figure 1]. Figure 13 .in Figure 13 a is a schematic diagram of a MIM capacitor based on the 37.6 nm thick two-dimensional Bi2MoO6 single crystal gate dielectric material in Example 3 and its frequency-dielectric constant curve. The results show that its dielectric constant is about 36 at 1 MHz. Figure 13 b shows the dielectric constant comparison curves of two-dimensional Bi2MoO6 single crystal gate dielectric materials with different thicknesses in Examples 1 to 4. The results show that the dielectric properties increase with the increase of thickness. Figure 13 c shows the leakage current density-electric field curve of the 21 nm thick two-dimensional Bi2MoO6 single crystal gate dielectric material in Example 1, indicating that its leakage current density during breakdown is lower than the low power limit, and the current density under the breakdown field of 3.9 MV / cm is lower than 10. -3 A / cm 2 It meets the application requirements of the gate dielectric. Example 5

[0046] In this embodiment, the MoS2 field-effect transistor consists of, from bottom to top, a SiO2 / Si substrate, a MoS2 channel layer, a two-dimensional Bi2MoO6 single-crystal gate dielectric layer, a source electrode, a gate electrode, and a drain electrode. Figure 14 As shown in Figure a; the thickness of the MoS2 channel layer is 6.6 nm; the thickness of the two-dimensional Bi2MoO6 single crystal gate dielectric layer is 21.9 nm as in Example 1; the source electrode, gate electrode, and drain electrode are all In / Au electrodes, with an In thickness of 10 nm and an Au thickness of 50 nm.

[0047] The fabrication method of the above-mentioned MoS2 field-effect transistor includes the following steps: Step 1: Obtain 1 to 5 layers of MoS2 nanosheets by mechanical exfoliation and transfer them to a SiO2 / Si (300 nm thick) substrate to form a MoS2 channel layer.

[0048] Step 2: Transfer the 21.9 nm thick two-dimensional Bi₂MoO₆ single-crystal gate dielectric material grown on fluorophlogopite in Example 1 to the MoS₂ channel layer to form a two-dimensional Bi₂MoO₆ single-crystal gate dielectric layer, i.e., the Bi₂MoO₆ top gate dielectric layer. The specific transfer method of the two-dimensional Bi₂MoO₆ single-crystal gate dielectric layer is as follows: spin-coat a 13% polystyrene solution (toluene as solvent) onto the surface of the two-dimensional Bi₂MoO₆ single-crystal gate dielectric material grown on the above-mentioned fluorophlogopite, bake at 180 °C for 30 minutes to form a polystyrene film, and then immerse the fluorophlogopite in ultrapure water to peel off the fluorophlogopite to obtain a polystyrene / Bi₂MoO₆ composite film; retrieve the polystyrene / Bi₂MoO₆ composite film from the SiO₂ / Si substrate in Step 1 where the MoS₂ channel layer was formed, bake at 110 °C for 15 minutes, and then immerse in acetone to remove the polystyrene film. The transferred MoS2 channel layer has no obvious wrinkles and forms a good van der Waals heterojunction with the two-dimensional Bi2MoO6 gate dielectric layer.

[0049] Step 3: Photolithography is used to lithographically pattern the source electrode and drain electrode at both ends of the MoS2 channel layer, and to lithographically pattern the gate electrode at the center of the two-dimensional Bi2MoO6 gate dielectric layer.

[0050] Step 4: Thermally evaporate and deposit 10 nm / 50 nm thick In / Au electrodes on the source electrode pattern, gate electrode pattern, and drain electrode pattern, with an electrode spacing of 5 μm, to ensure good ohmic contact between the electrodes and the MoS2 channel layer.

[0051] Step 5: Immerse the device deposited in step 4 in acetone, peel off the photoresist for 3 minutes, and dry it with nitrogen to fabricate a MoS2 field-effect transistor.

[0052] Figure 14 b represents the device.I ds - V ds The curve clearly shows the linear region and the saturation region. Figure 14 c is I ds - V g The curve, as shown in the inset, indicates a hysteresis voltage of 2.6 mV. I on / I off Greater than 10 6 . Figure 14 d is SS - I ds The curve shows a minimum SS of 61 mV / dec. Simultaneously, the device stability was tested, and the results are as follows: Figure 15 As shown. Among them. Figure 15 a is at 80-500 K I ds - V g The curves and insets show the hysteresis voltage at various temperatures. The results show that the device can operate stably in the temperature range of 80–500 K, and still exhibits a hysteresis voltage greater than 10 at 500 K. 4 The switching ratio meets the requirements of high-temperature and high-reliability applications. Figure 15 b is the transfer curve after 500 consecutive cyclic scans, indicating that the device has good stability. Figure 15 c represents the transfer curves during the initial fabrication phase and after 30 days of storage, demonstrating the long-term operational reliability of the device. These results indicate that the transistor device exhibits excellent thermal stability, cycle reliability, and environmental stability.

Claims

1. A two-dimensional Bi2MoO6 single-crystal gate dielectric material, characterized in that: The two-dimensional Bi2MoO6 single crystal gate dielectric material is an ultrathin nanosheet with a thickness of 7.5-70 nm and a lateral size of 5-30 µm, and has an orthorhombic crystal structure with [MoO4] 2- layers and [Bi2O2] 2+ layers, a Pca21 space group, and lattice constants a=b=5.53 Å, c=16.30 Å, α=β=γ=90°.

2. The method for preparing the two-dimensional Bi2MoO6 single crystal gate dielectric material of claim 1, characterized in that: Bi2O3, MoO3, and BiOCl were ground and mixed evenly in a molar ratio of 1.5–2:1:0.3–0.8 to obtain precursor powder. The precursor powder was placed at the bottom of a quartz boat, and fluorophlogopite was placed on top of the precursor powder. Then, the quartz boat was placed in a tube furnace, and two-dimensional Bi2MoO6 single-crystal gate dielectric material was grown on the fluorophlogopite by chemical vapor deposition using argon gas as a carrier.

3. The method for preparing the two-dimensional Bi₂MoO₆ single-crystal grating dielectric material according to claim 2, characterized in that: The purity of Bi2O3 and MoO3 is both above 99.9%, and the purity of BiOCl is above 99.5%.

4. The method of claim 2, wherein the method further comprises: The fluorophlogopite is placed 3–5 mm directly above the precursor powder.

5. The method for preparing the two-dimensional Bi₂MoO₆ single-crystal grating dielectric material according to claim 2, characterized in that: The chemical vapor deposition was performed at a temperature of 560–700 °C for 5–30 minutes, with an argon flow rate of 50–200 sccm.

6. A MoS2 field-effect transistor, characterized in that: From bottom to top, the structure consists of a substrate, a MoS2 channel layer, a gate dielectric layer, a source electrode, a gate electrode, and a drain electrode; the gate dielectric layer is formed from the two-dimensional Bi2MoO6 single-crystal gate dielectric material as described in claim 1.

7. The MoS2 field-effect transistor according to claim 6, characterized in that: The substrate is any one of SiO2 / Si, sapphire, quartz, gallium nitride, and aluminum nitride; the MoS2 channel layer has 1 to 5 layers with a total thickness of 0.6 to 6 nm; the source electrode, gate electrode, and drain electrode are any one of In / Au and Cr / Au, with In or Cr thickness of 5 to 15 nm and Au thickness of 20 to 100 nm.

8. A method for fabricating a MoS2 field-effect transistor according to claim 6, characterized in that: Includes the following steps: Step 1: Obtain 1 to 5 layers of MoS2 nanosheets by mechanical exfoliation and transfer them onto a substrate to form a MoS2 channel layer; Step 2: Transfer the two-dimensional Bi2MoO6 single crystal gate dielectric material as described in claim 1 onto the MoS2 channel layer to form a gate dielectric layer; Step 3: Photolithography is used to etch source electrode patterns and drain electrode patterns at both ends of the MoS2 channel layer, and to photolithography is used to etch gate electrode patterns at the center of the gate dielectric layer. Step 4: Thermally evaporate and deposit the source electrode, gate electrode, and drain electrode onto the source electrode pattern, gate electrode pattern, and drain electrode pattern; Step 5: Immerse the device deposited in step 4 in acetone, peel off the photoresist, and dry it with nitrogen to fabricate a MoS2 field-effect transistor.

9. The method for fabricating a MoS2 field-effect transistor according to claim 8, characterized in that: In step 2, a polystyrene solution is spin-coated onto the surface of the two-dimensional Bi2MoO6 single-crystal gate dielectric material grown on the fluorophlogopite as described in claim 2. The polystyrene film is formed by baking at 100–200 °C for 20–40 minutes. Then, the fluorophlogopite is immersed in ultrapure water to remove the fluorophlogopite, thereby obtaining a polystyrene / Bi2MoO6 composite film. The polystyrene / Bi2MoO6 composite film is retrieved from the substrate in step 1 where the MoS2 channel layer is formed. After baking at 100–200 °C for 10–30 minutes, the polystyrene film is removed by immersion in acetone, thereby obtaining a van der Waals heterojunction of the MoS2 channel layer / Bi2MoO6 gate dielectric layer.

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