Wafer-level chip P-surface electrode pretreatment method
By fabricating a Si3N4 thin film layer and a TiN diffusion barrier layer on the P-side of a wafer-level chip, and combining high-temperature heat treatment and magnetron sputtering technology, the problems of electroplating layer peeling and bulging were solved, thereby improving the structural stability and lifespan of the wafer-level chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-15
- Publication Date
- 2026-04-10
AI Technical Summary
In existing wafer-level chip P-side electroplating processes, hydrogen diffusion causes compressive stress in the substrate metal film, leading to defects such as plating layer peeling and bulging, which affect device reliability and lifespan.
Si3N4 thin films were prepared by PECVD, Ti adhesion layers were magnetron sputtered and subjected to high-temperature heat treatment to increase adhesion; TiN diffusion barrier layers were sputtered on the Ti adhesion layers to adsorb hydrogen and reduce hydrogen penetration; Au seed layers were prepared and electroplated to form stable electroplated Au layers.
It significantly improves interlayer adhesion, inhibits hydrogen diffusion, reduces metal stress, prevents electroplating layer bulging and peeling, and improves device reliability and lifespan.
Smart Images
Figure CN121843434A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of semiconductor devices, and more specifically to a method for pre-processing the P-side electrodes of a wafer-level chip. Background Technology
[0002] With the rapid iteration and development of semiconductor technology and optoelectronic devices, wafer-level chips, with their advantages in mass production, occupy an irreplaceable core position in many key fields such as industrial processing, optical communication, and medical aesthetics. Compared with traditional chip-level processing methods, wafer-level chips use an entire wafer as the processing carrier, enabling large-scale mass production of chips. This not only significantly reduces the production cost per chip but also effectively improves the consistency of chip performance and structural reliability, providing key support for the efficient development of the semiconductor and optoelectronic industries.
[0003] In the wafer-level chip manufacturing process, the electroplating of a metal layer on the P-side is a key technology that plays a decisive role in the core performance of the chip. This technology induces a reduction reaction by passing an electric current through the P-side of the wafer, causing a thin metal film to be uniformly deposited and covering the wafer surface. Its core value is reflected in multiple dimensions: on the one hand, it can significantly improve the chip's photoelectric conversion efficiency, anti-aging performance, and corrosion resistance, ensuring the stable operation of the device under complex operating conditions; on the other hand, it can effectively protect the wafer substrate, avoiding scratches and wear during processing and use, while optimizing the conductivity and thermal conductivity of the P-side electrodes and enhancing the hardness and durability of the electrode structure. Therefore, it has become a standard process step in wafer-level chip manufacturing.
[0004] However, in actual wafer-level mass production, the P-side electroplating metal layer process has always faced numerous technical bottlenecks, among which problems such as plating layer bulging, peeling, and surface defects are particularly prominent. These defects directly lead to drift in the electrical performance parameters of the chip and a decrease in structural stability, seriously affecting the final reliability and lifespan of the device, and becoming a key obstacle restricting the improvement of wafer-level chip production capacity and quality optimization.
[0005] To address the aforementioned issues, various pretreatment processes for P-side electroplating have been proposed in existing technologies, with typical solutions including substrate cleaning, seed layer metal cleaning, and metal heat treatment. These methods, by removing surface oil and impurities or adjusting the metal microstructure, improve the initial adhesion between the electroplated layer and the substrate, as well as the surface uniformity of the plating, to some extent. However, in-depth research has revealed that existing processes cannot address the core failure mechanism of the electroplating process—namely, the diffusion of hydrogen atoms generated during the electroplating reaction into the interior of the substrate metal film, leading to significant compressive stress in the substrate metal film. When this compressive stress exceeds the bonding strength between the electroplated layer and the substrate, as well as the substrate's own load-bearing limit, it can cause fatal defects such as plating peeling and blistering. Therefore, existing pretreatment processes cannot fundamentally solve the failure problem of electroplated layers, and there is an urgent need to develop a novel pretreatment technology to overcome the current technological bottlenecks. Summary of the Invention
[0006] To address the technical problems in existing P-side electrode pretreatment processes, such as hydrogen diffusion during electroplating causing compressive stress on the substrate metal film, leading to peeling and bulging, this invention provides a wafer-level chip P-side electrode pretreatment method to solve these problems. This invention reduces metal stress and effectively prevents bulging and peeling of the electroplated metal layer by enhancing the adhesion between the metal adhesion layer and the substrate layer and reducing hydrogen diffusion to the substrate.
[0007] The technical solution of this invention is as follows: A method for pre-processing the P-side electrodes of a wafer-level chip includes the following steps: (1) A Si3N4 thin film layer was prepared on the P-side of a wafer-level chip using PECVD (plasma chemical vapor deposition) process; (2) On the Si3N4 thin film, a Ti adhesion layer is sputtered by magnetron sputtering, and then high temperature heat treatment is performed to promote the chemical reaction between the Ti adhesion layer and the Si3N4 thin film, reduce the Si3N4 stress, and improve the adhesion between the substrate, the Si3N4 thin film and the Ti adhesion layer. (3) On the Ti adhesion layer, a TiN diffusion barrier layer is sputtered by magnetron sputtering, and hydrogen is adsorbed by hydrogen bonds during the electroplating process to reduce hydrogen penetration; (4) A seed layer of Au is magnetron sputtered on the TiN diffusion barrier layer; (5) An electroplating barrier layer is prepared on the Au seed layer using a photolithographic mask; (6) The Au seed layer treated in step (5) is electroplated with gold to form an electroplated Au layer.
[0008] Furthermore, before implementing step (1), the P-side of the wafer-level chip is cleaned to remove contaminants from the chip surface.
[0009] Furthermore, when cleaning the P-side of the wafer-level chip, deionized water, acetone, and ethanol are used for cleaning for 10-20 minutes each, followed by drying at 120°C for 20-40 minutes.
[0010] Furthermore, in step (1), the thickness of the prepared Si3N4 thin film is 100~300nm.
[0011] Furthermore, in step (2), the high-temperature heat treatment temperature is 750℃~850℃, and the heat treatment is carried out in an N2 atmosphere for 30~90 minutes.
[0012] Furthermore, in step (2), the thickness of the prepared Ti adhesion layer is 100-200 nm.
[0013] Furthermore, in step (3), the thickness of the prepared TiN diffusion barrier layer is 100~300nm.
[0014] Furthermore, in step (4), the thickness of the prepared Au seed layer is 50~100nm.
[0015] Furthermore, in step (5), the thickness of the electroplated barrier layer is 2~5μm.
[0016] Furthermore, in step (6), the thickness of the electroplated Au layer is 4~8μm.
[0017] The beneficial effects of this invention are as follows: (1) The wafer-level chip P-side electrode pretreatment method provided by this invention can significantly improve interlayer adhesion and ensure structural stability. After magnetron sputtering the Ti adhesive layer, this invention uses a high-temperature heat treatment method to effectively promote the chemical reaction between the Ti adhesive layer and the Si3N4 film. By constructing a more stable chemical bonding interface, the adhesion performance between the Ti adhesive layer and the Si3N4 film is greatly enhanced. At the same time, the high-temperature heat treatment also has the function of stress-relief annealing, which can effectively release the internal stress accumulated in the Si3N4 film during the preparation process and avoid interlayer bonding failure caused by stress concentration. Through the above dual effects, this invention fundamentally improves the overall adhesion between the substrate, the Si3N4 film and the Ti adhesive layer, providing a stable structural foundation for the subsequent deposition of electroplated metal layers.
[0018] (2) The wafer-level chip P-side electrode pretreatment method provided by this invention can suppress hydrogen diffusion and reduce metal stress, thus solving the core failure problem. This invention uses magnetron sputtering in a high-flow-rate N2 atmosphere to prepare a TiN diffusion barrier layer. The high-flow-rate N2 atmosphere ensures that sufficient exposed N atoms are formed on the film surface during sputtering. These exposed N atoms can preferentially adsorb hydrogen atoms generated during electroplating through hydrogen bonding, significantly reducing the amount of hydrogen atoms penetrating into the substrate metal film. The reduction in hydrogen penetration directly weakens the formation of hydrogen-induced compressive stress in the substrate metal film, thereby significantly reducing the stress level of the electroplated metal layer, effectively suppressing the generation of fatal defects such as bulging and peeling of the electroplated layer, and greatly improving the reliability and service life of the device. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a schematic diagram of the structure of the P-side of the chip prepared in Embodiment 1 of the present invention.
[0021] Figure 2 This is a schematic diagram of the chemical reaction between the Si3N4 layer and Ti after high-temperature heat treatment.
[0022] Figure 3 This is a schematic diagram of hydrogen adsorption in N-rich TiN.
[0023] In the figure, 1-wafer-level chip, 2-Si3N4 thin film, 3-Ti adhesion layer, 4-TiN diffusion barrier layer, 5-Au seed layer, 6-electroplated Au layer, 7-Ti2N layer, 8-H2 adsorption layer. Detailed Implementation
[0024] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.
[0025] Example 1 like Figures 1-3 As shown, a wafer-level chip P-side electrode pretreatment method includes the following steps: (1) Take a 4-inch wafer-level chip 1, clean its P-side with deionized water for 15 minutes, then clean its P-side with acetone for 15 minutes; finally clean its P-side with ethanol for 15 minutes. After cleaning, place the chip at 120°C to dry for 30 minutes; (2) A Si3N4 thin film 2 with a thickness of 200 nm was prepared on the P-side of the wafer-level chip 1 using the PECVD process; (3) On the Si3N4 thin film 2, a Ti adhesion layer 3 with a thickness of 150 nm is sputtered by magnetron sputtering; then annealing is carried out at 800 °C in N2 atmosphere for 60 minutes to promote the chemical reaction between the Ti adhesion layer 3 and the Si3N4 thin film 2, generate Ti2N layer 7, reduce Si3N4 stress, and improve the adhesion between wafer-level chip 1, Si3N4 thin film 2 and Ti adhesion layer 3; (4) On the Ti adhesion layer 3, the N2 flow rate is controlled to be 100 sccm, and the TiN diffusion barrier layer 4 with a thickness of 200 nm is magnetron sputtered; hydrogen bonds adsorb hydrogen in the electroplating process to reduce hydrogen penetration. (5) On the TiN diffusion barrier layer 4, an Au seed layer 5 with a thickness of 75 nm was magnetron sputtered; (6) An electroplating barrier layer with a thickness of 4 μm is prepared on the Au seed layer 5 by photolithography mask; (7) The Au seed layer 5 treated in step (6) is electroplated with gold to form an electroplated Au layer 6 with a thickness of 6 μm. An H2 adsorption layer 8 is formed on the surface of the TiN diffusion barrier layer 4.
[0026] Comparative Example A method for pre-processing the P-side electrodes of a wafer-level chip includes the following steps: (1) Take a 4-inch wafer-level chip 1, clean its P-side with deionized water for 15 minutes, then clean its P-side with acetone for 15 minutes; finally clean its P-side with ethanol for 15 minutes. After cleaning, place the chip at 120°C to dry for 30 minutes.
[0027] (2) A Si3N4 thin film 2 with a thickness of 200 nm was prepared on the P-side of the wafer-level chip 1 using the PECVD process; (3) On the Si3N4 thin film 2, a Ti adhesion layer 3 with a thickness of 150 nm is magnetron sputtered; (4) On the Ti adhesion layer 3, the N2 flow rate is controlled to be 50 sccm, and the TiN diffusion barrier layer 4 with a thickness of 200 nm is magnetron sputtered. (5) On the TiN diffusion barrier layer 4, an Au seed layer 5 with a thickness of 75 nm was magnetron sputtered; (6) An electroplating barrier layer with a thickness of 4 μm is prepared on the Au seed layer 5 by photolithography mask; (7) The Au seed layer 5 treated in step (6) is electroplated with gold to form an electroplated Au layer 6 with a thickness of 6 μm.
[0028] Test case The wafer-level chips with P-side electrodes prepared in Example 1 and the comparative example were subjected to experiments using the "400℃ rapid annealing-microscopic observation method" and the "400℃ rapid annealing-PU film adhesion and peeling verification method". 100 wafers from each of Example 1 and the comparative example were randomly selected for the experiment. The 400℃ rapid annealing-microscopic observation method involved rapid annealing at 400℃ for 1 min, followed by microscopic examination of the metal bulging. The 400℃ rapid annealing-PU film adhesion and peeling verification method involved rapid annealing at 400℃ for 1 min, followed by peeling the metal with a PU film to verify the metal peeling phenomenon. The specific experimental results are shown in Table 1 below: Table 1 - Experimental Results
[0029] As can be seen from the experimental results in Table 1, the wafer-level chip P-side electrode pretreatment method provided by this invention can suppress hydrogen diffusion and reduce metal stress, effectively suppressing the generation of electroplated layer bulging defects. Furthermore, it can significantly improve interlayer adhesion and ensure structural stability.
[0030] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.
Claims
1. A method for pre-processing the p-side electrode of a wafer-level chip, characterized in that, Includes the following steps: (1) A Si3N4 thin film layer was prepared on the P-side of a wafer-level chip using the PECVD process; (2) On the Si3N4 thin film, a Ti adhesion layer is sputtered by magnetron sputtering, and then high temperature heat treatment is performed to promote the chemical reaction between the Ti adhesion layer and the Si3N4 thin film, reduce the Si3N4 stress, and improve the adhesion between the substrate, the Si3N4 thin film and the Ti adhesion layer. (3) On the Ti adhesion layer, a TiN diffusion barrier layer is sputtered by magnetron sputtering, and hydrogen is adsorbed by hydrogen bonds during the electroplating process to reduce hydrogen penetration; (4) A seed layer of Au is magnetron sputtered on the TiN diffusion barrier layer; (5) An electroplating barrier layer is prepared on the Au seed layer using a photolithographic mask; (6) The Au seed layer treated in step (5) is electroplated with gold to form an electroplated Au layer.
2. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, Before implementing step (1), the P-side of the wafer-level chip is cleaned to remove contaminants from the chip surface.
3. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, When cleaning the P-side of the wafer-level chip, deionized water, acetone and ethanol are used for cleaning for 10-20 minutes respectively, and then dried at 120℃ for 20-40 minutes.
4. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, In step (1), the thickness of the prepared Si3N4 thin film is 100~300nm.
5. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, In step (2), the high-temperature heat treatment temperature is 750℃~850℃, and the heat treatment is carried out in a N2 atmosphere for 30~90 minutes.
6. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, In step (2), the thickness of the prepared Ti adhesion layer is 100-200 nm.
7. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, In step (3), the thickness of the prepared TiN diffusion barrier layer is 100~300nm.
8. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, In step (4), the thickness of the prepared Au seed layer is 50~100nm.
9. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, In step (5), the thickness of the electroplating barrier layer is 2~5μm.
10. The wafer-level chip p-side electrode pretreatment method as described in claim 1, characterized in that, In step (6), the thickness of the electroplated Au layer is 4~8μm.