Wafer-level chip packaging structure and electronic equipment

Abstract

The invention provides a wafer-level chip packaging structure and electronic equipment, relates to the field of semiconductors, and aims to solve the problems of low bandwidth density, poor signal integrity, long transmission delay and the like of electric signals in a wafer when the physical distance is relatively long. The wafer-level chip packaging structure comprises an adapter plate and a wafer-level chip. The adapter plate comprises a first rewiring layer and a second rewiring layer which are stacked, the first rewiring layer comprises an optical interconnection channel, and the second rewiring layer comprises an electric interconnection channel; the wafer-level chip is arranged on the adapter plate; the wafer-level chip comprises a plurality of device areas, each device area comprises a plurality of computing power chips and an exchange chip, and each computing power chip is electrically connected with the exchange chip through an electric interconnection channel; the switching chip of one device area is connected with the switching chip of the other device area through an optical interconnection channel. According to the invention, the interconnection bandwidth of the whole system is improved, and the overall communication efficiency can be improved.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a wafer-level chip packaging structure and electronic device. Background Technology

[0002] Wafer-level system interconnects can break through the scale walls and other constraints of traditional inter-chip interconnects. Currently, the industry has developed complete multi-layer interconnect implementations across the entire process flow. However, the data transmission medium for inter-layer communication in these solutions is still traditional level signals. Level signals face multiple challenges when the physical distance between nodes is large, including low bandwidth density, poor signal integrity, and long transmission latency. For wafer dimensions, the relatively far inter-layer distances exceed the capacity of level signals as a transmission medium. Adding routing to the communication channel to increase the node hop count inevitably leads to additional latency and power consumption overhead. Summary of the Invention

[0003] This application proposes a wafer-level chip packaging structure and electronic device, aiming to improve the problems of low bandwidth density, poor signal integrity and long transmission delay faced by electrical signals in wafers when the physical distance is long.

[0004] To achieve the above objectives, this application provides a wafer-level chip packaging structure, which includes an adapter board and a wafer-level chip. The adapter board includes a first wiring layer and a second wiring layer stacked together. The first wiring layer includes optical interconnect channels, and the second wiring layer includes electrical interconnect channels. The wafer-level chip is disposed on the adapter board. The wafer-level chip includes multiple device regions, each device region including multiple computing chips and a switching chip. Within each device region, the multiple computing chips are electrically connected to each other through electrical interconnect channels, and each computing chip is electrically connected to the switching chip through an electrical interconnect channel. The switching chip of one device region is connected to the switching chip of another device region through an optical interconnect channel.

[0005] In the above embodiments, optical interconnect channels and electrical interconnect channels are set up, with computing chips and switching chips within a single device area electrically connected via the electrical interconnect channel, and switching chips across multiple device areas electrically connected via the optical interconnect channel. Based on this architecture, data transmission between chips within a single device area at close range can be achieved using the electrical interconnect channel. The electrical interconnect channel has a simple hardware structure, low deployment and maintenance costs, and can meet the requirements for short-distance transmission. For data transmission between multiple device areas at long distances, optical interconnect channels can be used. This is because long-distance transmission requires wider bandwidth and higher transmission rates, which optical interconnect transmission can meet. This not only allows the electrical and optical interconnect channels to leverage their respective strengths and improve the overall system interconnect bandwidth, but also enhances overall communication efficiency and ensures the flexibility of the system architecture design.

[0006] In some embodiments, the wafer-level chip is disposed on the side of the second wiring layer away from the first wiring layer.

[0007] In some embodiments, the wafer-level chip is disposed on the side of the first wiring layer away from the second wiring layer.

[0008] In some embodiments, the optical interconnect channel includes a laser source, a modulator, and a photodetector; In some embodiments, the plurality of device regions include at least a first device region and a second device region. The first device region includes a first switching chip, and the second device region includes a second switching chip. The switching chip includes a transmitting circuit and a receiving circuit. The transmitting circuit of the first switching chip is electrically connected to a modulator, and the receiving circuit of the second switching chip is electrically connected to a photodetector. The modulator is configured to convert the laser light from the laser source into an optical signal based on the electrical signal from the transmitting circuit, and transmit the optical signal to the photodetector; the photodetector is configured to convert the optical signal into a current signal, and transmit the current signal to the receiving circuit of the second switching chip.

[0009] In some embodiments, the transmitting circuit includes a first data buffer, a serial converter, and a driver amplifier connected in sequence; the first data buffer is used to receive a first electrical signal transmitted by a computing chip in the same wafer region and transmit the first electrical signal to the serial converter, the serial converter is used to convert the first electrical signal into a serial signal and transmit the serial signal to the driver amplifier; the driver amplifier is used to amplify the serial signal and transmit the amplified electrical signal to the modulator.

[0010] In some embodiments, the receiving circuit includes a cross-group amplifier, a comparator, and a second data buffer connected in sequence; the cross-group amplifier is used to receive a current signal from a photodetector, convert the current signal into a level signal, and transmit the level signal to the comparator; the comparator is used to output a second electrical signal to the second data buffer according to the level signal.

[0011] In some embodiments, the switching chip further includes a distribution logic circuit, which is electrically connected to the transmitting circuit, the receiving circuit, and a plurality of computing chips.

[0012] In some embodiments, the switching chip further includes multiple thermal management modules, with thermal management modules respectively provided in the transmitting circuit and the receiving circuit.

[0013] In some embodiments, the second wiring layer further includes a vertical interconnect structure, one end of which is electrically connected to an optical interconnect channel and the other end of which is electrically connected to a switching chip.

[0014] A second aspect of this application provides an electronic device comprising a wafer-level chip packaging structure and a circuit board as described in any of the above embodiments, wherein the wafer-level chip packaging structure is electrically connected to the circuit board.

[0015] The electronic device described in the above embodiments uses optical interconnect channels and electrical interconnect channels. Within a single device area, computing chips and switching chips are electrically connected via electrical interconnect channels, while switching chips across multiple device areas are electrically connected via optical interconnect channels. Based on this architecture, data transmission between chips within a single device area at close range can be achieved using electrical interconnect channels. Electrical interconnect channels have a simple hardware structure, low deployment and maintenance costs, and are suitable for short-distance transmission. For data transmission between multiple device areas at long distances, optical interconnect channels can be used. This is because long-distance transmission requires wider bandwidth and higher transmission rates, which optical interconnect channels can meet. This not only allows both electrical and optical interconnect channels to leverage their respective strengths, increasing the overall system's interconnect bandwidth, but also improves overall communication efficiency and ensures flexibility in system architecture design. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0017] Figure 1 A front view of a wafer-level chip packaging structure provided in an embodiment of this application; Figure 2 A side view of a wafer-level chip packaging structure provided in an embodiment of this application; Figure 3 This is an architectural diagram of a wafer-level chip packaging structure provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0019] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0020] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0021] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part. It can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0022] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0023] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0024] With the advent of the AI ​​(Artificial Intelligence) era, hardware systems are constantly being updated and iterated to adapt to the high computing power and high bandwidth requirements of AI models, but many bottlenecks still exist. From a system perspective, current AI computing power platforms face significant limitations in exploring larger models, contradicting the Scaling Law followed by large models. Specifically, small-scale high-bandwidth domains can only support small-scale parallelism on high-performance chips, limited by interconnect bandwidth bottlenecks (e.g., 200GB / s). As the scale of parallelism expands, communication latency increases significantly. For example, when the parallelism increases from 4 to 32, system latency increases by approximately 3.3 times. Furthermore, existing hardware conditions are insufficient to effectively scale denser models with larger parameter scales (e.g., Qwen2.5-14B), resulting in most mainstream dense models being concentrated in a small range with fewer than 8 billion parameters, thus restricting the continuous exploration of the boundaries of AI computing power's capabilities for large models.

[0025] From a cluster networking perspective, the current expansion of high-bandwidth domains faces the constraint of a "scale wall." On the one hand, high-bandwidth domains are strictly limited by physical transmission distances. For example, the bandwidth within an NVLink domain can reach 900GB / s, but its effective transmission distance is usually less than 50 meters, making large-scale expansion across racks difficult. On the other hand, high-bandwidth domains incur significant overhead in networking: at the transaction transmission level, the latency introduced by multi-layer switching networks can be up to three times that of single-layer networks, and several MB to hundreds of MB of cache are required to maintain throughput; at the physical interconnect level, cross-rack optical interconnects suffer from signal attenuation, low reliability, high power consumption, and a photoelectric conversion delay of approximately 400ns; at the link utilization level, due to memory transaction order constraints, existing protocols struggle to achieve efficient load balancing, further limiting the communication efficiency and scalability of large-scale clusters.

[0026] Therefore, wafer-level packaging has become one of the trends in the evolution of future hardware systems. It adopts a modular approach, integrating all modules with different functions into a single wafer. Communication modules are integrated on the interposer (media layer), and different functional layers (logic layer / memory layer) are fabricated on top of it. However, wafer-level packaging technology still faces challenges such as long transmission distances.

[0027] Based on the above problems, such as Figure 1 and Figure 2 As shown, this application provides a wafer-level chip packaging structure 101, which includes an adapter board 20 and a wafer-level chip 10. The adapter board includes a first rewiring layer 21 and a second rewiring layer 22 stacked together. The first rewiring layer 21 includes optical interconnect channels, and the second rewiring layer 22 includes electrical interconnect channels. The wafer-level chip 10 is disposed on the adapter board 20. The wafer-level chip 10 includes multiple device regions, each device region including multiple computing chips and a switching chip. Within each device region, the multiple computing chips are electrically connected to each other through the electrical interconnect channels, and each computing chip is electrically connected to the switching chip through the electrical interconnect channels. The switching chip of one device region is connected to the switching chip of another device region through the optical interconnect channels.

[0028] Specifically, such as Figure 1The diagram shows a wafer-level chip 10 comprising a first device region 11, a second device region 12, a third device region 13, and a fourth device region 14. The first device region includes a switching chip S1 and three computing chips, designated N11, N12, and N13. The second device region includes a switching chip S2 and four computing chips, designated N21, N22, N23, and N24. The third device region includes a switching chip S3 and two computing chips, designated N31 and N32. The fourth device region includes a switching chip S4 and three computing chips, designated N41, N42, and N43.

[0029] It is understandable that the number of device regions included in the aforementioned wafer-level chip, as well as the number of switching chips and computing chips within a single device region, are not fixed and can be determined based on actual needs. Signal transmission within a single device region can be achieved simply through electrical interconnects. For signal transmission between device regions, the signal must first be transmitted to the switching chip in the current device region, then to the switching chip in the other device region, and finally to the computing chip.

[0030] In the above embodiments, optical interconnect channels and electrical interconnect channels are set up, with computing chips and switching chips within a single device area electrically connected via electrical interconnect channels, and switching chips across multiple device areas electrically connected via optical interconnect channels. Based on this architecture, data transmission between chips within a single device area at close range can be achieved via electrical interconnect channels. Electrical interconnect channels have a simple hardware structure, low deployment and maintenance costs, and are suitable for short-distance transmission. For data transmission between multiple device areas at long distances, optical interconnect channels can be used. This is because long-distance transmission requires wider bandwidth and higher transmission rates, which optical interconnect channels can meet. This not only allows electrical and optical interconnect channels to leverage their respective strengths, increasing the overall interconnect bandwidth of the structure, but also improves overall communication efficiency and ensures the flexibility of the structural architecture design.

[0031] In some embodiments, the wafer-level chip is disposed on the side of the second wiring layer away from the first wiring layer.

[0032] In some embodiments, the wafer-level chip is disposed on the side of the first wiring layer away from the second wiring layer.

[0033] In the above embodiments, the positions of the first and second wiring layers are not limited. It is possible for the first wiring layer to be disposed on top of the second wiring layer or vice versa, because the purpose of this application is to achieve signal transmission based on electrical interconnection channels in one device area and signal transmission based on optical interconnection channels between multiple device areas.

[0034] In some embodiments, such as Figure 3 As shown, the optical interconnect channel includes a modulator 23, a photodetector 24, and a laser source 25. The plurality of device regions include at least a first device region and a second device region. The first device region includes a first switching chip, and the second device region includes a second switching chip. The switching chip includes a transmitting circuit 13 and a receiving circuit 14. The transmitting circuit 13 of the first switching chip is electrically connected to the modulator 23, and the receiving circuit 14 of the second switching chip is electrically connected to the photodetector 24. The modulator 23 is configured to convert the laser light from the laser source 25 into an optical signal based on the electrical signal from the transmitting circuit 13, and transmit the optical signal to the photodetector 24. The photodetector 24 is configured to convert the optical signal into a current signal and transmit the current signal to the receiving circuit 14 of the second switching chip.

[0035] It is understandable that each switching chip corresponds to a laser source 25 in the optical interconnect channel, which assists its corresponding modulator 23 in converting electrical signals into optical signals. Whether one switching chip corresponds to one laser source 25, multiple switching chips correspond to one laser source 25, or one switching chip corresponds to multiple laser sources 25 is all acceptable.

[0036] In some embodiments, such as Figure 3 As shown, the transmitting circuit 13 includes a first data buffer 131, a serial converter 132, and a driver amplifier 133 connected in sequence. The first data buffer 131 is used to receive a first electrical signal transmitted by a computing chip in the same wafer area and transmit the first electrical signal to the serial converter 132. The serial converter 132 is used to convert the first electrical signal into a serial signal and transmit the serial signal to the driver amplifier 133. The driver amplifier 133 is used to amplify the serial signal and transmit the amplified electrical signal to the modulator 23.

[0037] In some embodiments, such as Figure 3As shown, the receiving circuit 14 includes a cross-group amplifier 141, a comparator 142, and a second data buffer 143 connected in sequence; the cross-group amplifier 141 is used to receive a current signal from the photodetector 24, convert the current signal into a level signal, and transmit the level signal to the comparator 142; the comparator 142 is used to output a second electrical signal to the second data buffer 143 according to the level signal.

[0038] In some embodiments, the switching chip further includes a distribution logic circuit, which is electrically connected to the sending circuit 13, the receiving circuit 14, and the plurality of computing power chips.

[0039] Specifically, the distribution logic circuit is used to distribute the electrical signal in the second data buffer 143 in the receiving circuit to multiple computing chips, and is also used to receive the first electrical signal from the computing chip and transmit the first electrical signal to the transmitting circuit 13.

[0040] In some embodiments, the switching chip further includes multiple thermal management modules, and thermal management modules are respectively provided in the transmitting circuit and the receiving circuit.

[0041] Specifically, the thermal management module is used to control the temperature of various components in the transmitting and receiving circuits.

[0042] In some embodiments, the second redistribution layer 22 further includes a vertical interconnect structure, one end of which is electrically connected to the optical interconnect channel and the other end of which is electrically connected to the switching chip.

[0043] In other embodiments, this application also provides an electronic device, which includes a wafer-level chip package structure 101 and a circuit board as described in any of the above embodiments, wherein the wafer-level chip package structure 101 is electrically connected to the circuit board.

[0044] The electronic device in the above embodiments uses optical interconnect channels and electrical interconnect channels. The computing chip and switching chip within a single device area are electrically connected via the electrical interconnect channel, while the switching chips across multiple device areas are electrically connected via the optical interconnect channel. Based on this architecture, data transmission between chips within a single device area at close range can be achieved using the electrical interconnect channel. The electrical interconnect channel has a simple hardware structure, low deployment and maintenance costs, and is suitable for short-distance transmission. For data transmission between multiple device areas at long distances, optical interconnect channels can be used. This is because long-distance transmission requires wider bandwidth and higher transmission rates, which optical interconnect channels can meet. This not only allows both electrical and optical interconnect channels to leverage their respective strengths, increasing the overall interconnect bandwidth of the structure, but also improves overall communication efficiency and ensures the flexibility of the structural architecture design.

[0045] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer-level chip packaging structure, characterized in that, include: The adapter board includes a first wiring layer and a second wiring layer stacked together. The first wiring layer includes an optical interconnect channel, and the second wiring layer includes an electrical interconnect channel. A wafer-level chip is disposed on the adapter board; the wafer-level chip includes multiple device regions, each device region includes multiple computing chips and a switching chip, within each device region, the multiple computing chips are electrically connected to each other through the electrical interconnect channel, and each computing chip is electrically connected to the switching chip through the electrical interconnect channel; the switching chip of one device region is connected to the switching chip of another device region through the optical interconnect channel.

2. The wafer-level chip packaging structure according to claim 1, characterized in that, The wafer-level chip is disposed on the side of the second wiring layer away from the first wiring layer.

3. The wafer-level chip packaging structure according to claim 1, characterized in that, The wafer-level chip is disposed on the side of the first wiring layer away from the second wiring layer.

4. The wafer-level chip packaging structure according to claim 1, characterized in that, The optical interconnect channel includes a laser source, a modulator, and a photodetector; The plurality of device regions include at least a first device region and a second device region. The first device region includes a first switching chip, and the second device region includes a second switching chip. The switching chip includes a transmitting circuit and a receiving circuit. The transmitting circuit of the first switching chip is electrically connected to the modulator, and the receiving circuit of the second switching chip is electrically connected to the photodetector. The modulator is configured to convert laser light from the laser source into an optical signal based on an electrical signal from the transmitting circuit, and to transmit the optical signal to the photodetector. The photodetector is configured to convert the optical signal into a current signal and transmit the current signal to the receiving circuit of the second switching chip.

5. The wafer-level chip packaging structure according to claim 4, wherein the transmitting circuit comprises a first data buffer, a serial converter, and a driver amplifier connected in sequence; The first data buffer is used to receive a first electrical signal transmitted by a computing chip in the same wafer region and transmit the first electrical signal to the serial converter. The serial converter is used to convert the first electrical signal into a serial signal and transmit the serial signal to the drive amplifier. The drive amplifier is used to amplify the serial signal and transmit the amplified electrical signal to the modulator.

6. The wafer-level chip packaging structure according to claim 4, characterized in that, The receiving circuit includes a crossgroup amplifier, a comparator, and a second data buffer that are connected in sequence. The cross-group amplifier is used to receive the current signal from the photodetector, convert the current signal into a level signal, and transmit the level signal to the comparator; the comparator is used to output a second electrical signal to the second data buffer according to the level signal.

7. The wafer-level chip packaging structure according to claim 4, characterized in that, The switching chip also includes a distribution logic circuit, which is electrically connected to the sending circuit, the receiving circuit, and the plurality of computing power chips.

8. The wafer-level chip packaging structure according to claim 4, characterized in that, The switching chip also includes multiple thermal management modules, with thermal management modules respectively provided in the transmitting circuit and the receiving circuit.

9. The wafer-level chip packaging structure according to claim 1, characterized in that, The second rewiring layer also includes a vertical interconnect structure, one end of which is electrically connected to the optical interconnect channel and the other end of which is electrically connected to the switching chip.

10. An electronic device, characterized in that, include: The wafer-level chip packaging structure as described in any one of claims 1 to 9; The circuit board, wherein the wafer-level chip packaging structure is electrically connected to the circuit board.

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