Three-dimensional integrated packaging structure

Abstract

The invention provides a three-dimensional integrated packaging structure, relates to the field of semiconductors, and aims to solve the problems that a heat dissipation part and a conductive structure in an existing three-dimensional integrated packaging structure fight for resources on a layout, the heat dissipation capacity is limited, and high-power-density hot spots cannot be handled. The packaging structure comprises a substrate, a first wafer and a second wafer are sequentially stacked on the substrate in the direction perpendicular to the substrate, and each of the first wafer and the second wafer comprises an active layer; the plurality of first through holes and the plurality of second through holes penetrate through the active layer; conductive structures are arranged in the first through hole and the second through hole, and the first wafer and the second wafer are electrically connected through the conductive structures; a gap is further formed in the second through hole, the gap is formed in the side, away from the inner wall of the second through hole, of the conductive structure, and the gap is filled with a heat dissipation material. According to the method and the device, invalid information can be eliminated to the greatest extent before data cross-layer transmission, so that the bandwidth requirement and cross-layer communication energy consumption are effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a three-dimensional integrated packaging structure. BACKGROUND

[0002] With the development of high power density chips and monolithic 3D integration (M3D), the problem of heat accumulation and hot spots between device layers is significantly exacerbated. Traditional heat dissipation (heat sink / air cooling / external cold plate) is difficult to achieve interlayer close-range and high-flux heat dissipation due to long heat conduction path and large interface thermal resistance. Existing chip liquid cooling and heat dissipation schemes mostly need to form microchannels in the silicon wafer or interlayer separately, or embed independent micro heat pipes and cooling structures between layers, which not only occupies additional area, but also competes with conductive structures for resources on the layout, resulting in high coupling of thermal and electrical circuits and limited design freedom. At the same time, microfluidic liquid channels require additional distribution manifolds and strict sealing processes, and are prone to flow unevenness, leakage and material compatibility problems during long-term operation, while the scheme based on thermal through silicon vias shortens the heat transfer path, but can only rely on solid thermal conduction, and the heat dissipation capacity is limited, which cannot cope with hot spots under high power density. SUMMARY

[0003] The present application provides a three-dimensional integrated packaging structure, which aims to improve the problem that the heat dissipation part and the conductive structure in the existing three-dimensional integrated packaging structure compete for resources on the layout, the heat dissipation capacity is limited, and cannot cope with hot spots under high power density.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application provide a three-dimensional integrated packaging structure, which includes a substrate, a plurality of wafers, a first via and a second via. The plurality of wafers includes a first wafer and a second wafer, and the first wafer and the second wafer are sequentially stacked on the substrate in a direction perpendicular to the substrate; the first wafer and the second wafer each include an active layer; the plurality of first vias and the plurality of second vias each penetrate the active layer; the first via and the second via each are provided with a conductive structure, and the conductive structure covers at least an inner wall of the first via and an inner wall of the second via; the first wafer and the second wafer are electrically connected through the conductive structure; wherein the second via is further provided with a gap, the gap is arranged on a side of the conductive structure away from the inner wall of the second via, and the gap is filled with a heat dissipation material.

[0005] The three-dimensional packaging structure provided by the above embodiments of the present application is characterized in that a gap is arranged on the side of the conductive structure away from the inner wall of the second through hole, and the gap is filled with a heat dissipation material. This scheme realizes a coupling design of heat dissipation and interconnection, shortens the heat conduction path, reduces the interlayer thermal resistance, and actively removes heat by using the heat dissipation material to realize fixed-point heat dissipation in the hot spot area, thereby breaking through the limitations of the existing microfluid channel and thermal through silicon via. The conductive structure of the second through hole is in a hollow form, which can not only maintain the normal function of electrical connection but also be filled with a heat dissipation material inside, serving as a vertical evaporation / condensation channel or a liquid supply / return riser to realize close-range and high-throughput heat dissipation. In this way, the chip can introduce an efficient liquid cooling path without occupying the original circuit area and without additional grooving or sacrificing the interconnection density. This scheme realizes decoupling of the conductive structure and the heat dissipation path in terms of layout and process, guarantees the integrity of high-density interconnection, and provides close-source and fixed-point arranged heat dissipation capacity, thereby effectively solving the problems of heat accumulation and hot spots in the chip interlayer.

[0006] In some embodiments, the second through hole further comprises a barrier layer arranged between the gap and the conductive structure.

[0007] In some embodiments, the packaging structure further comprises a microfluid channel manifold and a capillary structure, and the gaps of the plurality of second through holes are connected through the microfluid channel manifold and the capillary structure.

[0008] In some embodiments, the heat dissipation material comprises a phase change working medium.

[0009] In some embodiments, the heat dissipation material comprises a non-phase change working medium, the gap of at least one second through hole is configured as a non-phase change working medium inlet, and the gap of at least one second through hole is configured as a non-phase change working medium outlet. In some embodiments, in a direction perpendicular to the substrate, the second through hole comprises opposite first and second ends, the first end is provided with a first sealing layer, and the second end is provided with a second sealing layer; and the gap is located between the two sealing layers.

[0010] In some embodiments, a first compliant layer is arranged between the first sealing layer and the conductive structure, and a second compliant layer is arranged between the second sealing layer and the conductive structure.

[0011] In some embodiments, the first through hole and the second through hole are formed synchronously. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings needed to be used in some embodiments of the present application. Obviously, the drawings in the following description are only some of the drawings of the embodiments of the present application, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and not the actual size of the product involved in the embodiments of the present application, the actual process of the method.

[0013] Figure 1 A schematic diagram of a three-dimensional integrated packaging structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in some embodiments of the present application will be described clearly and completely in the following with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present application.

[0015] Unless otherwise required by the context, the term "comprising" is to be interpreted as open, inclusive meaning, i.e. "including, but not limited to".

[0016] Hereinafter, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0017] In describing some embodiments, the term "connected" and its derivatives can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated. It can be directly connected, or indirectly connected through an intermediate medium. For example, the term "connected" can be used in the description of some embodiments to indicate that two or more components have direct physical or electrical contact with each other.

[0018] In addition, the use of "based on" means open and inclusive, because the process, step, calculation or other action based on one or more conditions or values can be based on additional conditions or values in practice.

[0019] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0020] Chip liquid cooling and heat dissipation solutions of related technologies mostly need to form microchannels by separately slotting in silicon wafers or interposers, or embed independent micro heat pipes and cooling structures between layers, which not only occupies additional area, but also competes for resources with electrical interconnection through holes (solid metal conductive wires) on the layout, resulting in high coupling degree of thermal and electrical circuits and limited design freedom. At the same time, microfluidic liquid circuits require additional distribution manifolds and strict sealing processes, and are prone to problems such as uneven flow, leakage and material compatibility during long-term operation; while the scheme based on thermal through holes shortens the heat transfer path, but can only rely on solid thermal conduction, and the heat dissipation capacity is limited, which cannot cope with hot spots under high power density. Existing two-phase cooling circuits also have defects such as difficulty in starting, complex gas-liquid distribution, and poor stability in microscale.

[0021] Based on the above problems, as shown in Figure 1 The first embodiment of the present application provides a three-dimensional integrated packaging structure, which comprises a substrate, a plurality of wafers and a plurality of first through holes 12 and a plurality of second through holes 13, the plurality of wafers comprising a first wafer 101 and a second wafer 102, the first wafer 101 and the second wafer 102 being stacked in sequence on the substrate along a direction Z perpendicular to the substrate; the first wafer 101 and the second wafer 102 both comprise an active layer 11; the plurality of first through holes 12 and the plurality of second through holes 13 both penetrate the active layer 11; the first through hole 12 and the second through hole 13 both are provided with a conductive structure 14, and the conductive structure 14 covers at least the inner wall of the first through hole 12 and the inner wall of the second through hole 13; the first wafer 101 and the second wafer 102 are electrically connected through the conductive structure 14; wherein the second through hole 13 is further provided with a gap 15, the gap 15 is arranged on a side of the conductive structure 14 away from the inner wall of the second through hole 13, and the gap 15 is filled with a heat dissipation material.

[0022] Specifically, the above-mentioned chip still adopts monolithic three-dimensional integration (M3D) from bottom to top, the bottom layer is CMOS (Complementary Metal-Oxide-Semiconductor) control and interface, the middle layer is functional unit (such as storage / computing array), and the upper layer is I / O (Input / Output) or special function layer, and the above-mentioned conductive structure 14 can be a metal structure with good conductivity such as copper or silver.

[0023] The three-dimensional packaging structure provided by the above embodiments of the present application is characterized in that the gap 15 is arranged on the side of the conductive structure 14 away from the inner wall of the second through hole 13, and the heat dissipation material is filled in the gap 15. This scheme realizes the coupling design of heat dissipation and interconnection, shortens the heat conduction path, reduces the interlayer thermal resistance, and actively carries away heat by using the heat dissipation material, thereby realizing the fixed-point heat dissipation of the hot spot area, and breaking through the limitations of the existing micro-fluid channel and thermal through silicon via. The conductive structure 14 of the second through hole 13 is in a hollow form, which can not only maintain the normal function of electrical connection, but also can be filled with heat dissipation material inside, thereby realizing the near-distance and high-throughput heat dissipation as a vertical evaporation / condensation channel or a liquid supply / return riser. In this way, the chip can introduce an efficient liquid cooling path without additional grooving or sacrificing the interconnection density, and without occupying the original circuit area. The scheme realizes the decoupling of the conductive structure 14 and the heat dissipation path in the layout and process, ensures the integrity of high-density interconnection, and provides near-source and fixed-point arranged heat dissipation capacity, thereby effectively solving the problems of heat accumulation and hot spots in the chip interlayer.

[0024] It can be understood that the present application is simultaneously decoupled in three aspects of layout, process and material. The geometric specifications and forbidden area of the first through hole 12 and the second through hole 13 are unified in the layout, and the minimum safety distance and the guard ring / ground shield are arranged, so as to ensure the signal integrity and current safety.

[0025] In some embodiments, the second through hole 13 further comprises a barrier layer arranged between the gap 15 and the conductive structure 14.

[0026] It can be understood that the barrier layer can be a deposited medium liner and a barrier / inert thin layer, which is used to improve the chemical compatibility of the working medium and inhibit ion migration. In addition, the filling of the conductive structure 14 and the lining-sealing-filling are performed at different times in the process, and the low heat budget limit (≤ about 400 °C) is used for the high-temperature link to avoid thermal damage to the completed lower device.

[0027] The present application deposits a barrier layer on the inner wall of the conductive structure 14, so that the conductive structure 14 originally used for electrical interconnection is designed as a hollow conductive structure 14, and the cooling liquid flows in the hollow conductive structure 14, thereby realizing the coupling design of heat dissipation and interconnection. This way not only shortens the heat conduction path, reduces the interlayer thermal resistance, but also actively carries away heat by using the cooling liquid, thereby realizing the fixed-point heat dissipation of the hot spot area, and breaking through the limitations of the existing micro-fluid channel and thermal through silicon via.

[0028] In some embodiments, the packaging structure further comprises a micro-fluid channel manifold and a capillary structure, and the gaps 15 of the plurality of second through holes 13 are connected through the micro-fluid channel manifold and the capillary structure.

[0029] It can be understood that the micro-channel manifold and capillary structure are used to connect or parallel the gap 15 of the conductive structure 14 on the second through hole 13.

[0030] In some embodiments, the heat dissipation material includes a phase change working medium.

[0031] Specifically, the phase change working medium can be used for passive two-phase heat transfer. When the phase change working medium encounters heat, it evaporates to absorb heat, and when it is pre-cooled, it condenses into a liquid. When working with the phase change working medium, the conductive structure 14 near the hot spot is responsible for evaporation, and the conductive structure 14 away from the hot area is responsible for condensation. The condensed liquid spontaneously returns through the capillary channel without the need for an external pump, and has the characteristics of being passive and anti-pose.

[0032] In some embodiments, the heat dissipation material includes a non-phase change working medium, and the gap 15 of at least one second through hole 13 is configured as a non-phase change working medium inlet, and the gap 15 of at least one second through hole 13 is configured as a non-phase change working medium outlet.

[0033] Specifically, when the heat dissipation material uses a non-phase change working medium, the gap 15 of the conductive structure 14 serves as a liquid channel at this time, and the micro-channel manifold and capillary structure in the floor "connect" the hot area, and a controllable flow is provided by an external micro-pump or an optional on-chip current micro-pump, to achieve rapid following of dynamic hot spots and high heat exchange coefficient.

[0034] In some embodiments, along the direction Z perpendicular to the substrate, the second through hole 13 includes opposite first and second ends, the first end is provided with a first sealing layer, and the second end is provided with a second sealing layer; the gap 15 is located between the two sealing layers.

[0035] It can be understood that the above can be completed by welding, anode (anode bonding) or direct bonding through the metal frame on both ends of the through hole and the cover plate, to form a long-term stable first sealing layer and second sealing layer.

[0036] It can be understood that by setting the first sealing layer and the second sealing layer, leakage and material compatibility hazards can be avoided, and the startup and long-term stability of the two-phase loop can be improved.

[0037] In some embodiments, the first sealing layer and the sealing layer 15 have a certain thermal expansion coefficient, and the difference range of the thermal expansion coefficients is not fixed, as long as it is ensured that the two will not cause leakage of the heat dissipation material and crowding of the two. The difference range between the thermal expansion coefficients of the material of the first sealing layer and the material of the conductive structure 14 is to reduce the thermal cycle stress. Based on the same reason, the thermal expansion coefficients of the material of the second sealing layer and the material of the conductive structure 14 have a similar difference range.

[0038] In some embodiments, a first compliant layer is arranged between the first sealing layer and the conductive structure 14; and a second compliant layer is arranged between the second sealing layer and the conductive structure 14.

[0039] It can be understood that the first compliant layer and the second compliant layer are also arranged to reduce thermal cycle stress, and the compliant layer is usually an elastic material for absorbing residual stress.

[0040] In some embodiments, the first via hole 12 and the second via hole 13 are formed synchronously.

[0041] It can be understood that, in terms of process, only the conductive structure 14 of the second via hole 13 has the gap 15, and there is no difference between the first via hole 12 and the second via hole 13 in the process of forming the via hole, so they are formed synchronously.

[0042] In some examples, for reliability, the port of the second via hole 13 is also designed to have a gas exhausting / filtering cavity for factory evacuation-filling-sealing, to reduce the risk of non-condensable gas and particles, to provide a reserved temperature / pressure micro-sensing contact point for the main trunk, to facilitate uniform flow setting and in-service health monitoring; and to be matched with helium leak detection, pressure maintenance, thermal cycle and power step test processes in the production and screening links, and to realize automatic shunting or bypassing through the interconnection system and throttling / non-return components when an individual branch is abnormal. In terms of deployment and use, the application suggests that the second via hole 13 is preferentially arranged in the heat point dense area based on thermal simulation, to form a heat dissipation network with "local high density and global low overhead"; and passive two-phase is preferentially used for long-term stable load to pursue high reliability, and closed-loop convection based on non-phase change working medium can be used for peak or strong dynamic working conditions.

[0043] The application takes the "dual-purpose + sealed phase change" of the second via hole 13 as the core, and configures the via hole originally reserved for the conductive structure 14 as a hollow conductive structure 14 and fills in a phase change working medium to form a micro heat pipe on demand without increasing the area, changing the aperture and pitch, so that heat can be taken away vertically nearby, significantly shortening the heat dissipation path and reducing the interlayer thermal resistance, and relieving M3D interlayer heat accumulation and heat point instability from the source. Through decoupling of the layout and process, the conductive structure 14 maintains high-density interconnection capability and signal integrity, and the heat dissipation material undertakes near-source high-flux heat exchange, and the two do not interfere with each other. And in the heat point area, the heat dissipation material can be locally encrypted to realize "point strengthening" without sacrificing the global wiring degree of freedom.

[0044] The application adopts metal frame + cover plate permanent sealing and inert lining / barrier coating, cooperates with evacuation-filling-sealing process, avoids leakage and material compatibility hidden danger, improves the starting performance and long-term stability of two-phase loop; It can also run without pump (passive two-phase, gravity insensitive, high reliability), and can be switched to closed loop forced convection (adjustable flow, fast dynamic hot spot response). Under the condition of not increasing the chip area and packaging complexity, the junction temperature is reduced, the power margin and the service life are improved, the manufacturing path is highly compatible with the existing process, and it has engineering landing and mass production feasibility.

[0045] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any skilled person in the art can think of changes or substitutions within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A three-dimensional integrated package structure, comprising: The package structure comprises: a substrate, a plurality of wafers, including a first wafer and a second wafer, stacked in sequence on the substrate in a direction perpendicular to the substrate; the first wafer and the second wafer each comprise an active layer; a plurality of first vias and a plurality of second vias, each penetrating the active layer; each of the first vias and the second vias is provided with a conductive structure, and the conductive structure covers at least the inner wall of the first via and the inner wall of the second via; the first wafer and the second wafer are electrically connected by the conductive structure; wherein the second via is further provided with a gap, the gap is arranged on the side of the conductive structure away from the inner wall of the second via, and the gap is filled with a heat dissipation material.

2. The three-dimensional integrated package structure of claim 1, wherein, The second via further comprises a barrier layer, which is arranged between the gap and the conductive structure.

3. The three-dimensional integrated package structure of claim 2, wherein, The package structure further comprises a micro-channel manifold and a capillary structure, and the gaps of the plurality of second vias are connected through the micro-channel manifold and the capillary structure.

4. The three-dimensional integrated package structure of claim 3, wherein, The heat dissipation material comprises a phase change working medium.

5. The three-dimensional integrated package structure of claim 3, wherein, The heat dissipation material comprises a non-phase change working medium, at least one gap of the second via is configured as a non-phase change working medium inlet, and at least one gap of the second via is configured as a non-phase change working medium outlet.

6. The three-dimensional integrated package structure of claim 1, wherein, In a direction perpendicular to the substrate, the second via comprises opposite first and second ends, the first end is provided with a first sealing layer, and the second end is provided with a second sealing layer; the gap is located between the two sealing layers.

7. The three-dimensional integrated package structure of claim 6, wherein, A first compliant layer is arranged between the first sealing layer and the conductive structure; a second compliant layer is arranged between the second sealing layer and the conductive structure.

8. The three-dimensional integrated package structure of claim 1, wherein, The first via and the second via are formed synchronously.

Images