Host management of flash memory with shared write buffer

Abstract

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer. The HCI is further configured to perform a remedial action in response to receiving the notification, the remedial action including reallocating a portion of the first logical unit (LU).

Description

Cross Reference to Related Applications

[0001] This application claims priority to commonly owned U.S. Non-Provisional Patent Application No. 18 / 472,642, filed September 22, 2023, the contents of which are expressly incorporated by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure generally relates to host management of a flash memory device with a shared write buffer.

[0003] BACKGROUND Advances in technology have resulted in smaller and more powerful computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless telephones such as mobile and smart phones, tablets, and laptop computers, that are small, lightweight, and easily carried by users. These devices can communicate voice and data packets over wireless networks. Further, many such devices incorporate additional functionality such as digital still cameras, digital video cameras, digital recorders, and audio file players. Still further, such devices can process executable instructions, including software applications, such as web browsers, that can be used to access the Internet. As such, these devices can include significant computing capabilities.

[0004] Such computing devices often incorporate functionality that operates as a host device, such that data can be stored and retrieved from a flash memory device. For example, a host device can store audio, images, video, documents, etc. on a flash memory device. Prior to data being written to a main memory cell, the flash memory device can use a shared write buffer as a temporary storage area for incoming data writes from the host device. Using a shared write buffer has various advantages, such as reducing write latency perceived by the host device. However, if memory cells of the shared write buffer are reallocated for use as main memory cells or memory cells of the shared write buffer are worn out, the shared write buffer can be unavailable. SUMMARY

[0005] According to one implementation of the present disclosure, a host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer. The HCI is further configured to perform a remedial action in response to receiving the notification, the remedial action including reallocating a portion of a first logical unit (LU).

[0006] According to another implementation of the disclosure, a method includes receiving, at a host controller interface (HCI), a notification from a flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer. The method also includes performing a remedial action in response to receiving the notification, the remedial action including reallocating a portion of a first logical unit (LU).

[0007] According to another implementation of the disclosure, a non-transitory computer readable medium is configured to store instructions that, when executed by one or more processors, cause the one or more processors to receive, at a host controller interface (HCI), a notification from a flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer. The instructions also cause the one or more processors to perform a remedial action in response to receiving the notification, the remedial action including reallocating a portion of a first logical unit (LU).

[0008] According to another implementation of the disclosure, an apparatus includes means for receiving, at a host controller interface (HCI), a notification from a flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer. The apparatus also includes means for performing a remedial action, the remedial action including reallocating a portion of a first logical unit (LU), the remedial action performed in response to receiving the notification.

[0009] Other aspects, advantages, and features of the disclosure will become apparent after reading the entire application including the following sections: DETAILED DESCRIPTION, and Claims. DETAILED DESCRIPTION

[0010] FIG. 1 is a block diagram of a particular illustrative aspect of a system that can operate to perform host management of a flash memory having a shared write buffer in accordance with some examples of the present disclosure.

[0011] FIG. 2 is a block diagram of a particular illustrative aspect of a system that can operate to perform host management of a flash memory having a shared write buffer in accordance with some examples of the present disclosure. FIG. 1 is a block diagram of a particular illustrative aspect of a system that can operate to perform host management of a flash memory having a shared write buffer in accordance with some examples of the present disclosure.

[0012] FIG. 3A is a block diagram of a particular illustrative aspect of a system that can operate to perform host management of a flash memory having a shared write buffer in accordance with some examples of the present disclosure. FIG. 2 is a block diagram of a particular illustrative aspect of a system that can operate to perform host management of a flash memory having a shared write buffer in accordance with some examples of the present disclosure.

[0013] FIG. 3B is a block diagram of a particular illustrative aspect of a system that can operate to perform host management of a flash memory having a shared write buffer in accordance with some examples of the present disclosure. FIG. 3A is a block diagram of a particular illustrative aspect of a system that can operate to perform host management of a flash memory having a shared write buffer in accordance with some examples of the present disclosure.

[0014] is a block diagram of a particular illustrative aspect of a system that can operate to perform host management of a flash memory having a shared write buffer in accordance with some examples of the present disclosure.FIG. 4A is a method of host management of a flash memory with a shared write buffer that can be performed by a system in accordance with some examples of the present disclosure FIG. 2 is a diagram of an illustrative aspect of another remedial measure that can be performed by a system of

[0015] FIG. 4B is a ladder diagram of an illustrative aspect of operations associated with a remedial measure of FIG. 4A

[0016] FIG. 5A is a diagram of another illustrative aspect of a system of FIG. 1

[0017] FIG. 5B is a diagram of a particular illustrative aspect of a remedial measure that can be performed by a system of FIG. 5A

[0018] FIG. 5C is a ladder diagram of an illustrative aspect of operations associated with a remedial measure of FIG. 5B

[0019] FIG. 5D is a ladder diagram of an illustrative aspect of operations of FIG. 5C

[0020] FIG. 6 is a diagram of a particular implementation of a method of host management of a flash memory with a shared write buffer that can be performed by a system of FIG. 1

[0021] FIG. 7 is a block diagram of a particular illustrative example of a device operable to perform host management of a flash memory with a shared write buffer in accordance with some examples of the present disclosure. DETAILED DESCRIPTION

[0022] Computing devices often incorporate functionality to store data and retrieve data from a flash memory device. For example, a host device can store audio, images, video, documents, etc. on a flash memory device. The flash memory device includes a first memory type of memory cells (e.g., triple level cells (TLC)) for storing data. The flash memory device can also include a shared write buffer of memory cells of a second memory type (e.g., single level cells (SLC)). In some examples, the memory cells of the first memory type can store more data, while writing to the memory cells of the second memory type is faster, so the memory cells of the first memory type are used as the main memory cells to increase storage capacity, and the memory cells of the second memory type are used as the shared write buffer to reduce write latency.​​​​​​

[0023] The main memory is partitioned into logical units for various purposes, such as wear leveling and managing different types of memory usage. Often, a shared write buffer can become unavailable for different reasons. For example, if the used capacity of a logical unit reaches a capacity threshold, the shared write buffer is disabled and the memory units of that shared write buffer are reassigned to the logical unit. As another example, if the memory units assigned to a shared write buffer wear out, the shared write buffer can become unavailable.

[0024] Systems and methods of performing host management of flash memory with shared write buffers are disclosed. A flash memory device maintains a performance metric of memory units. For example, the flash memory device maintains a utilization metric of a logical unit, a durability metric of a shared write buffer, or both. The performance metric can include a write count, a program cycle time, an available storage capacity, or a combination thereof.

[0025] The flash memory device transmits a notification to the host device in response to detecting that the performance metric exceeds a performance threshold, and the host device performs one or more remedial measures in response to receiving the notification. For example, in response to receiving a notification that the utilization of a particular logical unit has exceeded a capacity threshold, the host device selects a least-utilized logical unit and transmits a command to the flash memory device to reassign a portion of the least-utilized logical unit to the particular logical unit. In another example, in response to receiving a notification that the utilization of a particular logical unit has exceeded a capacity threshold, the host device transmits one or more commands to the flash memory device to reassign memory units of a shared write buffer to the particular logical unit and to reassign the portion of the least-utilized logical unit to the shared write buffer. In both of the above examples, reassigning the portion of the least-utilized logical unit provides the technical advantage of enabling the shared write buffer to remain available after detecting that another logical unit becomes full.

[0026] In another example, in response to receiving a notification that the used durability of a shared write buffer has exceeded a durability threshold, the host device selects a portion of a least-utilized logical unit and transmits one or more commands to the flash memory device to reassign memory units of the shared write buffer to the least-utilized logical unit and to reassign the portion of the least-utilized logical unit to the shared write buffer. Replacing the memory units of the shared write buffer with the portion of the least-utilized logical unit having greater remaining durability provides the technical advantage of extending the life of the shared write buffer.

[0027] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For example, FIG. 1 The diagram depicts an instruction that the shared write buffer 182 corresponds to one or more memory address ranges ( FIG. 1 A memory mapping table 180 (representing a “memory address range” 184) indicates that, in some respects, the shared write buffer 182 corresponds to a single memory address range 184 (e.g., a contiguous memory range), and in other respects, the shared write buffer 182 corresponds to multiple memory address ranges 184 (e.g., non-contiguous memory ranges). For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in singular or optional plural form (as indicated by “(multiple)”), unless the aspect relating to a multiple of features is described.

[0028] In some figures, multiple instances of a particular type of feature are used. Although these features are physically and / or logically different, the same reference numerals are used for each feature, and these different instances are distinguished by adding letters to the reference numerals. Reference numerals are used without distinguishing letters when a feature is referenced herein as a group or a type of feature (e.g., when a specific feature among these features is not referenced). However, reference numerals are used with distinguishing letters when a specific feature among multiple features of the same type is mentioned herein. For example, see reference... FIG. 1 Multiple logic units are illustrated and associated with reference numerals 168A, 168B, and 168C. ​​When referring to a specific logic unit among these logic units (such as logic unit 168A), the distinguishing letter "A" is used. However, when referring to any one of these logic units or referring to these logic units as a group, reference numeral 168 is used without the distinguishing letter.

[0029] As used herein, the term “comprise” can be used interchangeably with “include,” “comprise” or “have.” Additionally, the term “wherein” can be used interchangeably with “where.” As used herein, “exemplary” indicates an example, an implementation, and / or aspect, and should not be construed as limiting or as indicating a preference or a preferred implementation. As used herein, ordinal terms (e.g., “first,” “second,” “third,” etc.) are used primarily for purposes of description and do not necessarily indicate a particular priority or order. As used herein, the term “set” refers to one or more of a particular element, and the term “plural” refers to multiple (e.g., two or more) of a particular element.

[0030] As used herein, “coupled” can include “communicatively coupled,” “electrically coupled,” or “physically coupled,” and can also (or alternatively) include any combination thereof. Two devices (or components) can be coupled (e.g., communicatively coupled, electrically coupled, or physically coupled) directly or indirectly via one or more other devices, components, wires, buses, networks (e.g., a wired network, a wireless network, or a combination thereof), etc. As an illustrative, non-limiting example, two devices (or components) that are electrically coupled can be included in the same device, can be included in different devices, and can be connected via electronics, one or more connectors, or inductive coupling. In some implementations, two devices (or components) that are communicatively coupled (such as electrically communicating) can transmit and receive signals (e.g., digital signals or analog signals) directly or indirectly via one or more wires, buses, networks, etc. As used herein, “directly coupled” can include two devices that are coupled (e.g., communicatively coupled, electrically coupled, or physically coupled) without an intervening component.

[0031] In this disclosure, terms such as “determine,” “calculate,” “estimate,” “shift,” “adjust,” and the like can be used to describe how one or more operations are performed. It should be noted that such terms are not to be construed as limiting and other techniques can be utilized to perform similar operations. Additionally, as referred to herein, “obtain,” “generate,” “calculate,” “estimate,” “use,” “select,” “access,” and “determine” are used interchangeably. For example, “obtaining,” “generating,” “calculating,” “estimating,” or “determining” a parameter (or signal) can refer to actively generating, estimating, calculating, or determining the parameter (or signal), or can refer to using, selecting, or accessing a parameter (or signal) such as one that has been generated by another component or device.

[0032] Reference is made to FIG. 1FIG. 1 illustrates a system 100 configured to perform host management of a flash memory having a shared write buffer, according to at least one aspect of the present disclosure. The system 100 includes a host device 102 configured to be coupled to a flash memory device 104.

[0033] The flash memory device 104 includes a device controller 162 coupled to a flash memory 164 (e.g., NAND memory) including memory cells 192. The device controller 162 has access to a memory map table 180. For example, the memory map table 180 is stored in a portion of the flash memory 164 or in a static random access memory (SRAM) coupled to the device controller 162. In some implementations, the memory map table 180 corresponds to a logical to physical address mapping table.

[0034] The memory map table 180 is configured to indicate memory cells of the flash memory 164 that are allocated to the shared write buffer 182. For example, the memory map table 180 indicates that the shared write buffer 182 corresponds to one or more memory address ranges 184. A particular memory address range 184 indicates a corresponding subset of the memory cells 192.

[0035] The memory map table 180 is further configured to indicate memory cells of the flash memory 164 that are allocated to the logical units 168. For example, the memory map table 180 indicates that the logical unit 168A corresponds to one or more memory address ranges 190A, the logical unit 168B corresponds to one or more memory address ranges 190B, the logical unit 168C corresponds to one or more memory address ranges 190C, one or more additional logical units correspond to respective memory address ranges, or a combination thereof. Each particular memory address range 190 indicates a corresponding subset of the memory cells 192.

[0036] In particular aspects, each memory cell in a first subset of the memory cells 192 allocated to the logical units 168 has a first memory type (e.g., triple level cell (TLC)), and each memory cell in a second subset of the memory cells 192 allocated to the shared write buffer 182 has a second memory type (e.g., single level cell (SLC)). In particular aspects, the memory cells of the first memory type can store more data, while the memory cells of the second memory type correspond to lower write latency.

[0037] The device controller 162 is configured to perform write operations on the flash memory 164 in accordance with a write buffer mode 170 that indicates whether the flash memory device 104 is configured to use a shared write buffer 182. For example, when the write buffer mode 170 is enabled, the shared write buffer 182 is available and will be used as a temporary storage for data writes. In particular aspects, the write buffer mode 170 is set based on default data, configuration settings, user input, commands from the HCI 112, or a combination thereof. In particular aspects, an indicator of the write buffer mode 170 is stored in a portion of the flash memory 164, a register, or another type of data storage.

[0038] The device controller 162 is coupled to or includes a performance threshold register 172 that is configured to store a performance threshold. The performance threshold register 172 that stores the performance threshold is provided as an illustrative example; in other examples, another type of data storage can be used to store the performance threshold. The device controller 162 is configured to determine a performance metric 174 and generate a notification 176 based on determining that the performance metric 174 exceeds the performance threshold (e.g., by comparing the performance metric 174 to the value of the performance threshold register 172). As described further below, the performance metric 174 can correspond to one or more aspects of operations associated with the write buffer mode 170, such as an endurance estimate of the shared write buffer 182 or an amount of usage of one or more logical units 168 that can affect the shared write buffer 182, as illustrative, non-limiting examples.

[0039] The host device 102 includes a host controller interface (HCI) 112 that is configured to be coupled to the flash memory device 104. In one example, the HCI 112 is configured to communicate with the device controller 162 of the flash memory device 104. The HCI 112 is configured to perform a remedial measure 114 in response to receiving the notification 176. The remedial measure 114 can include transmitting one or more remedial measure commands 178 to the device controller 162. According to some implementations, the HCI 112 is configured to transmit one or more commands to the device controller 162 and the device controller 162 is configured to transmit responses to the commands received from the HCI 112.

[0040] In a particular implementation, the device controller 162 is configured to transmit the notification 176 further based on determining that the write buffer mode 170 is enabled. In this implementation, the device controller 162 refrains from transmitting the notification 176 when the write buffer mode 170 is disabled. In some aspects, in response to detecting a transition of the write buffer mode 170 from disabled to enabled, the device controller 162 performs the comparison of the performance metric 174 to the value of the performance threshold register 172 and generates the notification 176 based on the performance metric 174 exceeding the value of the performance threshold register 172.

[0041] In a particular implementation, the HCI 112 performs the remedial action 114 further based on determining that the write buffer mode 170 is enabled at the flash memory device 104. In this implementation, the HCI 112 refrains from performing the remedial action 114 when the write buffer mode 170 is disabled. In some aspects, in response to detecting a transition of the write buffer mode 170 from disabled to enabled and determining that the remedial action 114 has not been performed for a previously received notification 176, the HCI 112 performs the remedial action 114. For example, the device controller 162 transmits the notification 176 when the write buffer mode 170 is enabled, the write buffer mode 170 transitions from enabled to disabled before the HCI 112 performs the remedial action 114, and subsequently the write buffer mode 170 transitions from disabled to enabled. In this example, the HCI 112 holds the notification 176 as a pending notification when the corresponding remedial action 114 is not performed and performs the remedial action 114 in response to determining that the write buffer mode 170 has transitioned from disabled to enabled and the notification 176 is pending.

[0042] During operation, the device controller 162 updates the performance metric 174 and determines whether the performance metric 174 exceeds a performance threshold (e.g., the value of the performance threshold register 172), as described with reference to FIG. 2 and FIG. 5A are further described. In some implementations, the device controller 162 performs the comparison of the performance metric 174 to the value of the performance threshold register 172 based on determining that the write buffer mode 170 is enabled.

[0043] Example 150 depicts a write operation using the shared write buffer 182. The host device 102 (e.g., the HCI 112) transmits a write command 152 indicating data 154 to the flash memory device 104. In particular aspects, the write command 152 indicates that the data 154 is to be stored at a particular memory location of the logical unit 168B. In response to determining that the write buffer mode 170 is enabled, the flash memory device 104 (e.g., the device controller 162) stores the data 154 in the shared write buffer 182 and transmits a response 156 to the host device 102 indicating that the write was successful. In some implementations, the performance metric 174 corresponds to a used endurance of the shared write buffer 182 (e.g., an estimated decrease in the cell endurance based on write / erase cycles or an increase in the estimated lifetime used percentage), and the device controller 162 updates the performance metric 174 in response to storing the data 154 in the shared write buffer 182, as described with reference to FIG. 5A Further described. Writing to the shared write buffer 182 can be faster than writing to the logical unit 168B, thereby reducing latency between the host device 102 transmitting the data 154 to the flash memory device 104 and receiving the response 156.

[0044] At a later time, the flash memory device 104 (e.g., the device controller 162) stores the data 154 to the storage 186. For example, the storage 186 includes the logical unit 168, and the flash memory device 104 writes the data 154 from the shared write buffer 182 to the particular memory location of the logical unit 168B. In particular aspects, as part of performing a data refresh from the shared write buffer 182 to the storage 186, the flash memory device 104 writes the data 154 to the logical unit 168B.

[0045] In some implementations, the performance metric 174 corresponds to a used logical unit capacity of the logical unit 168, and the device controller 162 updates the performance metric 174 (e.g., the used capacity of the logical unit 168B) in response to storing the data 154 in the logical unit 168B, as described with reference to FIG. 2 Further described.

[0046] In response to determining that the performance metric 174 is updated, the device controller 162 determines whether the performance metric 174 exceeds a value of the performance threshold register 172, as described with reference to FIG. 2 , FIG. 3B , FIG. 5A and FIG. 5C Further described. The device controller 162 generates the notification 176 in response to determining that the performance metric 174 exceeds the value of the performance threshold register 172, as described with reference to FIG. 2 , FIG. 3B , FIG. 5Aand FIG. 5C Further, the notification 176 is communicated to the host device 102. In some implementations, the device controller 162 performs the comparison of the performance metric 174 to the value of the performance threshold register 172, generates the notification 176, communicates the notification 176 to the host device 102, or a combination thereof based on determining that the write buffer mode 170 is enabled.

[0047] The HCI 112 receives the notification 176 from the flash memory device 104 indicating that the value of the performance threshold register 172 has been exceeded while the write buffer mode 170 is enabled (e.g., indicating that the flash memory device 104 is configured to use the shared write buffer 182). In response to receiving the notification 176, the HCI 112 performs the remedial action 114, which includes reallocating a portion of the logical unit 168A, as described with reference to FIG. 2 to FIG. 5D Further description. The remedial action 114 includes communicating one or more remedial action commands 178 to the device controller 162 to initiate one or more operations at the device controller 162. In some implementations, the HCI 112 performs the remedial action 114 based on determining that the write buffer mode 170 is enabled.

[0048] In a particular example, the notification 176 indicates that the used capacity of the logical unit 168B exceeds a capacity threshold indicated by the value of the performance threshold register 172 while the write buffer mode 170 is enabled. In response to receiving the notification 176, the HCI 112 identifies the logical unit 168A as the least utilized logical unit of the logical units 168, as described with reference to FIG. 2 Further description. In some implementations, the one or more remedial action commands 178 indicate that a portion of the logical unit 168A is to be reallocated to the logical unit 168B, as described with reference to FIG. 2 to FIG. 3B Further description. In alternative implementations, the one or more remedial action commands 178 indicate that the portion of the logical unit 168A is to be reallocated to the shared write buffer 182 and that the memory address range 184 of the shared write buffer 182 is to be reallocated to the logical unit 168B, as described with reference to FIG. 2 and FIG. 4A to FIG. 4B Further description. The device controller 162 performs the operations indicated in the one or more remedial action commands 178.

[0049] In another particular example, the notification 176 indicates that the used endurance of the shared write buffer 182 exceeds an endurance threshold indicated by a value of the performance threshold register 172 while the write buffer mode 170 is enabled. In response to receiving the notification 176, the HCI 112 identifies the logical unit 168A as the least utilized logical unit of the logical units 168 and generates one or more remedial action commands 178 that indicate that a portion of the logical unit 168A is to be reassigned to the shared write buffer 182 and that the memory address range 184 of the shared write buffer 182 is to be reassigned to the logical unit 168A (or another logical unit), as described with reference to FIG. 1. FIG. 5A to FIG. 5D The device controller 162 performs the operations indicated in the one or more remedial action commands 178.

[0050] A technical advantage of performing the remedial action 114 includes enabling the shared write buffer 182 to remain in use after a logical unit 168 becomes full or a memory cell assigned to the shared write buffer 182 wears out. In one example, a portion of the logical unit 168A is assigned to the logical unit 168B that is becoming full, such that the shared write buffer 182 does not have to be reassigned to the logical unit 168B. In another example, a portion of the logical unit 168A is assigned to the shared write buffer 182, such that the shared write buffer 182 can remain available when memory of the shared write buffer 182 is reassigned to the logical unit 168B that is becoming full or when memory of the shared write buffer 182 is wearing out.

[0051] It should be appreciated that the particular order of operations in the above examples or other examples described herein are provided for purposes of example and not limitation. In other examples, two or more of the operations can be performed in another order. For purposes of example, in some examples, the one or more remedial action commands 178 can indicate that the portion of the logical unit 168A is to be reassigned to the shared write buffer 182 before the memory address range 184 of the shared write buffer 182 is reassigned to the logical unit 168B that is becoming full. In other examples, the one or more remedial action commands 178 can indicate that the memory address range 184 of the shared write buffer 182 is to be reassigned to the logical unit 168B before the portion of the logical unit 168A is reassigned to the shared write buffer 182.

[0052] Referring to FIG. 2 FIG. 2 shows particular illustrative aspects of a system 200 configured to perform host management of flash memory having a shared write buffer. In particular aspects, FIG. 1 The system 100 of FIG. 1 includes one or more components of the system 200.

[0053] In FIG. 2 The device controller 162 is configured to maintain a utilization metric 274 for the logical unit 168. For example, the device controller 162 maintains a utilization metric 274A, a utilization metric 274B, and a utilization metric 274C for the logical unit 168A, the logical unit 168B, and the logical unit 168C, respectively. The utilization metrics 274 corresponding to the three logical units are provided as an illustrative example; in other examples, the utilization metrics 274 can correspond to fewer than three or more than three logical units. In some implementations, the utilization metrics 274 are stored as a utilization array. In some aspects, the utilization metric 274 for the logical unit 168 is related to a storage capacity of the logical unit 168, such as an indication of a used storage capacity of the logical unit 168 or an available storage capacity of the logical unit 168. Alternatively or additionally, the utilization metric 274 for the logical unit 168 is related to a durability of memory cells associated with the logical unit, such as an indication of a program cycle time for the logical unit 168, a count of write commands to the logical unit 168, or a combination thereof, as referenced with respect to FIG. 2. FIG. 5A Further described.

[0054] The device controller 162 can access an indicator or setting associated with one or more configuration modes (e.g., the write buffer mode 170, the capacity exception attribute 254, the reserved user space mode 270, the configuration mode 278, one or more additional configuration modes, or a combination thereof). The configuration mode is based on default data, a configuration setting, a user input, a command from the host device 102, or a combination thereof. For example, in a particular implementation, the HCI 112 transmits a command to the flash memory device 104 to set (e.g., enable) the capacity exception attribute 254 (e.g., an exception event control attribute) to activate the generation of an alert corresponding to a logical unit capacity. The device controller 162 is configured to generate an exception event alert 276 in response to determining that the exception event status 256 indicates that the utilization metric 274 has exceeded the logical unit capacity threshold 272 when the capacity exception attribute 254 is enabled.

[0055] In some implementations, the logical unit capacity threshold 272 indicates a storage capacity threshold (e.g., a threshold percentage), and the utilization metric 274 of the logical unit 168 indicates a used storage capacity of the logical unit 168 (e.g., a percentage of used storage capacity). The device controller 162 increases the used storage capacity indicated by the utilization metric 274 based on data writes to the logical unit 168 (e.g., data writes to previously unused memory cells of the logical unit 168). The device controller 162 also increases the used storage capacity indicated by the utilization metric 274 based on removal of a portion of the logical unit 168 (e.g., because the portion is reassigned to another logical unit or reassigned to the shared write buffer 182). The device controller 162 decreases the used storage capacity indicated by the utilization metric 274 based on data erasures at the logical unit 168 (e.g., erasure of one or more memory cells of the logical unit 168). The device controller 162 also decreases the used storage capacity indicated by the utilization metric 274 based on addition of a portion to the logical unit 168 (e.g., because the portion is reassigned from another logical unit or from the shared write buffer 182). In particular aspects, the used storage capacity exceeding the storage capacity threshold indicates that the logical unit 168 is becoming full.

[0056] In some implementations, the logical unit capacity threshold 272 is stored in the performance threshold register 172. In other implementations, another type of data storage (e.g., a portion of the flash memory 164) is used to store the logical unit capacity threshold 272. In some aspects, a particular size (e.g., 1 byte) of data storage is used to store the logical unit capacity threshold 272. In some implementations, a first value of the logical unit capacity threshold 272 (e.g., 00 in hexadecimal) indicates that comparisons to the logical unit capacity threshold 272 are disabled. A second value of the logical unit capacity threshold 272 (e.g., 01-09 in hexadecimal) within a range indicates a corresponding used storage capacity threshold (e.g., 10-90%). A third value of the logical unit capacity threshold 272 (e.g., 0A in hexadecimal) indicates a corresponding used storage capacity threshold (e.g., 100%).

[0057] In some implementations, the same logical unit capacity threshold 272 is used for comparison with each of the utilization metrics 274 of the logical units 168. In alternative implementations, a first logical unit capacity threshold 272 can be used for comparison with the utilization metric 274A of the logical unit 168A, and a second logical unit capacity threshold 272 can be used for comparison with the utilization metric 274B of the logical unit 168B. To illustrate, the device controller 162 can assign different logical unit capacity thresholds 272 for different logical units 168 based on various criteria, such as the type of data stored at the logical unit.

[0058] The logical unit capacity threshold 272 is based on default data, configuration settings, user input, a command from the host device 102, or a combination thereof. For example, in a particular implementation, the HCI 112 transmits a command to the flash memory device 104 to set the logical unit capacity threshold 272 to a particular value.

[0059] In a particular aspect, the device controller 162 is configured to update the exceptional event status 256 in response to an update to the utilization metrics 274. For example, the device controller 162 is configured to update the exceptional event status 256 (e.g., set a particular exceptional event status attribute) to indicate that the logical unit 168B exceeds the logical unit capacity threshold 272 in response to determining that the utilization metric 274B is greater than the logical unit capacity threshold 272.

[0060] In some implementations, the reserve user space mode 270 is enabled to indicate that a portion of the least utilized logical unit is to be reallocated to the logical unit that is becoming full, as described with reference to FIG. 2. FIG. 3A to FIG. 3B Further description. In alternative implementations, the reserve user space mode 270 is enabled to indicate that when a particular logical unit is becoming full, memory units of the shared write buffer 182 are to be reallocated to the particular logical unit, and a portion of the least utilized logical unit is to be reallocated to the shared write buffer 182, as described with reference to FIG. 2. FIG. 4A to FIG. 4B Further description.

[0061] In some implementations, the configuration mode 278 enables the device controller 162 to selectively reallocate the portion of the least utilized logical unit to the logical unit that is becoming full or to the shared write buffer 182 when the reserve user space mode 270 is enabled. For example, the configuration mode 278 is enabled to indicate that the portion of the least utilized logical unit is to be reallocated to the logical unit that is becoming full when the reserve user space mode 270 is enabled, as described with reference to FIG. 2. FIG. 3A to FIG. 3BThe configuration mode 278 is disabled to indicate that when the reserved user space mode 270 is enabled, memory cells of the shared write buffer 182 will be reassigned to the logical units that are running low, and the portion of the least utilized logical unit will be reassigned to the shared write buffer 182, as described with reference to FIG. 2. In these implementations, the configuration mode 278 is disabled to indicate that when the reserved user space mode 270 is enabled, memory cells of the shared write buffer 182 will be reassigned to the logical units that are running low, and the portion of the least utilized logical unit will be reassigned to the shared write buffer 182, as described with reference to FIG. 4A to FIG. 4B Further described.

[0062] During operation, the HCI 112 transmits a command to the flash memory device 104 to set the capacity exception attribute 254 to activate alert generation corresponding to logical unit (LU) capacity. In some implementations, the HCI 112 also transmits a command to the flash memory device 104 to enable the reserved user space mode 270 and a command to indicate whether the configuration mode 278 is enabled. Subsequently, in response to determining that the capacity exception attribute 254 indicates that alert generation is activated and the exception event status 256 indicates that the utilization metric 274B exceeds the logical unit capacity threshold 272, the device controller 162 generates an exception event alert 276 indicating that the utilization of the logical unit 168B has exceeded the logical unit capacity threshold 272. In particular aspects, the device controller 162 further generates the exception event alert 276 based on determining that the write buffer mode 170 is enabled and the reserved user space mode 270 is enabled. In particular aspects, the logical unit capacity threshold 272 corresponds to the value of the performance threshold register 172, and the exception event alert 276 corresponds to the notification 176. The device controller 162 transmits the exception event alert 276 to the host device 102.

[0063] The HCI 112 performs remedial measures 114 in response to receiving the exception event alert 276 indicating that the utilization of the logical unit 168B exceeds the logical unit capacity threshold 272 when the write buffer mode 170 is enabled and the reserved user space mode 270 is enabled. The HCI 112 generates one or more remedial measures commands 178 based on the utilization metric 264. In one example, the utilization metric 264 includes the utilization metric 264A of the logical unit 168A, the utilization metric 264B of the logical unit 168B, the utilization metric 264C of the logical unit 168C, one or more additional utilization metrics of one or more respective logical units 168, or a combination thereof.

[0064] In some implementations, the utilization metric 264 is a copy of the utilization metric 274, and the HCI 112 receives the utilization metric 264 from the device controller 162 at the same time as receiving the exception event alert 276.

[0065] In some implementations, the utilization metrics 264 are generated and maintained by the HCI 112. For example, the HCI 112 maintains the utilization metrics 264 as an array of utilization metrics that indicate parameters that are detectable at the host device 102, such as a write frequency, a command queue entry, and the like. In a particular aspect, the write frequency is based on a count of write commands for the logical unit 168 that are transmitted by the HCI 112 to the flash memory device 104 over time. In a particular aspect, the command queue entry indicates a count of write commands for the logical unit 168 that are queued for transmission to the flash memory device 104.

[0066] The utilization metrics 264 indicate used storage capacity for the logical unit 168. For example, the HCI 112 can increase or decrease the used storage indicated by the utilization metric 264A based on transmitting an erase command or a write command for the logical unit 168A to the flash memory device 104. As another example, the HCI 112 can increase or decrease the used storage indicated by the utilization metric 264A based on write commands for the logical unit 168A that are queued for transmission to the flash memory device 104, such as.

[0067] The HCI 112 increases the used storage capacity indicated by the utilization metrics 264 based on removal of a portion of the logical unit 168 (e.g., because the portion is reassigned to another logical unit or reassigned to the shared write buffer 182). The HCI 112 decreases the used storage capacity indicated by the utilization metrics 264 based on addition of a portion to the logical unit 168 (e.g., because the portion is reassigned from another logical unit or from the shared write buffer 182).

[0068] In some implementations, the utilization metrics 264 also indicate used endurance for the logical unit 168, as described with reference to FIG. 2B. FIG. 5A Further described. For example, the utilization metric 264A can be based on parameters such as a write frequency, a count of program cycles, a program cycle time, and the like. To illustrate, the HCI 112 can increase the used endurance indicated by the utilization metric 264A based on a count of write commands for the logical unit 168A that are transmitted or queued for transmission to the flash memory device 104. In some implementations, the HCI 112 can update the used endurance based on a program cycle time for the logical unit 168.

[0069] The HCI 112 determines that the logical unit 168A corresponds to the least utilized logical unit among the logical units 168 based on the utilization metrics 264 (e.g., values of the utilization array). For example, in response to determining that the utilization metric 264A indicates the lowest used storage capacity (or the largest available storage capacity) among the utilization metrics 264, the HCI 112 identifies the logical unit 168A as the least utilized logical unit. In another example, in response to determining that the utilization metric 264A indicates the used storage capacity and the used endurance corresponding to the lowest combined value (e.g., the lowest weighted average value) among the utilization metrics 264, the HCI 112 identifies the logical unit 168A as the least utilized logical unit, as referenced in FIG. 5A Further described.

[0070] In the example 250, the HCI 112 selects a portion 252 (e.g., the least utilized logical unit) of the logical unit 168A. In a particular aspect, the portion 252 includes unused memory units corresponding to a memory address range 190AA included in the memory address range 190A of the logical unit 168A. In a particular aspect, a size (e.g., a count of unused memory units) of the portion 252 is based on a default data, a configuration setting, a user input, an available storage capacity of the logical unit 168A, or a combination thereof. The HCI 112 performs the remedial action 114 including reallocating the portion 252, as referenced in FIG. 3A to FIG. 4B Further described.

[0071] Referring to FIG. 3A , a diagram of an example 300 of a remedial action 114 that can be performed by the system 200 of FIG. 2 The remedial action 114 includes reallocating the portion 252 to the logical unit 168B.

[0072] In one example, FIG. 2 The HCI 112 of the system 200 of FIG. 3B Further described. In some aspects, the HCI 112 performs the remedial action 114 to reallocate the portion 252 to the logical unit 168B based at least in part on determining that each of the write buffer mode 170, the reserved user space mode 270, and the configuration mode 278 is enabled.

[0073] In a particular aspect, the device controller 162 updates the utilization metrics 274A and 274B based on reallocating memory cells corresponding to the memory address range 190AA from the logical unit 168A to the logical unit 168B. In a particular aspect, the updated utilization metric 274B no longer exceeds (e.g., is less than or equal to) the logical unit capacity threshold 272. Accordingly, when the reserved user space mode 270 is enabled, the host device 102 can circumvent a default mechanism of the system 200 (e.g., by making the shared write buffer 182 unavailable by reallocating memory cells of the shared write buffer 182 to a full logical unit in accordance with a Universal Flash Storage (UFS) standard), thereby preventing the logical unit 168 from running out of space.

[0074] Reference is made to FIG. 3B FIG. 10 shows a ladder diagram of illustrative aspects of operations 350 associated with the remedial action 114 of FIG. 3A In a particular aspect, one or more of the operations 350 are performed by the HCI 112, the host device 102, the device controller 162, the flash memory 164, the flash memory device 104, FIG. 1 the system 100 of FIG. 2 the system 200 of or a combination thereof.

[0075] An example of an operation corresponding to the LU capacity threshold 352 being reached is illustrated. For example, the HCI 112 transmits a write command 152A to the flash memory device 104. In some implementations, the HCI 112 updates the utilization metric 264 at the same time as the write command 152A is transmitted to the flash memory device 104. For example, the write command 152A indicates that data is to be written to the logical unit 168B, and the HCI 112 updates the utilization metric 264B of the logical unit 168B (e.g., a count of write commands, a used storage capacity, a count of program loops, a program loop time, or a combination thereof).

[0076] In response to receiving the write command 152A and determining that the write buffer mode 170 is enabled, the device controller 162 configures the performance threshold register 172 to set the logical unit capacity threshold 272 (e.g., a pre-determined threshold), configures the capacity exception attribute 254 to activate the alert generation corresponding to the logical unit capacity, and stores the data indicated in the write command 152A to the shared write buffer 182. In response to storing the data in the shared write buffer 182, the device controller 162 transmits a response 156A to the HCI 112 indicating that the data write was successful.

[0077] In particular aspects, the HCI 112 transmits one or more additional commands to the device controller 162 and receives corresponding responses from the device controller 162 prior to flushing data from the shared write buffer 182. For example, the HCI 112 transmits a write command 152B to the device controller 162 and updates the utilization metric 264. In response to receiving the write command 152B, the device controller 162 stores the data indicated in the write command 152B to the shared write buffer 182 and transmits a response 156B to the HCI 112. The device controller 162 flushes the data from the shared write buffer 182 to the corresponding logical unit 168 and updates the utilization metric 274. For example, the device controller 162 writes the data of the write command 152B to one or more memory cells of the logical unit 168B and updates the utilization metric 274B of the logical unit 168B (e.g., a count of write commands, a used storage capacity, a count of program cycles, a program cycle time, or a combination thereof).

[0078] In particular aspects, the device controller 162 updates the exception event status 256 based on a comparison of the utilization metric 274 to the logical unit capacity threshold 272. For example, in response to determining that the utilization metric 274B exceeds the logical unit capacity threshold 272, the device controller 162 updates the exception event status 256 to indicate that the utilization of the logical unit 168B exceeds the logical unit capacity threshold 272. In response to determining that the exception event status 256 indicates that the utilization of the logical unit 168B exceeds the logical unit capacity threshold 272, the reserved user space mode 270 is enabled, and the capacity exception attribute 254 indicates that alert generation is activated, the device controller 162 transmits an exception event alert 276 to the HCI 112 indicating that the capacity of the logical unit 168B has exceeded the logical unit capacity threshold 272.

[0079] The HCI 112 performs a remedial measure 114 in response to receiving the exception event alert 276. For example, the HCI 112 identifies the logical unit 168A as a least utilized logical unit based on the utilization metric 264 and selects the portion 252 of the logical unit 168A as described with reference to FIG. 2

[0080] ​In some aspects, HCI 112 selects a remedial action 114 to perform based on determining that the reserve user space mode 270 and the configuration mode 278 are enabled. HCI 112 transmits an unmap command 306 to flash memory device 104 to unmap portion 252 from logical unit 168A. In response to receiving the unmap command 306, device controller 162 updates memory mapping table 180 to remove memory address range 190AA of portion 252 from logical unit 168A. Device controller 162 transmits a response 308 to host device 102 indicating that the unmap command was successfully performed. In particular aspects, device controller 162 and HCI 112 update utilization metric 274A and utilization metric 264A, respectively, corresponding to the removal of memory address range 190AA from logical unit 168A, as described with reference to FIG. 2

[0081] HCI 112 transmits a map command 310 to flash memory device 104 to map portion 252 to logical unit 168B. In response to receiving the map command 310, device controller 162 updates memory mapping table 180 to add memory address range 190AA to memory address range 190B of logical unit 168B and transmits a response 312 to host device 102 indicating that the map command was successfully performed. Thus, HCI 112 reallocates portion 252 of logical unit 168A to logical unit 168B.

[0082] In particular aspects, device controller 162 and HCI 112 update utilization metric 274B and utilization metric 264B, respectively, corresponding to the addition of memory address range 190AA to logical unit 168B, as described with reference to FIG. 2 In particular aspects, the updated utilization metric 274B no longer exceeds the logical unit capacity threshold 272.

[0083] Thus, operation 350 enables reallocating portion 252 from a least-utilized logical unit to a logical unit 168B that is becoming full. The technique of reallocating portion 252 (rather than shared write buffer 182) to logical unit 168B has the technical advantage of enabling shared write buffer 182 to remain in use.

[0084] Referring to FIG. 4A , a diagram of an example 400 of remedial actions 114 that can be performed by system 200 is shown. Remedial actions 114 include reallocating portion 252 to shared write buffer 182. FIG. 2

[0085] In one example, FIG. 2 ​​HCI 112 performs remedial action 114, which includes transmitting one or more remedial action commands 178 to device controller 162 to refresh data from shared write buffer 182, reallocating portion 252 corresponding to memory address range 190AA from logic unit 168A to shared write buffer 182, and reallocating memory address range 184 from shared write buffer 182 to logic unit 168B, as referenced. FIG. 4B Further description. In some respects, HCI 112 performs remedy 114 to reallocate portion 252 to shared write buffer 182, based at least in part on the determination that write buffer mode 170 is enabled, reserved user space mode 270 is enabled, and configuration mode 278 is disabled.

[0086] In response to receiving a refresh command, device controller 162 stores data from shared write buffer 182 to the corresponding logical cell and updates utilization metric 274. In response to reassigning memory address range 190AA from logical cell 168A to shared write buffer 182, device controller 162 updates utilization metric 274A based on removing the memory cell corresponding to memory address range 190AA from logical cell 168A.

[0087] In response to reassigning memory address range 184 from shared write buffer 182 to logical cell 168B, device controller 162 updates utilization metric 274B based on adding memory cells corresponding to memory address range 184 to logical cell 168B. In a specific aspect, the updated utilization metric 274B no longer exceeds (e.g., is less than or equal to) logical cell capacity threshold 272. Therefore, when reserved user space mode 270 is enabled, host device 102 can circumvent the default mechanism of system 200 (e.g., making shared write buffer 182 unavailable by reassigning memory cells of shared write buffer 182 to full logical cells according to the UFS standard), thereby preventing logical cell 168 from running out of space.

[0088] refer to FIG. 4B It shows the relationship with FIG. 4A The ladder diagram illustrates an exemplary aspect of operation 450 associated with remedy 114. In a particular aspect, one or more operations in operation 450 are controlled by HCI 112, host device 102, device controller 162, flash memory 164, flash memory device 104, ... FIG. 1 System 100 FIG. 2 The system 200 or a combination thereof is used to execute.

[0089] Remedial action 114 is performed after the LU capacity threshold 352 has been reached. In some aspects, HCI 112 selects the remedial action 114 to perform based on determining that the reserve user space mode 270 is enabled and the configuration mode 278 is disabled. Remedial action 114 includes reallocating a portion of the least utilized logical unit to the shared write buffer at block 420. For example, HCI 112 transmits a flush command 402 to the flash memory device 104. In response to receiving the flush command 402, the device controller 162 flushes data from the shared write buffer 182 to the corresponding logical unit 168 and updates the utilization metric 274 as described with reference to FIG. 2 After the data is written to the corresponding logical unit 168, the device controller 162 transmits a response 403 to the host device 102 indicating that the data from the shared write buffer 182 has been successfully flushed.

[0090] HCI 112 transmits an unmap command 404 to the flash memory device 104 indicating that the portion 252 is to be unmapped from the logical unit 168A. In response to the unmap command 404, the device controller 162 updates the memory mapping table 180 to remove the memory address range 190AA of the portion 252 from the logical unit 168A. The device controller 162 transmits a response 405 to the host device 102 indicating that the unmap command has been successfully executed. In particular aspects, the device controller 162 and HCI 112 update the utilization metric 274A and utilization metric 264A, respectively, corresponding to the removal of the memory address range 190AA from the logical unit 168A as described with reference to FIG. 2

[0091] HCI 112 transmits a convert command 406 to the flash memory device 104 to convert the memory address range 190AA from a first memory type (e.g., TLC) to a second memory type (e.g., SLC). In response to receiving the convert command 406, the device controller 162 converts the memory cells corresponding to the memory address range 190AA from having the first memory type to the second memory type and transmits a response 407 indicating that the convert command has been successfully executed.

[0092] HCI 112 transmits a map command 408 to the flash memory device 104 to map the portion 252 to the shared write buffer 182. In response to receiving the map command 408, the device controller 162 updates the memory mapping table 180 to add a memory address range 190AA corresponding to the shared write buffer 182 (in addition to the memory address range 184) and transmits a response 410 to the host device 102 indicating that the map command has been successfully executed. Thus, HCI 112 reallocates the portion 252 of the logical unit 168A to be used as the shared write buffer 182.​

[0093] The remedial action 114 also includes re-allocating the memory address range 184 of the shared write buffer 182 to the logical unit 168B at block 422. The HCI 112 transmits a unmap command 412 to the flash memory device 104 that indicates the memory address range 184 is to be un-mapped from the shared write buffer 182. In response to receiving the unmap command 412, the device controller 162 updates the memory mapping table 180 to remove the memory address range 184 from the shared write buffer 182. The device controller 162 transmits a response 413 to the host device 102 indicating that the unmap command has been successfully executed.

[0094] The HCI 112 transmits a convert command 414 to the flash memory device 104 to convert the memory address range 184 from a second memory type (e.g., SLC) to a first memory type (e.g., TLC). In response to receiving the convert command 414, the device controller 162 converts the memory cells corresponding to the memory address range 184 from having the second memory type to the first memory type, and transmits a response 415 to the host device 102 indicating that the convert command has been successfully executed.

[0095] The HCI 112 transmits a map command 416 to the flash memory device 104 to map the memory address range 184 to the logical unit 168B. In response to receiving the map command 416, the device controller 162 updates the memory address range 190B indicated in the memory mapping table 180 as corresponding to the logical unit 168B to include the memory address range 184, and transmits a response 418 to the host device 102 indicating that the map command has been successfully executed. Thus, the HCI 112 re-allocates the memory (e.g., corresponding to the memory address range 184) of the shared write buffer 182 to the logical unit 168B.

[0096] In particular aspects, the device controller 162 and the HCI 112 update the utilization metric 274B and the utilization metric 264B, respectively, corresponding to the addition of the memory address range 184 to the logical unit 168B, as described with reference to FIG. 2 In particular aspects, the updated utilization metric 274B no longer exceeds the logical unit capacity threshold 272.

[0097] Accordingly, operation 450 enables re-allocating the portion 252 from the least utilized logical unit to the shared write buffer 182 and re-allocating the memory address range 184 from the shared write buffer 182 to the logical unit 168B that is becoming full. The technical advantage of re-allocating the portion 252 to the shared write buffer 182 includes enabling the shared write buffer 182 to remain in use after re-allocating the memory address range 184 to the logical unit 168B.

[0098] Referring to FIG. 5A FIG. 5 illustrates certain example aspects of a system 500 configured to perform host management of a flash memory having a shared write buffer. In certain aspects, FIG. 1 The system 100 of FIG. 1 includes one or more components of the system 500.

[0099] The device controller 162 is configured to track a used shared write buffer endurance 574 of the shared write buffer 182. In some aspects, the used shared write buffer endurance 574 indicates a program cycle time of the shared write buffer 182, a count of write commands to the shared write buffer 182, or program / erase (P / E) cycles performed at the shared write buffer, or a combination thereof.

[0100] The device controller 162 has access to one or more configuration modes, such as the write buffer mode 170, the endurance exception attribute 554, the reserved shared write buffer mode 570, one or more additional configuration modes, or a combination thereof. The configuration modes are based on default data, configuration settings, user input, commands from the host device 102, or a combination thereof. For example, in a particular implementation, the HCI 112 transmits a command to the flash memory device 104 to set (e.g., enable) the endurance exception attribute 554 (e.g., an exception event control attribute) to activate the generation of an alert corresponding to the shared write buffer endurance. The device controller 162 is configured to generate an exception event alert 576 when the endurance exception attribute 554 is enabled in response to determining that the exception event status 556 indicates that the used shared write buffer endurance 574 has exceeded the shared write buffer endurance threshold 572.

[0101] The shared write buffer endurance threshold 572 indicates an endurance threshold (e.g., a threshold percentage), and the used shared write buffer endurance 574 indicates a used endurance (e.g., a percentage of an estimated endurance or lifetime) of the shared write buffer 182.

[0102] In some implementations, the shared write buffer endurance threshold 572 indicates a program cycle time threshold (e.g., a threshold duration), and the used shared write buffer endurance 574 indicates a program cycle time of the shared write buffer 182 (e.g., a detected program cycle time). The device controller 162 updates the program cycle time indicated by the used shared write buffer endurance 574 based on a program cycle time associated with a data write to the shared write buffer 182. In some implementations, the device controller 162 updates the used shared write buffer endurance 574 to indicate a most recent program cycle time of any memory cell to which data was written to the shared write buffer 182. In some implementations, the device controller 162 updates the used shared write buffer endurance 574 based on a previous program cycle time indicated by the used shared write buffer endurance 574 and a most recent program cycle time detected by the device controller 162 (e.g., a weighted sum of the previous program cycle time and the most recent program cycle time). In some implementations, the device controller 162 tracks program cycle times of memory cells 192 of the flash memory 164 and updates the used shared write buffer endurance 574 based on program cycle times of a subset of memory cells 192 included in the shared write buffer 182. For example, the device controller 162 updates the program cycle time indicated by the used shared write buffer endurance 574 based on adding or removing a portion to or from the shared write buffer 182. In a particular aspect, the program cycle time exceeding the program cycle time threshold indicates that the shared write buffer 182 is being worn out.

[0103] In some implementations, the shared write buffer endurance threshold 572 indicates a program cycle count threshold (e.g., a threshold count), and the used shared write buffer endurance 574 indicates a count of program cycles performed at memory cells allocated to the shared write buffer 182. The device controller 162 updates the count of program cycles indicated by the used shared write buffer endurance 574 based on an erase or write to a memory cell of the shared write buffer 182 (e.g., increments it by one). In some implementations, the device controller 162 tracks a count of program cycles performed at memory cells 192 of the flash memory 164 and updates the used shared write buffer endurance 574 based on a count of program cycles of a subset of memory cells 192 included in the shared write buffer 182. In one example, the device controller 162 updates the count of program cycles indicated by the used shared write buffer endurance 574 based on adding or removing a portion to or from the shared write buffer 182. In a particular aspect, the count of program cycles exceeding the program cycle count threshold indicates that the shared write buffer 182 is being worn out.

[0104] In some implementations, the shared write buffer endurance threshold 572 is stored in the performance threshold register 172. In other implementations, another type of data storage device (e.g., a portion of the flash memory 164) is used to store the shared write buffer endurance threshold 572. In some aspects, a particular size (e.g., 1 byte) of data storage device is used to store the shared write buffer endurance threshold 572. In some implementations, a first value of the shared write buffer endurance threshold 572 (e.g., 00 in hexadecimal) indicates that comparisons to the shared write buffer endurance threshold 572 are disabled. A second value of the shared write buffer endurance threshold 572 (e.g., 01-09 in hexadecimal) within a range indicates a corresponding used endurance threshold (e.g., 10-90%). A third value of the shared write buffer endurance threshold 572 (e.g., 0A in hexadecimal) indicates a corresponding used endurance threshold (e.g., 100%). In particular aspects, a particular program cycle time corresponds to a worn-out memory cell, and the shared write buffer endurance threshold 572 (e.g., 08 in hexadecimal) indicates that a particular percentage (e.g., 80%) of the particular program cycle time corresponds to a used endurance threshold. In particular aspects, a particular program cycle count corresponds to a worn-out memory cell, and the shared write buffer endurance threshold 572 (e.g., 08 in hexadecimal) indicates that a particular percentage (e.g., 80%) of the particular program cycle count corresponds to a used endurance threshold.

[0105] The shared write buffer endurance threshold 572 is based on default data, configuration settings, user input, commands from the host device 102, or a combination thereof. For example, in particular implementations, the HCI 112 transmits a command to the flash memory device 104 to set the shared write buffer endurance threshold 572 to a particular value.

[0106] In particular aspects, the device controller 162 is configured to update the exception event status 556 in response to an update to the used shared write buffer endurance 574. For example, the device controller 162 is configured to update the exception event status 556 (e.g., set a particular exception event status attribute) to indicate that the shared write buffer 182 exceeds the shared write buffer endurance threshold 572 in response to determining that the used shared write buffer endurance 574 is greater than the shared write buffer endurance threshold 572.

[0107] In some implementations, the reserve shared write buffer mode 570 is enabled to indicate that a portion of the least utilized logical units will be reallocated to the shared write buffer 182 if the shared write buffer 182 is being worn out, as referenced in FIG. 5B to FIG. 5DFurther description. In some implementations, the reserve shared write buffer mode 570 is disabled to indicate that re-allocating a portion of the logical units to the shared write buffer 182 is disabled when the shared write buffer 182 is being consumed.

[0108] During operation, the HCI 112 transmits a command to the flash memory device 104 to set the endurance exception attribute 554 to activate alert generation corresponding to shared write buffer endurance. In some implementations, the HCI 112 also transmits a command to enable the reserve shared write buffer mode 570. Subsequently, in response to determining that the endurance exception attribute 554 indicates that alert generation is activated and the exception event status 556 indicates that the used shared write buffer endurance 574 has exceeded the shared write buffer endurance threshold 572, the device controller 162 generates an exception event alert 576 indicating that the used endurance of the shared write buffer 182 has exceeded the shared write buffer endurance threshold 572. In particular aspects, the device controller 162 also generates the exception event alert 576 based on determining that each of the write buffer mode 170 and the reserve shared write buffer mode 570 are enabled. In particular aspects, the shared write buffer endurance threshold 572 corresponds to the value of the performance threshold register 172, and the exception event alert 576 corresponds to the notification 176. The device controller 162 transmits the exception event alert 576 to the host device 102.

[0109] When the write buffer mode 170 and the reserve shared write buffer mode 570 are enabled, the HCI 112 performs a remedial action 114 in response to receiving the exception event alert 576 indicating that the endurance of the shared write buffer 182 exceeds the shared write buffer endurance threshold 572. The HCI 112 generates one or more remedial action commands 178 based on the utilization metric 264. In some implementations, the utilization metric 264 is a copy of the utilization metric 274, and the HCI 112 receives the utilization metric 264 from the device controller 162 at the same time as receiving the exception event alert 576. In some implementations, the utilization metric 264 is generated and maintained by the HCI 112. The utilization metric 264 can indicate the used storage capacity of the logical units 168, and can also indicate the used endurance of the logical units 168, as described with reference to FIG. 2

[0110] The HCI 112 determines that the logical unit 168A corresponds to the least utilized logical unit of the logical units 168 based on the utilization metric 264, as described with reference to FIG. 2 ​Described. For example, the HCI 112 determines that the logical unit 168A corresponds to the least utilized logical unit based on determining that the value indicated by the utilization metric 264A is lowest among the utilization metrics 264. In particular aspects, the utilization metric 264A indicates a count of write commands to the logical unit 168A, a program cycle count of the logical unit 168A, a program cycle time of the logical unit 168A, an available storage capacity of the logical unit 168A, or a combination thereof.

[0111] In some implementations, the utilization metric 264A indicates a used endurance (or available endurance) of the logical unit 168A and a used storage capacity (or available storage capacity) of the logical unit 168A, and the HCI 112 determines that the logical unit 168A corresponds to the least utilized logical unit based on a combined value of the used endurance and the used storage capacity. For example, the count of write commands to the logical unit 168A, the program cycle count of the logical unit 168A, the program cycle time of the logical unit 168A, or a combination thereof indicates the used endurance.

[0112] In the example 550, the HCI 112 selects the portion 252 of the logical unit 168A (e.g., the least utilized logical unit). In particular aspects, the portion 252 corresponds to unused memory units corresponding to a memory address range 190AA included in the memory address range 190A of the logical unit 168A. The HCI 112 performs the remedial action 114 including reallocating the portion 252 to the shared write buffer 182, as described with reference to FIG. 5B to FIG. 5D Further described.

[0113] Referring to FIG. 5B , an example 520 of a remedial action 114 that can be performed by the system 500 of FIG. 5A is shown. The remedial action 114 includes reallocating the portion 252 to the shared write buffer 182.

[0114] In particular aspects, FIG. 2 The HCI 112 of the system 500 performs the remedial action 114 including transmitting one or more remedial action commands 178 to the device controller 162 to reallocate the portion 252 corresponding to the memory address range 190AA from the logical unit 168A to the shared write buffer 182, as described with reference to FIG. 2 The HCI 112 of the system 500 performs the remedial action 114 including transmitting one or more remedial action commands 178 to the device controller 162 to reallocate the portion 252 corresponding to the memory address range 190AA from the logical unit 168A to the shared write buffer 182, as described with reference to FIG. 5CFurther description. In some implementations, the remedial action 114 further includes transmitting a remedial action command 178 to the device controller 162 to re-allocate the memory address range 184 from the shared write buffer 182 to the logical unit 168A or another logical unit, as described with reference to FIG. 5C Further description.

[0115] In particular aspects, the device controller 162 updates the utilization metric 274A and the used shared write buffer endurance 574 based on re-allocating memory cells corresponding to the memory address range 190AA from the logical unit 168A to the shared write buffer 182, re-allocating memory cells corresponding to the memory address range 184 from the shared write buffer 182 to the logical unit 168A, or both. In particular aspects, the updated used shared write buffer endurance 574 no longer exceeds (e.g., is less than or equal to) the shared write buffer endurance threshold 572.

[0116] Referring to FIG. 5C to FIG. 5D , a ladder diagram illustrating exemplary aspects of operations 540 associated with the remedial action 114 of FIG. 5B In particular aspects, one or more of the operations 540 are performed by the HCI 112, the host device 102, the device controller 162, the flash memory 164, the flash memory device 104, FIG. 1 the system 100 of FIG. 5A the system 500 of

[0117] An example of operations corresponding to the reached shared write buffer endurance threshold 552 is illustrated. For example, the HCI 112 transmits a write command 152A to the device controller 162. In some implementations, the HCI 112 updates the utilization metric 264 at the same time as transmitting the write command 152A. For example, the write command 152A indicates that data is to be written to the logical unit 168B, and the HCI 112 updates the utilization metric 264B of the logical unit 168B (e.g., a count of write commands, a used storage capacity, or both).

[0118] In response to receiving the write command 152A and determining that the write buffer mode 170 is enabled, the device controller 162 configures the performance threshold register 172 to set the shared write buffer endurance threshold 572 (e.g., a pre-determined threshold), configures the endurance exception attribute 554 to activate the generation of an alert corresponding to the used shared write buffer endurance, and stores the data indicated in the write command 152A to the shared write buffer 182.

[0119] In some implementations, in response to receiving command 152A, device controller 162 sets one or more additional configuration modes (e.g., logical unit capacity threshold 272, capacity anomaly attribute 254, or both), as referenced. FIG. 3B As described. For example, a shared write buffer endurance threshold 572 is stored in a first performance threshold register 172, and a logic cell capacity threshold 272 is stored in a second performance threshold register 172. In some implementations, both the capacity anomaly attribute 254 and the endurance anomaly attribute 554 may be enabled simultaneously. For example, HCI 112 is configured to perform a reference in response to receiving an anomaly event alarm 276. FIG. 2 to FIG. 4B The described remedial action 114 is performed in response to receiving an anomaly event alarm 576, and references are executed. FIG. 5A to FIG. 5D The remedy described is 114.

[0120] Device controller 162 updates the used shared write buffer durability 574 based on writing data to shared write buffer 182. For example, in response to writing data to shared write buffer 182, device controller 162 updates the count of program cycles, program cycle time, or a combination thereof as indicated by the used shared write buffer durability 574.

[0121] In a specific aspect, device controller 162 updates the exception event state 556 based on a comparison of the used shared write buffer durability 574 with the shared write buffer durability threshold 572. For example, in response to determining that the used shared write buffer durability 574 has not exceeded the shared write buffer durability threshold 572, device controller 162 sets exception event state 556 to indicate that the used durability of shared write buffer 182 has not exceeded the shared write buffer durability threshold 572, and avoids generating exception event alarm 576. In response to storing data in shared write buffer 182, device controller 162 sends a response 156A to HCI 112 indicating that the data write was successful.

[0122] In certain aspects, HCI 112 transmits one or more additional commands to device controller 162 and receives corresponding responses from device controller 162. For example, HCI 112 transmits write command 152B to device controller 162 and updates utilization metric 264. In response to receiving write command 152B, device controller 162 stores the data indicated in write command 152B into shared write buffer 182, updates used shared write buffer durability 574, and transmits response 156B to HCI 112.

[0123] In particular aspects, the device controller 162 updates the exception event status 556 based on a comparison of the used shared write buffer endurance 574 to the shared write buffer endurance threshold 572. For example, in response to determining that the used shared write buffer endurance 574 exceeds the shared write buffer endurance threshold 572, the device controller 162 updates the exception event status 556 to indicate that the used endurance of the shared write buffer 182 exceeds the shared write buffer endurance threshold 572. In response to determining that the exception event status 556 indicates that the used endurance of the shared write buffer 182 exceeds the shared write buffer endurance threshold 572, the reserve shared write buffer mode 570 is enabled, and the endurance exception attribute 554 indicates that alert generation is activated, the device controller 162 transmits an exception event alert 576 to the HCI 112 indicating that the used endurance of the shared write buffer 182 has exceeded the shared write buffer endurance threshold 572.

[0124] The HCI 112 performs a remedial action 114 in response to receiving the exception event alert 576. In particular aspects, the HCI 112 performs the remedial action 114 based at least in part on determining that the reserve shared write buffer mode 570 is enabled. In particular aspects, the HCI 112 performs the remedial action 114 based at least in part on determining that the endurance exception attribute 554 indicates that alert generation is activated. FIG. 5D In particular aspects, the remedial action 114 includes reallocating a portion of the least utilized logical unit to the shared write buffer at block 420, as described with reference to FIG. 4. The device controller 162 also updates the used shared write buffer endurance 574 based on the update to the shared write buffer 182. For example, in response to performing the flush command 402, the device controller 162 updates the used shared write buffer endurance 574 corresponding to the erasure of the shared write buffer 182, as described with reference to FIG. 4. As another example, in response to performing the map command 408, the device controller 162 updates the used shared write buffer endurance 574 corresponding to the addition of the portion 252 to the shared write buffer 182, as described with reference to FIG. 4. FIG. 4B FIG. 5A FIG. 5A

[0125] ​​​The remedial action 114 also includes re-allocating the memory address range of the shared write buffer at block 522. For example, the HCI 112 transmits a unmap command 590 to the flash memory device 104 that instructs that the memory address range 184 is to be un-mapped from the shared write buffer 182. In response to receiving the unmap command 590, the device controller 162 updates the memory mapping table 180 to remove the memory address range 184 from the shared write buffer 182 and transmits a response 591 to the host device 102 indicating that the unmap command has been successfully executed. The device controller 162 also updates the used shared write buffer endurance 574 corresponding to the removal of the memory address range 184 from the shared write buffer 182, as described with reference to FIG. 5B. FIG. 5A

[0126] The HCI 112 transmits a convert command 592 to the flash memory device 104 to convert the memory address range 184 from a second memory type (e.g., SLC) to a first memory type (e.g., TLC). In response to receiving the convert command 592, the device controller 162 converts the memory cells corresponding to the memory address range 184 from having the second memory type to the first memory type and transmits a response 593 to the host device 102 indicating that the convert command has been successfully executed.

[0127] The HCI 112 transmits a map command 594 to the flash memory device 104 to map the memory address range 184 to the logical unit 168A. In response to receiving the map command 594, the device controller 162 updates the memory address range 190A (indicated in the memory mapping table 180 as corresponding to the logical unit 168A) to include the memory address range 184 and transmits a response 596 to the host device 102 indicating that the map command has been successfully executed. Thus, the HCI 112 re-allocates the memory of the shared write buffer 182 (e.g., corresponding to the memory address range 184) to the logical unit 168A. In particular aspects, the device controller 162 and the HCI 112 update the utilization metric 274A and the utilization metric 264A, respectively, corresponding to the addition of the memory address range 184 to the logical unit 168A, as described with reference to FIGS. 5A and 5B. In alternative implementations, the HCI 112 can re-allocate the memory of the shared write buffer 182 (e.g., corresponding to the memory address range 184) to another logical unit (e.g., the most utilized logical unit). FIG. 5A

[0128] ​​Accordingly, operation 540 enables re-allocating the portion 252 from the least utilized logical unit to the shared write buffer 182 that is being worn out, and allocating the memory address range 184 of the shared write buffer 182 to the logical unit 168A. The technical advantage of swapping the memory address range 184 and the portion 252 includes enabling the shared write buffer 182 to remain in use and extending the lifespan of the memory cells corresponding to the memory address range 184.

[0129] FIG. 6 is a system 100 that can be used by FIG. 1 a particular implementation of a method 600 of host management of a flash memory with a shared write buffer performed by the system 100 of FIG. 1. In particular aspects, one or more of the operations of the method 600 are performed by the HCI 112, the host device 102, the device controller 162, the flash memory 164, the flash memory device 104, FIG. 1 the system 100 of FIG. 1, FIG. 2 the system 200 of FIG. 2, the system 500 of FIG. 5, or a combination thereof.

[0130] The method 600 includes receiving, at a host controller interface (HCI), a notification from a flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer, at block 602. In one example, the HCI 112 receives the exception event alert 276 indicating that the logical unit 168B has exceeded the logical unit capacity threshold 272 while the write buffer mode 170 indicates that the flash memory device 104 is configured to use the shared write buffer 182, as described with reference to FIG. 2 In another example, the HCI 112 receives the exception event alert 576 indicating that the shared write buffer endurance threshold 572 has been exceeded while the write buffer mode 170 indicates that the flash memory device 104 is configured to use the shared write buffer 182, as described with reference to FIG. 5A

[0131] The method 600 also includes performing a remedial action in response to receiving the notification, the remedial action including re-allocating a portion of a first logical unit (LU), at block 604. In one example, the HCI 112 performs the remedial action 114 including re-allocating the portion 252 to the logical unit 168B, as described with reference to FIG. 3B ​described. To illustrate, portion 252 is reassigned to the logical unit 168B that is becoming full. In another example, the HCI 112 performs a remedial action 114 that includes reassigning portion 252 to the shared write buffer 182 and reassigning the memory address range 184 of the shared write buffer 182 to the logical unit 168B that is becoming full, as described with reference to FIG. 4B described. In yet another example, the HCI 112 performs a remedial action 114 that includes reassigning portion 252 to the shared write buffer 182 that is being worn out, as described with reference to FIG. 5C described.

[0132] Accordingly, the method 600 enables the shared write buffer 182 to remain available for use after the logical unit 168B becomes full, the shared write buffer 182 is worn out, or both.

[0133] FIG. 6 The method 600 can be implemented by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a digital signal processor (DSP), a controller, another hardware device, a firmware device, or any combination thereof. As an example, FIG. 6 The method 600 can be performed by a processor executing instructions, such as described with reference to FIG. 7 described.

[0134] Referring to FIG. 7 , a block diagram of a particular illustrative implementation of a device is depicted and generally designated 700. In various implementations, the device 700 can have more or fewer components than the components illustrated in FIG. 7. In the illustrative implementation, the device 700 can correspond to the host device 102. In the illustrative implementation, the device 700 can perform one or more operations described with reference to FIG. 7 described. FIG. 1 to FIG. 6

[0135] In a particular implementation, the device 700 includes a processor 706 (e.g., a CPU). The device 700 can include one or more additional processors 710 (e.g., one or more DSPs). The processor 710 can include a voice and music coder-decoder (CODEC) 708 that includes a speech coder (“vocoder”) encoder 736, a vocoder decoder 738, or both. The processor 710 can include the HCI 112 that is configured to be coupled to the flash memory device 104.

[0136] ​Device 700 can include memory 732 and codec 734. Memory 732 can include instructions 756 that are executable by one or more additional processors 710 (or processor 706) to implement the functionality described with reference to HCI 112. Device 700 can include modem 770 coupled to antenna 752 via transceiver 750.

[0137] Device 700 can include display 728 coupled to display controller 726. One or more speakers 792 and one or more microphones 794 can be coupled to codec 734. Codec 734 can include digital-to-analog converter (DAC) 702, analog-to-digital converter (ADC) 704, or both. In particular implementations, codec 734 can receive analog signals from microphone 794, convert the analog signals to digital signals using analog-to-digital converter 704, and provide the digital signals to voice and music codec 708. Voice and music codec 708 can process the digital signals. In particular implementations, voice and music codec 708 can provide the digital signals to codec 734. Codec 734 can convert the digital signals to analog signals using digital-to-analog converter 702, and can provide the analog signals to speaker 792.

[0138] In particular implementations, device 700 can be included in a system-in- package or system-on-chip device 722. In particular implementations, memory 732, processor 706, processor 710, display controller 726, codec 734, and modem 770 are included in system-in-package or system-on-chip device 722. In particular implementations, input device 730, power supply 744, and flash memory device 104 are coupled to system-in-package or system-on-chip device 722. In addition, in particular implementations, as illustrated, display 728, input device 730, speaker 792, microphone 794, antenna 752, flash memory device 104, and power supply 744 are external to system-in-package or system-on-chip device 722. In particular implementations, each of display 728, input device 730, speaker 792, microphone 794, antenna 752, flash memory device 104, and power supply 744 can be coupled to a component of system-in-package or system-on-chip device 722, such as an interface or a controller. For example, flash memory device 104 can be coupled to HCI 112. FIG. 7

[0139] ​The device 700 can comprise a smart speaker, a speaker bar, a mobile communication device, a smartphone, a cellular telephone, a laptop computer, a computer, a tablet device, a personal digital assistant, a display device, a television, a gaming console, a music player, a radio, a digital video player, a digital video disc (DVD) player, a tuner, a camera, a navigation device, a vehicle, a head-mounted device, an augmented reality head-mounted device, a mixed reality head-mounted device, a virtual reality head-mounted device, an aerial vehicle, a home automation system, a voice-activated device, a wireless speaker and voice-activated device, a portable electronic device, an automobile, a computing device, a communication device, an Internet of Things (IoT) device, a virtual reality (VR) device, a base station, a mobile device, or any combination thereof.

[0140] In connection with the described particular implementations, an apparatus comprises means for receiving, at a host controller interface (HCI), a notification from a flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer. For example, the means for receiving the notification can correspond to the HCI 112, the host device 102, FIG. 1 the system 100 of FIG. 1, FIG. 2 the system 200 of FIG. 2, the system 500 of FIG. 5, the processor 706, the processor 710, one or more other circuits or components configured to receive the notification, or any combination thereof.

[0141] The apparatus also comprises means for performing a remedial action comprising re-allocating a portion of a first logical unit (LU), the remedial action being performed in response to receiving the notification. For example, the means for performing the remedial action can correspond to the HCI 112, the host device 102, the device controller 162, the flash memory device 104, FIG. 1 the system 100 of FIG. 1, FIG. 2 the system 200 of FIG. 2, the system 500 of FIG. 5, the processor 706, the processor 710, one or more other circuits or components configured to perform the remedial action, or any combination thereof.

[0142] In some implementations, a non-transitory computer-readable medium (e.g., a computer-readable storage device, such as memory 732) includes instructions (e.g., instructions 756) that, when executed by one or more processors (e.g., one or more processors 710 or processor 706), cause the one or more processors to receive, at a host controller interface (HCI) (e.g., HCI 112) from a flash memory device (e.g., flash memory device 104), a notification (e.g., notification 176, exception event alert 276, exception event alert 576) that a performance threshold register value (e.g., value 172 of performance threshold register, logical unit capacity threshold 272, shared write buffer endurance threshold 572) has been exceeded when the flash memory device is configured to use a shared write buffer (e.g., shared write buffer 182). The instructions also cause the one or more processors to perform, in response to receiving the notification, a remedial action (e.g., remedial action 114) that includes reallocating a portion (e.g., portion 252) of a first logical unit (LU) (e.g., logical unit 168A).

[0143] Particular aspects of the present disclosure are described in the following According to embodiment 1, a host device includes a host controller interface (HCI) configured to couple to a flash memory device and configured to: receive, from the flash memory device, a notification that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer; and perform, in response to receiving the notification, a remedial action that includes reallocating a portion of a first logical unit (LU).

[0144] Embodiment 2 includes the host device of embodiment 1, wherein reallocating the portion of the first LU includes transmitting an unmap command to the flash memory device to update a memory mapping table at the flash memory device.

[0145] Embodiment 3 includes the host device of embodiment 1 or embodiment 2, wherein the remedial action further includes transmitting a command to the flash memory device to convert the portion of the first LU from a first memory type to a second memory type.

[0146] Embodiment 4 includes the host device of embodiment 3, wherein the first memory type is triple level cell (TLC) and the second memory type is single level cell (SLC).

[0147] Example 5 includes the host device of any of Examples 1-4, wherein the HCI is configured to: re-allocate memory of the shared write buffer to a second LU; and re-allocate the portion of the first LU for use as the shared write buffer.

[0148] Example 6 includes the host device of Example 5, wherein the HCI is configured to transmit a command to the flash memory device to flush the shared write buffer prior to re-allocating the memory of the shared write buffer to the second LU.

[0149] Example 7 includes the host device of Example 1 or Example 2, wherein the HCI is configured to re-allocate the portion of the first LU to a second LU of the flash memory device.

[0150] Example 8 includes the host device of any of Examples 1-7, wherein the performance threshold register value corresponds to a LU capacity threshold, and wherein the notification indicates that a utilization of a second LU of the flash memory device has exceeded the LU capacity threshold.

[0151] Example 9 includes the host device of Example 8, wherein the notification comprises an exception event alert.

[0152] Example 10 includes the host device of Example 9, wherein the HCI transmits a command to the flash memory device to set an exception event control attribute to activate an alert generation corresponding to a LU capacity, and wherein the exception event alert is generated in response to determining that the exception event control attribute indicates that the alert generation is activated and an exception event status indicates that the utilization of the second LU of the flash memory device has exceeded the LU capacity threshold.

[0153] Example 11 includes the host device of Example 1 or Example 2, wherein the performance threshold register value corresponds to a shared write buffer endurance threshold, and wherein the notification indicates that a used endurance of the shared write buffer has exceeded the shared write buffer endurance threshold.

[0154] Example 12 includes the host device of Example 11, wherein the notification comprises an exception event alert.

[0155] Example 13 includes the host device of Example 12, wherein the HCI transmits a command to the flash memory device to set an exception event control attribute to activate an alert generation corresponding to a shared write buffer endurance, and wherein the exception event alert is generated in response to determining that the exception event control attribute indicates that the alert generation is activated and an exception event status indicates that the used endurance of the shared write buffer has exceeded the shared write buffer endurance threshold.

[0156] Example 14 includes the host device of any one of Examples 11-13, wherein the HCI is configured to determine the used endurance of the shared write buffer based on a count of program loops performed at the shared write buffer, a program loop time of the shared write buffer, or both.

[0157] Example 15 includes the host device of any one of Examples 1-14, wherein the HCI is configured to identify a first LU based on detecting that the first LU corresponds to a least utilized LU of a plurality of LUs.

[0158] Example 16 includes the host device of Example 15, wherein the HCI is configured to determine that the first LU corresponds to the least utilized LU based on a value of a utilization array.

[0159] Example 17 includes the host device of Example 15 or Example 16, wherein the HCI is configured to determine that the first LU corresponds to the least utilized LU based on determining that the first LU has a greatest available storage capacity of the plurality of LUs.

[0160] Example 18 includes the host device of any one of Examples 15-17, wherein the HCI is configured to determine that the first LU corresponds to the least utilized LU based on a count of write commands to the first LU, a program loop count of the first LU, a program loop time of the first LU, an available storage capacity of the first LU, or a combination thereof.

[0161] According to Example 19, a method includes receiving, at a host controller interface (HCI) from a flash memory device, a notification that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer, and performing a remedial action in response to receiving the notification, the remedial action including reallocating a portion of a first logical unit (LU).

[0162] Example 20 includes the method of Example 19, wherein reallocating the portion of the first LU includes transmitting an unmap command to the flash memory device to update a memory mapping table at the flash memory device.

[0163] Example 21 includes the method of Example 19 or Example 20, wherein the remedial action further includes transmitting a command to the flash memory device to convert the portion of the first LU from a first memory type to a second memory type.

[0164] Example 22 includes the method of Example 21, wherein the first memory type is triple level cell (TLC) and the second memory type is single level cell (SLC).

[0165] Example 23 includes the method of any of Examples 19-22, and the method further includes reallocating memory of the shared write buffer to a second LU, wherein reallocating the portion of the first LU for use as the shared write buffer.

[0166] Example 24 includes the method of Example 23, and the method further includes transmitting a command to the flash memory device to flush the shared write buffer prior to reallocating the memory of the shared write buffer to the second LU.

[0167] Example 25 includes the method of Example 19 or Example 20, wherein the portion of the first LU is reallocated to a second LU of the flash memory device.

[0168] Example 26 includes the method of any of Examples 19-25, wherein the performance threshold register value corresponds to a LU capacity threshold, and wherein the notification indicates that a utilization of a second LU of the flash memory device has exceeded the LU capacity threshold.

[0169] Example 27 includes the method of Example 26, wherein the notification includes an exception event alert.

[0170] Example 28 includes the method of Example 27, and the method further includes transmitting a command to the flash memory device to set an exception event control attribute to activate an alert generation corresponding to a LU capacity, wherein the exception event alert is generated in response to determining that the exception event control attribute indicates that the alert generation is activated and an exception event status indicates that the utilization of the second LU of the flash memory device has exceeded the LU capacity threshold.

[0171] Example 29 includes the method of Example 19 or Example 20, wherein the performance threshold register value corresponds to a shared write buffer endurance threshold, and wherein the notification indicates that a used endurance of the shared write buffer has exceeded the shared write buffer endurance threshold.

[0172] Example 30 includes the method of Example 29, wherein the notification comprises an exception event alert.

[0173] Example 31 includes the method of Example 30, and the method further comprises transmitting a command to the flash memory device to set an exception event control attribute to activate an alert generation corresponding to shared write buffer endurance, wherein the exception event alert is generated in response to determining that the exception event control attribute indicates that the alert generation is activated and an exception event status indicates that the used endurance of the shared write buffer has exceeded the shared write buffer endurance threshold.

[0174] Example 32 includes the method of any one of Examples 29-31, and the method further comprises determining the used endurance of the shared write buffer based on a count of program cycles performed at the shared write buffer, a program cycle time of the shared write buffer, or both.

[0175] Example 33 includes the method of any one of Examples 19-32, and the method further comprises identifying a first LU based on detecting that the first LU corresponds to a least utilized LU of a plurality of LUs.

[0176] Example 34 includes the method of Example 33, and the method further comprises determining that the first LU corresponds to the least utilized LU based on a value of a utilization array.

[0177] Example 35 includes the method of Example 33 or Example 34, the method further comprising determining that the first LU corresponds to the least utilized LU based on determining that the first LU has a greatest available storage capacity of the plurality of LUs.

[0178] Example 36 includes the method of any one of Examples 33-35, and the method further comprises determining that the first LU corresponds to the least utilized LU based on a count of write commands to the first LU, a program cycle count of the first LU, a program cycle time of the first LU, an available storage capacity of the first LU, or a combination thereof.

[0179] According to embodiment 37, an apparatus comprises a memory configured to store instructions; and a processor configured to execute the instructions to perform the method of any of embodiments 19-36.

[0180] According to embodiment 38, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the method of any of embodiments 19-36.

[0181] According to embodiment 39, an apparatus comprises means for performing the method of any of embodiments 19-36.

[0182] According to embodiment 40, a non-transitory computer-readable medium configured to store instructions that, when executed by one or more processors, cause the one or more processors to: receive, at a host controller interface (HCI) from a flash memory device, a notification that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer; and perform a remedial action in response to receiving the notification, the remedial action comprising re-allocating a portion of a first logical unit (LU).

[0183] Embodiment 41 includes the non-transitory computer-readable medium of embodiment 40, wherein the performance threshold register value corresponds to a shared write buffer endurance threshold, and wherein the notification indicates that a used endurance of the shared write buffer has exceeded the shared write buffer endurance threshold.

[0184] According to embodiment 42, an apparatus comprises means for receiving, at a host controller interface (HCI) from a flash memory device, a notification that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer; and means for performing a remedial action, the remedial action comprising re-allocating a portion of a first logical unit (LU), the remedial action performed in response to receiving the notification.

[0185] Embodiment 43 includes the apparatus of embodiment 42, wherein the means for receiving and the means for performing are integrated into at least one of a computer, a communication device, a mobile device, an extended reality (XR) device, a head-mounted device, a vehicle, or a camera.

[0186] Those skilled in the art will further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the implementations disclosed herein can be implemented as electronic hardware, computer software executed by a processing unit or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or processor executable instructions depends upon the particular application and design constraints imposed on the overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0187] The steps of a method or algorithm described in connection with the implementations disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in Random Access Memory (RAM), flash memory, Read-only memory (ROM), Programmable Read-only memory (PROM), Erasable Programmable Read-only memory (EPROM), Electrically Erasable Programmable Read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transitory storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). The ASIC can reside in a computing device or a user terminal. In the alternative, the processor and the storage medium can reside as discrete components in a computing device or user terminal.

[0188] The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosed aspects. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein and made apparent to others skilled in the art by the teachings herein.

Claims

1. A host device, the host device comprising: A host controller interface (HCI) is configured to be coupled to a flash memory device and configured to: Receive a notification from the flash memory device that the performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer; and In response to receiving the notification, remedial measures are performed, including the reallocation of a portion of the first logical unit (LU).

2. The host device of claim 1, wherein the remedy further comprises transmitting a command to the flash memory device to convert the portion of the first LU from a first memory type to a second memory type.

3. The host device according to claim 2, wherein the first memory type is a three-level cell (TLC) and the second memory type is a single-level cell (SLC).

4. The host device of claim 1, wherein reallocating the portion of the first LU comprises transmitting a demapping command to the flash memory device to update the memory mapping table at the flash memory device.

5. The host device according to claim 1, wherein the HCI is configured as follows: The memory of the shared write buffer is reallocated to the second LU; and A portion of the first LU is reallocated to serve as the shared write buffer.

6. The host device of claim 5, wherein the HCI is configured to transmit a command to the flash memory device to refresh the shared write buffer before reallocating the memory of the shared write buffer to the second LU.

7. The host device of claim 1, wherein the HCI is configured to reallocate the portion of the first LU to a second LU of the flash memory device.

8. The host device of claim 1, wherein the performance threshold register value corresponds to an LU capacity threshold, and wherein the notification indicates that the utilization of a second LU of the flash memory device has exceeded the LU capacity threshold.

9. The host device of claim 8, wherein the notification includes an anomaly event alarm.

10. The host device of claim 9, wherein the HCI transmits a command to the flash memory device to set an abnormal event control attribute to activate alarm generation corresponding to LU capacity, and wherein the abnormal event alarm is generated in response to determining that the abnormal event control attribute indicates that alarm generation is activated and that an abnormal event status indicates that the utilization of the second LU of the flash memory device has exceeded the LU capacity threshold.

11. The host device of claim 1, wherein the performance threshold register value corresponds to a shared write buffer durability threshold, and wherein the notification indicates that the used durability of the shared write buffer has exceeded the shared write buffer durability threshold.

12. The host device of claim 11, wherein the notification includes an anomaly event alarm.

13. The host device of claim 12, wherein the HCI transmits a command to the flash memory device to set an anomaly event control attribute to activate alarm generation corresponding to the shared write buffer durability, and wherein the anomaly event alarm is generated in response to determining that the anomaly event control attribute indicates that alarm generation is activated and that an anomaly event status indicates that the used durability of the shared write buffer has exceeded the shared write buffer durability threshold.

14. The host device of claim 11, wherein the HCI is configured to determine the used durability of the shared write buffer based on a count of program cycles executed at the shared write buffer, the program cycle time of the shared write buffer, or both.

15. The host device of claim 1, wherein the HCI is configured to identify the first LU based on detecting that the first LU corresponds to the least used LU among a plurality of LUs.

16. The host device of claim 15, wherein the HCI is configured to determine, based on the value of the utilization array, that the first LU corresponds to the least utilized LU.

17. The host device of claim 15, wherein the HCI is configured to determine that the first LU corresponds to the least utilized LU based on determining that the first LU has the largest available storage capacity among the plurality of LUs.

18. The host device of claim 15, wherein the HCI is configured to determine that the first LU corresponds to the least utilized LU based on a count of write commands to the first LU, a program cycle count of the first LU, a program cycle time of the first LU, an available storage capacity of the first LU, or a combination thereof.

19. A method comprising: At the host controller interface (HCI), a notification is received from the flash memory device that the performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer; as well as In response to receiving the notification, remedial measures are performed, including the reallocation of a portion of the first logical unit (LU).

20. The method of claim 19, wherein the remedy further comprises transmitting a command to the flash memory device to convert the portion of the first LU from a first memory type to a second memory type.

21. The method of claim 20, wherein the first memory type is a three-level cell (TLC) and the second memory type is a single-level cell (SLC).

22. The method of claim 19, wherein reallocating the portion of the first LU comprises transmitting a demapping command to the flash memory device to update the memory mapping table at the flash memory device.

23. The method of claim 19, further comprising reallocating the memory of the shared write buffer to a second LU, wherein the portion of the first LU is reallocated to serve as the shared write buffer.

24. The method of claim 23, further comprising transmitting a command to the flash memory device to refresh the shared write buffer before reallocating the memory of the shared write buffer to the second LU.

25. The method of claim 19, wherein the portion of the first LU is reallocated to the second LU of the flash memory device.

26. The method of claim 19, wherein the performance threshold register value corresponds to an LU capacity threshold, and wherein the notification indicates that the utilization of a second LU of the flash memory device has exceeded the LU capacity threshold.

27. A non-transitory computer-readable medium configured to store instructions that, when executed by one or more processors, cause the one or more processors to: Receive a notification from the flash memory device at the host controller interface (HCI) that the performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer; and In response to receiving the notification, remedial measures are performed, including the reallocation of a portion of the first logical unit (LU).

28. The non-transitory computer-readable medium of claim 27, wherein the performance threshold register value corresponds to a shared write buffer durability threshold, and wherein the notification indicates that the used durability of the shared write buffer has exceeded the shared write buffer durability threshold.

29. An apparatus comprising: A component for receiving, at the host controller interface (HCI), a notification from a flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer; and Components for performing remedial measures, the remedial measures including the reallocation of a portion of a first logic unit (LU), the remedial measures being performed in response to receiving the notification.

30. The apparatus of claim 29, wherein the receiving component and the performing component are integrated into at least one of a computer, a communication device, a mobile device, an extended reality (XR) device, a head-mounted device, a vehicle, or a camera.

Images