A semiconductor chip testing system and method
By combining terahertz time-domain spectroscopy and superconducting quantum interference device arrays with topological data analysis, the problem of insufficient accuracy in locating microscopic leakage paths in semiconductor chip testing was solved, achieving high-precision leakage path identification and comprehensive defect assessment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 弘润半导体(苏州)有限公司
- Filing Date
- 2026-03-16
- Publication Date
- 2026-07-03
AI Technical Summary
Existing semiconductor chip testing technologies lack the precision to locate microscopic leakage paths and lack comprehensive analysis of material and electrical defects, resulting in insufficient test coverage and accuracy.
By combining terahertz time-domain spectroscopy equipment and superconducting quantum interference device array with topological data analysis algorithms, a three-dimensional topological model is constructed by scanning the wafer surface to collect reflection spectrum and electromagnetic field distribution data, abnormal current loops are identified, and a test report is generated through principal component analysis and weighted linear regression scoring.
It enables precise location of microscopic leakage paths, improves test accuracy and coverage, and provides a comprehensive quality assessment basis for chip production.
Smart Images
Figure CN121856766B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing technology, and in particular to a semiconductor chip testing system and method. Background Technology
[0002] Semiconductor chip testing technology is a crucial step in integrated circuit manufacturing to ensure chip functionality, performance, and reliability. As semiconductor process nodes continue to shrink, and chip complexity and application scenarios diversify, chip testing technology is shifting from traditional electrical testing to multi-dimensional, comprehensive analysis. Early testing methods primarily relied on automated test equipment (ATE) for functional verification and parameter measurement, applying electrical signals through probe cards to detect the chip's logical correctness and electrical characteristics. In recent years, with advancements in materials science and quantum technology, non-contact testing methods based on optical, acoustic, and electromagnetic fields have emerged. For example, infrared thermal imaging is used to detect chip hotspots, and terahertz spectroscopy is used to analyze material properties. These technologies have played a significant role in wafer-level testing, post-packaging testing, and reliability assessment, driving improvements in testing accuracy and efficiency. Furthermore, the introduction of data analysis techniques, such as machine learning and multivariate statistical methods, is being applied to test data processing and defect classification, further optimizing the testing process.
[0003] However, there are still areas for improvement in existing semiconductor chip testing technologies. First, existing testing technologies lack the precision to locate microscopic leakage paths, as they only correct test results through current compensation and cannot achieve precise location of leakage paths at the microscopic scale. Second, existing testing technologies are mostly single-dimensional tests, lacking comprehensive analysis of material and electrical defects, resulting in insufficient test coverage and accuracy. Summary of the Invention
[0004] In view of the aforementioned existing problems, the present invention is proposed.
[0005] Therefore, the present invention provides a semiconductor chip testing method to solve the problem of the inability to accurately locate leakage paths at the microscale.
[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:
[0007] In a first aspect, the present invention provides a semiconductor chip testing method, comprising,
[0008] Place the semiconductor wafer under test on the test platform, calibrate the terahertz time-domain spectroscopy device and the superconducting quantum interference device array, and generate an initialization report;
[0009] According to the initialization report, the semiconductor wafer under test is scanned using a terahertz time-domain spectroscopy device, the surface of the semiconductor wafer under test is irradiated with terahertz pulses, the reflection spectrum caused by lattice vibration is collected, the phonon spectrum characteristics of the reflection spectrum are analyzed, the type and spatial distribution of lattice defects are determined, a wafer defect distribution map is generated, and high-risk areas are marked.
[0010] High-risk areas are extracted from the wafer defect distribution map, the test platform is adjusted, the high-risk areas are scanned, and electromagnetic field distribution data is collected after applying test current to the test points of the semiconductor wafer under test through a superconducting quantum interference device array. The topology data analysis algorithm is used to calculate and construct a three-dimensional topology model, identify abnormal current loops, and generate a leakage path diagram.
[0011] By using the wafer defect distribution map and leakage path map, principal component analysis is performed to extract defect features such as defect density and leakage intensity, and a comprehensive defect score is calculated to generate a test report.
[0012] As a preferred embodiment of the semiconductor chip testing method of the present invention, the following steps are taken: placing the semiconductor wafer under test on the testing platform, calibrating the terahertz time-domain spectroscopy device and the superconducting quantum interference device array, and generating an initialization report.
[0013] An automated robotic arm fixes the semiconductor wafer under test to the vacuum adsorption fixture of the test platform, and the environmental parameters are obtained by adjusting the temperature and humidity of the test platform cavity through environmental control equipment.
[0014] The terahertz time-domain spectrometer is calibrated using a standard silicon reference sample, the spectral response is adjusted, and the calibrated terahertz time-domain spectrometer status data is generated.
[0015] By cooling the superconducting quantum interference device array with liquid nitrogen and applying a standard alternating current, calibrated channel consistency data of the superconducting quantum interference device array is generated.
[0016] An initialization report is generated by integrating wafer number, environmental parameters, calibrated terahertz time-domain spectroscopy equipment status data, and calibrated superconducting quantum interference device array channel consistency data.
[0017] In a preferred embodiment of the semiconductor chip testing method of the present invention, the step of scanning the semiconductor wafer under test using a terahertz time-domain spectroscopy device, irradiating the surface of the semiconductor wafer under test with terahertz pulses, and collecting the reflection spectrum caused by lattice vibrations, specifically involves:
[0018] Read the calibrated terahertz time-domain spectrometer status data from the initialization report, start the terahertz time-domain spectrometer, and emit terahertz pulses to irradiate the surface of the semiconductor wafer under test through the focusing lens;
[0019] A two-dimensional translation stage is controlled to move the semiconductor wafer under test for point-by-point scanning, and a photodetector is used to collect the reflection spectrum signal caused by lattice vibration.
[0020] In a preferred embodiment of the semiconductor chip testing method of the present invention, the steps of analyzing the phonon spectrum characteristics of the reflection spectrum, determining the lattice defect type and spatial distribution, generating a wafer defect distribution map, and marking high-risk areas specifically involve...
[0021] Terahertz reflection spectral data and theoretical spectral data calculated using first-principles calculations were collected from standard silicon wafer samples and integrated into a training dataset. A phonon scattering model was trained using a support vector machine with radial basis functions as kernel functions to establish the mapping relationship between phonon spectral characteristics and lattice defect types and lattice defect densities.
[0022] The phonon spectrum characteristics of the reflected spectrum signal are analyzed by phonon scattering model and mapping relationship to determine the lattice defect type and lattice defect density, and a three-dimensional dataset is generated by combining a two-dimensional translation stage.
[0023] The 3D dataset was used to generate a wafer defect distribution map using visualization software.
[0024] Statistical analysis of the lattice defect density in the wafer defect distribution map is performed. A defect threshold is set and regions with lattice defect densities greater than the defect threshold are screened to generate high-risk regions.
[0025] As a preferred embodiment of the semiconductor chip testing method of the present invention, the acquisition of electromagnetic field distribution data refers to reading the location of high-risk areas in the wafer defect distribution map, adjusting the distance from the surface of the semiconductor wafer under test, applying a test current to the test point of the semiconductor wafer under test using a probe card, and acquiring magnetic field strength and direction data through a superconducting quantum interference device array to generate electromagnetic field distribution data.
[0026] In a preferred embodiment of the semiconductor chip testing method of the present invention, the step of using a topology data analysis algorithm to calculate, construct a three-dimensional topology model, identify abnormal current loops, and generate a leakage path diagram specifically involves:
[0027] The electromagnetic field distribution data is transmitted to the topology data analysis node, and a point cloud dataset is constructed using the persistent cohomology method. Topological features are calculated, and a continuous field structure feature dataset is generated.
[0028] Map the continuous field structure feature dataset to a three-dimensional spatial coordinate system to generate a three-dimensional topological model;
[0029] Abnormal current loops are identified using a 3D topology model, an abnormal current loop dataset is generated, and visualization software is used to convert the abnormal current loop dataset into a leakage current path diagram.
[0030] As a preferred embodiment of the semiconductor chip testing method of the present invention, wherein: the defect feature extraction of defect density and leakage current intensity by performing principal component analysis specifically includes,
[0031] Defect density data and leakage current intensity data are extracted from wafer defect distribution maps and leakage current path maps, and then a unified dataset is generated after standardization processing.
[0032] Input the unified dataset into the principal component analysis algorithm, calculate the covariance matrix, select the main eigenvectors, and generate the main feature dataset.
[0033] As a preferred embodiment of the semiconductor chip testing method of the present invention, the calculation of the comprehensive defect score specifically involves:
[0034] Historical defect data and leakage current intensity data are collected, divided into sample set, training set and validation set, and enhanced standard samples are generated through linear interpolation and batch normalization.
[0035] Forward computation is performed using enhanced standard samples, and the weight parameters are optimized using least squares and ridge regression regularization to generate a trained weighted linear regression model.
[0036] Input the main feature dataset into the trained weighted linear regression model to calculate the comprehensive defect score dataset.
[0037] As a preferred embodiment of the semiconductor chip testing method of the present invention, the generation of the test report refers to generating a test report dataset based on the wafer number, lattice defect type and comprehensive defect score dataset, performing structured processing on the test report dataset, generating a test report, and completing the semiconductor testing.
[0038] Secondly, the present invention provides a semiconductor chip testing system, comprising,
[0039] The initialization module places the semiconductor wafer under test on the test platform, calibrates the terahertz time-domain spectroscopy device and the superconducting quantum interference device array, and generates an initialization report.
[0040] The defect module, based on the initialization report, uses a terahertz time-domain spectroscopy device to scan the semiconductor wafer under test, emits terahertz pulses to irradiate the surface of the semiconductor wafer under test, collects the reflection spectrum caused by lattice vibration, analyzes the phonon spectrum characteristics of the reflection spectrum, determines the type and spatial distribution of lattice defects, generates a wafer defect distribution map, and marks high-risk areas.
[0041] The leakage current module extracts high-risk areas based on the wafer defect distribution map, adjusts the test platform, scans the high-risk areas, applies test current to the test points of the semiconductor wafer under test through a superconducting quantum interference device array, collects electromagnetic field distribution data, and uses a topology data analysis algorithm to calculate, construct a three-dimensional topology model, identify abnormal current loops, and generate a leakage current path map.
[0042] The testing module uses the wafer defect distribution map and leakage path map to perform principal component analysis to extract defect features such as defect density and leakage intensity, calculates a comprehensive defect score, and generates a test report.
[0043] The beneficial effects of this invention are as follows: By using a superconducting quantum interference device array to collect magnetic field strength and direction data in the high-risk area space of the wafer defect distribution map, electromagnetic field distribution data is generated. This data is then processed using a topological data analysis algorithm to construct a three-dimensional topological model, identify abnormal current loops, and generate a leakage path map. This achieves precise positioning of microscopic leakage paths, overcomes the accuracy limitations of current compensation correction, and improves the positioning accuracy of microscopic leakage paths, providing a reliable basis for evaluating the electrical performance of semiconductor chips. Furthermore, by integrating terahertz time-domain spectroscopy for material defect detection and superconducting quantum interference device for electrical defect analysis, principal component analysis for dimensionality reduction and weighted linear regression scoring are used to provide a comprehensive quality assessment basis for chip production. Attached Figure Description
[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a flowchart of a semiconductor chip testing method.
[0046] Figure 2 The flowchart for initializing the calibration.
[0047] Figure 3 This is a flowchart for defect detection.
[0048] Figure 4 This is a flowchart for leakage current analysis. Detailed Implementation
[0049] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0050] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0051] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.
[0052] Reference Figures 1-4 This is one embodiment of the present invention, which provides a semiconductor chip testing method, including the following steps:
[0053] S1: Place the semiconductor wafer under test on the test platform, calibrate the terahertz time-domain spectroscopy device and the superconducting quantum interference device array, and generate an initialization report;
[0054] Specifically, the steps include the following:
[0055] The semiconductor wafer to be tested is removed from the wafer cassette and transferred by an automated robotic arm to a vacuum adsorption fixture on the testing platform. It is then fixed in place by vacuum adsorption to ensure that the wafer is firmly fixed to the testing platform and to prevent displacement during subsequent testing.
[0056] The planarity of the semiconductor wafer surface under test is confirmed to meet the test requirements by using a laser confocal displacement sensor. Specifically, the laser confocal displacement sensor is activated to emit a laser beam to scan the surface of the semiconductor wafer under test and collect surface height data. The planarity of the semiconductor wafer surface under test is calculated and adjusted by the laser confocal displacement sensor to avoid signal deviation caused by surface unevenness.
[0057] The environmental control function is activated to adjust the temperature and humidity of the chamber where the test platform is located. For example, the temperature is adjusted to 25°C and the humidity is adjusted to 50%RH. The environmental parameters are monitored in real time by high-precision temperature and humidity sensors inside the chamber to confirm that the temperature and humidity are within a stable range.
[0058] The calibration of a terahertz time-domain spectrometer using a standard silicon reference sample is as follows: Place the standard silicon reference sample on the test platform, activate the terahertz time-domain spectrometer to emit terahertz pulses to irradiate the surface of the standard silicon reference sample, acquire the reflection spectrum of the standard silicon reference sample through a photodetector, analyze the position of characteristic peaks in the reflection spectrum, for example, confirm that the silicon lattice vibration peak is located at 4.7 THz; compare the acquired reflection spectrum data with the known spectral characteristics of the standard silicon reference sample, adjust the emission power of the terahertz time-domain spectrometer and the gain of the photodetector, generate the calibrated terahertz time-domain spectrometer status data, and complete the calibration of the terahertz time-domain spectrometer.
[0059] The liquid nitrogen cooling function of the superconducting quantum interference device (SQU) array is activated, a standard alternating current is applied to calibrate the SQU array, the signal gain and bias parameters are adjusted, and the consistency of response across all channels is confirmed. The process is as follows:
[0060] The liquid nitrogen cooling function is activated, injecting liquid nitrogen into the cooling chamber of the superconducting quantum interference device (SQFID) array to lower the array's operating temperature to a superconducting state, for example, 77K. A standard alternating current is applied to the calibration coil of the SQFID array, and the magnetic field response signal is acquired through each channel of the SQFID array. The peak value and phase (offset relative to the input signal) are extracted using a fast Fourier transform and a lock-in amplifier. The consistency of each channel is compared, and the signal gain and bias parameters of the SQFID array are adjusted to generate calibrated channel consistency data of the SQFID array, ensuring that the magnetic field response signal of all channels is consistent.
[0061] The unique serial number of the semiconductor wafer under test is read by the barcode scanning device of the testing platform; the temperature and humidity data of the current cavity are obtained from the sensors of the environmental control device; the spectral response status of the terahertz time-domain spectrometer after calibration and the channel response consistency status of the superconducting quantum interference device array after calibration are recorded; the wafer serial number of the semiconductor wafer under test, environmental parameters, the status data of the calibrated terahertz time-domain spectrometer and the channel consistency data of the calibrated superconducting quantum interference device array are integrated into a structured text format and named the initialization report.
[0062] S2: Based on the initialization report, use a terahertz time-domain spectroscopy device to scan the semiconductor wafer under test, emit terahertz pulses to irradiate the surface of the semiconductor wafer under test, collect the reflection spectrum caused by lattice vibration, analyze the phonon spectrum characteristics of the reflection spectrum, determine the type and spatial distribution of lattice defects, generate a wafer defect distribution map, and mark high-risk areas;
[0063] Specifically, the steps include the following:
[0064] S2.1: Based on the terahertz time-domain spectrometer calibration status information in the initialization report, start the terahertz time-domain spectrometer, emit terahertz pulses to irradiate the surface of the semiconductor wafer under test, control the two-dimensional translation stage to move the semiconductor wafer under test to scan point by point, and use a photodetector to collect the reflection spectrum signal caused by lattice vibration, specifically:
[0065] The calibration status information of the terahertz time-domain spectrometer stored in the initialization report is read, the pulse source of the terahertz time-domain spectrometer is started, and a terahertz pulse is generated. The terahertz pulse is guided to the surface of the semiconductor wafer under test through the focusing lens of the terahertz time-domain spectrometer, and the irradiation area covers the specified scanning point of the semiconductor wafer under test.
[0066] The two-dimensional translation stage is controlled to move the semiconductor wafer under test along the X and Y axes to perform point-by-point scanning with a scanning step size to ensure that the entire test area of the semiconductor wafer under test is covered; a photodetector is used to collect the reflection spectrum signal caused by the lattice vibration on the surface of the semiconductor wafer under test in real time, and the time domain data of the reflection spectrum signal is recorded simultaneously.
[0067] The time-domain data of the reflection spectrum signal is converted into frequency-domain data by fast Fourier transform, generating a reflection spectrum signal that includes lattice vibration characteristics.
[0068] S2.2: The reflection spectrum signal is transmitted to the phonon scattering analysis node of the distributed computing platform. The phonon spectrum characteristics of the reflection spectrum are analyzed using a pre-trained phonon scattering model. Model inference and estimation of lattice defect types and densities are performed. Combined with the scanning position coordinates, spatial distribution data is generated and converted into a wafer defect distribution map. Regions with defect densities exceeding a predetermined threshold are marked as high-risk areas in the wafer defect distribution map. Specifically:
[0069] The reflectance spectrum signal collected by the photodetector is converted into a digital signal format through a high-speed data interface; the digitized reflectance spectrum signal is then transmitted over a network to the phonon scattering analysis node of the distributed computing platform to ensure data integrity, for example, by using the MQTT protocol to achieve low-latency transmission.
[0070] S2.2.1: Constructing a pre-trained phonon scattering model. Specific operations include: collecting terahertz reflection spectral data from standard silicon wafer samples, including known lattice defect types (such as vacancies, dislocations, and doping inhomogeneities) and their corresponding spectral characteristic peak positions; simulating the phonon scattering behavior of silicon crystals under different defect states using first-principles calculations to generate theoretical spectral data; integrating the terahertz reflection spectral data from standard silicon wafer samples and the theoretical spectral data to form a training dataset; selecting a support vector machine (SVM) as the basis for the pre-trained phonon scattering model, configuring radial basis functions as kernel functions, and inputting the training dataset into the SVM; training the SVM using supervised learning methods to establish the mapping relationship between phonon spectral features (including characteristic peak shifts, peak shape changes, peak widths, peak intensities, and multi-peak relationships) and lattice defect types and defect densities; verifying the classification accuracy of the trained SVM using independent standard silicon wafer samples, adjusting the hyperparameters of the SVM and optimizing the classification accuracy, generating a trained phonon scattering model for statistical inference and prediction of lattice defects based on terahertz reflection spectral features.
[0071] In the trained phonon scattering model, lattice defect identification does not rely on a single spectral feature, but rather on a comprehensive analysis of multidimensional phonon spectral features in the reflection spectrum. These phonon spectral features include characteristic peak shifts, peak shape changes, peak widths, peak intensities, and the relative relationships between multiple peaks. By constructing feature vectors based on these multidimensional features, the inference of lattice defect types and defect densities can be achieved.
[0072] S2.2.2: Phonon spectral characteristics of the reflection spectrum are analyzed using a pre-trained phonon scattering model to infer the type and density of lattice defects. This data, combined with the scan position coordinates, forms spatial distribution data and is converted into a wafer defect distribution map. Specifically:
[0073] The reflection spectrum signal transmitted to the phonon scattering analysis node of the distributed computing platform is input into the pre-trained phonon scattering model. The pre-trained phonon scattering model extracts phonon spectrum feature parameters (including characteristic peak position, peak shape, peak width, peak intensity, and relative relationships of multiple peaks) from the reflection spectrum signal, compares the characteristic peak position with the known position of the standard silicon lattice vibration peak, calculates the difference of phonon spectrum features, and generates phonon spectrum feature data.
[0074] Phonon spectrum feature data is input into a pre-trained phonon scattering model. The pre-trained phonon scattering model uses a support vector machine classifier to extract feature vectors related to lattice defect types based on the amplitude and shape of the phonon spectrum feature data. The feature vectors are compared with known lattice defect type features in the training data to infer the lattice defect type, such as vacancies, dislocations, or doping inhomogeneities.
[0075] By using regression analysis of a pre-trained phonon scattering model, the lattice defect density at each scanning position is estimated based on the mapping relationship between the mapped phonon spectrum feature data and the trained phonon scattering model, generating lattice defect type probability information and corresponding lattice defect density estimation data; the lattice defect type and lattice defect density data are associated with the scanning position coordinates recorded by the two-dimensional translation stage to generate a three-dimensional dataset containing lattice defect type, lattice defect density and corresponding spatial coordinates.
[0076] The coordinates of each scan position in the 3D dataset are mapped one-to-one with the lattice defect type and lattice defect density to form spatial distribution data. The spatial distribution data is then input into visualization software, which uses a 2D heatmap format to represent the distribution of lattice defect type and lattice defect density. Colors are assigned according to the magnitude of the lattice defect density, for example, red represents high density, yellow represents medium density, and green represents low density, thus generating a wafer defect distribution map.
[0077] S2.3: Read the lattice defect density data stored in the wafer defect distribution map, perform statistical analysis on the lattice defect density data, calculate the mean and standard deviation of the lattice defect density at all scan positions, and set the defect threshold to the mean lattice defect density plus twice the standard deviation; compare the lattice defect density at each scan position in the wafer defect distribution map with the defect threshold, filter out areas where the lattice defect density is greater than the defect threshold, record the spatial coordinates of the filtered areas, and generate a list containing the spatial coordinates of high-risk areas.
[0078] S3: Extract high-risk areas based on the wafer defect distribution map, adjust the test platform, scan the high-risk areas, apply test current to the test points of the semiconductor wafer under test through a superconducting quantum interference device array, collect electromagnetic field distribution data, and use topology data analysis algorithm to calculate, construct a three-dimensional topology model, identify abnormal current loops, and generate leakage path diagram;
[0079] Specifically, the steps include the following:
[0080] S3.1: Read the wafer defect distribution map, analyze the spatial coordinate range of the high-risk area, and send it to the test platform control center; control the robotic arm to move the superconducting quantum interference device array directly above the high-risk area and adjust the distance between it and the surface of the semiconductor wafer under test; start the superconducting quantum interference device array to scan the high-risk area, apply test current to the test point of the semiconductor wafer under test using the probe card, collect magnetic field strength and direction data, and record them as electromagnetic field distribution data, specifically:
[0081] The wafer defect distribution map is read, and the spatial coordinate range data of the high-risk areas is extracted, including the X-axis and Y-axis boundary coordinates of each high-risk area. The spatial coordinate range data of the high-risk areas is converted into a standard format and transmitted to the test platform control center using the TCP protocol. The test platform control center receives the spatial coordinate range data of the high-risk areas, selects the center coordinates of the first high-risk area as the initial target position, and drives the robotic arm to move along the X-axis, Y-axis, and Z-axis to position the superconducting quantum interference device array directly above the center coordinates of the first high-risk area. The distance between the superconducting quantum interference device array and the surface of the semiconductor wafer under test is measured by a laser ranging sensor. After adjusting the Z-axis height of the robotic arm, the position of the superconducting quantum interference device array is confirmed to be stable, and the positioning data of the high-risk areas is generated.
[0082] Based on the location data of the high-risk area, the scanning function of the superconducting quantum interference device array is activated to cover the spatial coordinate range of the high-risk area. The probe card is used to contact the test point of the semiconductor wafer under test, and a test current is applied. The superconducting quantum interference device array collects the magnetic field strength and direction data of the high-risk area in real time through a high-sensitivity magnetic field sensor, records the magnetic field vector value of each scanning position, integrates the collected magnetic field strength and direction data into electromagnetic field distribution data, and stores it as a structured dataset.
[0083] S3.2: Transmit the electromagnetic field distribution data to the topology data analysis node of the distributed computing platform, use topology data analysis algorithms to extract continuous field structure features, construct a three-dimensional topology model, identify abnormal current loops, generate a leakage current path diagram, and mark the location and intensity, specifically:
[0084] S3.2.1: Transmit the electromagnetic field distribution data to the topology data analysis node of the distributed computing platform via the network interface; calculate the electromagnetic field distribution data using the topology data analysis algorithm, and extract continuous field structure features, such as closed loops or branch paths, using the persistent cohomology method, specifically:
[0085] Electromagnetic field distribution data is input into a topology data analysis algorithm. This data includes the spatial coordinates of the semiconductor wafer under test at each scanning position, as well as the corresponding magnetic field strength and direction vector. A point cloud dataset is constructed using this data, representing the spatial coordinates and corresponding magnetic field strength and direction at each scanning position. The topological features of the point cloud dataset are calculated using a persistent cohomology method. A Vietoris-Rips complex sequence is constructed, and the Vietoris-Rips complex filtering radius is progressively increased. Zero-dimensional and one-dimensional cohomology groups are calculated to generate a persistent barcode, expressed as:
[0086] ;
[0087] in, Ordered pairs representing topological features. Indicates the first The radius (or scale) at which a topological feature first appears during the Vietoris-Rips complex filtering process, also known as the birth radius. Indicates the first The radius (or scale) at which a topological feature disappears during complex filtering is also known as the death radius. The number representing the topological feature. This represents the total number of topological features extracted from electromagnetic field distribution data using the persistent cohomology method.
[0088] Special note, This refers to the standard mathematical expression of persistent barcodes, representing the lifecycle of topological features. Long-lived topological features are selected from persistent barcodes. For example, closed loops correspond to long-lasting features in a one-dimensional homology group, and branching paths correspond to merged features in a zero-dimensional homology group, generating a continuous field structure feature dataset.
[0089] S3.2.2: Based on the characteristics of the continuous field structure, a three-dimensional topological model reflecting the electromagnetic field distribution is constructed. Abnormal current loops in the three-dimensional topological model are analyzed, and current paths with closed or branched forms are identified. Specifically:
[0090] The continuous field structure feature dataset is input into the three-dimensional visualization processing software, and the closed loop and branch path are mapped to the three-dimensional spatial coordinate system. The Z-axis of the three-dimensional spatial coordinate system represents the weighted value of the magnetic field strength. The geometric representation of the continuous field structure features is constructed through spline interpolation, and a three-dimensional topological model reflecting the electromagnetic field distribution is generated to show the spatial distribution characteristics of the magnetic field strength.
[0091] The surface in the 3D topology model is analyzed to extract regions where the magnetic field strength exceeds the magnetic field threshold. The magnetic field threshold is set based on the mean and standard deviation of the magnetic field strength. The topological shape of the extracted regions is used to identify closed loops or branch paths. Closed loops are represented as circular current paths, while branch paths are represented as bifurcated or non-closed current trajectories. The closed loops and branch paths are mapped to the spatial coordinate system of the semiconductor wafer under test, and the location coordinates and morphological descriptions of abnormal current loops are recorded to generate an abnormal current loop dataset.
[0092] The abnormal current loop dataset is converted into a leakage current path diagram using visualization processing software. The location coordinates of the abnormal current loop are marked with highlighted lines, and the current intensity is represented by the color intensity (e.g., dark color represents high intensity). The leakage current path diagram with location and intensity labels is generated.
[0093] Preferably, traditional detection techniques often rely on statistical analysis or simple geometric methods, which are difficult to capture complex field structures. However, this method can effectively identify complex geometric shapes in electromagnetic field distribution data through persistent cohomology, overcoming the limitations of traditional methods for irregular defect patterns. Furthermore, it uses 3D visualization software to map the continuous field structure feature dataset to a 3D spatial coordinate system, generating a leakage path diagram. Compared with traditional 2D defect distribution maps, this method can provide more comprehensive spatial distribution information, making it easier for analysts to quickly and intuitively assess the severity and location of wafer defects.
[0094] S4: Using the wafer defect distribution map and leakage path map, perform principal component analysis to extract defect features such as defect density and leakage intensity, calculate the comprehensive defect score, and generate a test report.
[0095] Specifically, the steps include the following:
[0096] S4.1: Read the wafer defect distribution map and leakage path map, extract defect density data and leakage intensity data, and integrate them into a unified dataset; start the principal component analysis algorithm to extract the main features, input them into the pre-trained weighted linear regression model, and calculate the comprehensive defect score, specifically:
[0097] Access the wafer defect distribution map and extract the defect density data of the high-risk areas, including the spatial coordinates of each high-risk area and the corresponding lattice defect density value; access the leakage path map and extract the leakage intensity data of the abnormal current loops, including the spatial coordinates of each abnormal current loop and the corresponding current intensity value.
[0098] The defect density and leakage current data are preprocessed, including data cleaning, spatial coordinate standardization, and data alignment, to ensure a one-to-one correspondence between the spatial coordinates of the defect density and leakage current data. For example, the same X-axis and Y-axis grid division is used. The preprocessed defect density and leakage current data are then matched according to their spatial coordinates and merged into a unified dataset. This unified dataset contains the lattice defect density value and current intensity value corresponding to each spatial coordinate point and is stored in a structured format.
[0099] The unified dataset is input into the principal component analysis (PCA) algorithm. The PCA algorithm standardizes the lattice defect density and current intensity values in the unified dataset, calculates the mean and standard deviation of each feature, and generates a standardized unified dataset. Using the standardized unified dataset, the covariance matrix of the lattice defect density and current intensity values is calculated, expressed as:
[0100] ;
[0101] in, Represents the covariance matrix. This represents the total number of spatial coordinate points in the unified dataset. Represents the matrix form of the standardized unified dataset. Indicates transpose;
[0102] The covariance matrix is decomposed into eigenvalues to obtain eigenvalues and corresponding eigenvectors. The eigenvalues are sorted in descending order, and the eigenvectors corresponding to the two largest eigenvalues are selected as the principal eigenvectors to generate the principal eigenvector set.
[0103] The linear projection of each data point in the standardized unified dataset onto the principal feature vector set is calculated. Specifically, the standardized lattice defect density value and the standardized current intensity value are weighted and combined with the principal feature vectors to generate the coordinate value of each data point in the principal component space. The coordinate value represents the low-dimensional representation of the lattice defect density value and the current intensity value in the principal component space. The projection results of all data points are summarized to generate the principal feature dataset, which contains the two principal component values corresponding to each standardized spatial coordinate point.
[0104] Check the structure of the main feature dataset to ensure that each standardized spatial coordinate point corresponds to two principal component values, and verify that the dimension of the main feature dataset is the product of the total number of data points and the number of principal components. If missing or redundant principal component values are found, the main feature dataset is corrected, for example, by removing invalid data points or recalculating the projection. After confirming the completeness and correctness of the main feature dataset, the main feature dataset is output.
[0105] S4.1.1: Input the main feature dataset into the pre-trained weighted linear regression model. The pre-trained weighted linear regression model calculates the weighted score for each spatial coordinate point based on the principal component values in the main feature dataset, generating a comprehensive defect score dataset, specifically:
[0106] Historical defect data and leakage current intensity data are collected. Historical defect data includes lattice defect density values at spatial coordinate points on the semiconductor wafer under test, and leakage current intensity data includes current intensity values at corresponding spatial coordinate points. These data are then divided into a sample set, a training set, and a validation set according to their data type. The sample set is used for feature augmentation, the training set for weight parameter optimization, and the validation set for evaluating the performance of the weighted linear regression model. The resulting sample set, training set, and validation set are then generated. Feature augmentation is performed on the divided sample set by filling missing values in the historical defect data and leakage current intensity data using linear interpolation methods, such as interpolation based on the lattice defect density values or current intensity values of neighboring points. Feature scaling is also performed on the sample set, for example, scaling the lattice defect density values and current intensity values to a range of 0 to 1. Batch normalization is then used to standardize the sample set, calculating the mean and standard deviation of each batch of data. The lattice defect density values and current intensity values are adjusted to have a zero mean and a unit standard deviation to generate enhanced standard samples.
[0107] Forward computation is performed on the enhanced standard samples, combining the lattice defect density and current intensity values with the initial weight parameters in a weighted linear combination to generate the predicted values of the fitting matrix. The actual leakage current characteristic values corresponding to the lattice defect density and current intensity values are extracted from the training set to generate the actual values of the training set. The residual between the predicted values of the fitting matrix and the actual values of the training set is calculated to generate a residual tensor. The residual tensor is minimized using the least squares method to optimize the weight parameters of the fitting matrix, generating preliminary weight parameters. Ridge regression regularization is used to perform hyperparameter tuning on the preliminary weight parameters; for example, the regularization coefficient is adjusted to balance the complexity and fitting accuracy of the weighted linear regression model, generating optimized weight parameters. Multiple batches of parameterized stacks are performed on the enhanced standard samples through batch connection, integrating the optimized weight parameters to generate the constructed weighted linear regression model.
[0108] The training set is input into the constructed weighted linear regression model. The historical defect data and leakage current intensity data in the training set are dynamically weighted using the least squares method to generate intermediate weight parameters. Simultaneously, the validation set is input into the constructed weighted linear regression model, and the error between the predicted and actual values of the validation set is calculated to generate the validation set loss. The early stopping method is applied to monitor the validation set loss. Training is terminated when the validation set prediction error exceeds a predefined convergence threshold for 20 consecutive rounds. The predefined convergence threshold is set according to the testing requirements. The intermediate weight parameters are finally optimized using the least squares method to generate the trained weighted linear regression model.
[0109] The main feature dataset is input into a trained weighted linear regression model. The weighted linear regression model calculates the weighted score for each spatial coordinate point based on the principal component values in the main feature dataset and the optimized weight parameters, generating a comprehensive defect score dataset. The comprehensive defect score dataset is then post-processed, for example, by using a threshold check to verify whether each comprehensive defect score value is within a predefined range of 0 to 100. If it exceeds the range, it is adjusted to a boundary value to ensure the rationality of the comprehensive defect score dataset. Finally, the comprehensive defect score dataset is output.
[0110] S4.2: Based on the spatial coordinates of the leakage point, associate the corresponding wafer number, lattice defect type, and comprehensive defect score dataset to generate a test report dataset. The test report dataset contains the wafer number, lattice defect type, leakage point coordinates, and comprehensive defect score value for each spatial coordinate point. The test report dataset is then structured to generate a test report, thus completing the semiconductor testing.
[0111] Preferably, principal component analysis (PCA) is used to extract the main feature dataset through standardization and covariance matrix decomposition, preserving the main variation information of lattice defect density and current intensity values. Compared with traditional techniques that rely on raw data or simple statistical features (such as averages), this method reduces noise interference through dimensionality reduction, improving the accuracy and precision of feature extraction, making it suitable for complex wafer defect pattern analysis. Secondly, compared with traditional methods based on rule thresholds or simple linear models, this invention utilizes a pre-trained weighted linear regression model, optimizing weight parameters through least squares and ridge regression regularization. Based on the principal component values in the main feature dataset, a comprehensive defect score dataset is calculated, obtaining a comprehensive defect score value for each spatial coordinate point. This provides a more accurate defect score and balances the contributions of lattice defect density and current intensity values, significantly improving the ability to distinguish complex defects.
[0112] This embodiment also provides a semiconductor chip testing system, including:
[0113] The initialization module places the semiconductor wafer under test on the test platform, calibrates the terahertz time-domain spectroscopy device and the superconducting quantum interference device array, and generates an initialization report.
[0114] The defect module, based on the initialization report, uses a terahertz time-domain spectroscopy device to scan the semiconductor wafer under test, emits terahertz pulses to irradiate the surface of the semiconductor wafer under test, collects the reflection spectrum caused by lattice vibration, analyzes the phonon spectrum characteristics of the reflection spectrum, determines the type and spatial distribution of lattice defects, generates a wafer defect distribution map, and marks high-risk areas.
[0115] The leakage current module extracts high-risk areas based on the wafer defect distribution map, adjusts the test platform, scans the high-risk areas, applies test current to the test points of the semiconductor wafer under test through a superconducting quantum interference device array, collects electromagnetic field distribution data, and uses a topology data analysis algorithm to calculate, construct a three-dimensional topology model, identify abnormal current loops, and generate a leakage current path map.
[0116] The testing module uses the wafer defect distribution map and leakage path map to perform principal component analysis to extract defect features such as defect density and leakage intensity, calculates a comprehensive defect score, and generates a test report.
[0117] This embodiment also provides a computer device applicable to semiconductor chip testing methods, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the semiconductor chip testing method proposed in the above embodiment.
[0118] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.
[0119] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the semiconductor chip testing method proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.
[0120] In summary, this invention: By utilizing high-risk regions in a wafer defect distribution map and employing a superconducting quantum interference device array, magnetic field strength and direction data are collected to generate electromagnetic field distribution data. This data is then processed using a topological data analysis algorithm to construct a three-dimensional topological model, identify abnormal current loops, and generate a leakage path map. This achieves precise localization of microscopic leakage paths, overcomes the accuracy limitations of current compensation correction, and improves the localization accuracy of microscopic leakage paths, providing a reliable basis for evaluating the electrical performance of semiconductor chips. Furthermore, by integrating terahertz time-domain spectroscopy for material defect detection and superconducting quantum interference device-based electrical defect analysis, principal component analysis for dimensionality reduction and weighted linear regression scoring are used to provide a comprehensive quality assessment basis for chip manufacturing.
[0121] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A semiconductor chip testing method, characterized in that: include, Place the semiconductor wafer under test on the test platform, calibrate the terahertz time-domain spectroscopy device and the superconducting quantum interference device array, and generate an initialization report; According to the initialization report, the semiconductor wafer under test is scanned using a terahertz time-domain spectroscopy device, the surface of the semiconductor wafer under test is irradiated with terahertz pulses, the reflection spectrum caused by lattice vibration is collected, the phonon spectrum characteristics of the reflection spectrum are analyzed, the type and spatial distribution of lattice defects are determined, a wafer defect distribution map is generated, and high-risk areas are marked. High-risk areas are extracted from the wafer defect distribution map, the test platform is adjusted, the high-risk areas are scanned, and electromagnetic field distribution data is collected after applying test current to the test points of the semiconductor wafer under test through a superconducting quantum interference device array. The topology data analysis algorithm is used to calculate and construct a three-dimensional topology model, identify abnormal current loops, and generate a leakage path diagram. By using the wafer defect distribution map and leakage path map, principal component analysis is performed to extract defect features such as defect density and leakage intensity, and a comprehensive defect score is calculated to generate a test report.
2. The semiconductor chip testing method as described in claim 1, characterized in that: The semiconductor wafer under test is placed on the test platform, the terahertz time-domain spectroscopy device and the superconducting quantum interference device array are calibrated, and an initialization report is generated. An automated robotic arm fixes the semiconductor wafer under test to the vacuum adsorption fixture of the test platform, and the environmental parameters are obtained by adjusting the temperature and humidity of the test platform cavity through environmental control equipment. The terahertz time-domain spectrometer is calibrated using a standard silicon reference sample, the spectral response is adjusted, and the calibrated terahertz time-domain spectrometer status data is generated. By cooling the superconducting quantum interference device array with liquid nitrogen and applying a standard alternating current, calibrated channel consistency data of the superconducting quantum interference device array is generated. An initialization report is generated by integrating wafer number, environmental parameters, calibrated terahertz time-domain spectroscopy equipment status data, and calibrated superconducting quantum interference device array channel consistency data.
3. The semiconductor chip testing method as described in claim 2, characterized in that: The process involves using a terahertz time-domain spectroscopy device to scan the semiconductor wafer under test, emitting terahertz pulses to irradiate the surface of the semiconductor wafer under test, and collecting the reflection spectrum caused by lattice vibrations. Specifically... Read the calibrated terahertz time-domain spectrometer status data from the initialization report, start the terahertz time-domain spectrometer, and emit terahertz pulses to irradiate the surface of the semiconductor wafer under test through the focusing lens; A two-dimensional translation stage is controlled to move the semiconductor wafer under test for point-by-point scanning, and a photodetector is used to collect the reflection spectrum signal caused by lattice vibration.
4. The semiconductor chip testing method as described in claim 3, characterized in that: The analysis of the phonon spectrum characteristics of the reflection spectrum determines the type and spatial distribution of lattice defects, generates a wafer defect distribution map, and marks high-risk areas. Specifically, Terahertz reflection spectral data and theoretical spectral data calculated using first-principles calculations were collected from standard silicon wafer samples and integrated into a training dataset. A phonon scattering model was trained using a support vector machine with radial basis functions as kernel functions to establish the mapping relationship between phonon spectral characteristics and lattice defect types and lattice defect densities. The phonon spectrum characteristics of the reflected spectrum signal are analyzed by phonon scattering model and mapping relationship to determine the lattice defect type and lattice defect density, and a three-dimensional dataset is generated by combining a two-dimensional translation stage. The 3D dataset was used to generate a wafer defect distribution map using visualization software. Statistical analysis of the lattice defect density in the wafer defect distribution map is performed. A defect threshold is set and regions with lattice defect densities greater than the defect threshold are screened to generate high-risk regions.
5. The semiconductor chip testing method as described in claim 4, characterized in that: The acquisition of electromagnetic field distribution data refers to reading the location of high-risk areas in the wafer defect distribution map, positioning the superconducting quantum interference device array to the high-risk area using a robotic arm, adjusting the distance between the array and the surface of the semiconductor wafer under test, applying a test current to the test point of the semiconductor wafer under test using a probe card, and acquiring magnetic field strength and direction data through the superconducting quantum interference device array to generate electromagnetic field distribution data.
6. The semiconductor chip testing method as described in claim 5, characterized in that: The process involves using topology data analysis algorithms to construct a three-dimensional topology model, identify abnormal current loops, and generate a leakage current path diagram. Specifically... The electromagnetic field distribution data is transmitted to the topology data analysis node, and a point cloud dataset is constructed using the persistent cohomology method. Topological features are calculated, and a continuous field structure feature dataset is generated. Map the continuous field structure feature dataset to a three-dimensional spatial coordinate system to generate a three-dimensional topological model; Abnormal current loops are identified using a 3D topology model, an abnormal current loop dataset is generated, and visualization software is used to convert the abnormal current loop dataset into a leakage current path diagram.
7. The semiconductor chip testing method as described in claim 6, characterized in that: The defect features extracted by performing principal component analysis to determine defect density and leakage current intensity are specifically as follows: Defect density data and leakage current intensity data are extracted from wafer defect distribution maps and leakage current path maps, and then a unified dataset is generated after standardization processing. Input the unified dataset into the principal component analysis algorithm, calculate the covariance matrix, select the main eigenvectors, and generate the main feature dataset.
8. The semiconductor chip testing method as described in claim 7, characterized in that: The calculation of the comprehensive defect score is specifically as follows: Historical defect data and leakage current intensity data are collected, divided into sample set, training set and validation set, and enhanced standard samples are generated through linear interpolation and batch normalization. Forward computation is performed using enhanced standard samples, and the weight parameters are optimized using least squares and ridge regression regularization to generate a trained weighted linear regression model. Input the main feature dataset into the trained weighted linear regression model to calculate the comprehensive defect score dataset.
9. The semiconductor chip testing method as described in claim 8, characterized in that: The generation of test reports refers to generating a test report dataset based on wafer number, lattice defect type, and comprehensive defect score dataset, performing structured processing on the test report dataset, generating a test report, and completing semiconductor testing.
10. A semiconductor chip testing system, based on the semiconductor chip testing method according to any one of claims 1 to 9, characterized in that: include, The initialization module places the semiconductor wafer under test on the test platform, calibrates the terahertz time-domain spectroscopy device and the superconducting quantum interference device array, and generates an initialization report. The defect module, based on the initialization report, uses a terahertz time-domain spectroscopy device to scan the semiconductor wafer under test, emits terahertz pulses to irradiate the surface of the semiconductor wafer under test, collects the reflection spectrum caused by lattice vibration, analyzes the phonon spectrum characteristics of the reflection spectrum, determines the type and spatial distribution of lattice defects, generates a wafer defect distribution map, and marks high-risk areas. The leakage current module extracts high-risk areas based on the wafer defect distribution map, adjusts the test platform, scans the high-risk areas, applies test current to the test points of the semiconductor wafer under test through a superconducting quantum interference device array, collects electromagnetic field distribution data, and uses a topology data analysis algorithm to calculate, construct a three-dimensional topology model, identify abnormal current loops, and generate a leakage current path map. The testing module uses the wafer defect distribution map and leakage path map to perform principal component analysis to extract defect features such as defect density and leakage intensity, calculates a comprehensive defect score, and generates a test report.