System and method for power management using voltage drop monitoring

Abstract

The present technology relates to systems and methods for power management using voltage drop monitoring. In an embodiment, the present technology provides an apparatus including a voltage monitor including a signal generator configured to receive a clock signal and to generate a reference signal. A first circuit is coupled to the signal generator and configured to receive the reference signal and generate a first signal by providing a delay to the reference signal. The first circuit includes a first delay path characterized by a first threshold voltage. An edge detector is coupled to the first circuit and is configured to generate a second signal based on a timing difference between the first signal and the reference signal. The system enables accurate real-time detection of voltage fluctuations, thereby facilitating efficient power management and improved performance. Other embodiments are also present.

Description

Technical Field

[0001] This technology relates to semiconductor devices. Background Technology

[0002] The rapid development of artificial intelligence (AI) technologies has significantly increased the demand for complex and power-intensive chips, such as graphics processing units (GPUs) and tensor processing units (TPUs). These chips consist of arrays of identical cores optimized for parallel processing, which is beneficial for the computationally intensive tasks required in AI applications. However, the parallel nature of these operations increases the power consumption of these chips, posing challenges to data centers hosting AI servers.

[0003] The power demands of AI-driven computing systems are amplified by advancements in semiconductor technology. Transistor scaling methods, characteristic of Moore's Law, have evolved to accommodate modern chip architectures, including 2.5D and 3D stacking. These advanced architectures allow for higher computational throughput by integrating multiple transistor layers within a single chip or by placing multiple chips close together. While these technologies increase processing power, they also exacerbate power consumption challenges in AI-driven environments due to the higher density and power consumption associated with these designs.

[0004] Some methods for voltage monitoring and power management typically rely on polling mechanisms or external feedback systems, which introduce delays in detecting and responding to voltage drops. Furthermore, these systems are not always well-suited for managing the complexities of power dissipation in 2.5D and 3D stacked architectures, where the proximity of densely packaged components leads to more significant heat build-up and voltage fluctuations.

[0005] Various methods have been explored to improve power management in integrated circuits, but they have proven insufficient. It is important to recognize the need for new and improved power management methods and systems. Summary of the Invention

[0006] On one hand, this disclosure relates to a device including a voltage monitor, the voltage monitor comprising: a signal generator configured to receive a clock signal and generate a reference signal based on the clock signal; a first circuit coupled to the signal generator, the first circuit being configured to receive the reference signal and generate a first signal by providing a delay to the reference signal, the first circuit including a first delay path characterized by a first threshold voltage; and a detector coupled to the first circuit, the detector being configured to generate a second signal based on a timing difference between the first signal and the reference signal, the second signal being associated with a voltage change.

[0007] On the other hand, this disclosure relates to an apparatus including a processing unit comprising a voltage monitor, the voltage monitor comprising: a signal generator configured to receive a clock signal and generate a reference signal; a first circuit coupled to the signal generator, the first circuit being configured to receive the reference signal and generate a first signal by providing a delay to the reference signal; and a detector coupled to the first circuit, the detector being configured to generate a second signal based at least on a first timing difference between the first signal and the reference signal, the second signal being associated with a voltage change in the processing unit.

[0008] On the other hand, this disclosure relates to an apparatus including a voltage monitor, the voltage monitor comprising: a signal generator configured to receive a clock signal and generate a reference signal; a first circuit coupled to the signal generator, the first circuit including a first delay path configured to receive the reference signal and generate a first signal by providing a delay to the reference signal; and a detector coupled to the first circuit, the detector being configured to generate a second signal based at least on a timing difference between the first signal and the reference signal, the second signal being associated with a voltage change. Attached Figure Description

[0009] A further understanding of the nature and advantages of particular embodiments can be achieved by referring to the remainder of the specification and the accompanying drawings, wherein similar reference numerals are used to refer to similar components. In some instances, sub-labels are associated with reference numerals to identify one of a plurality of similar components. When reference numerals are mentioned without specifying existing sub-labels, it is desirable to refer to all such plurality of similar components.

[0010] Figure 1 This is a simplified diagram illustrating a semiconductor device according to an embodiment of the present technology.

[0011] Figure 2 This is a simplified diagram illustrating a processing unit with a voltage monitor according to an embodiment of the present technology.

[0012] Figure 3 This is a simplified diagram illustrating a voltage monitoring device according to an embodiment of the present technology.

[0013] Figure 4 This is a simplified diagram illustrating the configuration of the delay path within a voltage monitoring device according to an embodiment of the present technology.

[0014] Figure 5 This is a simplified diagram illustrating the output generated by an edge detector according to an embodiment of the present technology.

[0015] Figure 6This is a graph illustrating the chip voltage fluctuations over time according to an embodiment of the present technology, showing the minimum voltage recorded during operation.

[0016] Figure 7 This is a diagram illustrating a method for determining the temperature of a processing unit using one or more delay paths according to an embodiment of the present technology.

[0017] Figure 8 This is a diagram illustrating a method for programming a voltage drop indicator bit according to an embodiment of the present technology.

[0018] Figure 9 This is a flowchart illustrating a method for optimizing power management and performance in a semiconductor device using a voltage monitor, according to an embodiment of the present technology.

[0019] Figure 10 This is a diagram illustrating a method for controlling power regulation actions based on voltage drop events using programmable parameters according to an embodiment of the present technology.

[0020] Figure 11 This is a simplified diagram illustrating a semiconductor device according to an embodiment of the present technology. Detailed Implementation

[0021] This technology relates to a device for monitoring voltage changes in an electronic system. In one embodiment, the technology provides a device including a voltage monitor. The voltage monitor includes a signal generator configured to receive a clock signal and generate a reference signal. A first circuit is coupled to the signal generator and configured to receive the reference signal and generate a first signal by providing a delay to the reference signal. The first circuit includes a first delay path characterized by a first threshold voltage. An edge detector is coupled to the first circuit and configured to generate a second signal based on a timing difference between the first signal and the reference signal, wherein the second signal is associated with a voltage change. The system achieves accurate real-time detection of voltage fluctuations, thereby contributing to efficient power management and improved performance. Other embodiments also exist.

[0022] The following description is presented to enable those skilled in the art to make and use the invention, and is incorporated into the context of a particular application. Various modifications and uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein apply to a wide range of embodiments. Therefore, the invention is not intended to be limited to the presented embodiments, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

[0023] In the following detailed description, many specific details are set forth in order to provide a more thorough understanding of the present technology. However, those skilled in the art will understand that the present technology can be practiced without being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring the present technology.

[0024] This directs the reader's attention to all papers and documents filed concurrently with and publicly available for inspection with this specification, the contents of which are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any appended claims, abstracts, and figures) may be replaced by alternative features used for the same, equivalent, or similar purposes. Therefore, unless otherwise expressly stated, each disclosed feature is merely one example of a series of generally equivalent or similar features.

[0025] Furthermore, any element in the claims that is not expressly described as a "means" for performing the specified function or a "step" for performing a particular function shall not be construed as a "means" or "step" as specified in paragraph 6 of Chapter 112 of 35 U.S.C. Specifically, the use of "step" or "action" in the claims herein is not intended to invoke paragraph 6 of Chapter 112 of 35 U.S.C.

[0026] When an element is referred to herein as “connected” or “coupled” to another element, it should be understood that the element may be directly connected to the other element or that there may be an intermediary element between the elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, it should be understood that there is no intermediary element in the “direct” connection between the elements. However, the presence of a direct connection does not preclude the existence of other connections in which intermediary elements may be present.

[0027] When an element is referred to herein as being "placed" relative to another element in a certain way (e.g., placed on it, between it, below it, adjacent to it, or placed in some other relative manner), it should be understood that the element may be placed directly relative to the other element (e.g., placed directly on the other element), or that there may be an intervening element between these elements. Conversely, when an element is referred to as being "placed directly" relative to another element, it should be understood that there is no intervening element in the "direct" instance. However, the presence of direct placement does not preclude other instances in which intervening elements may be present.

[0028] Similarly, when an element is referred to herein as being “joined” to another element, it should be understood that the element may be directly joined to the other element (without any intermediary element), or that there may be an intermediary element between the joined elements. Conversely, when an element is referred to as being “directly joined” to another element, it should be understood that there is no intermediary element in the “direct” joint between the elements. However, the presence of a direct joint does not preclude other forms of joint in which an intermediary element may be present.

[0029] Similarly, when an element is referred to herein as a “layer,” it should be understood that the layer may be a single layer or comprise multiple layers. For example, a conductive layer may comprise a variety of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may comprise a variety of dielectric materials or multiple layers of dielectric materials. When a layer is described as coupled or connected to another layer, it should be understood that the coupled or connected layer may contain intermediary elements present between the coupled or connected layers. Conversely, when a layer is referred to as being “directly” connected or coupled to another layer, it should be understood that there are no intermediary elements between the layers. However, the presence of directly coupled or connected layers does not preclude the possibility of other connections where intermediary elements may exist.

[0030] Furthermore, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for interpretive purposes only and are not limited to any fixed direction or orientation. Rather, they are used only to indicate the relative position and / or orientation between the various parts of an object and / or component.

[0031] Furthermore, for ease of description, the methods and processes described herein may be described in a specific order. However, it should be understood that unless the context otherwise indicates, intermediate processes may occur before and / or after any part of the described process, and other procedures may be reordered, added, and / or omitted according to various embodiments.

[0032] Unless otherwise indicated, all figures used herein to express quantity, size, etc., should be understood to be modified by the term “about” in all instances. In this application, unless expressly stated otherwise, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms “and” and “or” means “and / or”. Furthermore, the use of the terms “comprising” and “having,” as well as other forms such as “includes / included” and “has / have / had,” should be considered non-exclusive. Moreover, unless expressly stated otherwise, terms such as “element” or “component” cover both elements and components that constitute a single unit and elements and components that constitute more than one unit.

[0033] As used herein, the phrase “at least one of…” preceding a series of items separated by the terms “and” or “or” modifies the list as a whole, not each member of the list (i.e., each item). The phrase “at least one of…” does not require selection of at least one of every listed item; rather, the phrase allows for the inclusion of at least one of any one item and / or at least one of any combination of items. For example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer only to A, only to B, or only to C; and / or any combination of A, B, and C. This is explicitly stated in examples where selection of “at least one of each of A, B, and C”, or alternatively, “at least one of A, at least one of B, and at least one of C”, is desired.

[0034] One general aspect includes a device comprising a voltage monitor, the voltage monitor comprising: a signal generator configured to receive a clock signal and generate a reference signal based on the clock signal; a first circuit coupled to the signal generator, the first circuit being configured to receive the reference signal and generate a first signal by providing a delay to the reference signal, the first circuit including a first delay path characterized by a first threshold voltage; and a detector coupled to the first circuit, the detector being configured to generate a second signal based on a timing difference between the first signal and the reference signal, the second signal being associated with a voltage change.

[0035] The implementation may include one or more of the following features. The first circuitry further includes a second delay path characterized by a second threshold voltage different from the first threshold voltage. The voltage monitor further includes a controller coupled to the first circuitry, the controller being configured to select the first delay path. The device further includes an encoder coupled to the detector, the encoder being configured to convert a second signal into a third signal representing an amount representing a voltage change. The first delay path is characterized by a first length, and the voltage monitor further includes a second circuit coupled to the first circuitry, the second circuitry being configured to adjust the first length at least based on the voltage change. The device further includes a logic unit coupled to the voltage monitorry, the logic unit being configured to generate a fourth signal to adjust operating parameters at least based on the voltage change. The operating parameters include a clock frequency or a supply voltage.

[0036] Another general aspect includes an apparatus comprising a processing unit including a voltage monitor, the voltage monitor comprising: a signal generator configured to receive a clock signal and generate a reference signal; a first circuit coupled to the signal generator, the first circuit being configured to receive the reference signal and generate a first signal by providing a delay to the reference signal; and a detector coupled to the first circuit, the detector being configured to generate a second signal based at least on a first timing difference between the first signal and the reference signal, the second signal being associated with a voltage change in the processing unit.

[0037] The implementation may include one or more of the following features: A first circuit includes a first delay path characterized by a first threshold voltage. The first circuit further includes a second delay path characterized by a second threshold voltage different from the first threshold voltage. A voltage monitor further includes a controller coupled to the first circuit, the controller being configured to select the first delay path. The voltage monitor is configured to determine the temperature of the processing unit based at least on a second signal. The processing unit further includes a logic unit coupled to the voltage monitor, the logic unit being configured to generate a third signal to adjust operating parameters of the processing unit based at least on voltage changes. Operating parameters include a clock frequency or a supply voltage.

[0038] Another general aspect includes a device comprising a voltage monitor, the voltage monitor comprising: a signal generator configured to receive a clock signal and generate a reference signal; a first circuit coupled to the signal generator, the first circuit including a first delay path configured to receive the reference signal and generate a first signal by providing a delay to the reference signal; and a detector coupled to the first circuit, the detector being configured to generate a second signal associated with a voltage change based at least on a timing difference between the first signal and the reference signal. The voltage monitor further includes a controller coupled to the first circuit, the controller being configured to select the first delay path. The first delay path is characterized by a first length, and the voltage monitor further includes a second circuit coupled to the first circuit, the second circuit being configured to adjust the first length. The device further includes a logic unit coupled to the voltage monitor, the logic unit being configured to generate a third signal to adjust operating parameters at least based on a voltage change. The operating parameters include a clock frequency or a supply voltage.

[0039] Figure 1This is a simplified diagram illustrating a semiconductor device 100 according to an embodiment of the present technology. This diagram is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. In various embodiments, the semiconductor device 100 may include integrated circuits (ICs) designed for various applications, such as AI computing, data processing, machine learning (ML), and / or the like. These applications require advanced power management systems due to high processing demands and the need for efficient energy use.

[0040] In one embodiment, semiconductor device 100 includes a core 102. For example, the term "core" may refer to the central processing area of ​​the semiconductor device responsible for performing primary processing tasks. Core 102 may support various operations, such as arithmetic calculations, data processing, control logic execution, deep learning, or high-speed data processing. Depending on the implementation, the core may be replicated within semiconductor device 100 to enable parallel processing for enhanced performance and efficiency. Core 102 may include, but is not limited to, a general-purpose core in a central processing unit (CPU), a dedicated core in a graphics processing unit (GPU), or a dedicated neural core designed to accelerate AI operations.

[0041] In various instances, core 102 includes an array of processing units. For example, core 102 includes processing unit 103. The term "processing unit" can refer to a computing unit within the core that performs a specific computational task. Processing unit 103 may include various functional blocks, such as an arithmetic logic unit (ALU), a control unit, memory registers, and / or the like.

[0042] In various implementations, processing unit 103 may include logic unit 104 and voltage monitor 105 (also referred to as voltage drop monitor VDM). The term "logic unit" can refer to a functional block responsible for managing computational tasks and local processing within the processing unit. For example, logic unit 104 may include basic computational circuitry, such as adders, multipliers, control logic, and / or the like. In some instances, logic unit 104 may be configured to perform memory and control functions, such as storing, retrieving, and manipulating data.

[0043] In some instances, voltage monitor 105 may be coupled to logic unit 104. The term "voltage monitor" or "voltage drop monitor" can refer to a component or circuit system designed to monitor and measure voltage levels within a processing unit. For example, voltage monitor 105 measures voltage at different points in processing unit 103, detecting voltage fluctuations or drops that may affect performance. Voltage fluctuations may be caused by changes in workload or variations in power supply, and voltage monitor 105 helps ensure that processing unit 103 continues to operate reliably by detecting and responding to such changes in real time. Depending on the implementation, one or more voltage monitors in semiconductor device 100 may share a common clock signal, which operates at a frequency close to or equal to that of the core functional block.

[0044] Voltage monitor 105 may work in conjunction with logic unit 104 to adjust the supply voltage and / or clock frequency by generating appropriate electrical signals based on detected voltage changes. This ensures that the voltage supplied to processing unit 103 is high enough to maintain functionality without becoming excessive, which helps minimize power dissipation and optimize overall efficiency. The term "supply voltage" may refer to the potential supplied to a circuit or component. In various instances, the supply voltage may range from the processor's core voltage to the voltage supplied to memory or other subsystems in the device. The term "clock frequency" may refer to the rate at which a clock signal oscillates, thereby determining the speed at which the processor or digital circuitry operates. In some instances, voltage monitor 105 detects voltage fluctuations or drops and transmits raw data or detection signals to logic unit 104. Logic unit 104 may process the data from voltage monitor 105 and generate one or more control signals (e.g., first signal 106 and / or second signal 107) to adjust the operating conditions of processing unit 103 based on voltage change information.

[0045] As an example, logic unit 105 may output a first signal 106 and / or a second signal 107 to adjust the operating parameters of processing unit 103. The term "operating parameters" may refer to any adjustable characteristic or setting that affects the performance, power consumption, or functionality of the processing unit. Examples of operating parameters may include, but are not limited to, supply voltage, clock frequency, power mode, processing speed, temperature threshold, and / or the like.

[0046] In some implementations, the first signal 106 may include a control signal for adjusting the voltage supplied to the processing unit 103, thereby ensuring that it remains within an optimal performance range without wasting power. The second signal 107 may include a control signal for adjusting the clock frequency of the processing unit 103, thereby allowing dynamic frequency scaling based on voltage levels and processing requirements. These control signals may be transmitted to a regulator 108, which, depending on the implementation, may be an on-chip power management component or an external voltage regulator. Upon receiving the signal, the regulator 108 adjusts the operating parameters (e.g., supply voltage and / or clock frequency) as instructed, thereby ensuring that the semiconductor device 100 operates within desired power and performance parameters.

[0047] Figure 2 This is a simplified diagram illustrating a processing unit 200 with a voltage monitor according to an embodiment of the present technology. This diagram is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. In various embodiments, the processing unit 200 may be a semiconductor device (e.g., Figure 1 The semiconductor device 100 is part of a semiconductor device that can be used in various applications such as AI computing, data processing or machine learning.

[0048] According to some embodiments, processing unit 200 includes a voltage monitor 201 and / or a logic unit 207, which work together to detect voltage fluctuations and adjust operating parameters to optimize power consumption and performance. For example, voltage monitor 201 includes a signal generator 202. For instance, the term "signal generator" can refer to a component or circuit that generates an electrical signal, which may be based on certain input parameters (e.g., a clock signal or voltage level). Signal generator 202 can generate signals for synchronization, control, or measurement purposes.

[0049] In some implementations, signal generator 202 may be configured to receive a clock signal. The term "clock signal" can refer to a periodically oscillating signal used for the operation of various components in a synchronous electronic system. For example, a clock signal can regulate the timing of operations in processing unit 200, thereby ensuring that different components of the system operate synchronously. In some instances, the clock signal may be derived from a core clock used across semiconductor devices, thereby allowing different processing units to remain synchronized during operation.

[0050] In some embodiments, signal generator 202 may be configured to generate a reference signal based on a clock signal. For example, the term "reference signal" may refer to a signal within the system used as a baseline for comparison or measurement purposes. The reference signal may maintain consistent timing or voltage characteristics and serve as a baseline against which other signals are compared to detect any voltage drops or fluctuations.

[0051] In various embodiments, voltage monitor 201 includes circuitry 203 coupled to signal generator 202. Circuitry 203 may be configured to receive a reference signal and generate a first signal by providing a delay to the reference signal. In some cases, circuitry 203 may also be referred to as a delay path circuit. For example, the term "delay" may refer to the time required for an electrical signal to propagate through a circuit or path. In circuitry 203, a delay may be introduced to measure changes in the speed of signal propagation, which may be affected by voltage fluctuations. Voltage affects the switching speed of transistors or other components within circuitry 203. For example, when the voltage drops, the switching speed of components decreases, thereby increasing the delay. Conversely, when the voltage stabilizes or increases, the switching speed increases, thereby reducing the delay. The relationship between voltage and delay makes it possible to use delay as an indicator of voltage changes within a system.

[0052] Circuit 203 provides delay information on a time scale equivalent to a clock cycle period, thereby ensuring real-time detection of voltage changes. By introducing a delay into the reference signal from signal generator 202, circuit 203 can generate a first signal that is offset from the reference signal in time. The first signal can then be compared with the reference signal to detect how much the delay has changed, thereby providing a voltage change indication in processing unit 200.

[0053] In various implementations, voltage monitor 201 includes a controller 204 coupled to circuit 203. For example, the term "controller" can refer to a circuit or component that manages, directs, or regulates the operation of other components within a system. In some instances, controller 204 may be responsible for managing the operation of circuit 203 and controlling its behavior in response to changing conditions (e.g., process, voltage, temperature, and / or the like). For example, controller 204 may be configured to select or adjust delay paths within circuit 203, as will be described in more detail below.

[0054] In some embodiments, voltage monitor 201 includes detector 205 coupled to circuit 203. The term "detector" can refer to circuitry designed to identify and process changes in signal characteristics, such as signal transitions or edges. For example, detector 205 may include an edge detector configured to detect and measure timing differences between signal transitions, such as rising or falling edges of a reference signal and a first signal generated by circuit 203.

[0055] In various instances, detector 205 may be configured to generate a second signal based on a timing difference between a first signal and a reference signal. The term "timing difference" can refer to the time interval or difference between two related events (e.g., transition points of electrical signals, such as rising or falling edges). The timing difference can indicate the amount of delay introduced by circuitry 203, which is associated with voltage changes in processing unit 200. The term "voltage change" can refer to any change in the voltage level supplied to the circuitry, such as an increase or decrease in voltage over time. For the purposes of this disclosure, "voltage change" and "voltage drop" may be used interchangeably depending on the context to describe voltage fluctuations.

[0056] In some implementations, voltage monitor 201 may further include circuitry 206, which can be configured to adjust parameters of circuitry 203 (e.g., the path length of the delay path) to achieve a baseline reading that can effectively measure voltage drop. In some cases, circuitry 206 may also be referred to as calibration circuitry. Calibration ensures that a balanced baseline reading is maintained to accurately detect voltage changes. Depending on the implementation, calibration may be performed during periods of low chip activity, allowing the system to establish a stable baseline under static conditions. Once calibrated, circuitry 206 ensures that the system can measure voltage drop with high accuracy during normal operating conditions, where voltage fluctuations can affect the performance of processing unit 200.

[0057] In various implementations, logic unit 207 may receive a second signal from detector 205, reflecting voltage changes within processing unit 200. Logic unit 207 may be configured to interpret the second signal and determine whether corrective action is needed to optimize power consumption or performance. For example, if a voltage fluctuation detected by voltage monitor 201 indicates a voltage drop, then logic unit 207 may generate a control signal to optimize power management. In some implementations, logic unit 207 may communicate with a voltage regulator or clock management circuitry to adjust the voltage or clock frequency.

[0058] Figure 3 This is a simplified diagram illustrating a voltage monitoring device 300 according to an embodiment of the present technology. This diagram is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art.

[0059] In some embodiments, the voltage monitor 300 may include a signal generator 301 configured to receive a clock signal from a clock source 307. For example, the clock source 307 may include, but is not limited to, an internal oscillator, a phase-locked loop (PLL), an external clock generator, and / or the like. In some instances, the clock source 307 may include a dedicated system clock that provides a reference frequency for the entire semiconductor device. In some embodiments, the signal generator 301 may be configured to generate a reference signal based on the clock signal. The reference signal can be used as a baseline to which other signals are compared to detect any voltage drop or fluctuation.

[0060] In various embodiments, voltage monitor 300 includes circuitry 303 coupled to signal generator 301. Circuitry 303 may be configured to receive a reference signal and generate a first signal by providing a delay to the reference signal. The delay introduced by circuitry 303 provides an indication of voltage changes within a semiconductor device. In some instances, circuitry 303 may include one or more delay paths, each characterized by different threshold voltages or configurations (e.g., path lengths), thereby allowing it to adapt to various operating conditions (e.g., process, voltage, temperature, and / or the like). The term "delay path" may refer to an electrical path or circuit that introduces a measurable delay to signal propagation.

[0061] exist Figure 3 In the embodiment described herein, circuit 303 includes three delay paths: a first delay path 309a (e.g., path 0), a second delay path 309b (e.g., path 1), and a third delay path 309c (e.g., path 2). The internal components of the delay paths may include, but are not limited to, transistor-based logic circuits, resistor-capacitor (RC) circuits, or other delay-inducing components that ensure a measurable time difference is introduced into each path as the reference signal propagates.

[0062] The delay path can be characterized by different threshold voltages and / or lengths. The term "threshold voltage" can refer to the minimum voltage level required to activate the transistor or other switching elements within the delay path. The threshold voltage determines the sensitivity of the delay path to voltage variations. For example, a lower threshold voltage allows the delay path to be more sensitive to smaller voltage fluctuations, while a higher threshold voltage makes the path less sensitive to small voltage variations but more stable under certain conditions. In some instances, the first delay path 309a can be characterized by a first threshold voltage. The second delay path 309b can be characterized by a second threshold voltage, different from the first threshold voltage.

[0063] The term "length" or "path length" refers to the physical or electrical distance a signal must travel through a given circuit path. By designing delay paths of different lengths, the system can fine-tune the sensitivity and resolution of the voltage monitoring process. By incorporating one or more delay paths with different threshold voltages and lengths, the system can adapt to different operating conditions. This allows the voltage monitor 300 to operate across a wide voltage range, thus enabling an adaptive voltage monitoring system that can adapt to a wide range of operating conditions.

[0064] In some implementations, only one delay path can be selected at a time, based on the operating conditions of the semiconductor device. The ability to select a specific delay path based on process, voltage, or temperature (PVT) conditions ensures that circuit 303 can adjust its sensitivity and resolution for specific operating conditions. The selection process can be managed by multiplexer 308, which is configured to receive control signals (e.g., sel_path[1:0]) and route reference signals through the selected delay path, which then generates a delayed signal (e.g., a first signal) for monitoring voltage changes within the system.

[0065] In various embodiments, the voltage monitor 300 further includes a controller 302 coupled to the circuit 303. The controller 302 can be configured to manage the operation of delay paths within the circuit 303. For example, the controller 302 can generate one or more control signals (e.g., path_enable[2:0] and / or cfg_length0[3:0] to cfg_length2[3:0]) to control the enabling of specific delay paths and configure their lengths based on the operational needs of the system. Depending on the implementation, the delay paths in the circuit 303 can be configurable in length, thereby providing flexibility in adapting to different clock frequencies and PVT conditions.

[0066] According to some embodiments, the voltage monitor 300 further includes a detector 304 coupled to the circuit 303. For example, the detector 304 may include an edge detector configured to detect and measure a timing difference between signal transitions, such as rising or falling edges of a reference signal and a first signal generated by the circuit 303. The detector 304 may be configured to generate a second signal based on the timing difference between the first signal and the reference signal. The timing difference indicates the amount of delay introduced by the circuit 303, which is associated with voltage changes in the processing unit.

[0067] In various embodiments, the output of detector 304 (e.g., a second signal) can provide feedback on voltage conditions within the semiconductor device. The second signal may represent the degree of delay introduced by a selected delay path in circuit 303, corresponding to a voltage change. In some cases, the second signal may consist of a series of binary values ​​(e.g., a series of 1s followed by a series of 0s), where the length of the series of 1s is related to the magnitude of the detected voltage drop.

[0068] In some instances, the second signal may be further processed by an edge selector 305 coupled to detector 304. The term "edge selector" may refer to a component or circuit designed to isolate and select transitions or edges of a signal. For example, edge selector 305 may receive the second signal from detector 304 and isolate specific edges (e.g., rising or falling edges) to refine the detection of voltage changes.

[0069] In various embodiments, the voltage monitor 300 further includes an encoder 306. The term "encoder" can refer to a component or circuit that converts one data format into another. For example, encoder 306 may be configured to convert a second signal into a third signal representing an amount representing a voltage change. In some cases, encoder 306 may include a logic circuitry system for calculating a binary value proportional to the instantaneous voltage drop. In an example, encoder 306 may be configured to receive an output (e.g., a second signal) from detector 304 and convert it into a binary format. This conversion simplifies the representation of detected voltage fluctuations, making processing and interpretation within the system easier.

[0070] Figure 4 This is a simplified diagram illustrating the configuration of a delay path 400 within a voltage monitoring device according to an embodiment of the present technology. This diagram is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. In various embodiments, the delay path 400 may be a delay path circuit designed to measure voltage fluctuations in a semiconductor device (e.g., Figure 3 The circuit 303) part.

[0071] As shown, delay path 400 may include a series of configurable delay stages (e.g., 401a to e), each of which introduces an incremental delay to the input signal (e.g., s_in) as it propagates through the path to produce an output signal (e.g., s_out). In various embodiments, delay path 400 can be configured to various lengths using control signals (e.g., cfg_length[3:0]). These control signals determine how many delay stages are included in the path the signal travels from the input to the output. The flexibility of the path length allows the system to adjust its sensitivity to voltage fluctuations. In this example, the length of delay path 400 can be adjusted to up to 16 different lengths, such as... Figure 4 The diagram shows how the voltage monitor can maintain accurate measurements across a wide range of operating parameters.

[0072] Figure 5 This is a simplified diagram illustrating a 128-bit output generated by a voltage monitor 500 according to an embodiment of the present technology. This diagram is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art.

[0073] As shown, voltage monitor 500 includes detector 501, which can be coupled to different components within voltage monitor 500. For example, detector 501 is configured to receive representations of different delay paths (e.g., from different delay paths within voltage monitor 500) Figure 3 One or more voltage-related signals (e.g., signals 502, 503, and 504) of the delay path 309a to c). These signals can be processed by detector 501 to evaluate the reference signal and the voltage-related signals generated by the delay path circuit (e.g., ...). Figure 3 The timing difference between the delayed signals generated by the circuit 303).

[0074] In various instances, detector 501 may output a thermometer-style reading, represented as a binary sequence (e.g., 128 bits). For example, the output signal 505 of detector 501 may contain a series of 1s followed by a series of 0s, where the number of 1s corresponds to the magnitude of the detected voltage drop. The boundary position 506 between the series of 1s and 0s serves as an indicator of the speed at which the signal propagates through the delay path, which is associated with the voltage level in the semiconductor device.

[0075] Voltage monitors can operate in various modes depending on the system's operating state and the desired monitoring behavior. These modes provide flexibility in tracking and analyzing voltage behavior, enabling the system to adjust power settings and / or record voltage data in real time for information and diagnostic purposes. For example, in the first mode (which may also be referred to as real-time voltage monitoring), the voltage monitor polls for voltage drop information at periodic intervals while the semiconductor device is in functional mode. The first mode allows the system to monitor voltage changes in real time and make immediate adjustments to operating parameters (such as voltage and clock frequency) for power optimization.

[0076] The second mode (also known as worst-case voltage monitoring) can be used to capture the worst-case voltage drop over a selected time interval while the semiconductor device is operating in its functional mode. In this mode, the voltage monitor can enable a feature called sticky_mode, which retains the lowest voltage reading recorded during the monitoring period. This ensures that the lowest voltage point experienced during operation is preserved for informational purposes. The second mode can be useful for post-operation analysis or debugging where the voltage behavior of the system under different operating conditions can be evaluated.

[0077] The third mode (also known as the test mode) can be used during diagnostic and testing procedures, such as scan tests or transition delay fault (TDF) tests. In this mode, the sticky_mode feature is enabled, and the voltage monitor captures and holds the lowest voltage drop experienced during the test. The third mode can be used for data collection and debugging purposes, providing information about the voltage characteristics of the semiconductor device under controlled test conditions.

[0078] Figure 6 Figure 600 illustrates chip voltage fluctuations over time according to an embodiment of the present technology, showing the minimum voltage recorded during operation. This figure is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. As shown, the sticky_mode feature can be enabled in a second or third mode, where the voltage monitor captures and holds the lowest voltage drop recorded during the monitoring period. The captured minimum voltage 601 provides an indication of the lowest point reached during the monitoring period, thereby ensuring that even transient voltage drops can be retained for subsequent analysis.

[0079] Figure 7 Figure 700 illustrates a method for determining the temperature of a processing unit using one or more delay paths according to an embodiment of the present technology. This figure is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art.

[0080] In various implementations, a voltage monitor can be configured to determine the temperature of the processing unit. For example, the delay behavior of different delay paths varies with temperature due to the effects of temperature on transistor mobility and threshold voltage (e.g., Vt). For delay paths with higher threshold voltages (e.g., SVT paths), the decrease in threshold voltage dominates as temperature increases, resulting in path acceleration. In contrast, for paths with lower threshold voltages (e.g., ULVT paths), the decrease in mobility due to increased temperature has a greater impact than the decrease in threshold voltage, resulting in path deceleration. By comparing the delays of different paths (e.g., SVT and ULVT paths), the voltage monitor can infer the temperature of the processing unit. The difference in voltage drop between these paths (e.g., in...) Figure 7 The symbol (denoted as "δ") can be used as a temperature indicator. In some instances, the system can be calibrated at room temperature (or another reference temperature) so that any systematic change in the voltage drop between delay paths can be used to detect temperature fluctuations.

[0081] Figure 8Figure 800 illustrates a method for programming a voltage drop indicator bit according to an embodiment of the present technology. This figure is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be appreciated by those skilled in the art.

[0082] In various embodiments, the system can utilize pre-programmed voltage drop indicator bits to achieve real-time detection of voltage drops within the semiconductor device. Each indicator bit is configured with a specific voltage drop threshold, allowing the system to respond quickly to different levels of voltage drop. Figure 8 As shown, bits 0 through 8 can be programmed with increasing voltage drop thresholds, ensuring real-time monitoring of a wide voltage drop range. When a voltage drop event occurs, the corresponding drop indicator bit is triggered, generating a signal to initiate corrective actions, such as adjusting the voltage or clock frequency to stabilize the system. This immediate response ensures fast and efficient power management, reducing the likelihood of system instability caused by power fluctuations.

[0083] Figure 9 This is a flowchart illustrating a method 900 for optimizing power management and performance in a semiconductor device using a voltage monitor, according to an embodiment of the present technology. This figure is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art.

[0084] At step 901, method 900 may include synchronizing the processing unit array with dedicated voltage monitors. Each voltage monitor may be supplied with a fixed-frequency clock to maintain synchronization across the array. Synchronization ensures that all voltage monitors within the system operate based on the same fixed-frequency clock, thereby allowing consistent voltage measurements across the entire semiconductor device.

[0085] At step 902, method 900 may include performing a calibration routine on all voltage monitors during idle mode. The calibration process may be performed under static chip conditions to establish a reference voltage for each voltage monitor, thereby providing a baseline for further monitoring.

[0086] At step 903, method 900 may include monitoring transient voltage drops and / or temperature. For example, during functional mode, a voltage monitor array continuously monitors the voltage drop across processing units on a cycle-by-cycle basis. This allows the system to capture any voltage fluctuations in real time and detect temperature changes that may affect the performance of the semiconductor device.

[0087] At step 904, method 900 may include applying adjustments to operating parameters based on monitored voltage drops and / or temperatures. These adjustments may involve dynamically modifying the processing unit's voltage supply, clock frequency, or other operating parameters to maintain stable and efficient operation. By applying these adjustments in response to monitored data, the system can maintain consistent performance under varying workload conditions and prevent performance degradation caused by voltage or thermal fluctuations.

[0088] In various implementations, adjustments to operating parameters may involve scaling the clock frequency, voltage supply, or both to ensure the processing unit operates within desired power and performance ranges. These adjustments may be based on real-time data collected from a voltage monitor that continuously tracks voltage and / or temperature fluctuations across the processing unit. For example, in a frequency scaling scenario, the system may adjust the clock frequency while maintaining a constant voltage supply. This approach is useful when small adjustments to processing speed are needed to address workload variations without increasing power consumption. By decreasing or increasing the clock frequency in response to monitored data, the system can prevent processing unit overload and maintain high performance. In a frequency and voltage scaling scenario, the system may adjust both the clock frequency and voltage supply to ensure power efficiency.

[0089] Figure 10 Figure 1000 illustrates a method for controlling power regulation action based on voltage drop events using programmable parameters according to an embodiment of the present technology. This figure is merely illustrative and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art. In various embodiments, logic units (e.g., Figure 2 The logic unit 207 may include a register set storing user-defined voltage and frequency scaling settings. The stored settings may include programmable parameters, such as voltage thresholds and time intervals for triggering and stopping power regulation actions.

[0090] In some instances, the system can be programmed with threshold parameters to trigger power regulation actions when certain conditions are met. For example... Figure 10 The time interval Δt is shown in the figure. A This can represent the time interval within which the voltage drop must persist for the system to activate power regulation. If the voltage drop duration exceeds Δt... A The logic unit can then activate energy-saving or current-throttling mechanisms to stabilize system performance. In some embodiments, the system can be programmed with a voltage upper limit and a corresponding time interval Δt. B , in Δt B Afterward, the power throttling routine can be turned off. This allows the system to resume normal operation once the voltage stabilizes, thus ensuring that the power regulation mechanism does not activate unnecessarily.

[0091] In various implementations, the logic unit can be designed to enhance debug capabilities by incorporating a register set that continuously records voltage monitoring data for a predetermined number of clock cycles. In the event of a functional problem occurring on the chip, the recorded values ​​can be read and analyzed to help debug the cause of the fault.

[0092] Figure 11 This is a simplified diagram illustrating a semiconductor device 1100 according to an embodiment of the present technology. This diagram is merely illustrative and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be recognized by those skilled in the art.

[0093] In various embodiments, the semiconductor device 1100 may include a first circuit 1101 and a second circuit 1102 stacked in a 3D configuration. The first circuit 1101 may represent a main processing unit, which may include elements such as a processing core, logic unit, or other digital components. The second circuit 1102 may serve as support circuitry and may include power management components such as a voltage regulator, a phase-locked loop (PLL), or other circuitry responsible for controlling and optimizing the power supply to the first circuit 1101. The vertical stacking of these circuits allows for efficient communication between them, enabling the second circuit 1102 to monitor and regulate the power conditions of the first circuit 1101.

[0094] In some instances, the first circuit 1101 may include a voltage monitor configured to monitor voltage fluctuations in real time (e.g., Figure 2 (Voltage monitor 201). The voltage monitor can send signals to the second circuit 1102, where the power supply can be adjusted—for example, by modulating the output of a voltage regulator—to ensure stable and efficient operation of the semiconductor device 1100.

[0095] In some embodiments, the second circuit 1102 may include logic units (e.g. Figure 2 The logic unit 207 may contain a programmable algorithm for managing voltage and frequency scaling. The logic unit is used to adjust the operating conditions of the first circuit 1101 by controlling the supply voltage and clock frequency based on real-time monitoring data. In some cases, the second circuit 1102 may host a clock source, such as a PLL, to control the frequency of the first circuit 1101, thereby allowing different processing units to be tuned to their optimal operating conditions.

[0096] In various implementations, the first circuit 1101 and the second circuit 1102 are connected via an interconnect 1103, which allows data and control signals to flow between the two circuits. This ensures that the second circuit 1102 can adjust the power supply and clock frequency of the first circuit 1101 in real time, thereby optimizing the overall performance and power efficiency of the semiconductor device 1100.

[0097] While the foregoing is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the foregoing description and illustrations should not be construed as limiting the scope of the technology as defined by the appended claims.

Claims

1. A device including a voltage monitor, the voltage monitor comprising: A signal generator configured to receive a clock signal and generate a reference signal based on the clock signal; A first circuit coupled to the signal generator, the first circuit being configured to receive the reference signal and generate a first signal by providing a delay to the reference signal, the first circuit including a first delay path characterized by a first threshold voltage; and A detector coupled to the first circuit is configured to generate a second signal based on a timing difference between the first signal and the reference signal, the second signal being associated with a voltage change.

2. The device of claim 1, wherein the first circuit further includes a second delay path characterized by a second threshold voltage different from the first threshold voltage.

3. The device of claim 1, wherein the voltage monitor further includes a controller coupled to the first circuit, the controller being configured to select the first delay path.

4. The device of claim 1, further comprising an encoder coupled to the detector, the encoder being configured to convert the second signal into a third signal representing an amount representing the voltage change.

5. The device of claim 1, wherein the first delay path is characterized by a first length, the voltage monitor further comprising a second circuit coupled to the first circuit, and the second circuit being configured to adjust the first length at least based on the voltage change.

6. The device of claim 1, further comprising a logic unit coupled to the voltage monitor, the logic unit being configured to generate a fourth signal to adjust operating parameters at least based on the voltage change.

7. The device according to claim 6, wherein the operating parameters include clock frequency or supply voltage.

8. An apparatus including a processing unit, the processing unit including a voltage monitor, the voltage monitor comprising: A signal generator configured to receive a clock signal and generate a reference signal; A first circuit coupled to the signal generator is configured to receive the reference signal and generate the first signal by providing a delay to the reference signal. and A detector coupled to the first circuit is configured to generate a second signal based at least on a first timing difference between the first signal and the reference signal, the second signal being associated with a voltage change in the processing unit.

9. The device of claim 8, wherein the first circuit includes a first delay path characterized by a first threshold voltage.

10. The device of claim 9, wherein the first circuit further includes a second delay path characterized by a second threshold voltage different from the first threshold voltage.

11. The device of claim 9, wherein the voltage monitor further includes a controller coupled to the first circuit, the controller being configured to select the first delay path.

12. The device of claim 8, wherein the voltage monitor is configured to determine the temperature of the processing unit based at least on the second signal.

13. The device of claim 8, wherein the processing unit further includes a logic unit coupled to the voltage monitor, the logic unit being configured to generate a third signal to adjust the operating parameters of the processing unit at least based on the voltage change.

14. The device of claim 13, wherein the operating parameters include clock frequency or supply voltage.

15. An apparatus including a voltage monitor, the voltage monitor comprising: A signal generator configured to receive a clock signal and generate a reference signal; A first circuit coupled to the signal generator, the first circuit including a first delay path configured to receive the reference signal and generate the first signal by providing a delay to the reference signal; and A detector coupled to the first circuit, the detector being configured to generate a second signal based at least on the timing difference between the first signal and the reference signal, the second signal being associated with a voltage change.

16. The device of claim 15, wherein the voltage monitor further includes a controller coupled to the first circuit, the controller being configured to select the first delay path.

17. The device of claim 15, wherein the first delay path is characterized by a first length, and the voltage monitor further includes a second circuit coupled to the first circuit, and the second circuit is configured to adjust the first length.

18. The device of claim 15, further comprising a logic unit coupled to the voltage monitor, the logic unit being configured to generate a third signal to adjust operating parameters at least based on the voltage change.

19. The device of claim 18, wherein the operating parameters include a clock frequency.

20. The device of claim 18, wherein the operating parameters include the supply voltage.

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