Wide-range bipolar enabling negative voltage stabilizer and control method

Abstract

The embodiment of the invention relates to the technical field of power voltage stabilizers, in particular to a wide-range bipolar enabled negative voltage stabilizer and a control method, and the method comprises the steps: receiving a wide-range bipolar external enable signal; inputting the external enable signal to a positive pressure signal processing path and a negative pressure signal processing path in parallel for independent detection and processing; in the positive voltage signal processing path, a positive polarity voltage signal is clamped and identified by using the threshold value characteristic of a first NMOS (N-channel Metal Oxide Semiconductor) transistor; in the negative voltage signal processing path, the negative polarity voltage signal is clamped and identified by using the threshold value characteristic of a second NMOS (N-channel Metal Oxide Semiconductor) transistor; performing level conversion and logic conditioning on the intermediate signals processed by the two paths to generate internal enable control signals; and according to the internal enabling control signal, controlling the starting or shutoff of the negative-pressure low-voltage-difference linear voltage regulator, and performing performance optimization when the negative-pressure low-voltage-difference linear voltage regulator is controlled to be started.

Description

Technical Field

[0001] This application relates to the field of power voltage regulator technology, and in particular to a wide-range bipolar enabled negative voltage regulator and its control method. Background Technology

[0002] With the rapid advancement of integrated circuit technology and the increasing prevalence of IoT nodes and portable electronic devices, these highly integrated systems place extremely stringent demands on power management. Power management chips, as a core component, bear the critical responsibility of isolating external power interference and providing a continuous, stable voltage, directly impacting the performance and reliability of the entire system. Among numerous power management solutions, low-dropout linear regulators (LDL-LEF) have become an ideal choice for powering precision chips due to their high integration, low quiescent power consumption, excellent power supply rejection ratio (PSRR), and low output noise.

[0003] Traditional low-dropout linear regulators typically operate in the positive voltage domain. However, in advanced applications such as communication infrastructure, medical electronics, industrial automation, and test and measurement, traditional negative-voltage low-dropout linear regulators cannot accommodate both positive and negative bipolar enable signals. This necessitates additional level-shifting circuitry, leading to system complexity and high power consumption. Systems often need to handle both positive and negative voltage rails simultaneously, for example, to provide negative power to operational amplifiers, sensors, or display drivers. This has created an urgent need for negative-voltage low-dropout linear regulators. Such negative regulators face a unique system-level challenge: in modern mixed-voltage systems, the central processing unit responsible for unified power timing control can typically only output enable signals in the positive voltage domain, directly contradicting the negative voltage enable logic required by negative regulators. Therefore, advanced negative regulator designs must overcome this limitation by integrating innovative circuit structures such as level shifting to enable intelligent response to control signals from the positive voltage domain. This allows for reliable start-stop control under a single positive voltage enable signal, simplifying system power management design and improving the overall integration and reliability of the solution. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a wide-range bipolar enabled negative voltage regulator and control method. This solves the problem that traditional negative voltage low dropout linear regulators cannot be compatible with positive and negative bipolar enable signals, requiring additional level conversion circuits that lead to system complexity and high power consumption. At the same time, it improves the stability of the negative voltage low dropout linear regulator under different load conditions. It is applicable to fields such as communication infrastructure, medical and health, and industrial instrumentation, and has wide versatility and practicality.

[0005] To achieve the above objectives, the present invention provides a wide-range bipolar enabled negative voltage regulator control method, comprising:

[0006] Step S1: Receive a wide-range, bipolar external enable signal;

[0007] Step S2: Input the external enable signal in parallel to one positive pressure signal processing path and one negative pressure signal processing path for independent detection and processing;

[0008] Step S3: In the positive voltage signal processing path, the threshold characteristics of the first NMOS transistor are used to clamp and identify the positive voltage signal; in the negative voltage signal processing path, the threshold characteristics of the second NMOS transistor are used to clamp and identify the negative voltage signal.

[0009] Step S4: The intermediate signals after processing the two paths are level-converted and logic-conditioned to generate an internal enable control signal.

[0010] Step S5: Based on the internal enable control signal, control the start-up or shutdown of the negative voltage low differential linear regulator, and perform performance optimization when controlling the start-up of the negative voltage low differential linear regulator.

[0011] Furthermore, in step S2, the positive pressure signal processing path and the negative pressure signal processing path are input and current-limited through high-resistance resistors.

[0012] Furthermore, in step S3, the threshold voltage of the first NMOS transistor is used to limit the amplitude of the positive input signal within a first preset voltage range, while the threshold voltage of the second NMOS transistor is used to limit the amplitude of the negative input signal within a second preset voltage range.

[0013] Further, in step S3, the first preset voltage range is 98% to 102% of the threshold voltage of the first NMOS transistor, and the second preset voltage range is 98% to 102% of the threshold voltage of the second NMOS transistor.

[0014] Furthermore, in step S4, the level conversion and logic conditioning of the intermediate signals after processing the two paths includes:

[0015] Step S41: The intermediate signal from the negative voltage signal processing path is inverted and level-shifted by an inverter circuit composed of PMOS transistors and NMOS transistors.

[0016] Step S42: The signal after level shifting is combined with the intermediate signal from the positive pressure signal processing path;

[0017] Step S43: The merged signals are processed by a logic gate to generate an internal enable control signal for controlling the negative pressure low differential linear regulator.

[0018] Furthermore, in step S43, the logic gate is a NOR gate, whose first input terminal receives the output signal from the inverter circuit, and whose second input terminal directly receives the intermediate signal from the positive voltage signal processing path.

[0019] Furthermore, in step S5, performance optimization during the startup of the low-dropout linear regulator with negative pressure control includes:

[0020] Based on the change in output load current, an adaptive gate bias is provided to the power adjustment transistor of the negative voltage low dropout linear regulator, while the frequency compensation characteristics of the loop are dynamically adjusted.

[0021] Furthermore, in step S5, the frequency compensation characteristics of the dynamically adjusted loop include:

[0022] Step S51: Real-time detection of the output load current of the negative voltage low differential linear regulator;

[0023] Step S52: Based on the detected load current value, automatically switch the compensation network structure in the negative voltage low differential linear regulator loop;

[0024] Step S53: Under light load conditions, the dominant pole frequency is configured to a first frequency value, and under heavy load conditions, the dominant pole frequency is configured to a second frequency value.

[0025] A wide-range bipolar enabled negative voltage regulator applied to the aforementioned wide-range bipolar enabled negative voltage regulator control method, comprising:

[0026] A bidirectional enable circuit is used to process positive or negative enable signals and generate internal enable control signals.

[0027] A bandgap reference is used to provide a stable bandgap voltage that does not change with temperature.

[0028] A gain module, connected to the bandgap reference, is used to multiply the bandgap voltage by a fixed coefficient to generate a reference voltage.

[0029] An error amplifier, whose first input terminal receives the reference voltage and whose second input terminal is connected to a feedback node;

[0030] A buffer is connected to the output of the error amplifier;

[0031] The power transistor is an NMOS power transistor, whose gate is connected to the output terminal of the buffer, whose source is connected to the negative power supply voltage VIN, and whose drain is used as the output voltage VOUT.

[0032] The error amplifier, buffer, and power transistor form an analog feedback loop, which is used to modulate the power transistor to achieve a stable output voltage.

[0033] The bidirectional enable circuit, bandgap reference, gain module, error amplifier, buffer, and power transistor are integrated on the same chip.

[0034] Furthermore, the bidirectional enable circuit includes:

[0035] An input current-limiting resistor is connected at one end to an external enable signal input terminal.

[0036] The positive voltage signal processing branch includes a first NMOS transistor whose gate and source are cross-connected to the other end of the input current limiting resistor to form a positive voltage signal clamping structure for limiting the positive voltage enable signal.

[0037] The negative voltage signal processing branch includes a second NMOS transistor, a third NMOS transistor, a PMOS transistor, and a resistor, which is used to process the negative voltage enable signal and convert the signal to a suitable operating range.

[0038] The level conversion module includes a common-source, common-gate, inverting structure composed of the PMOS transistor and the third NMOS transistor;

[0039] The logic synthesis module employs NOR gate logic, and its two input terminals receive signals from the level conversion module and the positive voltage signal processing branch, respectively, to generate an internal enable control signal.

[0040] Compared with the prior art, the beneficial effect of the present invention is that, in the conventional structure, the body terminal of the NMOS transistor is usually grounded. When a negative voltage enable signal is input, the source voltage of MN1 is much lower than its body terminal, which will cause the source-body parasitic diode to be forward biased and conduct, generating a large current path. This not only increases static power consumption, but may also cause latch-up effect leading to circuit failure. The present invention completely eliminates the forward bias risk of this parasitic diode by connecting the body terminal of MN1 to the most negative potential (VEE). For MN4, when its source voltage increases due to positive voltage input, the conventional body effect will cause its threshold voltage to increase, causing the clamping point to drift. The present invention eliminates its own body effect by shorting the source terminal of MN4 to the body terminal, keeping its threshold voltage stable, thereby ensuring the accuracy and consistency of the positive voltage clamping point.

[0041] Furthermore, this invention utilizes the process-dependent threshold voltage of NMOS transistors. This design realizes a circuit mechanism that is simple in structure, can automatically adapt to different semiconductor processes, and can reliably clamp and protect the positive and negative bidirectional enable signals. This method not only ensures the safety of subsequent circuits but also provides accurate start-stop criteria. At the same time, it achieves a good balance between performance and power consumption, enhancing the robustness and manufacturability of the entire chip.

[0042] Furthermore, this invention successfully merges the processing paths of positive and negative polarity enable signals through a NOR gate logic decision circuit, realizing intelligent recognition and unified response to bidirectional enable signals. This circuit can not only correctly start the LDO under both valid inputs, but also ensure the absolute safety of the system through a priority shutdown mechanism. At the same time, its simple structure helps to reduce chip area and power consumption, demonstrating the comprehensive advantages of high reliability, high integration and excellent anti-interference.

[0043] Furthermore, this invention links the bias circuit with the load state. Under light load, a small bias current is used. Although the switching speed of the power transistor is slightly slower, it effectively reduces the static power consumption introduced by the bias circuit itself, which is suitable for low power consumption scenarios. Under heavy load or sudden load increase, it immediately switches to a large bias current to provide the power transistor gate with fast charging and discharging capability, which greatly improves the response speed and avoids large output voltage drops or overshoots caused by insufficient gate drive.

[0044] Furthermore, this invention intelligently solves the classic stability problem of LDO loop characteristics changing drastically with load by sensing the load status in real time and automatically adjusting the loop compensation network. It ensures that the negative voltage low dropout linear regulator maintains excellent stability and transient response across the entire load range. At the same time, its model-based design method gives designers powerful optimization capabilities, ultimately realizing a high-performance, highly robust, and user-independent adaptive system.

[0045] Furthermore, this invention, through a bidirectional enable circuit design, achieves compatible startup of the negative voltage low-dropout linear regulator with both positive and negative polarity enable signals, significantly improving the control integration and flexibility in mixed voltage systems. Existing negative voltage low-dropout linear regulators typically only respond to negative enable signals and cannot be directly controlled by positive voltage signals output by digital control units such as MCUs. This necessitates the addition of level conversion or inverting circuits, resulting in structural complexity, response delay, and increased cost. This invention innovatively proposes a dual-path enable circuit structure, achieving reliable startup under both positive and negative enable signals. The same enable signal can simultaneously control both positive and negative power domains, greatly simplifying the system power management architecture, reducing the complexity of peripheral circuits and overall cost, and providing crucial support for highly integrated power systems.

[0046] Furthermore, this invention features ultra-low quiescent current, effectively reducing standby power consumption and making it suitable for power-sensitive new energy and portable devices. Existing negative-voltage low-dropout linear regulators often suffer from high quiescent current during standby or startup, especially in wide-voltage applications where their power consumption disadvantage is more pronounced, limiting their application in battery-powered scenarios. This invention, by optimizing circuit structure and device parameters, maintains extremely low quiescent current in both positive and negative voltage startup states, significantly reducing system standby power consumption, extending device battery life, and improving energy efficiency.

[0047] Furthermore, this invention broadens the applicable voltage range and application scenarios of negative voltage low-dropout linear regulators (LDLs), supporting more robust power management solutions. Traditional LDLs have limitations in enable signal recognition range and load adaptability, making it difficult to meet the high requirements for voltage accuracy and stability in communication, industrial control, and precision analog systems. This invention, through an internal dual-path coordination and feedback control mechanism, enables the enable circuit to achieve consistent and reliable on / off thresholds over a wide voltage range, enhancing the LDO's operational stability under complex voltage environments and opening up possibilities for its application in high-end communication equipment, medical electronics, and automotive electronics.

[0048] Furthermore, this invention achieves compatible startup of the negative voltage low dropout linear regulator with both positive and negative polarity enable signals through dual-path enable circuit design and body bias technology, eliminating the need for additional level conversion circuits, simplifying the system power management architecture, and reducing the complexity of peripheral circuits and overall cost. This invention optimizes the enable circuit structure and device parameters, enabling the enable circuit to maintain ultra-low quiescent current in both positive and negative voltage startup states, reducing system standby power consumption and extending the battery life of battery-powered devices.

[0049] Furthermore, this invention provides adaptive gate bias based on load current and dynamically adjusts loop frequency compensation characteristics to solve the stability problem of LDO loop characteristics changing drastically with load, ensuring excellent stability and transient response across the entire load range; it utilizes the threshold characteristics of NMOS transistors to achieve signal clamping, automatically adapting to different semiconductor processes, enhancing chip robustness and manufacturability, and broadening the applicable voltage range and application scenarios of negative voltage low dropout linear regulators. Attached Figure Description

[0050] Figure 1 This is a flowchart of the wide-range bipolar enabled negative voltage regulator control method of the present invention;

[0051] Figure 2 This is a structural flowchart of the negative pressure low differential pressure linear regulator of the present invention;

[0052] Figure 3 This is the enable waveform diagram of the enable circuit of this invention;

[0053] Figure 4 This is a circuit diagram of the enabling module of the present invention;

[0054] Figure 5 This is a timing diagram of the voltage waveforms at voltage nodes (points A to D) in the enable circuit of this invention. Detailed Implementation

[0055] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0056] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0057] Please see Figure 1 As shown, Figure 1 This is a flowchart of the control method for a wide-range bipolar enabled negative voltage regulator according to the present invention.

[0058] The present invention provides a wide-range bipolar enabled negative voltage regulator control method, comprising:

[0059] Step S1: Receive a wide-range, bipolar external enable signal;

[0060] Step S2: Input the external enable signal in parallel to one positive pressure signal processing path and one negative pressure signal processing path for independent detection and processing;

[0061] Step S3: In the positive voltage signal processing path, the threshold characteristics of the first NMOS transistor (MN4) are used to clamp and identify the positive voltage signal; in the negative voltage signal processing path, the threshold characteristics of the second NMOS transistor (MN1) are used to clamp and identify the negative voltage signal.

[0062] Step S4: The intermediate signals after processing the two paths are level-converted and logic-conditioned to generate an internal enable control signal.

[0063] Step S5: Based on the internal enable control signal, control the start-up or shutdown of the negative voltage low differential linear regulator, and perform performance optimization when controlling the start-up of the negative voltage low differential linear regulator.

[0064] In this embodiment of the invention, the voltage range of the external enable signal typically covers -5.5V to +5.5V. This range ensures compatibility with common positive logic levels (e.g., 1.8V, 3.3V, 5V) and typical negative power supply domains (e.g., -3.3V, -5V). The lower limit of the range (most negative voltage) is determined by the breakdown voltage and process tolerance of the second NMOS transistor (MN1), ensuring that the circuit is not damaged. The upper limit of the range (most positive voltage) is determined by the gate oxide reliability and breakdown voltage of the first NMOS transistor (MN4). The criterion for a wide range is that the input signal voltage is within the safe input voltage range allowed by the circuit design, and this range must simultaneously contain meaningful positive and negative voltage values. The criterion for bipolarity is that the circuit has the ability to distinguish between positive and negative valid signals and intermediate invalid signals, and can make a unified and correct response (activate LDO) to valid signals of both polarities.

[0065] In this embodiment of the invention, the threshold characteristics of the first NMOS transistor (MN4) and the second NMOS transistor (MN1) are used for clamping and identification in step S3, which further includes: introducing a cross-coupled body biasing technique to connect the body terminal of the first NMOS transistor (MN4) to its source, and connecting its source and body terminal together to the input current limiting resistor; at the same time, connecting the body terminal of the second NMOS transistor (MN1) to the negative power supply voltage.

[0066] In traditional structures, the body of an NMOS transistor is typically grounded. When a negative voltage enable signal is input, the source voltage of MN1 is much lower than its body, causing the source-body parasitic diode to be forward biased and conduct, creating a large current path. This not only increases static power consumption but may also trigger a latch-up effect, leading to circuit failure. This invention completely eliminates the forward bias risk of this parasitic diode by connecting the body of MN1 to the most negative potential (VEE). For MN4, when its source voltage increases due to a positive voltage input, the traditional body effect causes its threshold voltage to increase, resulting in clamping point drift. This invention eliminates its own body effect by shorting the source of MN4 to its body, keeping its threshold voltage stable, thereby ensuring the accuracy and consistency of the positive voltage clamping point.

[0067] Specifically, in step S2, the positive pressure signal processing path and the negative pressure signal processing path use high-resistance resistors for signal input and current limiting.

[0068] Specifically, in step S3, the threshold voltage of the first NMOS transistor is used to limit the amplitude of the positive input signal within a first preset voltage range, and the threshold voltage of the second NMOS transistor is used to limit the amplitude of the negative input signal within a second preset voltage range. The body terminal of the first NMOS transistor is shorted to the source terminal, and the body terminal of the second NMOS transistor is connected to the negative power supply voltage VIN.

[0069] Specifically, in step S3, the first preset voltage range is 98% to 102% of the absolute value of the threshold voltage of the first NMOS transistor, and the second preset voltage range is 98% to 102% of the absolute value of the threshold voltage of the second NMOS transistor.

[0070] In this embodiment of the invention, the threshold voltages of the first NMOS transistor (MN4) and the second NMOS transistor (MN1) are inherent electrical parameters determined by those skilled in the art based on the selected semiconductor manufacturing process (e.g., standard CMOS process), with typical values ​​ranging from 0.3V to 0.7V. In a specific embodiment of the invention, to achieve optimal signal clamping and power consumption balance, an NMOS transistor with a threshold voltage of approximately 0.5V is preferably selected; therefore, the first preset voltage range and the second preset voltage range are also determined by the selected process. For example, when a process with a threshold voltage of 0.5V is selected, the first preset voltage range is approximately 0.49V to 0.51V; if a process with a threshold voltage of 0.7V is selected, the range is correspondingly approximately 0.686V to 0.714V.

[0071] This invention utilizes the process-dependent threshold voltage of NMOS transistors. This design realizes a circuit mechanism that is simple in structure, can automatically adapt to different semiconductor processes, and can reliably clamp and protect positive and negative bidirectional enable signals. This method not only ensures the safety of subsequent circuits, but also provides accurate start-stop criteria, while achieving a good balance between performance and power consumption, thus enhancing the robustness and manufacturability of the entire chip.

[0072] Specifically, in step S4, the level conversion and logic conditioning of the intermediate signal after processing the two paths includes:

[0073] Step S41: The intermediate signal from the negative voltage signal processing path is inverted and level-shifted by an inverter circuit composed of PMOS transistors and NMOS transistors.

[0074] Step S42: The signal after level shifting is combined with the intermediate signal from the positive pressure signal processing path;

[0075] Step S43: The merged signals are processed by a logic gate to generate an internal enable control signal for controlling the negative pressure low differential linear regulator.

[0076] Specifically, in step S43, the logic gate is a NOR gate, whose first input terminal receives the output signal from the inverter circuit, and whose second input terminal directly receives the intermediate signal from the positive voltage signal processing path.

[0077] In this embodiment of the invention, a logic gate is used to process the merged signals to generate an internal enable control signal for controlling the negative voltage low-dropout linear regulator. Specifically, the logic gate is a NOR gate, and its logic function is: when any input terminal is high, the output is low; only when all input terminals are low, the output is high. The implementation of this process is as follows: when a valid positive voltage enable signal is received, the intermediate signal from the positive voltage signal processing path (i.e., the second input signal of the NOR gate) is low; at the same time, the intermediate signal from the negative voltage signal processing path is level-converted by an inverter and input to the first input of the NOR gate, which is also low. At this time, both inputs of the NOR gate are at a low level. According to its logic function, it outputs a high level. This high-level signal serves as a valid internal enable control signal, controlling the negative voltage low-dropout linear regulator to start. When a valid negative voltage enable signal is received, the intermediate signal from the positive voltage signal processing path (i.e., the signal at the second input of the NOR gate) is at a low level. Simultaneously, the intermediate signal from the negative voltage signal processing path is level-converted by an inverter and input to the first input of the NOR gate, which is at a high level. At this time, since the first input of the NOR gate is at a high level, according to its logic function, it outputs a low level. This low-level signal serves as a valid internal enable control signal, controlling the negative voltage low-dropout linear regulator to start. When no valid enable signal is received or the enable signal is invalid, the intermediate signal from the positive voltage signal processing path (i.e., the signal at the second input of the NOR gate) is at a high level. In this case, regardless of the signal state at the first input of the NOR gate (high or low), since the second input is already high, the output of the NOR gate will be forced to a low level. This low-level signal acts as an invalid internal enable control signal, keeping the negative voltage low-dropout linear regulator in the off state.

[0078] This invention successfully merges the processing paths of positive and negative polarity enable signals through an NOR gate logic decision circuit, realizing intelligent recognition and unified response to bidirectional enable signals. This circuit can not only correctly start the LDO under both valid inputs, but also ensure the absolute safety of the system through a priority shutdown mechanism. At the same time, its simple structure helps to reduce chip area and power consumption, demonstrating the comprehensive advantages of high reliability, high integration and excellent anti-interference.

[0079] Specifically, in step S5, performance optimization during the startup of the low-dropout linear regulator with negative pressure control includes:

[0080] Based on the change in output load current, an adaptive gate bias is provided to the power adjustment transistor of the negative voltage low dropout linear regulator, while the frequency compensation characteristics of the loop are dynamically adjusted.

[0081] In this embodiment of the invention, the adaptive gate bias provided to the power regulator is specifically achieved through a charge pump bias circuit based on load current. The driving capability of this charge pump bias circuit is regulated by the digital control signal output by the load detection and compensation switching circuit. Under light load conditions, it outputs a first bias current, and under heavy load conditions, it outputs a second bias current several times the first bias current to dynamically change the gate charging speed of the power regulator, thereby optimizing its transient response. The first bias current is set as the minimum necessary current to maintain the stable operation of the charge pump circuit itself. Its value must ensure that it can provide a bias to the gate of the power regulator higher than its subthreshold leakage current, thereby maintaining the stability of the gate potential, but not enough to support a fast transient response. Its typical order of magnitude is 10nA~100nA. The second bias current is determined according to the target load transient response time and the gate voltage swing (ΔV_gate) of the power regulator. Its calculation formula satisfies the following relationship:

[0082] I_bias2≈C_gate×ΔV_gate / t_target;

[0083] Where C_gate is the total gate capacitance of the power regulator, ΔV_gate is the gate voltage change required for the power regulator to go from the off state to full turn-on (or vice versa), and t_target is the required gate voltage settling time of the system (which is directly related to the load transient response time).

[0084] This invention links the bias circuit with the load state. Under light load, a small bias current is used. Although the switching speed of the power transistor is slightly slower, it effectively reduces the static power consumption introduced by the bias circuit itself, which is suitable for low power consumption scenarios. Under heavy load or sudden load increase, it immediately switches to a large bias current to provide the power transistor gate with fast charging and discharging capability, which greatly improves the response speed and avoids large output voltage drop or overshoot caused by insufficient gate drive.

[0085] Specifically, in step S5, the frequency compensation characteristics of the dynamically adjusted loop include:

[0086] Step S51: Real-time detection of the output load current of the negative voltage low differential linear regulator;

[0087] Step S52: Based on the detected load current value, automatically switch the compensation network structure in the negative voltage low differential linear regulator loop;

[0088] Step S53: Under light load conditions, the dominant pole frequency is configured to a first frequency value, and under heavy load conditions, the dominant pole frequency is configured to a second frequency value.

[0089] In this embodiment of the invention, the determination of light load and heavy load conditions is based on the ratio of the output load current of the low-dropout linear regulator to its maximum rated output current (IMAX). This determination is automatically completed by an internal load detection and window comparison circuit. When the real-time detected output load current ILOAD ≤ 10%IMAX, the circuit determines that the current condition is light load. When the real-time detected output load current ILOAD ≥ 50%IMAX, the circuit determines that the current condition is heavy load. The first and second frequency values ​​are not fixed values, but are determined by circuit model calculation based on the topology of the low-dropout linear regulator, output capacitor, load capacitor, target phase margin, and transconductance of the power regulator.

[0090] This invention intelligently solves the classic stability problem of LDO loop characteristics changing drastically with load by sensing the load status in real time and automatically adjusting the loop compensation network. It ensures that the negative voltage low dropout linear regulator maintains excellent stability and transient response across the entire load range. At the same time, its model-based design method gives designers powerful optimization capabilities, ultimately realizing a high-performance, highly robust, and user-independent adaptive system.

[0091] Please see Figures 2-5 As shown, Figure 2 This is a structural flowchart of the negative pressure low differential pressure linear regulator of the present invention; Figure 3 This is the enable waveform diagram of the enable circuit of this invention; Figure 4 This is a circuit diagram of the enabling module of the present invention; Figure 5 This is a timing diagram of the voltage waveforms at voltage nodes (points A to D) in the enable circuit of this invention.

[0092] Specifically, a wide-range bipolar enabled negative voltage regulator applied to the aforementioned wide-range bipolar enabled negative voltage regulator control method includes:

[0093] A bidirectional enable circuit is used to process positive or negative enable signals and generate internal enable control signals.

[0094] A bandgap reference is used to provide a stable bandgap voltage that does not change with temperature.

[0095] A gain module, connected to the bandgap reference, is used to multiply the bandgap voltage by a fixed coefficient to generate a reference voltage.

[0096] An error amplifier, whose first input terminal receives the reference voltage and whose second input terminal is connected to a feedback node;

[0097] A buffer is connected to the output of the error amplifier;

[0098] The power transistor is an NMOS power transistor, whose gate is connected to the output terminal of the buffer, whose source is connected to the negative power supply voltage VIN, and whose drain is used as the output voltage VOUT.

[0099] The error amplifier, buffer, and power transistor form an analog feedback loop, which is used to modulate the power transistor to achieve a stable output voltage.

[0100] The bidirectional enable circuit, bandgap reference, gain module, error amplifier, buffer, and power transistor are integrated on the same chip.

[0101] Specifically, the bidirectional enable circuit includes:

[0102] An input current-limiting resistor is connected at one end to an external enable signal input terminal.

[0103] The positive voltage signal processing branch includes a first NMOS transistor whose gate and source are cross-connected to the other end of the input current limiting resistor to form a positive voltage signal clamping structure for limiting the positive voltage enable signal.

[0104] The negative voltage signal processing branch includes a second NMOS transistor (MN1), a third NMOS transistor (MN3), a PMOS transistor (MP1), and resistors R2 to R6, which are used to process the negative voltage enable signal and convert the signal to a suitable operating range.

[0105] The level conversion module includes a common-source cascode inverting structure composed of the PMOS transistor (MP1) and the third NMOS transistor (MN3), which is used to output the inverted negative voltage processing signal;

[0106] The logic synthesis module employs NOR gate logic, and its two input terminals receive signals from the level conversion module and the positive voltage signal processing branch, respectively, to generate an internal enable control signal.

[0107] In this embodiment of the invention, a bandgap reference is used to provide a stable bandgap voltage that does not change with temperature. This voltage is approximately 1.2V. The gain module multiplies the bandgap voltage by a fixed coefficient to obtain a reference voltage. A fuse is typically configured in the gain module to adjust the gain coefficient to obtain the desired voltage. The reference voltage is sent to the input of the error amplifier. The error amplifier, buffer, and power transistor constitute an analog feedback loop. Typically, the loop gain of the feedback loop is large. In this design, the entire analog loop is a unity-gain circuit used to modulate the power transistor, achieving good static characteristics (such as load regulation and line regulation) and good dynamic characteristics (such as power supply rejection and noise). Unlike a positive voltage LDO, this negative voltage low-dropout linear regulator operates in the range of -5V to 0V, and the power supply voltage is at the bottom of the circuit, using the negative power supply VIN as the power supply voltage. When the LDO outputs a large current, it draws current from VIN. Due to the regulation of the closed-loop circuit, the output voltage VOUT remains relatively stable.

[0108] In this embodiment of the invention, the enable circuit needs to meet the requirement of bidirectional enable, that is, regardless of whether the enable signal is in a positive voltage state or a negative voltage state, it needs to be able to start the negative voltage low dropout linear regulator normally. The enable circuit signal waveform is shown in Figure 3. When the enable signal is in the negative voltage operating range, the negative voltage low dropout linear regulator can start normally when the enable voltage is in the range of -5 to Vth1 (this voltage is the threshold voltage). When the enable signal is in the positive voltage operating range, the negative voltage low dropout linear regulator works normally when the enable voltage is in the range of Vth2 (this voltage is the threshold voltage) to 5V.

[0109] The enable circuit in this invention is as follows: Figure 4As shown, GND is the zero voltage in this design, VIN is the negative power supply, and EN is the enable signal. This circuit mainly consists of two paths. The first path, composed of R1 and MN4, directly processes the input enable signal. The second path, composed of MN1-MN3, MP1, and R2-R6, processes the enable signal, converting it to a suitable operating range for the enable circuit to handle. When the enable signal EN is positive, the gate-source voltage VGS of the switching transistor MN4 (source and body shorted) is V - EN - V_R1 (R1 is the voltage across the input current-limiting resistor). When VGS is greater than the threshold voltage, MN4 turns on, clamping the positive voltage signal. Therefore, MN4 acts like a voltage limiter, preventing voltages exceeding 0V in the first path from entering the Schmitt trigger input. Similarly, for MN1, since the gate voltage is 0V, MN1 will only turn on when VGS is greater than the threshold voltage, thus preventing voltages greater than 0V from entering the second path. In a negative voltage low-dropout linear regulator system, logic levels are usually defined with GND (0V) as the reference point. A high level refers to 0V or a positive voltage (relative to the negative power supply VIN); a low level refers to a negative voltage (such as -5V).

[0110] In this embodiment of the invention, Figure 5 This is a timing diagram analysis of the specific working process of the enable circuit in this invention, where signals A through D represent... Figure 5The waveform information at points A to D in the diagram is shown. The dashed lines represent the voltage at the same moment, and -5V to 5V is the operating voltage range. The following analysis details two scenarios: negative voltage enable startup and positive voltage enable startup. Negative voltage startup: In signal region 1, as the enable signal increases from -5V to -900mV (threshold voltage), the voltage at point A gradually rises following the enable signal after MN1 turns on, and only rises to a maximum of -900mV. For the voltage at point B, since the gate voltage and source voltage of MP1 are the same, MP1 will not turn on, and the voltage at point B remains at -5V. Therefore, MN3 will not conduct, the voltage at point C is 0V, and the voltage at point D almost follows the enable signal. Finally, after passing through a NAND gate, the output voltage OUT is 0V, and the negative voltage low-dropout linear regulator starts. In signal region 2, when the enable signal rises from -900mV to 600mV, the gate of MN1 is grounded and the source is connected to the input, VGS = 0V - V - EN. When V - EN (the voltage value corresponding to the external enable signal EN) > -900mV, VGS < the threshold voltage, MN1 is cut off, and the voltage at point A remains around -900mV. As the enable signal gradually rises, the gate voltage of MP1 remains at -900mV. When the enable signal causes the VGS voltage of MP1 to meet the conduction condition, the signal at point B slowly turns on and rises. The signal at point C will remain at 0V. Since the voltage at point D is also limited by MN4, it can only reach a maximum of approximately -900mV. After passing through the NAND gate, the output voltage OUT is -5V, and the low-dropout linear regulator is turned off. Positive voltage start-up: In signal region 3, when the enable signal decreases from 600mV (threshold voltage) to 5V and then from 5V back to 600mV, the voltage at point A is limited by MN1, and can only rise to a maximum of -900mV. For the voltage at point B, as the difference between the gate and source voltages of MP1 gradually increases, the conduction degree of MP1 becomes increasingly greater. The voltage at point B, limited by MN2, can only reach a maximum of -900mV. However, the voltage at point C decreases to -5V due to the conduction of MN3. At this time, the voltage at point D remains at the fixed threshold, so after passing through the NAND gate, the output voltage OUT is 0V, and the low-dropout linear regulator is started. In signal region 4, similar to signal region 2, the OUT output is -5V, and the low-dropout linear regulator is turned off. In signal region 5, similar to signal region 1, the OUT output is 0V, and the negative voltage low differential linear regulator starts.

[0111] This invention, through a bidirectional enable circuit design, achieves compatible startup of a low-dropout negative voltage regulator with both positive and negative polarity enable signals, significantly improving the control integration and flexibility in mixed voltage systems. Existing low-dropout negative voltage regulators typically only respond to negative enable signals and cannot be directly controlled by positive voltage signals output by digital control units such as MCUs. This necessitates the addition of level conversion or inverting circuits, resulting in structural complexity, response delay, and increased cost. This invention innovatively proposes a dual-path enable circuit structure, achieving reliable startup under both positive and negative enable signals. The same enable signal can simultaneously control both positive and negative power domains, greatly simplifying the system power management architecture, reducing the complexity of peripheral circuits and overall cost, and providing crucial support for highly integrated power systems.

[0112] This invention features ultra-low quiescent current, effectively reducing standby power consumption and making it suitable for power-sensitive new energy and portable devices. Existing low-dropout linear regulators often suffer from high quiescent current during standby or startup, especially in wide-voltage applications, where their power consumption disadvantage is more pronounced, limiting their application in battery-powered scenarios. This invention optimizes the circuit structure and component parameters, enabling the circuit to maintain extremely low quiescent current under both positive and negative voltage startup conditions, significantly reducing system standby power consumption, extending device battery life, and improving energy efficiency.

[0113] This invention broadens the applicable voltage range and application scenarios of low-dropout linear regulators (LDLs), supporting more robust power management solutions. Traditional LDLs have limitations in enable signal recognition range and load adaptability, making it difficult to meet the high voltage accuracy and stability requirements of communication, industrial control, and precision analog systems. This invention, through an internal dual-path coordination and feedback control mechanism, enables the enable circuit to achieve consistent and reliable on / off thresholds over a wide voltage range, enhancing the LDO's operational stability under complex voltage environments and opening up possibilities for its application in high-end communication equipment, medical electronics, and automotive electronics.

[0114] This invention achieves compatible startup of a negative voltage low-dropout linear regulator with both positive and negative polarity enable signals through a dual-path enable circuit design and body bias technology, eliminating the need for additional level conversion circuits, simplifying the system power management architecture, and reducing the complexity of peripheral circuits and overall cost. This invention optimizes the enable circuit structure and device parameters, ensuring that the enable circuit maintains ultra-low quiescent current in both positive and negative voltage startup states, reducing system standby power consumption and extending the battery life of battery-powered devices.

[0115] This invention provides adaptive gate bias based on load current and dynamically adjusts loop frequency compensation characteristics to solve the stability problem of LDO loop characteristics with drastic load changes, ensuring excellent stability and transient response across the entire load range. It utilizes the threshold characteristics of NMOS transistors to achieve signal clamping, automatically adapting to different semiconductor processes, enhancing chip robustness and manufacturability, and broadening the applicable voltage range and application scenarios of negative voltage low dropout linear regulators.

[0116] The above embodiments are merely illustrative examples and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A control method for a wide-range bipolar enabled negative voltage regulator, characterized in that, include: Step S1: Receive a wide-range, bipolar external enable signal; Step S2: Input the external enable signal in parallel to one positive pressure signal processing path and one negative pressure signal processing path for independent detection and processing; Step S3: In the positive voltage signal processing path, the threshold characteristics of the first NMOS transistor are used to clamp and identify the positive voltage signal; in the negative voltage signal processing path, the threshold characteristics of the second NMOS transistor are used to clamp and identify the negative voltage signal. Step S4: The intermediate signals after processing the two paths are level-converted and logic-conditioned to generate an internal enable control signal. Step S5: Based on the internal enable control signal, control the start-up or shutdown of the negative voltage low differential linear regulator, and perform performance optimization when controlling the start-up of the negative voltage low differential linear regulator.

2. The wide-range bipolar enabled negative voltage regulator control method according to claim 1, characterized in that, In step S2, the positive pressure signal processing path and the negative pressure signal processing path are input and current-limited through high-resistance resistors.

3. The wide-range bipolar enabled negative voltage regulator control method according to claim 1, characterized in that, In step S3, the threshold voltage of the first NMOS transistor is used to limit the amplitude of the positive input signal within a first preset voltage range, while the threshold voltage of the second NMOS transistor is used to limit the amplitude of the negative input signal within a second preset voltage range.

4. The wide-range bipolar enabled negative voltage regulator control method according to claim 3, characterized in that, In step S3, the first preset voltage range is 98% to 102% of the threshold voltage of the first NMOS transistor, and the second preset voltage range is 98% to 102% of the threshold voltage of the second NMOS transistor.

5. The wide-range bipolar enabled negative voltage regulator control method according to claim 1, characterized in that, In step S4, the level conversion and logic conditioning of the intermediate signals after processing the two paths includes: Step S41: The intermediate signal from the negative voltage signal processing path is inverted and level-shifted by an inverter circuit composed of PMOS transistors and NMOS transistors. Step S42: The signal after level shifting is combined with the intermediate signal from the positive pressure signal processing path; Step S43: The merged signals are processed by a logic gate to generate an internal enable control signal for controlling the negative pressure low differential linear regulator.

6. The wide-range bipolar enabled negative voltage regulator control method according to claim 5, characterized in that, In step S43, the logic gate is a NOR gate, whose first input terminal receives the output signal from the inverter circuit, and whose second input terminal directly receives the intermediate signal from the positive voltage signal processing path.

7. The wide-range bipolar enabled negative voltage regulator control method according to claim 1, characterized in that, In step S5, performance optimization during the startup of the low-dropout linear regulator with negative pressure control includes: Based on the change in output load current, an adaptive gate bias is provided to the power adjustment transistor of the negative voltage low dropout linear regulator, while the frequency compensation characteristics of the loop are dynamically adjusted.

8. The wide-range bipolar enabled negative voltage regulator control method according to claim 7, characterized in that, In step S5, the frequency compensation characteristics of the dynamically adjusted loop include: Step S51: Real-time detection of the output load current of the negative voltage low differential linear regulator; Step S52: Based on the detected load current value, automatically switch the compensation network structure in the negative voltage low differential linear regulator loop; Step S53: Under light load conditions, the dominant pole frequency is configured to a first frequency value, and under heavy load conditions, the dominant pole frequency is configured to a second frequency value.

9. A wide-range bipolar enabled negative voltage regulator applied to the wide-range bipolar enabled negative voltage regulator control method according to any one of claims 1-8, characterized in that, include: A bidirectional enable circuit is used to process positive or negative enable signals and generate internal enable control signals. A bandgap reference is used to provide a stable bandgap voltage that does not change with temperature. A gain module, connected to the bandgap reference, is used to multiply the bandgap voltage by a fixed coefficient to generate a reference voltage. An error amplifier, whose first input terminal receives the reference voltage and whose second input terminal is connected to a feedback node; A buffer is connected to the output of the error amplifier; The power transistor is an NMOS power transistor, whose gate is connected to the output terminal of the buffer, whose source is connected to the negative power supply voltage VIN, and whose drain is used as the output voltage VOUT. The error amplifier, buffer, and power transistor form an analog feedback loop, which is used to modulate the power transistor to achieve a stable output voltage. The bidirectional enable circuit, bandgap reference, gain module, error amplifier, buffer, and power transistor are integrated on the same chip.

10. The wide-range bipolar enabled negative voltage regulator according to claim 9, characterized in that, The bidirectional enable circuit includes: An input current-limiting resistor is connected at one end to an external enable signal input terminal. The positive voltage signal processing branch includes a first NMOS transistor whose gate and source are cross-connected to the other end of the input current limiting resistor to form a positive voltage signal clamping structure for limiting the positive voltage enable signal. The negative voltage signal processing branch includes a second NMOS transistor, a third NMOS transistor, a PMOS transistor, and a resistor, which is used to process the negative voltage enable signal and convert the signal to a suitable operating range. The level conversion module includes a common-source, common-gate, inverting structure composed of the PMOS transistor and the third NMOS transistor; The logic synthesis module employs NOR gate logic, and its two input terminals receive signals from the level conversion module and the positive voltage signal processing branch, respectively, to generate an internal enable control signal.

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