Memory system and operating method and system

Abstract

The invention provides a memory system and an operation method and system. The memory system comprises a memory device and a controller coupled with the memory device; the controller is configured to: receive a command including address information of target data and a flag bit; the flag bit is configured to indicate whether to delete the target data; and executing deletion operation on the target data according to the condition that the flag bit is in the state of indicating to delete the target data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory system and its operating method and system. Background Technology

[0002] With the rapid development of data storage technology, more and more data storage systems are appearing in electronic devices used by people, such as Secure Digital Memory Card (SD card), Universal Flash Storage (UFS), and Solid State Drives (SSD). Summary of the Invention

[0003] This disclosure provides a memory system and its operation method / system.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a memory system, including a memory device and a controller coupled to the memory device; the controller is configured to:

[0006] Receive a command including address information of the target data and a flag bit; the flag bit is configured to indicate whether to delete the target data;

[0007] The deletion operation is performed on the target data based on the state indicated by the flag bit.

[0008] In one alternative implementation, the target data is stored in the memory device.

[0009] In an alternative implementation, the controller is further configured to:

[0010] In response to the command, the mapping information from the logical address to the physical address of the target data is removed.

[0011] In one alternative implementation, the memory device includes a plurality of memory blocks; prior to performing the deletion operation, the controller is further configured to:

[0012] Valid data located in the same storage block as the target data is transferred to another storage block.

[0013] In one alternative implementation, after the deletion operation is completed, the controller is further configured to:

[0014] Generate the completion response information for the command.

[0015] In one alternative implementation, the command includes a demapping command or a dataset management command.

[0016] Secondly, embodiments of this disclosure provide a system including a memory system and a host coupled to the memory system; the memory system includes a memory device and a controller coupled to the memory device; wherein,

[0017] The host is configured to send a command including address information of the target data and a flag bit; the flag bit is configured to indicate whether to delete the target data;

[0018] The controller is configured to: receive the command; and perform a deletion operation on the target data according to the state indicated by the flag bit indicating that the target data should be deleted.

[0019] In one alternative implementation, the host includes a memory and a processor coupled to the memory; the processor is configured to:

[0020] Receive request;

[0021] Based on the request including the requirement to delete the target data, the flag is set to indicate a state indicating the deletion of the target data.

[0022] In one alternative implementation, the target data is stored in the memory device.

[0023] In an alternative implementation, the controller is further configured to:

[0024] In response to the command, the mapping information from the logical address to the physical address of the target data is removed.

[0025] In one alternative implementation, the memory device includes a plurality of memory blocks; prior to performing the deletion operation, the controller is further configured to:

[0026] Valid data located in the same storage block as the target data is transferred to another storage block.

[0027] In one alternative implementation, after the deletion operation is completed, the controller is further configured to:

[0028] Generate a completion response message for the command and send the completion response message to the host.

[0029] In one alternative implementation, the command includes a demapping command or a dataset management command.

[0030] Thirdly, embodiments of this disclosure provide a method for operating a memory system, including:

[0031] Receive a command including address information of the target data and a flag bit; the flag bit is configured to indicate whether to delete the target data;

[0032] The deletion operation is performed on the target data based on the state indicated by the flag bit.

[0033] In one alternative implementation, the target data is stored in the memory device.

[0034] In one optional implementation, the operation method further includes:

[0035] In response to the command, the mapping information from the logical address to the physical address of the target data is removed.

[0036] In one optional implementation, before performing the deletion operation, the operation method further includes:

[0037] Valid data located in the same storage block as the target data is transferred to another storage block.

[0038] In one optional implementation, after the deletion operation is completed, the operation method further includes:

[0039] Generate the completion response information for the command. Attached Figure Description

[0040] Figure 1 A schematic diagram of the system provided in the embodiments of this disclosure;

[0041] Figure 2 A schematic diagram of a memory card provided in an embodiment of this disclosure;

[0042] Figure 3 A schematic diagram of a solid-state drive provided in an embodiment of this disclosure;

[0043] Figure 4 Schematic diagram of the composition of the memory device provided in the embodiments of this disclosure Figure 1 ;

[0044] Figure 5 Schematic diagram of the composition of the memory device provided in the embodiments of this disclosure Figure 2 ;

[0045] Figure 6 Schematic diagram of the system composition provided in the embodiments of this disclosure Figure 1 ;

[0046] Figure 7 A schematic diagram of the framework flow provided for embodiments of this disclosure Figure 1 ;

[0047] Figure 8 Schematic diagram of the system composition provided in the embodiments of this disclosure Figure 2 ;

[0048] Figure 9 A schematic diagram illustrating the format of the demapping command provided in this embodiment of the disclosure;

[0049] Figure 10 A schematic diagram illustrating the format of dataset management commands provided in embodiments of this disclosure;

[0050] Figure 11 A schematic diagram illustrating a data transfer operation provided in an embodiment of this disclosure;

[0051] Figure 12 A schematic diagram of the framework flow provided for embodiments of this disclosure Figure 2 ;

[0052] Figure 13 This is a flowchart illustrating the operation method of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0053] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0054] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0055] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0056] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] The memory systems in the embodiments of this disclosure include, but are not limited to, memory systems including three-dimensional NAND type memory. For ease of understanding, the memory systems provided in this disclosure will be described using a memory system including three-dimensional NAND type memory as an example.

[0059] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided for embodiments of this disclosure. In embodiments of this disclosure, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1As shown, system 100 may include a host system 101 and a memory system 102. The memory system 102 may include one or more memory devices 103 and a memory controller 104. The host system 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host system 101 may be configured to send data to or receive data from the memory system 102.

[0060] In some embodiments, memory controller 104 is coupled to memory device 103 and host 101 and is configured to control memory device 103. Memory controller 104 can manage data stored in memory device 103 and communicate with host 101. In some embodiments, memory controller 104 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 104 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0061] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0062] In such Figure 2 In one example shown, the memory controller 104 and a single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a connection between the memory card 201 and a host (e.g., Figure 1 The memory card connector 202 is coupled to the host 101. Figure 3 In another example shown, the memory controller 104 and multiple memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include components for connecting the SSD 203 to a host computer (e.g., Figure 1 The SSD connector 204 is coupled to the host 101. In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0063] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuitry, provided for embodiments of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0064] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first threshold voltage distribution, and a second memory state "1" may correspond to a second threshold voltage distribution. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0065] like Figure 4As shown, each memory string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of memory strings 304 within the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0066] like Figure 4 As shown, the memory string 304 can be organized into multiple memory blocks 303, each of which may have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase a memory cell 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0067] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit line 311, word line 312, common-source line 310, bottom select line 309, and top select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0068] Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0069] Page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory strings by applying a bit line voltage generated from voltage generator 404.

[0070] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The row decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0071] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and send it to or receive and buffer data from memory array 301.

[0072] In some embodiments, Figure 6 Schematic diagram of the system composition provided in the embodiments of this disclosure Figure 1 ,like Figure 6 As shown, the system includes a host 601 and a memory system 501. The memory system 501 includes a memory device 503 and a controller 502. The controller 502 is coupled to the host 601 through a host interface 504 and to the memory device 503 through a memory interface 505. The controller 502 may include a Flash Translation Layer (FTL). Specifically, the controller 502 may include a first processor 506 and a mapping management module 508 coupled to the first processor 506 through a bus 509, for implementing mapping management functions.

[0073] In some specific examples, host 601 supports an operating system (OS) and includes a file system and underlying drivers. Users can issue requests at the application layer of the operating system. The file system can translate these requests into commands conforming to the corresponding protocols via the underlying drivers. Memory system 501 receives the commands through host interface 504 and executes the corresponding operations. For example, when a user initiates a file storage operation at the application layer, host 601 can send a write command to memory system 501. Controller 502 can receive the write command and, in response, receive the write data corresponding to the file and the logical address of the write data. The write data is temporarily stored in the cache 507 of controller 502. Mapping management module 508 can allocate physical addresses for the write data and establish a logical address to physical address (L2P) mapping relationship for the write data, storing the mapping information corresponding to this mapping relationship. Controller 502 can send programming commands to memory device 503 via memory interface 505. Memory device 503 can receive the programming command and, in response, receive the write data and the physical address of the write data, storing the write data in the memory array at the location corresponding to the physical address of the write data. To improve user experience, during file storage, the system typically reports completion as soon as the data is stored in the cache 507 of the controller 502, avoiding excessive waiting time. Similarly, during file deletion, after the target data is demapped and rendered invalid, the system reports completion. However, the target data stored in the storage device 503 is not immediately erased. This means that even after file deletion, the corresponding data can still be recovered from the storage device 503 using technical means, posing a serious data security risk.

[0074] In view of the above problems, the present disclosure provides the following implementation methods.

[0075] This disclosure provides a system including a memory system and a host coupled to the memory system; the memory system includes a memory device and a controller coupled to the memory device; wherein the host is configured to: send a command including address information of target data and a flag bit; the flag bit is configured to indicate whether to delete the target data; the controller is configured to: receive the command; and perform a deletion operation on the target data according to the flag bit indicating that the target data is to be deleted.

[0076] In some embodiments, refer to Figure 6The system includes a memory system 501 and a host 601 coupled to the memory system 501. The memory system 501 includes a memory device 503 and a controller 502 coupled to the memory device 503. Here, the memory device 503 can be the memory device 300 in the example above. The host 601 includes a memory 602 and a second processor 603 coupled to the memory 602. The host 601 is coupled to a host interface 504 in the controller 502 via an interface 604. Here, the second processor 603 is an example of a processor in the host of the system provided in this disclosure.

[0077] In some embodiments, host 601 is configured to send a command including address information of target data and a flag bit; the flag bit is configured to indicate whether to delete the target data.

[0078] In some specific examples, the second processor 603 can be configured to execute Figure 7 Specifically, the second processor 603 can be configured to: execute step S701 to receive a request; execute step S702 to determine whether the request includes a requirement to delete target data; if yes, execute step S703 to generate a command including address information of the target data and a flag bit, and set the flag bit to indicate the state of deleting the target data; if no, execute step S704 to generate a command including address information of the target data; and finally execute step S705 to send the command. Here, sending the command may include sending the command to the memory system 501 through interface 604.

[0079] In some specific examples, taking host 601 including the file system as an example, Figure 8 Schematic diagram of the system composition provided in the embodiments of this disclosure Figure 2 Combined with reference Figure 6 and Figure 8 The host 601 may include an application layer 610 and a kernel layer. The kernel layer may further include a file system layer 611, a block device layer 612, and a device driver layer 613. The memory 602 may be configured to store the software of each layer. When the second processor 603 runs the software stored in the memory 602, the functions of each layer can be implemented.

[0080] In some specific examples, in conjunction with reference Figure 7 and Figure 8The request can be a file deletion request initiated by the user through the application layer 610. The target data can be data stored in the memory system 501 corresponding to the target file specified in the file deletion request. Specifically, the target data is stored in the memory device 503 of the memory system 501. The address information of the target data can include multiple logical address ranges. The file system layer 611 can generate corresponding block input / output (Bio) information according to the call of the application layer 610. Each Bio can include a logical address range. When the file deletion request includes the need to delete the target data, the Bio can carry deletion prompt information. The file system layer 611 can send multiple Bios to the block device layer 612. The block device layer 612 will then combine the multiple Bios into a request information and send the request to the device driver layer 613. The device driver layer 613 can generate an unmap command or a dataset management command according to the request. Based on the deletion prompt information carried in the request, it will use a bit in the reserved area of ​​the unmap command or dataset management command as a flag bit and set the flag bit to indicate the status of deleting the target data. Here, the reserved area in the command includes at least one bit that has not yet been configured to have any effect. These bits can be "0" by default. Setting the flag to indicate the state of deleting target data can include setting the flag of the target data to "1".

[0081] In a specific example, the interface 604 of host 601 and the host interface 504 of controller 502 are linked according to the SCSI protocol specification, and the command including the address information of the target data and the flag bits is the demapping command. Figure 9 The format of the demapping command is shown. The flag bit of the target data can be one of the bits in Byte 2 to Byte 5 of the demapping command, or one of the bits in other reserved areas.

[0082] In a specific example, interface 604 of host 601 and host interface 504 of controller 502 are linked according to the NVMe protocol specification. The commands, including the address information of the target data and the flag bits, are data set management commands. Figure 10The format of Command Dword 11 for dataset management commands is shown. The flag bit for the target data can be one bit from Bits 31:03 in Command Dword 11 of the dataset management command, or one bit from another reserved area. Furthermore, in the dataset management command, Bit 02 in Command Dword 11 is set to 1 to indicate the removal of the logical address-to-physical address mapping information for the target data.

[0083] In other specific examples, when host 601 communicates with controller 502 via other protocols, commands including address information and flag bits of the target data can also be commands conforming to other protocol standards.

[0084] In this embodiment of the disclosure, when a user has a need to completely delete sensitive or private data, when the host generates a command that indicates the removal of the mapping information of the target data, it can use the reserved area in the command, use a bit in the reserved area as the flag bit of the target data, set the flag bit to indicate the state of deleting the target data, and send the command including the address information of the target data and the flag bit to the controller 502.

[0085] In some embodiments, the controller 502 is configured to: receive the command; and perform a deletion operation on the target data according to the flag bit being in a state indicating that the target data should be deleted.

[0086] In some embodiments, the controller 502 is further configured to: in response to the command, remove the mapping information from the logical address to the physical address of the target data.

[0087] In some specific examples, the mapping management module 508 in controller 502 is configured to maintain a mapping table, which includes mapping information from logical addresses to physical addresses of data stored in memory device 503. The mapping management module 508 in controller 502 can be configured to, in response to a demapping command or a dataset management command, look up the mapping information from logical addresses to physical addresses of the target data in the mapping table based on the logical address of the target data carried in the command, and then demap the logical address to physical address of the target data. Specifically, the logical address in the mapping entry corresponding to the mapping information from logical addresses to physical addresses of the target data can be deleted from the mapping table, retaining only the physical address of the target data, or the mapping entry can be marked as invalid. After the mapping information from the logical address to the physical address of the target data is removed, the target data can no longer be obtained from the memory system 501 through the original logical address. That is, the target data in the memory device 503 will become invalid data. If the flag bit is not in the state indicating the deletion of the target data, the target data in the memory device 503 will not be deleted immediately, but will continue to be stored in the memory device 503. The controller 502 can be configured to delete the target data that has become invalid data in the idle state, or when the amount of invalid data in the memory device 503 reaches a threshold, through garbage collection or other operations that can run in the background.

[0088] In some specific examples, when the flag is in the state indicating that target data should be deleted, performing a deletion operation on the target data can mean erasing the target data from the memory device 503. That is, the controller 502 can be configured to send an erase command to the memory device 503 to erase the target data in the memory device 503. As a result, the target data will be completely deleted and can no longer be retrieved from the memory device 503.

[0089] In some embodiments, the memory device 503 includes multiple storage blocks. In a deletion operation, the target data may include multiple parts, which are stored in different storage blocks respectively. In addition, other valid data may also be stored in the storage block where the target data is stored. Before performing the deletion operation, the controller 502 is also configured to transfer the valid data located in the same storage block as the target data to another storage block.

[0090] In a specific example, Figure 11 This is a schematic diagram of a data transfer operation provided in an embodiment of the present disclosure, such as... Figure 11As shown, the target data may include multiple parts stored in multiple storage blocks. For example, the target data may include multiple parts stored in three storage blocks, Block0, Block1, and Block2. After demapping the logical address to physical address mapping information of the target data, the target data becomes invalid data F1 to F13. Before performing a deletion operation on the target data, the valid data V1 to V4 located in the same storage block as the target data needs to be transferred to another storage block, Blockx. Then, the three storage blocks, Block0 to Block2, can be erased on a block-by-block basis. Here, storage block Blockx can be a free storage block or a storage block containing other valid data before receiving the valid data V1 to V4. The process of transferring the valid data may include first performing a read operation on the area storing valid data in storage blocks Block0 to Block2, and then writing the read data into storage block Blockx.

[0091] In a specific example, controller 502 can be configured to perform Figure 12 Specifically, the controller 502 can be configured to: execute step S801, receiving a command including the address information of the target data and a flag bit; execute step S802, determining whether the flag bit is in the state indicating deletion of the target data; if yes, execute step S803, removing the mapping information from the logical address to the physical address of the target data; execute step S804, transferring the valid data located in the same storage block as the target data to another storage block; execute step S805, performing a deletion operation on the target data; and execute step S807, generating a command completion response message; otherwise, execute step S806, removing the mapping information from the logical address to the physical address of the target data; and execute step S807, generating a command completion response message. That is, when the flag bit is in the state indicating deletion of the target data, the command completion response message will only be sent back to the host after the target data has been deleted, ensuring that the target data has been completely deleted.

[0092] In a specific example, the flash conversion layer of controller 502 may include a deletion module. The deletion module may be configured to determine the state of the flag bit when it receives a command including address information of target data and a flag bit, and when the flag bit is in the state indicating deletion of target data, initiate a data transfer operation and a deletion operation, and send a corresponding command to memory device 503 through memory interface 505 to transfer the valid data located in the same memory block as the target data to another memory block, and delete the target data in memory device 503.

[0093] In this embodiment of the disclosure, when the file deletion request initiated by the application layer includes the requirement to delete target data, the host can generate a command including a flag indicating the state of deleting target data and send the command to the memory system. The controller can respond to the command to perform a deletion operation on the target data. The controller will only send the command completion response information back to the host after the deletion operation on the target data stored in the memory device is completed. Thus, the target data can be deleted immediately, avoiding the situation where the target data can be obtained from the memory device through technical means later, thereby protecting sensitive or private data.

[0094] It should be noted that the system in the above embodiments mainly takes a host device with a file system as an example, but this disclosure is not limited to this. In other embodiments, commands including the address information and flag bits of the target data can be sent directly to the storage system without going through the file system. For example, using an SPDK (Storage Performance Development Kit) application or other applications that can generate NVMe commands can directly generate commands including the address information and flag bits of the target data to achieve complete deletion of the target data.

[0095] This disclosure also provides a memory system, with reference to Figure 6 The memory system includes a memory device 503 and a controller 502 coupled to the memory device 503; the controller 502 is configured to: receive a command including address information of target data and a flag bit; the flag bit is configured to indicate whether to delete the target data; and perform a deletion operation on the target data according to the flag bit indicating that the target data is to be deleted.

[0096] In some embodiments, the target data is stored in the memory device 503.

[0097] In some embodiments, the controller 502 is further configured to: in response to a command, remove the mapping information from the logical address to the physical address of the target data.

[0098] In some embodiments, the memory device 503 includes a plurality of memory blocks; prior to performing the deletion operation, the controller 502 is further configured to transfer valid data located in the same memory block as the target data to another memory block.

[0099] In some embodiments, after the deletion operation is completed, the controller 502 is also configured to generate a completion response message for the command.

[0100] In some embodiments, the command that includes the address information and flag bits of the target data can be a demapping command or a dataset management command.

[0101] In this embodiment of the disclosure, the controller can demap the target data in response to a demapping command or a dataset management command, and perform a deletion operation on the target data stored in the memory device according to the flag bit in the command indicating that the target data should be deleted. The controller will only generate a command completion response after the deletion operation is completed. This can achieve the complete deletion of the target data and avoid the situation where the target data can be recovered from the memory device by technical means after the demapping operation is performed. This can protect sensitive or private data and improve the data security of the memory system.

[0102] This disclosure also provides a method for operating a memory system. Figure 13 This is a flowchart illustrating the operation method of the memory system provided in the embodiments of this disclosure, as shown below. Figure 13 As shown, the operation method of the memory system includes the following steps:

[0103] Step S10: Receive a command including address information of the target data and a flag bit; the flag bit is configured to indicate whether to delete the target data;

[0104] Step S20: Based on the flag indicating that the target data is to be deleted, perform a deletion operation on the target data.

[0105] In some embodiments, the operation method further includes: in response to the command, unmapping the mapping information from the logical address to the physical address of the target data.

[0106] In some embodiments, prior to performing the deletion operation, the method further includes: transferring valid data located in the same storage block as the target data to another storage block.

[0107] In some embodiments, after the deletion operation is completed, the operation method further includes: generating completion response information for the command.

[0108] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0109] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0110] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory system, characterized in that, Includes a memory device and a controller coupled to the memory device; the controller is configured to: Receive commands including the address information and flag bits of the target data; The flag is configured to indicate whether the target data should be deleted; The deletion operation is performed on the target data based on the state indicated by the flag bit.

2. The memory system according to claim 1, characterized in that, The target data is stored in the memory device.

3. The memory system according to claim 2, characterized in that, The controller is also configured to: In response to the command, the mapping information from the logical address to the physical address of the target data is removed.

4. The memory system according to claim 3, characterized in that, The memory device includes multiple memory blocks; prior to performing the deletion operation, the controller is further configured to: Valid data located in the same storage block as the target data is transferred to another storage block.

5. The memory system according to claim 2, characterized in that, After the deletion operation is completed, the controller is further configured to: Generate the completion response information for the command.

6. The memory system according to claim 1, characterized in that, The commands include demapping commands or dataset management commands.

7. A system, characterized in that, It includes a memory system and a host coupled to the memory system; the memory system includes a memory device and a controller coupled to the memory device; wherein, The host is configured to send a command including address information of the target data and a flag bit; the flag bit is configured to indicate whether to delete the target data; The controller is configured to: receive the command; and perform a deletion operation on the target data according to the state indicated by the flag bit indicating that the target data should be deleted.

8. The system according to claim 7, characterized in that, The host includes a memory and a processor coupled to the memory; the processor is configured to: Receive request; Based on the request including the requirement to delete the target data, the flag is set to indicate a state indicating the deletion of the target data.

9. The system according to claim 7, characterized in that, The target data is stored in the memory device.

10. The system according to claim 9, characterized in that, The controller is also configured to: In response to the command, the mapping information from the logical address to the physical address of the target data is removed.

11. The system according to claim 10, characterized in that, The memory device includes multiple memory blocks; prior to performing the deletion operation, the controller is further configured to: Valid data located in the same storage block as the target data is transferred to another storage block.

12. The system according to claim 9, characterized in that, After the deletion operation is completed, the controller is further configured to: Generate a completion response message for the command and send the completion response message to the host.

13. The system according to claim 7, characterized in that, The commands include demapping commands or dataset management commands.

14. A method for operating a memory system, characterized in that, include: Receive commands including the address information and flag bits of the target data; The flag is configured to indicate whether the target data should be deleted; The deletion operation is performed on the target data based on the state indicated by the flag bit.

15. The method of operating the memory system according to claim 14, characterized in that, The target data is stored in the memory device.

16. The method of operating the memory system according to claim 15, characterized in that, The operation method further includes: In response to the command, the mapping information from the logical address to the physical address of the target data is removed.

17. The method of operating a memory system according to claim 16, characterized in that, Before performing the deletion operation, the operation method further includes: Valid data located in the same storage block as the target data is transferred to another storage block.

18. The method of operating the memory system according to claim 15, characterized in that, After the deletion operation is completed, the operation method further includes: Generate the completion response information for the command.

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