Electronic design multi-agent system with graph structure control and feedback iteration capability and operation method thereof

Abstract

The invention discloses an electronic design multi-agent system with graph structure control and feedback iteration capabilities and an operation method thereof. The electronic design multi-agent system comprises a natural language analysis module, a decision planning agent, a functional module agent set, a schematic diagram construction agent, an assembly agent, a simulation verification agent and a feedback iteration module. The system receives a circuit design requirement described by a natural language, automatically constructs a sub-task dependency graph, distributes parallel tasks, retrieves matched components and generates a local schematic diagram through a multi-agent cooperation mechanism, and assembles the local schematic diagram into a complete schematic diagram. The system automatically triggers task re-planning, device re-matching and graph structure optimization through simulation verification and error feedback to form closed-loop iterative control. According to the method, automatic conversion from the natural language to the schematic diagram conforming to the electrical specification is achieved, the problems that a traditional EDA tool is complex in operation and existing AI aided design lacks systematicness and self-optimization capacity are solved, the design threshold is remarkably lowered, and the design efficiency and quality are improved.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to an electronic design multi-agent system and its operation method that has graph structure control and feedback iteration capabilities. Background Technology

[0002] Electronic Design Automation (EDA) tools play a crucial role in modern circuit development, especially in printed circuit board (PCB) design. As electronic systems become increasingly complex and integrated, PCB design tasks encompass multiple stages, from schematic design, component selection and connection, and electrical parameter configuration, to circuit simulation, placement and routing, and rule verification. This involves a complex workflow and numerous toolchains. Current mainstream PCB design tools include KiCAD, Altium Designer, Cadence OrCAD, Mentor Graphics PADS, and simulation tools such as Ngspice and LTspice. Engineers need to repeatedly switch between these heterogeneous tools, which is not only inefficient but also prone to introducing human error.

[0003] Traditional PCB design workflows primarily rely on two approaches: interactive design via a graphical user interface (GUI), which requires engineers to have extensive experience using the tools and knowledge of circuit design; and automation via scripting languages ​​(such as Python and SKILL), which requires programming skills and is difficult to adapt to changing design requirements. Neither approach enables efficient cross-toolchain collaboration, significantly limiting the level of design automation, especially when dealing with complex system designs, where engineers often spend considerable time on tool operation rather than creative design.

[0004] In recent years, with the rapid development of natural language processing technology, especially large language models (LLMs), natural language-based EDA task expression and control have become possible. LLMs can perform deep semantic understanding of users' natural language commands and automatically generate corresponding schematic structures, connection logic, simulation parameters, and tool operation scripts, thereby significantly lowering the threshold for PCB design and improving the level of design intelligence. However, existing LLMs still face many challenges when handling PCB-level EDA tasks: on the one hand, they lack a deep understanding of EDA toolchain structures and design rules, making it difficult to generate schematics and simulation schemes that conform to electrical specifications and design logic; on the other hand, during task execution, complex designs often involve multiple parallel subtasks (such as symbol selection, electrical connections, parameter settings, model configuration, etc.), requiring modular and high-concurrency processing strategies, which a single large model architecture cannot handle. Furthermore, the results generated by LLMs usually lack effective verification mechanisms, failing to automatically detect design errors and perform iterative optimization, resulting in unstable design quality and unreliable reliability.

[0005] To address the aforementioned issues, the introduction of a multi-agent collaborative mechanism has become an important research direction for EDA intelligence. Under this mechanism, different agents are responsible for different specialized sub-tasks in the PCB design process. For example, the "component parsing agent" extracts component information from the circuit description, the "connection rule agent" establishes valid pin connections, the "simulation model configuration agent" loads the correct simulation library and generates corresponding instructions, and the "scheduling agent" optimizes and controls the task sequence. Agents communicate and collaborate by sharing context and intermediate states, forming a task-driven, modular, automated design process. This multi-agent collaborative architecture combines the semantic understanding and code generation capabilities of LLMs (Local Management Models), while also possessing the advantages of task decoupling, parallel execution, and module expansion. This not only significantly improves the intelligence level of the PCB design process but also enhances the system's adaptability to diverse design scenarios. However, existing research still has significant shortcomings in task graph structure control, multi-agent systematic collaboration, and feedback iterative optimization mechanisms, failing to form a complete closed-loop design system.

[0006] An existing method for automatic schematic generation utilizes predefined circuit module templates and programmatic techniques, combined with symbol invocation and rule-based connection strategies, to achieve the programmatic construction of electronic circuit schematics. This method, primarily implemented using Python scripts, allows users to define circuit module types (such as resistor series, operational amplifier circuits, etc.), automatically invokes symbols and executes wiring connection logic, ultimately generating schematic files. The main process includes: the designer pre-defines a standard circuit structure template in code; the system automatically searches for and invokes corresponding device definitions from the symbol library based on the module template content; the system connects the devices according to preset connection rules; the system automatically constructs the schematic graphic structure based on symbols and connection relationships; and multiple schematic samples can be generated simultaneously through parameter configuration or loop control structures. However, while this method can improve schematic generation efficiency to some extent, especially in scenarios with structured regularization, it remains essentially a single-point script-based automation tool, lacking intelligence and systemicity. It cannot achieve functions such as natural language-driven operation, module decoupling and collaboration, semantic understanding, circuit behavior prediction, rule verification, and result feedback. This technology is poorly adaptable to complex, non-standardized circuit designs, requiring all templates to be predefined manually, and cannot be automatically adjusted and optimized according to design goals.

[0007] Another existing technology is driven by prompt engineering. It guides a language model to generate circuit design-related code snippets or tool commands by inputting natural language descriptions, assisting users in circuit design input, script generation, and parameter configuration. The main process includes: the user inputs circuit functional requirements or design objectives via natural language; the model parses the text and generates schematic script code; the user pastes the generated code into an EDA tool or simulation software and runs it; if errors occur, the text is manually modified and regenerated, forming a trial-and-error iteration; finally, the individual modules and simulation structure are manually combined and verified. Although this technology initially demonstrates the potential of generating EDA task code from natural language, it is essentially still at a shallow application stage of "text-to-code," lacking capabilities such as task graph modeling, symbol structure generation, graph connection constraint modeling, agent collaboration, simulation verification, and intelligent feedback. This method cannot automatically understand the internal logical relationships of the circuit design, lacks a global grasp of the design goals, the quality of the generated code depends on the accuracy of the prompts, and the error correction process relies entirely on manual intervention, failing to form a closed-loop optimization process. Furthermore, this technology lacks the ability to perform multi-task parallel processing, making it inefficient when dealing with complex system designs and difficult to guarantee interface consistency between modules and overall system performance.

[0008] In summary, the current field of electronic design automation (EDA) faces several key challenges: Traditional EDA processes rely on professionals using graphical interfaces or scripting languages ​​to gradually build circuit schematics, making it difficult to directly extract component requirements, functional module relationships, and connection rules from natural language descriptions. This results in high design barriers, complex processes, and poor reusability. Most existing EDA tools cannot automatically complete symbol calls, pin connections, and schematic construction, especially in areas such as multi-module assembly, electrical rule control, and simulation verification feedback, which still rely on manual operation. There is a lack of a systematic mechanism to ensure the correctness of schematic generation, the rationality of module assembly, and the effectiveness of functional achievement. Furthermore, existing technologies generally lack closed-loop feedback mechanisms, failing to automatically locate the root cause of problems and perform targeted optimizations when design verification fails, making it difficult to balance design quality and efficiency. These challenges urgently require a new electronic design automation architecture that can automatically translate natural language requirements into designs compliant with electrical specifications and achieve continuous optimization of design quality through multi-agent collaboration and feedback iteration mechanisms. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this invention provides an electronic design multi-agent system and its operation method that possesses graph structure control and feedback iteration capabilities.

[0010] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is as follows:

[0011] A multi-agent electronic design system with graph structure control and feedback iteration capabilities, the system comprising:

[0012] The natural language parsing module is used to receive natural language input from users, generate semantic vectors, and extract function sets and constraint sets from them as structured design tasks.

[0013] The decision planning agent is used to decompose the structured design task into functions, generate a set of subtasks, construct a directed graph of subtask dependencies, and perform logical consistency verification.

[0014] Multiple functional module agents are assigned to handle specific subtasks, which are used to match relevant components in the device database through vector retrieval and output a structured set of devices.

[0015] The schematic construction agent is used to generate local schematics and corresponding operation command sequences based on subtask information and device results, following a predefined set of rule constraints.

[0016] The assembly agent is used to receive the set of subgraphs and the task dependency graph, perform schematic subgraph merging and electrical connections between modules, and generate a complete schematic.

[0017] The simulation verification agent is used to perform rule checks and behavioral simulations on the generated schematics and compare the verification results with the design goals.

[0018] The feedback iteration module constructs error feedback information when the verification results do not meet the design goals, triggering task replanning, device rematching, or graph structure optimization to form closed-loop iterative control.

[0019] The subtasks depend on a directed graph that must be a directed acyclic graph, and the execution order of the subtasks is determined by a topological sorting algorithm to achieve parallel processing and collaborative scheduling of tasks.

[0020] Furthermore, when performing logical consistency verification, the decision planning agent executes a loop detection algorithm and checks the completeness of the input and the explicit definition of the constraints for each subtask. When an abnormal graph structure or a conflict of task constraints is detected, the task replanning process is triggered.

[0021] Furthermore, when the functional module agent performs device matching, it uses a weighted cosine similarity calculation method to perform vector retrieval in the device database to obtain Top-K matching device results. The device results include component symbols, pin definitions, package types, and electrical characteristic information.

[0022] Furthermore, the rule checks performed by the simulation verification agent include electrical rule checks (ERC) and design rule checks (DRC). When an error is detected, structured error information is generated and fed back to the decision planning agent to guide subsequent iterative optimization.

[0023] Furthermore, when constructing the error feedback vector, the feedback iteration module includes error metric values, rule-checked error sets, simulation configuration, simulation results, and current schematic structure information. It can also automatically locate the set of subtasks that cause functional failure and optimize the failed subtasks through a semantic reconstruction function.

[0024] Furthermore, the system applies a reinforcement learning scoring function to the task dependency graph to dynamically adjust the task execution order and dependencies, and introduces a mutation operator in the device vector space to expand the search diversity and improve the system convergence efficiency.

[0025] Furthermore, during the iterative optimization process, the schematic construction agent performs edge-level or block-level graph structure optimization, adjusts the local schematic structure through graph patching algorithms, repairs connection errors or optimizes the layout, and follows pin compatibility, network classification and power domain partitioning rules.

[0026] Furthermore, the system dynamically allocates task priorities and computing resources based on the historical performance data of each agent, including generation accuracy and error correction rate, and optimizes the overall task allocation strategy until the preset error threshold and zero-rule error condition are met.

[0027] This invention also discloses an operation method for the above-mentioned electronic design multi-agent system, characterized by comprising the following steps:

[0028] a) Receive circuit design requirements described in natural language and extract the function set and constraint set through semantic parsing;

[0029] b) Construct a structured design task, perform functional decomposition, generate a set of subtasks and their dependencies in a directed graph, and verify the logical consistency of the graph structure;

[0030] c) Perform topology sorting, assign corresponding functional module agents to each subtask, match devices through vector retrieval, and construct a local schematic diagram;

[0031] d) Assemble the schematic diagrams of each part, establish electrical connections between modules, and generate a complete schematic diagram;

[0032] e) Perform rule checks and circuit simulation. When verification fails, construct an error feedback vector to trigger task replanning and device rematching.

[0033] f) Apply reinforcement learning to score and adjust the task graph, perform structural optimization on the schematic diagram, and repeat steps c) to e) until the design goal is met.

[0034] Furthermore, in step e), the system automatically locates the task subgraph that causes the functional failure, generates a new subtask representation through a semantic reconstruction function, expands the search radius in the vector space, and dynamically adjusts the task allocation strategy based on the historical performance of each agent to achieve closed-loop iterative control of "automatic construction - automatic verification - automatic optimization".

[0035] Compared with the prior art, the advantages of the present invention are as follows:

[0036] The electronic design multi-agent system with graph structure control and feedback iteration capabilities provided by this invention has the following significant advantages compared to existing technologies:

[0037] First, this invention achieves seamless conversion from natural language to circuit design through a multi-agent collaborative architecture, significantly lowering the technical threshold for PCB design. Traditional EDA tools require users to have deep professional knowledge and tool operation experience, while this system allows designers to directly describe design requirements using natural language, and the system automatically completes the entire process from semantic parsing and task decomposition to schematic generation. This transformation not only enables non-professionals to participate in circuit design, but also allows professional engineers to focus their energy on creative design rather than tedious tool operations, significantly improving design efficiency. Experimental data shows that for medium-complexity circuit design tasks, using this system can shorten design time by 60-70% while reducing the human error rate by approximately 85%.

[0038] Secondly, this invention effectively solves the problem of function-structure-interface disconnect in circuit design through task dependency graph construction and graph structure control mechanisms. The system automatically decomposes complex design tasks into multiple parallel subtasks and accurately describes the dependencies between tasks through directed acyclic graphs, ensuring logical consistency and interface compatibility of each module design. This structured task planning system not only improves the systematicity and integrity of the design but also supports parallel task processing, greatly enhancing design efficiency. Compared with traditional linear design flows, the parallel task processing capability of this system can shorten the design cycle of complex systems by more than 40%, making it particularly suitable for complex circuit design scenarios involving multi-module collaboration.

[0039] Third, this invention significantly improves design quality and reliability through a closed-loop feedback iterative mechanism. After generating the initial schematic, the system automatically performs Electrical Rule Check (ERC) and Design Rule Check (DRC), and conducts behavioral-level simulation verification, comparing the results with the design objectives. When verification fails or errors exist, the system can accurately locate the problematic module and automatically trigger task replanning, component rematching, or graph structure optimization, forming a closed-loop iterative logic of "automatic construction—automatic verification—automatic optimization." This self-feedback optimization capability enables the system to continuously improve design quality without human intervention until preset indicators are met. Tests show that after 3-5 rounds of iterative optimization, the design scheme generated by this system achieves over 95% functional correctness and electrical specification compliance, approaching the level of manual design by professional engineers.

[0040] Fourth, the multi-agent architecture of this invention possesses high flexibility and scalability. The modular design of each functional agent supports specialized training and optimization for specific design domains; the task scheduling mechanism can dynamically adjust task allocation strategies based on the agent's historical performance, optimizing overall system performance; and the vector retrieval and device matching mechanism supports a continuously expanding device database, adapting to the rapid integration of new components. This architectural design enables the system to adapt to a wide range of design needs, from simple analog circuits to complex mixed-signal systems, while also supporting customized integration according to enterprise-specific design specifications and processes.

[0041] Fifth, this invention continuously improves system performance through reinforcement learning and adaptive mechanisms. The system records the execution process, success stories, and lessons learned from failures for each design task, and optimizes the task graph construction strategy, component matching accuracy, and error correction efficiency through reinforcement learning algorithms. With increased usage, the system gradually masters design knowledge and experience in specific domains, forming a personalized "design style" to provide users with more accurate and efficient design services. Practical application data shows that after training through 100 design tasks, the system's first-time design success rate increased by approximately 40%, and the average number of iterations decreased by 50%.

[0042] Finally, this invention effectively solves the challenge of cross-toolchain collaboration, achieving seamless integration of the EDA tool ecosystem. The system-generated command sequences can directly interface with mainstream EDA tools (such as KiCAD, Altium Designer, Ngspice, etc.), automatically completing subsequent tasks such as schematic drawing, PCB layout, and circuit simulation, eliminating the time wastage and data conversion errors caused by tool switching in traditional design processes. This cross-platform collaboration capability not only improves the continuity and data consistency of the design process but also provides an intelligent upgrade path for enterprises' existing EDA tool investments, demonstrating significant engineering application value and commercial prospects. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of an electronic design multi-agent system with graph structure control and feedback iteration capabilities in an embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] I. System Architecture and Components

[0047] like Figure 1 As shown, the electronic design multi-agent system with graph structure control and feedback iteration capabilities described in this invention mainly includes the following core components in its overall architecture:

[0048] (1) Natural Language Parsing Module: As the system's input interface, it receives circuit design requirements described by the user in natural language. ,in This module represents the natural language space. It encodes the input text using a pre-trained language model to generate semantic vectors.

[0049]

[0050] The semantic vector was then subjected to deep analysis to extract the functional set. and constraint set :

[0051]

[0052] Finally, a structured design task representation is constructed:

[0053]

[0054] (2) Decision-making and planning agency As the core scheduler of the system, it receives structured tasks. It also performs functional decomposition, breaking down the overall design task into a set of subtasks that can be processed in parallel:

[0055]

[0056] Each subtask Includes specific functional requirements, constraints, and keyword embedding vectors:

[0057]

[0058] in Embedded vectors for subtask keywords are used for subsequent device retrieval and task allocation.

[0059] (3) Task Graph Construction and Verification Module: Performs task logic structure reasoning on the set of subtasks and establishes a dependency directed graph:

[0060]

[0061] This module performs rigorous graph structure verification, including:

[0062] Cyclic checking ensures the graph structure is a directed acyclic graph:

[0063]

[0064] Task completeness check to ensure that each subtask has a valid definition:

[0065]

[0066] Dependency integrity verification checks for any tasks with undefined prerequisite dependencies.

[0067]

[0068] When any of the above anomalies is detected, the task rescheduling mechanism is triggered:

[0069]

[0070] (4) Scheduler: For the validated task dependency graph Execute the topological sorting algorithm to generate the optimal task execution sequence:

[0071]

[0072] This sequence ensures that subtasks are executed in the order of their dependencies, while maximizing the execution efficiency of parallel tasks.

[0073] (5) Functional module proxy set { The system includes multiple specialized functional agents, each agent... Responsible for handling specific types of subtasks. When an assigned subtask is received... Then, the agent first processes the keyword vector. Perform deep semantic embedding:

[0074]

[0075] Subsequently, in the pre-built device database Perform weighted cosine similarity retrieval in the middle:

[0076]

[0077] in This is a learnable weight matrix used to adjust the importance of different feature dimensions. The proxy selects the Top-K matching set of devices:

[0078]

[0079] The final output is structured device information, including key attributes such as device symbol, pin definitions, and package type.

[0080]

[0081] (6) Constructing a proxy using a schematic diagram : Receive subtask information and device matching results, and combine them with a predefined set of rule constraints. Constructing a local schematic diagram:

[0082]

[0083] The rule constraint set includes electrical specifications such as pin connection rules, logical relationship definitions, network category classification, and power domain control.

[0084]

[0085] This agent generates specific operation command sequences to guide the EDA tools in performing the actual schematic construction:

[0086]

[0087] After all subtasks are completed, the system obtains a set of schematic sub-graphs:

[0088]

[0089] (7) Assembly and distribution agency : Responsible for integrating the scattered schematic sub-diagrams into a complete design. First, construct the global logic connection diagram:

[0090]

[0091] Then, the connection rule set R_C is applied to verify the legality of the electrical connections between modules:

[0092]

[0093] Finally, the layout diagram fusion algorithm is executed to generate a complete and executable schematic diagram:

[0094]

[0095] (8) Simulation verification agent Perform double validation on the generated schematic. First, perform rule checks:

[0096]

[0097] If an error is found, construct an error set:

[0098]

[0099] Simultaneously generate simulation scripts and execute circuit simulations:

[0100]

[0101]

[0102] The simulation results were compared and verified with the original functional requirements:

[0103]

[0104] (9) Feedback Iteration Control Module: When verification fails, construct a comprehensive error feedback vector:

[0105]

[0106] This module coordinates multiple subsystems to perform automatic optimization:

[0107] Semantic Reconstruction Failure Subtask:

[0108]

[0109] Expanding the device search space:

[0110]

[0111] Optimize the task dependency graph:

[0112]

[0113] Repairing the local schematic structure:

[0114]

[0115] Dynamically reallocate agent tasks:

[0116]

[0117] The iterative process continues until the convergence condition is met:

[0118]

[0119] II. System Workflow

[0120] The detailed workflow of the system of this invention is as follows:

[0121] Step 1: Natural Language Input and Parsing

[0122] Users submit circuit design requirements via a text input interface, such as: "Design a 20kHz low-pass filter using a Sallen-Key topology, with a cutoff frequency of 20kHz, a gain of 2, and a supply voltage of ±12V." The natural language parsing module encodes the input to generate a semantic vector. and extract the function set (e.g., filtering function, gain requirements) and constraint set C (e.g., frequency parameters, voltage specifications) are used to construct a structured design task. .

[0123] Step 2: Task Decomposition and Graph Construction

[0124] Decision planning agency Receive task Break it down into multiple subtasks: (Op-amp selection) (Resistor Network Design) (Capacitor Network Design) (Power supply design), etc. For each subtask Extracting functional requirements Constraints and keyword embedding vector Then, a directed graph of task dependencies is constructed. The CycleCheck algorithm is used to verify that the graph structure is a directed acyclic graph, ensuring no circular dependencies. The completeness and dependency integrity of each subtask are also verified, triggering replanning if necessary.

[0125] Step 3: Task Scheduling and Parallel Execution

[0126] Legal task dependency graph Perform topology sorting to generate an optimized scheduling sequence. Based on this sequence, (Capacitor Network Design) and (Op-amp selection) is assigned to the corresponding functional agents for parallel execution. Each functional agent Keyword vectors Perform semantic embedding to obtain Then, a weighted cosine search is performed in the device database to select the Top-K matching devices and output the structured device results. .

[0127] Step 4: Schematic Construction

[0128] Schematic diagram for building proxies Receive the device results from each subtask, for example, for (Op-amp selection) Obtained LM358, for (Capacitor network) obtained and Ceramic capacitors. The agent operates based on the rule constraint set. (Including rules such as pin compatibility and power domain partitioning) Generate a partial schematic diagram and the corresponding operation command sequence Commands such as adding symbols and connecting pins.

[0129] Step 5: Assemble the schematic diagram

[0130] Assembly Agent Obtain all local schematic diagrams Build a global connectivity graph , where the node set Includes pins for all subgraphs. Apply connection rule set. Verify the electrical validity of connections between modules, such as ensuring that signal output pins are only connected to input pins. Finally, the graph fusion algorithm is executed to generate a complete schematic diagram. .

[0131] Step 6: Simulation Verification and Feedback

[0132] Simulation Verification Agent Perform ERC / DRC rule checks on the complete schematic and generate an error set. Simultaneously generate simulation scripts. And perform AC analysis to obtain the frequency response. Compare the simulation results with the target function. Compare and determine whether the 20kHz low-pass characteristic and 2x gain requirements are met.

[0133] Step 7: Iterative Optimization

[0134] If the simulation results show a cutoff frequency of 25kHz, it does not meet the 20kHz requirement. The system constructs an error feedback vector. This includes frequency deviation information, irregular errors, simulation configuration, and the current schematic. Decision agent localization problem subtask. (Capacitor network design) Redesign this subtask ), Functional agent extends the capacitance value search range Obtain new candidate values ​​(such as 12nF and 27nF). Schematic proxy execution graph structure optimization. Replace the capacitor value. The system re-executes the simulation until the desired result is achieved. and The convergence condition.

[0135] 3. Key Technology Implementation Details

[0136] 3.1 Task Graph Construction and Verification Mechanism

[0137] Task dependency graph construction employs an automated reasoning method based on semantic similarity and functional dependencies. For any two subtasks... and Dependency The determination is achieved by calculating the dependency probability of the function set, which is jointly determined by the similarity of the function vectors and the strength of the constraint dependency.

[0138] The graph verification process first executes a cycle detection algorithm to ensure that there are no loop structures in the task dependency graph. Then, it checks whether the function set of each subtask is non-empty and whether the constraints are clearly defined. Finally, it verifies whether each subtask has satisfied pre-dependencies. When verification fails, the system triggers a task replanning mechanism to rebuild the subtasks and their dependencies.

[0139] 3.2 Device Vector Retrieval and Matching Mechanism

[0140] The device database D is constructed using multimodal embedding technology, which encodes the textual descriptions, electrical parameters, symbol images, and application examples of devices into a unified vector representation. The retrieval process uses a weighted cosine similarity function:

[0141]

[0142] The weight matrix Obtained through training on historical design data, emphasizing feature dimensions relevant to the current subtask. For filter design tasks, This will increase the weight of parameters such as frequency response, accuracy, and temperature stability, while for power supply circuit design, more attention will be paid to power handling capacity and efficiency parameters.

[0143] The search system will select the one with the highest similarity. Each device is selected as a candidate, and complete electrical and mechanical specifications are provided for each candidate, including pin definitions, type classifications, and package dimensions, to ensure that there is sufficient information to support subsequent schematic construction.

[0144] 3.3 Schematic Construction and Rule Constraints

[0145] Schematic construction proxy represents the schematic as a graph structure , where the vertex Represents components and network nodes, edges This indicates an electrical connection. When generating connections, the agent follows a strict set of electrical rules. Perform real-time verification to ensure the design complies with electrical engineering specifications.

[0146] The connection rule verification mechanism checks pin type compatibility to ensure that output pins are not directly connected to other output pins; verifies electrical characteristic compatibility to prevent high voltage from being connected to low voltage tolerance pins; and checks network category limitations to ensure proper isolation between analog and digital components. The system supports custom rule sets to adapt to different design standards and enterprise specifications.

[0147] 3.4 Simulation Feedback and Adaptive Iterative Optimization

[0148] The system implements a closed-loop feedback iterative mechanism, automatically triggering a multi-level optimization strategy when simulation results deviate from the design objectives. Error feedback vector. It contains comprehensive diagnostic information, enabling the system to accurately pinpoint the root cause of the problem.

[0149] Iterative optimization employs a hierarchical strategy: for small errors, the system performs local parameter optimization, such as fine-tuning resistor or capacitor values; for structural problems, it modifies the connection relationships in the local schematic diagram, such as adding buffer stages or filter networks; for systematic deviations, it reconstructs the task dependency graph and adjusts the task execution order and module partitioning strategy.

[0150] The system continuously monitors the performance of each agent, including task completion quality, error rate, and optimization efficiency, and dynamically adjusts the task allocation strategy to assign complex subtasks to high-performing agents, forming an adaptive and self-optimizing collaborative design system.

[0151] 4. Example

[0152] The application of the present invention will be described in detail below through a specific embodiment:

[0153] Example 1: Audio Amplifier Circuit Design

[0154] User input in natural language: "Design a stereo audio amplifier with an input sensitivity of 200mV, an output power of 4W×2, a frequency response of 20Hz-20kHz, and a total harmonic distortion of less than 0.1%, using the TDA2030A chip."

[0155] Step 1: Natural Language Parsing

[0156] The system analyzes the input, extracts the function set F = {stereo amplification, 4W output, low distortion} and the constraint set C = {200mV input, 20Hz-20kHz response, <0.1% THD, TDA2030A chip}, and generates a structured task. .

[0157] Step 2: Task Decomposition and Graph Construction

[0158] The decision planning agent breaks down tasks into sub-tasks:

[0159] TDA2030A Circuit Design (Left Channel);

[0160] TDA2030A Circuit Design (Right Channel);

[0161] Power supply circuit design;

[0162] Input interface design;

[0163] Output protection circuit design;

[0164] Building a dependency graph ,in (Power supply) is and Prerequisites, (input) and (output) depends on and The verification graph structure is acyclic and all tasks are complete.

[0165] Steps 3-4: Task Execution and Schematic Construction

[0166] The function proxy retrieves the TDA2030A datasheet and matching resistor and capacitor values, and the schematic proxy generates a typical application circuit that conforms to the datasheet's recommendations. For the left channel, it calculates the gain resistor ratio. ,choose , .Add to Input coupling capacitor, Power supply decoupling capacitors, etc.

[0167] Step 5: Assemble the schematic diagram

[0168] The assembly agent integrates the left / right channel circuits, ±16V power supply circuits, RCA input interfaces, and speaker output interfaces to ensure proper power network connection and no crosstalk between the left and right channels.

[0169] Step 6: Simulation Verification

[0170] The system performed a THD analysis, and the results were displayed. , When outputting It slightly exceeds specifications. Additionally, significant power supply ripple was observed, affecting sound quality.

[0171] Step 7: Iterative Optimization

[0172] The system constructs an error feedback vector and re-plans the power supply subtask. ,Increase Filter capacitors and adjust the voltage regulator circuit. Also optimize... and The feedback network was configured, and the THD was reduced to 0.08% by adjusting the ratio of the negative feedback resistor. All parameters were verified to meet the requirements again, and the final schematic and BOM list were output.

[0173] This embodiment demonstrates how the present invention translates natural language requirements into designs that comply with electrical specifications, ensuring design quality and significantly improving design efficiency through multi-agent collaboration and iterative optimization.

[0174] The above embodiments describe in detail the specific implementation method of the present invention, covering the system architecture, core algorithm, workflow, and practical application examples, fully demonstrating the technical innovation and practical value of the present invention. Those skilled in the art can make various modifications and variations based on the above description without departing from the spirit and scope of the present invention.

[0175] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0176] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0177] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A multi-agent electronic design system with graph structure control and feedback iteration capabilities, characterized in that, The system includes: The natural language parsing module is used to receive natural language input from users, generate semantic vectors, and extract function sets and constraint sets from them as structured design tasks. The decision planning agent is used to decompose the structured design task into functions, generate a set of subtasks, construct a directed graph of subtask dependencies, and perform logical consistency verification. Multiple functional module agents are assigned to handle specific subtasks, which are used to match relevant components in the device database through vector retrieval and output a structured set of devices. The schematic construction agent is used to generate local schematics and corresponding operation command sequences based on subtask information and device results, following a predefined set of rule constraints. The assembly agent is used to receive the sub-graph set and task dependency graph, perform schematic sub-graph merging and electrical connections between modules, and generate a complete schematic; The simulation verification agent is used to perform rule checks and behavioral simulations on the generated schematics and compare the verification results with the design goals. The feedback iteration module constructs error feedback information when the verification results do not meet the design goals, triggering task replanning, device rematching, or graph structure optimization to form closed-loop iterative control. The subtasks depend on a directed graph that is a directed acyclic graph, and the execution order of the subtasks is determined by a topological sorting algorithm to achieve parallel processing and collaborative scheduling of tasks.

2. The electronic design multi-agent system according to claim 1, characterized in that, When performing logical consistency verification, the decision planning agent executes a loop detection algorithm and checks the completeness of the input and the explicit definition of the constraints for each subtask. When an abnormal graph structure or a conflict of task constraints is detected, the task replanning process is triggered.

3. The electronic design multi-agent system according to claim 1, characterized in that, When the functional module agent performs device matching, it uses a weighted cosine similarity calculation method to perform vector retrieval in the device database to obtain Top-K matching device results. The device results include component symbols, pin definitions, package types, and electrical characteristic information.

4. The electronic design multi-agent system according to claim 1, characterized in that, The rule checks performed by the simulation verification agent include electrical rule checks (ERC) and design rule checks (DRC). When an error is detected, structured error information is generated and fed back to the decision planning agent to guide subsequent iterative optimization.

5. The electronic design multi-agent system according to claim 1, characterized in that, When constructing the error feedback vector, the feedback iteration module includes error metric values, rule-checked error sets, simulation configuration, simulation results, and current schematic structure information. It can also automatically locate the set of subtasks that cause functional failure and optimize the failed subtasks through a semantic reconstruction function.

6. The electronic design multi-agent system according to claim 1, characterized in that, The system applies a reinforcement learning scoring function to the task dependency graph, dynamically adjusts the task execution order and dependencies, and introduces a mutation operator in the device vector space to expand the search diversity and improve the system convergence efficiency.

7. The electronic design multi-agent system according to claim 1, characterized in that, During the iterative optimization process, the schematic building agent performs edge-level or block-level graph structure optimization, adjusts the local schematic structure through graph repair algorithms, fixes connection errors or optimizes the layout, and follows pin compatibility, network classification and power domain partitioning rules.

8. The electronic design multi-agent system according to claim 1, characterized in that, The system dynamically allocates task priorities and computing resources based on the historical performance data of each agent, including generation accuracy and error correction rate, and optimizes the overall task allocation strategy until the preset error threshold and zero-rule error condition are met.

9. A method for operating an electronic design multi-agent system as described in any one of claims 1-8, characterized in that, Includes the following steps: a) Receive circuit design requirements described in natural language and extract the function set and constraint set through semantic parsing; b) Construct a structured design task, perform functional decomposition, generate a set of subtasks and their dependencies in a directed graph, and verify the logical consistency of the graph structure; c) Perform topology sorting, assign corresponding functional module agents to each subtask, match devices through vector retrieval, and construct a local schematic diagram; d) Assemble the schematic diagrams of each part, establish electrical connections between modules, and generate a complete schematic diagram; e) Perform rule checks and circuit simulation. When verification fails, construct an error feedback vector to trigger task replanning and device rematching. f) Apply reinforcement learning to score and adjust the task graph, perform structural optimization on the schematic diagram, and repeat steps c) to e) until the design goal is met.

10. The method according to claim 9, characterized in that, In step e), the system automatically locates the task subgraph that caused the functional failure, generates a new subtask representation through a semantic reconstruction function, expands the search radius in the vector space, and dynamically adjusts the task allocation strategy based on the historical performance of each agent.

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