Adaptive window comparator

Abstract

The invention relates to an adaptive window comparator. In some examples, a circuit (200) includes a window comparator circuit (202). The window comparator circuit is configured to: receive an input signal and a feedback signal; determining a delayed representation of the feedback signal based on a window control signal; determining a time window based on the feedback signal and the delayed representation of the feedback signal; determining that the input signal and the feedback signal are locked in response to the occurrence of a rising edge of the input signal in the time window or in response to the occurrence of a falling edge of the input signal in the time window; and in response to the rising edge of the input signal appearing outside the time window or in response to the falling edge of the input signal appearing outside the time window, providing a pulse signal having an assertion value during a programming period.

Description

Technical Field

[0001] This disclosure relates to an adaptive window comparator. Background Technology

[0002] A delay-locked loop (DLL) observes a periodic input signal or a reference signal to form a feedback signal matched to a specific delay. Based on this delay, the DLL determines a correction value to modify the timing of the feedback signal, thereby reducing or increasing the delay. Summary of the Invention

[0003] In some examples, a circuit includes a window comparator circuit having first, second, and third inputs and first and second outputs. The circuit also includes a counter having first and second inputs and an output, the first input of the counter being coupled to the first output of the window comparator circuit, and the second input of the counter being coupled to the second output of the window comparator circuit. The circuit further includes a current generator having an input, a window control output, and a plurality of delay outputs, the input of the current generator being coupled to the output of the counter, and the window control output being coupled to the third input of the window comparator circuit. The circuit also includes a plurality of delay circuits coupled in series between the first input and the second input of the window comparator circuit, each delay circuit having a delay control input coupled to a corresponding of the plurality of delay outputs of the current generator.

[0004] In some examples, a circuit includes a window comparator circuit. The window comparator circuit is configured to receive an input signal and a feedback signal. The window comparator circuit is also configured to determine a delay representation of the feedback signal based on a window control signal. The window comparator circuit is further configured to determine a time window based on the feedback signal and the delay representation of the feedback signal. The window comparator circuit is also configured to determine that the input signal and the feedback signal are locked in response to a rising edge of the input signal appearing within the time window or a falling edge of the input signal appearing within the time window. The window comparator circuit is further configured to provide a pulse signal with an assertion value within a programmed time period in response to a rising edge of the input signal appearing outside the time window or a falling edge of the input signal appearing outside the time window. Attached Figure Description

[0005] Figure 1 This is a block diagram of the example system.

[0006] Figure 2 This is a block diagram of the example DLL.

[0007] Figure 3 This is a block diagram of an example window comparator circuit.

[0008] Figure 4 This is a schematic diagram of an example delay circuit.

[0009] Figure 5 This is a schematic diagram of an example current generator.

[0010] Figure 6 This is a timing diagram of the example waveform.

[0011] Figure 7 This is a timing diagram of the example waveform.

[0012] Figure 8 This is a flowchart of the example method. Detailed Implementation

[0013] As described above, the DLL observes a periodic input signal or reference signal to form a feedback signal that matches a specific delay. Based on this delay, the DLL determines a correction value to modify the timing of the feedback signal, thereby reducing or increasing the delay. Some existing methods are inherently binary, reducing the delay of the feedback signal when it lags behind the input signal and increasing it when it leads the input signal. However, this presents challenges. For example, when the values ​​of the input and feedback signals are close—for instance, when their rising edges are close to each other in time—the DLL may repeatedly cause the phase of the input signal to exceed or fall below the phase of the feedback signal, resulting in feedback signal jitter, for example, by using a phase-frequency detection circuit.

[0014] The examples in this specification provide an adaptive window comparator. The adaptive window comparator contains a window that a DLL attempts to lock an input signal within. For example, instead of attempting to align the rising edges of the input and feedback signals, the DLL determines the feedback window via the adaptive window comparator. The feedback window can be a time interval between the rising edge of the feedback signal and the corresponding rising edge represented by a delay of the feedback signal. The DLL shifts the time of the feedback window forward or backward such that the rising edge of the input signal is within the feedback window. In response to determining that the rising edge of the input signal appears within the feedback window, the DLL determines that the feedback window is locked to the input signal. In some examples, the DLL may modify the width of the feedback window to control the precision of the rising edge of the feedback signal relative to the corresponding rising edge of the input signal, which will be considered locked to the feedback window.

[0015] Figure 1This is a block diagram of example system 100. System 100 can be any system or apparatus in which a clock signal is provided by a first component, said clock signal being retied via a DLL and provided to a second component. For example, system 100 may be adapted to perform clock and / or data recovery. In some examples, system 100 includes component 102, DLL 104, and component 106. In the example, component 102 provides an input signal to DLL 104. Component 102 can be any suitable component capable of providing an input signal such as a clock signal, and its range is not limited herein. For example, component 102 can be a controller, processor, oscillator, analog clock generation circuitry, or any other one or more analog and / or digital components.

[0016] In the example, DLL 104 receives the input signal and provides a feedback signal. In some examples, DLL 104 may also provide one or more additional signals representing different phases of the feedback signal. DLL 104 may delay the input signal to form the feedback signal. For example, DLL 104 may determine whether the rising edge of the input signal is within the time window or threshold deviation of the corresponding rising edge of the feedback signal. In response to the rising edge of the input signal not being within the time window of the corresponding rising edge of the feedback signal, DLL 104 modifies the delay of the feedback signal. In response to the rising edge of the input signal being within the time window of the corresponding rising edge of the feedback signal, DLL 104 determines that there is a lock-in between the feedback signal and the input signal. DLL 104 provides the feedback signal to component 106 as an output signal. Component 106 may be any suitable component capable of receiving signals such as clock signals, the output signal of DLL 104, etc., and its range is not limited herein. For example, component 106 may be a controller, processor, oscillator, analog clock generation circuit, or any other one or more analog and / or digital components. In some examples, DLL 104 also provides one or more other signals to component 106, component 102, or any other suitable component, wherein the one or more other signals represent different phases of the feedback signal.

[0017] Figure 2 This is a block diagram of example DLL 200. In the example, DLL 200 is suitable for implementation as DLL 104 in system 100. In the example, DLL 200 includes window comparator circuitry 202, counter 204, current generator 206, and delay circuitry 208-1…208-N. Although described herein as a component of system 100, DLL 200 may be suitable for implementation in other systems in various examples. For example, DLL 200 may be suitable for implementation in any system or apparatus where it is desired to match the phase of the generated feedback signal within a defined accuracy range of the input signal.

[0018] In an example, window comparator circuit 202 has first, second, and third input terminals and first and second output terminals. Window comparator circuit 202 receives an input signal at the first input terminal of window comparator circuit 202, such as from component 102. Window comparator circuit 202 is coupled to the output terminal of delay circuit 208-N at the second input terminal. The third input terminal of window comparator circuit 202 is coupled to the window control output terminal of current generator 206. Window comparator circuit 202 also has first and second output terminals. Counter 204 has a first input terminal coupled to the first output terminal of window comparator circuit 202 and has a second input terminal coupled to the second output terminal of window comparator circuit 202. Counter 204 has an output terminal coupled to the input terminal of current generator 206. In some examples, the coupling between counter 204 and current generator 206 is a single coupling through which multiple bits of digital data can be serially transmitted. In other examples, there may be multiple couplings between counter 204 and current generator 206 such that a corresponding single bit of digital data can be provided via each of the multiple couplings. Current generator 206 includes multiple current output terminals, each of which is correspondingly coupled to one of delay circuits 208-1 to 208-N. For example, the first current output terminal of current generator 206 is coupled to the current input of delay circuit 208-1, the second current output terminal of current generator 206 is coupled to the current input of delay circuit 208-2, and the Nth current output terminal of current generator 206 is coupled to the current input of delay circuit 208-N. In Figure 2 the example, 12 delay circuits 208 are shown. However, in other examples, any other suitable number of delay circuits may be used, such as 4, 8, or any other suitable number. In the example, the input terminal of delay circuit 208-1 receives an input signal (e.g., coupled to or can be coupled to the first input terminal of window comparator circuit 202). The output of corresponding delay circuit 208-X is coupled to the input terminal of the next delay circuit 208-(X + 1), where X is an integer and 0 < X < N. Each output terminal of the corresponding delay circuit may also represent a different phase of a feedback signal provided at the output terminal of delay circuit 208-N, where the feedback signal is an output signal of DLL 200 that can be provided to another component, such as component 106.

[0019] In the operational example, window comparator circuit 202 receives an input signal and a feedback signal. Window comparator circuit 202 generates a delayed representation of the feedback signal (e.g., a delayed feedback signal) based on a window control signal received from current generator 206. Therefore, window comparator circuit 202 forms a window whose starting point is aligned with the rising edge of the feedback signal and whose ending point is aligned with the rising edge of the delayed feedback signal. In response to the input signal having a rising edge that precedes the rising edge of the feedback signal, window comparator circuit 202 provides a signal with a logic high value (e.g., UPDNZ) at its first output and a signal pulse (UPDATE_PULSE) at its second output. Conversely, in response to the input signal having a rising edge that follows the rising edge of the delayed feedback signal, window comparator circuit 202 provides UPDNZ with a logic low value at its first output and UPDATE_PULSE at its second output. Finally, in response to the input signal having a rising edge that appears in the window (e.g., after the rising edge of the feedback signal and before the rising edge of the delayed feedback signal), the window comparator circuit 202 no longer provides UPDATE_PULSE at the second output of the window comparator circuit 202.

[0020] Counter 204 receives UPDNZ and UPDATE_PULSE and generates a control word based on UPDNZ and UPDATE_PULSE. In this example, the control word is a digital value with multiple bits. Counter 204 increments or decrements its count in response to the reception of a rising edge of UPDATE_PULSE. For example, counter 204 increments its count in response to the reception of a rising edge of UPDATE_PULSE and UPDNZ with logic high values. Conversely, counter 204 decrements its count in response to the reception of a rising edge of UPDATE_PULSE and UPDNZ with logic low values. Counter 204 can be implemented according to any suitable hardware architecture, the range of which is not limited herein. Counter 204 provides each corresponding bit of the control word to current generator 206 to control the current supplied by current generator 206 to delay circuit 208.

[0021] Current generator 206 receives a control word from counter 204 and provides a current signal to delay circuit 208 based on the value of the control word. Current generator 206 also provides a window control signal to window comparator circuit 202, the window control signal having a fractional value of the current signal provided to delay circuit 208. In some examples, current generator 206 has a binary weighted architecture. In such an architecture, current generator 206 includes multiple current sources, and each current source is configured to provide a 2-bit current signal. mThe value of the current is used to control the switching of the corresponding current source. In this example, m is a bit position in the control word, and the control word contains bits <8:0>. In other examples, the control word may have any suitable number of bits, corresponding to the number of current sources of the current generator 206. When the value of the control word increases, for example because the input signal follows the delayed feedback signal, the value of the current supplied by the current generator 206 to the delay circuit 208 decreases, thereby increasing the delay provided by the delay circuit 208. Conversely, when the value of the control word decreases, for example because the input signal precedes the feedback signal, the value of the current supplied by the current generator 206 to the delay circuit 208 increases, thereby decreasing the delay provided by the delay circuit 208.

[0022] Each delay circuit 208 receives a corresponding current signal from the current generator 206 and implements a delay based on the received current signal. For example, when the value of the received current signal increases, the amount of delay provided by the delay circuit 208 decreases. Conversely, when the value of the received current signal decreases, the amount of delay provided by the delay circuit 208 increases. The delay circuit 208 may have any suitable architecture, the range of which is not limited herein. In the example, the total delay from the input signal to the feedback signal provided by DLL 200 is N*C_DLY*V_threshold / I_SUM, where C_DLY is the capacitance of each corresponding capacitor of the delay circuit 208, V_threshold is the threshold voltage of each corresponding delay circuit 208 as further described below, and I_SUM is the value of the current signal provided by the current generator 206 to each corresponding delay circuit 208.

[0023] Figure 3 This is a block diagram of an example window comparator circuit 300. In at least some examples, the window comparator circuit 300 is suitable for implementation as a window comparator circuit 202, as described above. Figure 2 As described. In the example, the window comparator circuit 300 includes a first D flip-flop (DFF) 302, a first delay circuit 304, a second DFF 306, an AND logic circuit 308, an XOR circuit 310, a second delay circuit 312, a pulse generation circuit 314, a first inverter circuit 316, a second inverter circuit 318, and an AND logic circuit 320.

[0024] In the example architecture of the window comparator circuit 300, the first DFF 302 has a clock input for receiving an input signal, a data input for providing a feedback signal, and a data output. The first delay circuit 304 has a first input coupled to the data input of the first DFF 302, a second input for receiving a window control signal, and an output. The second DFF 306 has a clock input coupled to the clock input of the first DFF 302, a data input coupled to the output of the first delay circuit 304, and a data output. The AND logic circuit 308 has a first input coupled to the data output of the first DFF 302, a second input coupled to the data output of the second DFF 306, and an output. The XOR logic circuit 310 has a first input coupled to the data output of the first DFF 302, a second input coupled to the data output of the second DFF 306, and an output. The second delay circuit 312 has an input coupled to the clock input of the first DFF 302 and an output. Pulse generation circuit 314 has an input coupled to the output of second delay circuit 312 and has an output. First inverter circuit 316 has an input coupled to the output of pulse generation circuit 314 and has an output. Second inverter circuit 318 has an input coupled to the output of XOR logic circuit 310 and has an output. AND logic circuit 320 has a first input coupled to the output of inverter circuit 316, a second input coupled to the output of second inverter circuit 318, and an output. In the example, window comparator circuit 300 provides UPDNZ at the output of AND logic circuit 308 and UPDATE_PULSE at the output of AND logic circuit 320.

[0025] In an example of the operation of the window comparator circuit 300, the first DFF 302 receives a feedback signal, and in response to the rising edge of the received input signal, latches the value of the feedback signal provided at the data input of the first DFF 302 to the output of the first DFF 302. The first delay circuit 304 receives the feedback signal and generates or provides a delayed feedback signal. In this example, the delay amount of the rising edge of the delayed feedback signal is determined at least partially based on the value of the window control signal. For example, when the value of the window control signal increases, the delay amount decreases, and vice versa. The second DFF 306 receives the delayed feedback signal, and in response to the rising edge of the received input signal, latches the value of the delayed feedback signal provided at the data input of the second DFF 306 to the output of the second DFF 306.

[0026] In response to both the first DFF 302 and the second DFF 306 providing a logic high value at their respective data outputs, the AND logic circuit 308 provides a UPDNZ with a logic high value at its output. Otherwise, the AND logic circuit 308 provides a UPDNZ with a logic low value at its output. In response to only one of DFF 302 or DFF 306 providing a logic high value at its respective data output, the XOR logic circuit 310 provides a signal (e.g., LOCK) with a logic high value at its output. Otherwise, the XOR logic circuit 310 provides a LOCK with a logic low value. In some examples, a LOCK with a logic high value indicates that the input signal has a rising edge appearing within the window formed by the first DFF 302 and the second DFF 306. For example, based on the output signal of the first DFF 302, it is determined that the input signal has a rising edge that occurs after the corresponding rising edge of the feedback signal, and based on the output signal of the second DFF 306, it is determined that the input signal has a rising edge that occurs before the corresponding rising edge of the delayed feedback signal.

[0027] The second delay circuit 312 forms a delayed representation of the input signal, and in response to a rising edge appearing in the delayed representation of the input signal, the pulse generation circuit 314 provides a pulse signal (RSTZ). The first inverter 316 inverts RSTZ, and the second inverter 318 inverts LOCK. In response to both RSTZ and LOCK having logic low values, the AND logic circuit 320 provides an UPDATE_PULSE with a logic high value. Otherwise, the AND logic circuit 320 provides an UPDATE_PULSE with a logic low value. As described above, in some examples, an UPDATE_PULSE having a logic high value causes the counter 204 to increment or decrement a determined count based on the value of UPDNZ, thereby modifying the control word provided to the current generator 206. This then modifies the window control signal and the feedback signal, thereby moving the comparison window of the window comparator circuit 300.

[0028] In the examples, the size or width of the comparison window can correspond to the accuracy of the phase of the feedback signal provided by the delay circuit 208 relative to the phase of the received input signal. In some examples, the width of the comparison window can be approximately three times the minimum current step size of the current provided by the current generator 206. In other examples, the width of the comparison window can have any other suitable relationship with the minimum current step size of the current provided by the current generator 206.

[0029] Figure 4 This is a schematic diagram of an example delay circuit 400. In at least some examples, the delay circuit 400 is suitable for implementation as a first delay circuit 304, as described above regarding... Figure 3As described above. In at least some examples, delay circuit 400 may also be adapted to be any one or more of delay circuits 208-1 to 208-N, as described above. Figure 2 As described. In the example, the delay circuit 400 includes an inverter circuit 402, an AND logic circuit 404, a switch 406, a capacitor 408, a Schmitt trigger 410, and a switch 412.

[0030] In the example architecture of delay circuit 400, inverter circuit 402 has an input coupled to the output of Schmitt trigger 410 and an output. AND logic circuit 404 has a first input coupled to the output of inverter circuit 402, a second input receiving the input signal of delay circuit 400, and an output. Switch 406 has a control terminal coupled to the output of AND logic circuit 404, a first terminal receiving a current signal, and a second terminal. Capacitor 408 has a first terminal coupled to the second terminal of switch 406 and a second terminal coupled to ground terminal 414 providing a ground voltage potential. Schmitt trigger 410 has an input coupled to the second terminal of switch 406 and an output. Switch 412 has a control terminal coupled to the output of Schmitt trigger 410, a first terminal coupled to the second terminal of switch 406, and a second terminal coupled to ground terminal 414.

[0031] In some examples, the data input signal (e.g., the signal to be delayed) is received at the second input of the AND logic circuit 404, the control signal for controlling the amount of delay of the delay unit 400 is received at the first end of the switch 406, and the data output signal (e.g., a delayed representation of the signal received at the second input of the AND logic circuit 404) is provided at the output of the Schmitt trigger 410.

[0032] In an example of the operation of delay circuit 400, in response to the reception of a delayed representation of an input signal with a logic high value and an input signal with a logic low value, AND logic circuit 404 provides a signal with a logic high value to close switch 406. In response to the closure of switch 406, capacitor 408 begins to charge. In some examples, the charging rate of capacitor 408 is determined based on the current value of the control signal received at the first terminal of switch 406; the larger the current, the faster capacitor 408 charges, and vice versa. While capacitor 408 is charging, the voltage supplied at the input of Schmitt trigger 410 increases. In response to the voltage supplied at the input of Schmitt trigger 410 exceeding the threshold voltage of Schmitt trigger 410, Schmitt trigger 410 provides a signal with a logic high value at its output. The signal having a logic high value at the output of Schmitt trigger 410 causes switch 412 to close, thereby discharging capacitor 408 to ground terminal 414. When capacitor 408 discharges, the voltage supplied by capacitor 408 at the input of Schmitt trigger 410 decreases. In response to the voltage at the input of Schmitt trigger 410 decreasing below its threshold voltage, Schmitt trigger 410 provides a signal with a logic low value at its output. This logic low value causes switch 412 to open and delay circuit 400 to reset, awaiting a subsequent logic high value of the input signal received at the second input of AND logic circuit 404.

[0033] In implementation Figure 3 In an example of the delay circuit 400 of the first delay circuit 304 of the window comparator circuit 300, the capacitor 408 may have a capacitance approximately equal to that implemented as Figure 2 The example of the delay circuit 208-1 to 208-N of the DLL 200 corresponds to one-third of the capacitance of the capacitor 408.

[0034] Figure 5 This is a schematic diagram of an example current generator 500. In at least some examples, current generator 500 is suitable for implementation as current generator 206, as described above. Figure 2 As described. In the example, the current generator includes transistors 502, 504-1, ..., 504-N, transistor 506, current sources 508-0, ..., 508-m, and switches 510-0, ..., 510-m.

[0035] In the example architecture of current generator 500, transistor 502 has a first terminal coupled to a voltage supply (VCC) terminal, a second terminal coupled to the second terminal of transistor 502, and a control terminal coupled to the second terminal of transistor 502. Transistor 504-1 has a first terminal coupled to the VCC terminal, a second terminal coupled to the control terminal of delay circuit 208-1, and a control terminal coupled to the control terminal of transistor 502. Transistor 504-N has a first terminal coupled to the VCC terminal, a second terminal coupled to the control terminal of delay circuit 208-N, and a control terminal coupled to the control terminal of transistor 502. In this way, each transistor pair formed by transistor 502 and the corresponding transistor 504 forms a current mirror, such that the drain current of transistor 502 is replicated to the corresponding transistor 504. Similarly, transistor 506 has a first terminal coupled to the VCC terminal, a second terminal providing a window control signal (e.g., such that the second control terminal is coupled to the control terminal of the first delay circuit 304), and a control terminal coupled to the control terminal of transistor 502. Therefore, transistors 502 and 506 form another current mirror. Current source 508-0 has a first terminal coupled to the second terminal of transistor 502, and also has a second terminal. Switch 510-0 has a first terminal coupled to the second terminal of current source 508-0, a second terminal coupled to ground terminal 512 providing a ground voltage potential, and a bit coupled to counter 204 and configured to receive a control word. <0> The control terminal. Current source 508-m has a first terminal coupled to the second terminal of transistor 502, and a second terminal. Switch 510-m has a first terminal coupled to the second terminal of current source 508-m, a second terminal coupled to ground terminal 512, and a bit coupled to counter 204 and configured to receive the control word. <m>The control terminal.

[0036] In an example of the operation of current generator 500, in response to a logic high value in a bit of the control word, the corresponding switch in switch 510 closes. In response to the closure of switch 510, current from the corresponding current source 508 flows through transistor 502 from the VCC terminal to the ground terminal 512 and is replicated to transistors 504 and 506. The replicated current is provided by transistor 504 to the corresponding delay circuit 208 to control the delay amount of delay circuit 208. The replicated current is also provided by transistor 506 to the first delay circuit 304 to control the width of the comparison window formed by the window comparator circuit 300.

[0037] In some examples, transistors 504 each have substantially the same width and length as transistor 502. In an example of the current generator 500 implemented in DLL 200, where the capacitance of the capacitor in the first delay circuit 304 is one-third that of the delay circuit 208, transistor 506 may have substantially similar characteristics to transistor 504 (e.g., aspect ratio). Conversely, in an example of the current generator 500 implemented in DLL 200, where the capacitor in the delay circuit 304 has substantially the same capacitance as the delay circuit 208, the size of transistor 506 may be approximately one-third the size of transistor 504 (e.g., the aspect ratio is one-third that of transistor 504). In other examples, the one-third ratio can be any other suitable value such that the window control signal has a value that is a scaled representation of I_SUM. In yet another example, I_SUM itself can be used as the window control signal.

[0038] In the example, the step size (dT_step) of the current generator 500 is approximately equal to N*C_DLY*V_threshold*(1 / (Z*iLSB*(Z+1)), where Z is the value of the control word and iLSB is the amount by which I_SUM increases or decreases by Z. Based on the dT_step determined as shown above, the error (T_err) after asserting the LOCK (e.g., the transition from logic low to logic high) is approximately equal to 2*dT_step. In the example, T_err represents the absolute value of the time error between the input signal and the feedback signal.

[0039] As described above, Figure 2 Each output of the delay circuit 208 of the DLL 200 provides a corresponding phase of the feedback signal. For a DLL 200 with 12 delay circuits... Figure 2 For example, the phase separation is approximately 30 degrees. The error (P_err) for any given phase is approximately equal to (T_err / T_period)*360, where T_period is approximately equal to N*C_DLY*V_threshold / (Z*iLSB). Therefore, P_err is approximately equal to 720° / (Z+1), and the percentage of P_err is approximately equal to 200 / (N+1).

[0040] Figure 6 This is a timing diagram for example waveform 600. In some examples, waveform 600 represents a waveform that can exist... Figure 2 At least some signals in DLL 200. Therefore, when describing waveform 600, reference can be made to the components or signals of DLL 200. Waveform 600 includes the input signal (IN), feedback signal (FB), delayed feedback signal (FB_dly), UPDNZ, UPDATE_PULSE, and LOCK. Waveform 600 illustrates the operation of DLL 200, where the delay of DLL 200 (e.g., implemented by delay circuit 208) is excessive, and the rising edge of IN precedes the rising edge of FB, and is therefore outside the comparison window.

[0041] As shown in waveform 600, the period of FB(T_fb1, ..., T_fbn) and the width of the comparison window are reduced by adjusting the delay time of DLL200. As further shown in waveform 600, in response to the reception of the rising edge of IN, a pulse is provided in the UPDATE_PULSE signal while LOCK has a logic low value. In response to this pulse in the UPDATE_PULSE signal, counter 204 decrements its determined count, causing current generator 206 to increase the current supplied to delay circuit 208 and window comparator circuit 202, thereby reducing the period of FB and the width of the comparison window. In response to the rising edge of IN appearing in the comparison window (e.g., after the rising edge of FB and before the corresponding edge of FB_dly), LOCK with a logic high value is provided, and other pulses are not included in UPDATE_PULSE until IN no longer has a rising edge appearing in the comparison window.

[0042] Figure 7 This is a timing diagram for example waveform 700. In some examples, waveform 700 represents a waveform that can exist... Figure 2 At least some signals in DLL 200. Therefore, when describing waveform 700, reference can be made to the components or signals of DLL 200. Waveform 700 includes the input signal (IN), feedback signal (FB), delayed feedback signal (FB_dly), UPDNZ, UPDATE_PULSE, and LOCK. Waveform 700 illustrates the operation of DLL 200, where the delay of DLL 200 (e.g., implemented by delay circuit 208) is too short, and the rising edge of IN follows the rising edge of FB_dly, and is therefore outside the comparison window.

[0043] As shown in waveform 700, the period of FB(T_fb1, ..., T_fbn) and the width of the comparison window are increased by adjusting the delay time of DLL200. As further shown in waveform 700, in response to the reception of the rising edge of IN, a pulse is provided in the UPDATE_PULSE signal while LOCK has a logic low value. In response to this pulse in the UPDATE_PULSE signal, counter 204 increments its determined count, causing current generator 206 to reduce the current supplied to delay circuit 208 and window comparator circuitry, thereby increasing the period of FB and the width of the comparison window. In response to the rising edge of IN appearing in the comparison window (e.g., after the rising edge of FB and before the corresponding edge of FB_dly), LOCK with a logic high value is provided, and other pulses are not included in the UPDATE_PULSE signal until IN no longer has a rising edge appearing in the comparison window.

[0044] Figure 8 This is a flowchart of example method 800. In some examples, method 800 is a method for determining the lock between the feedback signal and the input signal. Method 800 can be at least partially derived from... Figure 2 The implementation of DLL 200. Therefore, when describing method 800, reference may be made to the components or signals of DLL 200.

[0045] At operation 802, an input signal is received. In some examples, the input signal is a clock signal that locks the DLL 200 relative to its determining feedback signal (e.g., a feedback clock signal) and / or provides multiple individual phase signals.

[0046] At operation 804, DLL 200 determines the delayed representation of the feedback signal based on the window control signal. In some examples, the window control signal is provided by current generator 206, as described above. The delayed representation of the feedback signal can be determined by delay circuitry, such as delay circuitry 304, also as described above.

[0047] At operation 806, DLL 200 determines a comparison window (e.g., a time window) based on the feedback signal and its delayed representation. In some examples, the comparison window is determined by window comparison circuitry 300, as described above herein.

[0048] At operation 808, DLL 200 determines that the reference signal and feedback signal are locked in response to the rising edge of the reference signal appearing in the time window, or in response to the falling edge of the reference signal appearing in the time window. In some examples, the determination of the lock is performed by window comparison circuitry 300, as described above herein.

[0049] At operation 810, in response to a rising edge of the reference signal occurring outside the time window, or in response to a falling edge of the reference signal occurring outside the time window, DLL 200 provides a pulse signal having an assertion value within a specified time period. In some examples, the pulse signal is provided by window comparison circuitry 300, as described above herein.

[0050] In this description, the term "coupled" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0051] A device "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or through a combination thereof.

[0052] The circuits or devices described herein as containing certain components may alternatively be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., semiconductor dies and / or integrated circuit (IC) packages), and may be coupled to at least some passive elements and / or sources during or after manufacturing, for example, by an end user and / or a third party, to form the described structure.

[0053] While some components may be described herein as belonging to a specific process technology, these components may be interchangeable with components from other process technologies. The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors respectively coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors respectively coupled in series between the same two nodes as a single resistor or capacitor.

[0054] The phrase "ground voltage potential" as used in the foregoing description includes chassis grounding, wire grounding, floating grounding, virtual grounding, digital grounding, universal grounding, and / or any other form of grounding connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of said parameter. Modifications to the examples are possible within the scope of the claims, and other examples are possible.

[0055] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnects or their ends between device elements, circuit elements, integrated circuits, devices, or semiconductor components. Additionally, a voltage rail, or more simply "rail," may also be referred to as a voltage terminal and can generally mean a common node or a set of coupled nodes at the same potential in a circuit.< / m>

Claims

1. A circuit comprising: A window comparator circuit having first, second, and third input terminals and first and second output terminals; A counter having first and second input terminals and an output terminal, wherein the first input terminal of the counter is coupled to the first output terminal of the window comparator circuit, and the second input terminal of the counter is coupled to the second output terminal of the window comparator circuit; A current generator having an input terminal, a window control output terminal, and multiple delay output terminals, wherein the input terminal of the current generator is coupled to the output terminal of the counter, and the window control output terminal is coupled to the third input terminal of the window comparator circuit; as well as Multiple delay circuits are coupled in series between the first input terminal and the second input terminal of the window comparator circuit, and each delay circuit has a delay control input terminal coupled to a corresponding of the multiple delay output terminals of the current generator.

2. The circuit according to claim 1, wherein the window comparator circuit comprises: The first delay circuit has input and output terminals; A first D flip-flop has a clock input, a data input, and an output, wherein the data input of the first D flip-flop is coupled to the input of the first delay circuit; The second D flip-flop has a clock input, a data input, and an output. The clock input of the second D flip-flop is coupled to the clock input of the first D flip-flop, and the data input of the second D flip-flop is coupled to the output of the first delay circuit. A second delay circuit has an input and an output terminal, wherein the input terminal of the second delay circuit is coupled to the clock input terminal of the first d flip-flop; A pulse generator having an input and an output, wherein the input of the pulse generator is coupled to the output of the second delay circuit; A first logic circuit has first and second input terminals and an output terminal, wherein the first input terminal of the first logic circuit is coupled to the output terminal of the first D flip-flop, and the second input terminal of the first logic circuit is coupled to the output terminal of the second D flip-flop. A second logic circuit has first and second input terminals and an output terminal. The first input terminal of the second logic circuit is coupled to the output terminal of the first D flip-flop, and the second input terminal of the second logic circuit is coupled to the output terminal of the second D flip-flop. The output terminal of the second logic circuit is coupled to the first output terminal of the window comparator circuit. A first inverter circuit has an input terminal and an output terminal, wherein the input terminal of the first inverter circuit is coupled to the output terminal of the pulse generator; A second inverter circuit has an input terminal and an output terminal, wherein the input terminal of the second inverter circuit is coupled to the output terminal of the first logic circuit; as well as A third logic circuit has first and second input terminals and an output terminal. The first input terminal of the third logic circuit is coupled to the output terminal of the first inverter circuit, and the second input terminal of the third logic circuit is coupled to the output terminal of the second inverter circuit. The output terminal of the third logic circuit is coupled to the second output terminal of the window comparator circuit.

3. The circuit according to claim 2, wherein the first logic circuit is an XOR logic circuit, the second logic circuit is an AND logic circuit, and the third logic circuit is an AND logic circuit.

4. The circuit according to claim 2, wherein the first delay circuit comprises: The third inverter circuit has input and output terminals; A fourth logic circuit having first and second input terminals and an output terminal, wherein the first input terminal of the fourth logic circuit is coupled to the output terminal of the third inverter circuit, and the second input terminal of the fourth logic circuit is coupled to the data input terminal of the first d flip-flop; A first switch has first and second terminals and a control terminal, the first terminal of the first switch being coupled to the third input terminal of the window comparator circuit, and the control terminal of the first switch being coupled to the output terminal of the fourth logic circuit. A capacitor having first and second terminals, the first terminal of the capacitor being coupled to the second terminal of the first switch, and the second terminal of the capacitor being coupled to a ground terminal; A Schmitt trigger having an input and an output, wherein the input of the Schmitt trigger is coupled to the second terminal of the first switch, and the output of the Schmitt trigger is coupled to the input of the third inverter circuit and the data input of the second D flip-flop; as well as A second switch has first and second terminals and a control terminal. The first terminal of the second switch is coupled to the second terminal of the first switch, the control terminal of the second switch is coupled to the output terminal of the Schmitt trigger, and the second terminal of the second switch is coupled to the ground terminal.

5. The circuit according to claim 4, wherein the fourth logic circuit is an AND logic circuit.

6. The circuit of claim 1, wherein the current generator comprises: Multiple current mirrors include multiple first transistors and second transistors, each first transistor having a terminal coupled to a corresponding one of the multiple delayed outputs, and each second transistor having a terminal coupled to the third input of the window comparator circuit; Multiple current sources are coupled in parallel to one of the first transistors; as well as Multiple switches, each switch coupled between a corresponding current source and a ground terminal, and each switch having a control terminal coupled to a corresponding current source among the multiple delayed outputs of the current generator.

7. The circuit of claim 6, wherein the current source is binary weighted.

8. The circuit of claim 1, wherein the output terminal of the counter includes a multi-bit output, the input terminal of the current generator includes a multi-bit input, and the corresponding bit terminals of the counter and the current generator are coupled together.

9. A circuit comprising: The window comparator circuit is configured as follows: Receive input signals and feedback signals; Based on the window control signal, determine the delay representation of the feedback signal; A time window is determined based on the feedback signal and the delay representation of the feedback signal; In response to the rising edge of the input signal appearing in the time window, or in response to the falling edge of the input signal appearing in the time window, it is determined that the input signal and the feedback signal are locked; and In response to the rising edge of the input signal appearing outside the time window, or in response to the falling edge of the input signal appearing outside the time window, a pulse signal having an assertion value is provided within the programming time period.

10. The circuit according to claim 9, further comprising: The counter is configured as follows: The pulse signal and the uplink / downlink signal are received from the window comparator circuit. and In response to the pulse signal having an assertion value, the count value is incremented when the uplink / downlink signal has an assertion value, and the count value is decremented when the uplink / downlink signal has a deassertion value; A current generator is configured to: Receive the count value from the counter; In response to the count value, multiple switches coupled to the binary weighted current source array are controlled to provide multiple delayed control signals; and The window control signal is provided to the window comparator circuit; as well as The delay circuit is configured as follows: Receive the plurality of delay control signals; and The input signal is delayed by a time amount determined according to the plurality of delay control signals to form the feedback signal.

11. The circuit of claim 10, wherein the delay circuit is configured to provide a corresponding phase signal of the input signal for each delay control signal.

12. The circuit of claim 10, wherein the count value is a digital value comprising a plurality of bits, and wherein each bit of the count value controls a corresponding one of the plurality of switches.

13. The circuit of claim 10, wherein the window comparator circuit is configured to determine whether, during operation of the circuit, the input signal and the feedback signal are adaptively locked in response to different delays of the input signal.

14. The circuit according to claim 10, wherein: The window comparator circuit has first, second, and third input terminals and first and second output terminals; The counter has first and second input terminals and an output terminal. The first input terminal of the counter is coupled to the first output terminal of the window comparator circuit, and the second input terminal of the counter is coupled to the second output terminal of the window comparator circuit. The current generator has an input terminal, a window control output terminal, and multiple delay output terminals. The input terminal of the current generator is coupled to the output terminal of the counter, and the window control output terminal is coupled to the third input terminal of the window comparator circuit. The delay circuit includes a plurality of delay circuits coupled in series between the first input terminal and the second input terminal of the window comparator circuit, each delay circuit having a delay control input terminal coupled to a corresponding of the plurality of delay output terminals of the current generator.

15. The circuit of claim 14, wherein the current generator comprises: Multiple current mirrors include multiple first transistors and second transistors, each first transistor having a terminal coupled to a corresponding one of the multiple delayed outputs, and each second transistor having a terminal coupled to the third input of the window comparator circuit; Multiple current sources are coupled in parallel to one of the first transistors; as well as Multiple switches, each switch coupled between a corresponding current source and a ground terminal, and each switch having a control terminal coupled to a corresponding current source among the multiple delayed outputs of the current generator.

16. The circuit of claim 15, wherein the current source is binary weighted.

17. The circuit of claim 14, wherein the window comparator circuit comprises: The first delay circuit has input and output terminals; A first D flip-flop has a clock input, a data input, and an output, wherein the data input of the first D flip-flop is coupled to the input of the first delay circuit; The second D flip-flop has a clock input, a data input, and an output. The clock input of the second D flip-flop is coupled to the clock input of the first D flip-flop, and the data input of the second D flip-flop is coupled to the output of the first delay circuit. A second delay circuit has an input and an output terminal, wherein the input terminal of the second delay circuit is coupled to the clock input terminal of the first d flip-flop; A pulse generator having an input and an output, wherein the input of the pulse generator is coupled to the output of the second delay circuit; A first logic circuit has first and second input terminals and an output terminal, wherein the first input terminal of the first logic circuit is coupled to the output terminal of the first D flip-flop, and the second input terminal of the first logic circuit is coupled to the output terminal of the second D flip-flop. A second logic circuit has first and second input terminals and an output terminal. The first input terminal of the second logic circuit is coupled to the output terminal of the first D flip-flop, and the second input terminal of the second logic circuit is coupled to the output terminal of the second D flip-flop. The output terminal of the second logic circuit is coupled to the first output terminal of the window comparator circuit. A first inverter circuit has an input terminal and an output terminal, wherein the input terminal of the first inverter circuit is coupled to the output terminal of the pulse generator; A second inverter circuit has an input terminal and an output terminal, wherein the input terminal of the second inverter circuit is coupled to the output terminal of the first logic circuit; as well as A third logic circuit has first and second input terminals and an output terminal. The first input terminal of the third logic circuit is coupled to the output terminal of the first inverter circuit, and the second input terminal of the third logic circuit is coupled to the output terminal of the second inverter circuit. The output terminal of the third logic circuit is coupled to the second output terminal of the window comparator circuit.

18. The circuit of claim 17, wherein the first logic circuit is an XOR logic circuit, the second logic circuit is an AND logic circuit, and the third logic circuit is an AND logic circuit.

19. The circuit of claim 17, wherein the first delay circuit comprises: The third inverter circuit has input and output terminals; A fourth logic circuit having first and second input terminals and an output terminal, wherein the first input terminal of the fourth logic circuit is coupled to the output terminal of the third inverter circuit, and the second input terminal of the fourth logic circuit is coupled to the data input terminal of the first d flip-flop; A first switch has first and second terminals and a control terminal, the first terminal of the first switch being coupled to the third input terminal of the window comparator circuit, and the control terminal of the first switch being coupled to the output terminal of the fourth logic circuit. A capacitor having first and second terminals, the first terminal of the capacitor being coupled to the second terminal of the first switch, and the second terminal of the capacitor being coupled to a ground terminal; A Schmitt trigger having an input and an output, wherein the input of the Schmitt trigger is coupled to the second terminal of the first switch, and the output of the Schmitt trigger is coupled to the input of the third inverter circuit and the data input of the second D flip-flop; as well as A second switch has first and second terminals and a control terminal. The first terminal of the second switch is coupled to the second terminal of the first switch, the control terminal of the second switch is coupled to the output terminal of the Schmitt trigger, and the second terminal of the second switch is coupled to the ground terminal.

20. The circuit of claim 19, wherein the fourth logic circuit is an AND logic circuit.

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