Driving circuit, driving assembly and driving module

Abstract

The invention discloses a driving circuit, a driving assembly and a driving module. The driving circuit comprises a plurality of transistor devices which are connected in parallel, wherein grid electrodes of the transistor devices are used for receiving control signals; and the plurality of filter circuits are in one-to-one correspondence with the plurality of transistor devices, each filter circuit comprises a capacitor and a first resistor which are connected in series, and each filter circuit is connected between the grid electrode and the first electrode of the corresponding transistor device.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more particularly to drive circuits, drive components, and drive modules. Background Technology

[0002] Due to their excellent switching performance, power gallium nitride (GaN) switches have become one of the key components for achieving high-efficiency, high-power-density power conversion. In high-current, high-power applications, such as low-voltage high-power motor drive modules, a single GaN switch is often insufficient to meet the current carrying capacity requirements. Therefore, connecting multiple GaN switches in parallel to expand the current capacity is the main technical approach.

[0003] However, existing drive circuits consisting of multiple power gallium nitride switches connected in parallel still need improvement. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit, a driving component, and a driving module.

[0005] This application discloses a driving circuit, including: Multiple transistor devices connected in parallel, wherein the gates of the multiple transistor devices are used to receive control signals; Multiple filter circuits correspond one-to-one with multiple transistor devices. Each filter circuit includes a capacitor and a first resistor connected in series. Each filter circuit is connected between the gate and the first electrode of the corresponding transistor device.

[0006] In some alternative implementations, the driving circuit further includes: A plurality of second resistors are provided, each corresponding to one of the plurality of transistor devices, and each second resistor is connected between the gate and the first electrode of the corresponding transistor device.

[0007] In some alternative implementations, the driving circuit further includes: Multiple third resistors correspond one-to-one with multiple transistor devices. The first end of each third resistor is connected to the gate of the corresponding transistor device, and the second end is used to receive the control signal.

[0008] In some alternative embodiments, the resistance of the second resistor is greater than the resistance of the first resistor, and / or the resistance of the second resistor is greater than the resistance of the third resistor.

[0009] In some alternative implementations, the first or second terminal of the third resistor is connected to the filter circuit.

[0010] In some alternative implementations, the first or second end of the third resistor is connected to the second resistor.

[0011] In some alternative embodiments, the control signal includes a first-level signal and a second-level signal, and the driving circuit further includes: An on-resistor is connected at one end to the second end of the plurality of third resistors, and at the other end is used to receive the first level signal. The shut-off resistor has one end connected to the second end of the plurality of third resistors, and the other end is used to receive the second level signal.

[0012] In some alternative implementations, the resistance of the turn-on resistor is greater than the resistance of the turn-off resistor.

[0013] In some alternative embodiments, one plate of the capacitor is connected to the gate of the corresponding transistor device, and the first resistor is connected to the first electrode of the corresponding transistor device.

[0014] This application also discloses a driving component, which includes two driving circuits as described in any of the preceding claims, wherein a plurality of transistor devices in one driving circuit are connected in series with a plurality of transistor devices in the other driving circuit in a one-to-one correspondence.

[0015] This application also discloses a driver module, including: A substrate, wherein the driving circuit described in any of the preceding claims or the driving component described in the claims is disposed on the substrate; A driver for outputting the control signals.

[0016] In some alternative embodiments, the plurality of transistor devices connected in parallel are distributed along a first direction, which is parallel to the substrate; the driving module further includes: At least one first trace extends along the first direction, wherein for two adjacent transistor devices in the first direction, one end of the first trace is connected to the gate of one of the transistor devices and the other end is connected to the gate of the other transistor device. A wiring structure is connected to the midpoint of the first trace and is used to transmit the control signal to the first trace.

[0017] In some alternative embodiments, the number of the first traces is multiple and they are spaced apart along a first direction, and the connection structure includes: At least one second trace extends along the first direction, and for two adjacent first traces in the first direction, one end of the second trace is connected to the midpoint of one of the first traces and the other end is connected to the midpoint of the other first trace. The third trace connects to the midpoint of the second trace and is used to transmit the control signal to the second trace.

[0018] In some alternative implementations, the driver module further includes: Multiple first return traces extend along the first direction and are spaced apart in the first direction, and correspond to the multiple first traces. For two adjacent transistor devices in the first direction, one end of the first return trace is connected to the first electrode of one of the transistor devices, and the other end is connected to the first electrode of the other transistor device. The first return traces overlap with the orthographic projection portion of the corresponding first traces on the substrate. At least one second return trace, corresponding to the at least one second trace, extends along the first direction. For two adjacent first return traces in the first direction, one end of the second return trace is connected to the midpoint of one first return trace, and the other end is connected to the midpoint of the other first return trace. The second return trace overlaps with the orthographic projection portion of the corresponding second trace on the substrate. The third return trace has one end connected to the midpoint of the second return trace and the other end connected to the driver; the third return trace overlaps with the orthographic projection of the third trace on the substrate.

[0019] Compared with related technologies, the driving circuit, driving component and driving module of this application have multiple filter circuits corresponding to multiple transistor devices one by one. Each filter circuit includes a capacitor and a first resistor connected in series. Each filter circuit is connected between the gate and the first electrode of the corresponding transistor device. The capacitor in the filter circuit can introduce a new resonant point to the driving circuit. The first resistor provides damping for the oscillation on the capacitor and consumes the oscillation energy. This setting is beneficial to eliminating false triggering oscillation.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0022] Figure 1 This is a schematic diagram of the driving circuit according to an embodiment of this application.

[0023] Figure 2 This is a schematic diagram of the driving component according to an embodiment of this application.

[0024] Figure 3This is a schematic diagram of the first, second, and third traces in an embodiment of this application.

[0025] Figure 4 This is a schematic diagram of the first return trace, the second return trace, and the third return trace according to an embodiment of this application.

[0026] Figure 5 for Figure 3 and Figure 4 A schematic diagram of the stacked layers.

[0027] Reference numerals: 1. Driver; 2. Filter circuit; 3. First trace; 4. Second trace; 5. Third trace; 6. First return trace; 7. Second return trace; 8. Third return trace; T1. Transistor device; C1. Capacitor; R1. First resistor; R2. Second resistor; R3. Third resistor; R4. Turn-on resistor; R5. Turn-off resistor; GateS. Control signal. Detailed Implementation

[0028] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0029] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0030] In related technologies, in practical parallel applications, the parameter dispersion of each parallel power gallium nitride switch (e.g., GaN-HEMT) (such as differences in Qg - total gate charge, Ciss - input capacitance, Rds_on - on-resistance, Vth - threshold voltage, etc.) and the existence of parasitic parameters in the drive circuit (such as stray inductance) make ensuring the synchronicity of the switching action of each parallel transistor and the uniformity of current distribution a key challenge in designing the drive circuit. Moreover, the PCB trace length and characteristics in the drive circuit of each parallel transistor device cannot be exactly the same, which causes differences in parasitic inductance. Combined with the differences in device characteristics, transistor devices in parallel applications are particularly prone to false-triggering oscillation.

[0031] According to the applicant's analysis, this phenomenon can be attributed to two reasons: First, compared with traditional IGBTs or MOSFETs, enhancement-mode GaN HEMTs typically have a lower gate threshold voltage (Vth). Second, the high-speed switching capability of GaN HEMTs generates significant switching noise.

[0032] To address the aforementioned problems, this application discloses a driving circuit. For example... Figure 1 As shown, the driving circuit may include: a plurality of transistor devices T1 connected in parallel, the gates of the plurality of transistor devices T1 being used to receive control signals GateS; a plurality of filter circuits 2, corresponding one-to-one with the plurality of transistor devices T1, each filter circuit 2 including a capacitor C1 and a first resistor R1 connected in series, each filter circuit 2 being connected between the gate and the first electrode of the corresponding transistor device T1.

[0033] In the driving circuit of this application, multiple filter circuits 2 correspond one-to-one with multiple transistor devices T1. Each filter circuit 2 includes a capacitor C1 and a first resistor R1 connected in series. Each filter circuit 2 is connected between the gate and the first electrode of the corresponding transistor device T1. The capacitor C1 in the filter circuit 2 can introduce a new resonant point to the driving circuit. The first resistor R1 provides damping for the oscillation on the capacitor C1 and consumes the oscillation energy. This arrangement is beneficial to eliminating false triggering oscillation.

[0034] The driving circuit of the embodiments of this application will be described in detail below: The aforementioned transistor device T1 is preferably a power gallium nitride (GaN) switch. The power GaN switch can employ a high electron mobility transistor (HEMT) structure, comprising a stacked substrate, a buffer layer, a GaN channel layer, and an AlGaN barrier layer. The substrate serves as the mechanical support for the device, and its material includes sapphire, silicon carbide (SiC), or silicon. Silicon substrates are advantageous for cost reduction, while SiC substrates offer better thermal conductivity and electrical performance. The buffer layer, grown on the substrate, primarily reduces the lattice mismatch between the substrate and the upper layers, minimizing defects and providing a more stable foundation for subsequent epitaxial growth. The GaN channel layer is a high-quality GaN layer with high electron mobility, providing a low-resistance channel for electron transport. The AlGaN barrier layer is located above the GaN channel layer, forming a heterojunction with GaN. Due to the piezoelectric and spontaneous polarization effects generated when the two materials are bonded, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface. The 2DEG is crucial for the high-efficiency conduction of the power GaN switch. This power gallium nitride switch may also include a gate, a source, and a drain. The gate, which can be made of a metallic material, controls the conduction and cutoff of the two-dimensional electron gas in the channel, thereby realizing the switching function. The source and drain can be located in the metal contact region on the AlGaN barrier layer, serving as the current input and output ports, forming ohmic contacts with the two-dimensional electron gas in the channel to ensure efficient current injection and outflow.

[0035] The number of transistor devices T1 is multiple. The characteristics of different transistor devices can be the same or different. Each transistor device T1 includes a gate, a first terminal, and a second terminal. The first terminal can be the source, and the second terminal can be the drain; or, the first terminal can be the drain, and the second terminal can be the source. Multiple transistor devices T1 connected in parallel means that the first terminals of multiple transistor devices T1 are interconnected, and the second terminals of multiple transistor devices T1 are interconnected. Furthermore, the gates of multiple transistor devices T1 are used to jointly receive the same control signal GateS from driver 1. The first terminal of each transistor device T1 can be connected to the GND terminal of driver 1 to receive the Gate-GND signal. The filter circuit 2 can be a passive filter circuit, which may include a capacitor C1 and a first resistor R1. The type of capacitor C1 can be, but is not limited to, a ceramic capacitor, a film capacitor, etc. The first resistor R1 is connected in series with the capacitor C1. The number of filter circuits 2 is consistent with the number of transistor devices T1, and they correspond one-to-one. Each filter circuit 2 is connected between the gate and the first electrode of the corresponding transistor device T1. Specifically, one end (one plate) of the capacitor C1 is connected to the gate of its corresponding transistor device T1, the other plate of the capacitor C1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the first electrode of the corresponding transistor device T1.

[0036] The capacitance of capacitor C1 can be 1nF-2.2nF. This setting ensures that the Vgs voltage (gate-source voltage) of transistor T1 is not affected by noise, and that the Miller spike on the Vgs voltage does not exceed the threshold voltage Vth of transistor T1. The main functions of capacitor C1 include: filtering out interference from various noises on the power board on the gate voltage signal of transistor T1, suppressing high-frequency ringing; and absorbing Miller current. In bridge circuit applications, high switching noise (dV / dt) coupled current through Cgd (parasitic capacitance between the gate and drain) may raise the gate voltage, even exceeding the threshold voltage Vth, leading to unexpected conduction. The larger the capacitor, the more significant the effect of suppressing Miller spikes, but it will also reduce the switching speed and increase the switching losses of the transistor. Most importantly, this capacitor introduces a new resonant point to the entire drive circuit network. In both actual measurements and simulations of parallel transistor T1, the value of the capacitor has a decisive influence on whether false triggering oscillations occur.

[0037] The resistance of the first resistor R1 can be 2Ω-10Ω. The main function of the first resistor R1 is to provide damping for the oscillation on capacitor C1, consume oscillation energy, and especially help eliminate false triggering oscillations, while maintaining the suppression effect of Cgs (parasitic capacitance between the gate and drain) on Miller spikes.

[0038] The driving circuit in this embodiment further includes multiple second resistors R2. Each second resistor R2 corresponds to a transistor device T1 and is connected between the gate of the transistor device T1 and its first electrode (source). The second resistor R2 can be called a gate pull-down resistor or a turn-off resistor. In an optional embodiment, the second resistor R2 is connected in parallel with the filter circuit 2 between the gate and the first electrode (source). The main functions of the first resistor are: first, to provide a discharge path for the gate charge of the transistor device T1, preventing accidental increase in gate voltage due to charge accumulation that could lead to false turn-on; and second, to pull the gate down to the source potential as close as possible when the transistor device T1 is turned off, maintaining reliable turn-off of the transistor device T1. The resistance of the second resistor R2 can be approximately 15KΩ, for example, 15KΩ.

[0039] The driving circuit of this application also includes multiple third resistors R3. Each third resistor R3 corresponds to a transistor device T1. The third resistor R3 is connected to the control signal GateS path: its first end is connected to the gate of the corresponding transistor device T1, and its second end is used to receive the aforementioned control signal GateS. This resistor is usually called a gate series resistor or a driving resistor. The third resistor R3 can independently control the switching speed of the corresponding transistor device T1. Theoretically, the difference in the switching process of different transistor devices T1 due to differences in Qg (total gate charge) or Ciss (input capacitance) can be slightly compensated by fine-tuning the resistance value; most importantly, it can form damping in the parasitic loop, which helps to suppress oscillation. The resistance of the second resistor R2 can be about 10Ω, for example, 10Ω, to ensure the synchronous turn-on timing of the multiple transistor devices T1 connected in parallel.

[0040] In one embodiment, the first terminal of the third resistor R3 is connected to the filter circuit 2, and the second terminal is used to receive the control signal GateS. In another embodiment, the second terminal of the third resistor R3 is connected to the filter circuit 2 and is used to receive the control signal GateS. In yet another embodiment, the first terminal of the third resistor R3 is connected to the second resistor R2. In still another embodiment, the second terminal of the third resistor R3 is connected to the second resistor R2 and is used to receive the control signal GateS.

[0041] In an alternative embodiment that includes a second resistor R2 and a third resistor R3, in order to optimize performance (e.g., to ensure that the pull-down effect is stronger than the shunting effect of the filter circuit 2), the resistance value of the second resistor R2 can be set to be greater than the resistance value of the first resistor R1, and / or, the resistance value of the second resistor R2 can be set to be greater than the resistance value of the third resistor R3.

[0042] The aforementioned control signal GateS may include a first-level signal and a second-level signal. One of these signals is high, and the other is low. For example, the first-level signal is high, and the second-level signal is low. The first-level signal can be output from the SRC terminal of driver 1, and the second-level signal can be output from the SNK terminal of driver 1. In an optional embodiment, the drive circuit may further include an on-resistor R4 and a off-resistor R5. One end of the on-resistor R4 is connected to the second terminal of each of the third resistors R3, and the other end receives the aforementioned first-level signal. One end of the off-resistor R5 is connected to the second terminal of each of the third resistors R3, and the other end receives the second-level signal. This structure allows for independent adjustment of the on- and off-resistance speeds. In a more preferred embodiment, the resistance value of the on-resistor R4 is designed to be greater than the resistance value of the off-resistor R5 to achieve a faster off-resistance speed (reducing off-resistance losses) and a relatively slower on-resistance speed.

[0043] This application also provides a driver component, such as Figure 2 As shown, the driving assembly includes two driving circuits of either of the aforementioned types. For these two driving circuits, a plurality of transistor devices T1 in one driving circuit are connected in series with a plurality of transistor devices T1 in the other driving circuit, each corresponding to a different transistor device T1. One of the two driving circuits constitutes the upper bridge arm driving circuit, and the other constitutes the lower bridge arm driving circuit. The first terminal of each transistor device T1 in the upper bridge arm driving circuit can be connected to the SW signal terminal of driver 1. The first terminal of each transistor device T1 in the lower bridge arm driving circuit can be connected to the GND terminal of driver 1 to receive the Gate-GND signal. For distinction, the control signal received by the gate of each transistor device in the upper bridge arm driving circuit is GateS1, and the control signal received by the gate of each transistor device in the lower bridge arm driving circuit is GateS2.

[0044] This application also provides a driving module, the core of which is to integrate the aforementioned driving circuit or driving component onto a hardware platform. The driving module may include a substrate and a driver 1. The aforementioned driving circuit or driving component may be disposed on the substrate, and the driver 1 is used to provide the aforementioned control signal GateS.

[0045] The substrate serves as a platform for mechanical support and electrical interconnection, and the aforementioned drive circuits or drive components are mounted (e.g., soldered or surface-mounted) on this substrate. The substrate can be a printed circuit board (PCB), a direct copper-clad ceramic substrate (DBC), an active metal brazed ceramic substrate (AMB), or an insulated metal substrate (IMS), etc. The driver 1 is disposed on or connected to the substrate, and its main function is to generate and output the control signal GateS for driving the transistor device T1.

[0046] To improve the signal transmission balance between the gates of multiple parallel transistor devices T1 (reducing the signal delay difference caused by differences in trace length), such as Figure 3 As shown, the driving module also includes at least one first trace 3 extending along a first direction X. The aforementioned parallel-connected transistor devices T1 can be distributed on the substrate along the first direction X. For two adjacent transistor devices T1 in the arrangement direction, one end of the first trace 3 is connected to the gate of one of the transistor devices T1, and the other end is connected to the gate of the adjacent transistor device T1. In this way, the first trace 3 electrically connects adjacent gates. In addition, there is a wiring structure (including a second trace 4 and a third trace 5) connected to the midpoint (or its equivalent electrical midpoint) of the first trace 3, and responsible for transmitting and injecting the control signal GateS from the driver 1 into this midpoint of the first trace 3. This "midpoint drive" structure helps to transmit the control signal GateS simultaneously and equidistantly to the transistors at both ends of the trace, reducing signal transmission delay differences.

[0047] In more complex layouts, multiple first traces 3 can be configured. These first traces 3 are also spaced apart along the first direction. To further optimize signal equalization, the wiring structure can employ at least one second trace 4. This second trace 4 also extends along the first direction X. For two adjacent first traces 3 in the arrangement direction, one end of the second trace 4 is connected to the midpoint (or its equivalent electrical midpoint) of one of the first traces 3, and the other end is connected to the midpoint of the adjacent first trace 3. The wiring structure can also include a third trace 5. The third trace 5 is connected to the midpoint of the second trace 4 and is used to transmit the control signal GateS to the second trace 4. This hierarchical midpoint-driven structure can effectively achieve uniform distribution of the control signal GateS in large-scale parallel layouts.

[0048] like Figure 4 and Figure 5As shown, the driving module of this application may further include a plurality of first return traces 6, at least one second return trace 7, and a third return trace 8. The plurality of first return traces 6 extend along a first direction X and are spaced apart in the first direction X, and correspond to a plurality of first traces 3. For two adjacent transistor devices T1 in the first direction X, one end of the first return trace 6 is connected to the first electrode of one transistor device T1, and the other end is connected to the first electrode of the other transistor device T1; the first return trace 6 and the corresponding first trace 3 overlap on the orthographic projection portion on the substrate. At least one second return trace 7 corresponds to at least one second trace 4. The second return trace 7 extends along a first direction X. For two adjacent first return traces 6 in the first direction X, one end of the second return trace 7 is connected to the midpoint of one first return trace 6, and the other end is connected to the midpoint of the other first return trace 6. The second return trace 7 overlaps with the orthographic projection portion of the corresponding second trace 4 on the substrate. One end of the third return trace 8 is connected to the midpoint of the second return trace 7, and the other end is connected to the driver 1. The third return trace 8 overlaps with the orthographic projection portion of the third trace 5 on the substrate.

[0049] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A driving circuit, characterized in that, include: Multiple transistor devices connected in parallel, wherein the gates of the multiple transistor devices are used to receive control signals; Multiple filter circuits correspond one-to-one with multiple transistor devices. Each filter circuit includes a capacitor and a first resistor connected in series. Each filter circuit is connected between the gate and the first electrode of the corresponding transistor device.

2. The driving circuit according to claim 1, characterized in that, The driving circuit also includes: A plurality of second resistors are provided, each corresponding to one of the plurality of transistor devices, and each second resistor is connected between the gate and the first electrode of the corresponding transistor device.

3. The driving circuit according to claim 1 or 2, characterized in that, The driving circuit also includes: Multiple third resistors correspond one-to-one with multiple transistor devices. The first end of each third resistor is connected to the gate of the corresponding transistor device, and the second end is used to receive the control signal.

4. The driving circuit according to claim 3, characterized in that, The resistance of the second resistor is greater than the resistance of the first resistor, and / or the resistance of the second resistor is greater than the resistance of the third resistor.

5. The driving circuit according to claim 3, characterized in that, The first or second end of the third resistor is connected to the filter circuit.

6. The driving circuit according to claim 3, characterized in that, The first or second end of the third resistor is connected to the second resistor.

7. The driving circuit according to claim 3, characterized in that, The control signal includes a first-level signal and a second-level signal, and the driving circuit further includes: An on-resistor is connected at one end to the second end of the plurality of third resistors, and at the other end is used to receive the first level signal. The shut-off resistor has one end connected to the second end of the plurality of third resistors, and the other end is used to receive the second level signal.

8. The driving circuit according to claim 7, characterized in that, The resistance of the turn-on resistor is greater than the resistance of the turn-off resistor.

9. The driving circuit according to claim 1, characterized in that, One plate of the capacitor is connected to the gate of the corresponding transistor device, and the first resistor is connected to the first electrode of the corresponding transistor device.

10. A driving component, characterized in that, The driving component includes two driving circuits according to any one of claims 1-9, wherein a plurality of transistor devices in one driving circuit are connected in series with a plurality of transistor devices in the other driving circuit in a one-to-one correspondence.

11. A driving module, characterized in that, include: A substrate, wherein the driving circuit according to any one of claims 1-9 or the driving component according to claim 10 is disposed on the substrate; A driver for outputting the control signals.

12. The driving module according to claim 11, characterized in that, The multiple transistor devices connected in parallel are distributed along a first direction, which is parallel to the substrate; The driver module also includes: At least one first trace extends along the first direction, wherein for two adjacent transistor devices in the first direction, one end of the first trace is connected to the gate of one transistor device and the other end is connected to the gate of the other transistor device. A wiring structure is connected to the midpoint of the first trace and is used to transmit the control signal to the first trace.

13. The driving module according to claim 12, characterized in that, The number of the first traces is multiple and they are spaced apart along a first direction. The connection structure includes: At least one second trace extends along the first direction, and for two adjacent first traces in the first direction, one end of the second trace is connected to the midpoint of one of the first traces and the other end is connected to the midpoint of the other first trace. The third trace connects to the midpoint of the second trace and is used to transmit the control signal to the second trace.

14. The driving module according to claim 13, characterized in that, The driver module also includes: Multiple first return traces extend along the first direction and are spaced apart in the first direction, and correspond to the multiple first traces. For two adjacent transistor devices in the first direction, one end of the first return trace is connected to the first electrode of one of the transistor devices, and the other end is connected to the first electrode of the other transistor device. The first return traces overlap with the orthographic projection portion of the corresponding first traces on the substrate. At least one second return trace, corresponding to the at least one second trace, extends along the first direction. For two adjacent first return traces in the first direction, one end of the second return trace is connected to the midpoint of one first return trace, and the other end is connected to the midpoint of the other first return trace. The second return trace overlaps with the orthographic projection portion of the corresponding second trace on the substrate. The third return trace has one end connected to the midpoint of the second return trace and the other end connected to the driver; the third return trace overlaps with the orthographic projection of the third trace on the substrate.

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