Semiconductor device and preparation method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and a memory system. The semiconductor device comprises a first channel structure, a first bit line structure, an interconnection structure, a second bit line structure and a second channel structure which are sequentially arranged in the first direction, the first channel structure extends in the first direction, the second channel structure extends in the first direction, the first bit line structure extends in the second direction, and the interconnection structure extends in the second direction. The second bit line structure extends in the second direction, and the interconnection structure is connected with the first bit line structure and the second bit line structure; wherein the interconnection structure comprises an interconnection channel extending in the first direction, the size of the end, close to the first bit line structure, of the interconnection channel is smaller than the size of the end, close to the second bit line structure, of the interconnection channel, and the first direction intersects with the second direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for fabricating a semiconductor device. Background Technology

[0002] Semiconductor devices can include memory devices used to implement storage functions, such as dynamic random access memory (DRAM). DRAM is widely used in the memory of electronic devices such as computers and mobile phones due to its simple structure, large capacity, high density, low power consumption, and high speed.

[0003] As the integration level of semiconductor devices continues to increase, the manufacturing difficulty of semiconductor devices increases, and the miniaturization performance decreases. Summary of the Invention

[0004] In a first aspect, some embodiments of this application provide a semiconductor device. The semiconductor device includes a first channel structure, a first bit line structure, an interconnect structure, a second bit line structure, and a second channel structure arranged sequentially in a first direction. The first channel structure extends along the first direction, the second channel structure extends along the first direction, the first bit line structure extends in a second direction, the second bit line structure extends in the second direction, and the interconnect structure is connected to the first bit line structure and the second bit line structure. The interconnect structure includes an interconnect channel extending along the first direction, the end dimension of the interconnect channel near the first bit line structure being smaller than the end dimension near the second bit line structure, and the first direction intersects the second direction.

[0005] In an exemplary embodiment, the end dimension of the interconnect channel is the dimension in a plane perpendicular to the first direction.

[0006] In an exemplary embodiment, the interconnect channel decreases in size along the first direction in a plane perpendicular to the first direction.

[0007] In an exemplary embodiment, each interconnect channel decreases in size along a first direction in a plane perpendicular to the first direction.

[0008] In an exemplary embodiment, the interconnect structure further includes interconnect lines extending along a second direction and / or a third direction, with interconnect channels and interconnect lines alternately arranged in the first direction, wherein the first direction, the second direction, and the third direction intersect each other.

[0009] In an exemplary embodiment, the first bit line structure includes a first bit line portion and a second bit line portion arranged in a second direction, the second bit line structure includes a third bit line portion and a fourth bit line portion arranged in the second direction, and the first bit line portion and the third bit line portion are stacked in the first direction; the interconnection structure includes a first interconnection structure and a second interconnection structure, the first interconnection structure is connected to the first bit line portion and the third bit line portion respectively, and the second interconnection structure is connected to the second bit line portion and the fourth bit line portion respectively.

[0010] In an exemplary embodiment, the first interconnect structure is connected to the end of the first bit line portion that is away from the second bit line portion and the end of the third bit line portion that is adjacent to it in the third direction that is away from the fourth bit line portion; the second interconnect structure is connected to the end of the second bit line portion that is away from the first bit line portion and the end of the fourth bit line portion that is adjacent to it in the third direction that is away from the third bit line portion; wherein, the first direction, the second direction and the third direction intersect each other.

[0011] In an exemplary embodiment, the first bit line portion, the second bit line portion, the third bit line portion, and the fourth bit line portion all extend continuously along the second direction.

[0012] In an exemplary embodiment, the first interconnect structure is connected to the end of the first bit line portion that is away from the second bit line portion and the end of the third bit line portion that is aligned with it in the first direction that is away from the fourth bit line portion; the second interconnect structure is connected to the end of the second bit line portion that is away from the first bit line portion and the end of the fourth bit line portion that is aligned with it in the first direction that is away from the third bit line portion.

[0013] In an exemplary embodiment, the first bit line portion includes a plurality of first bit line sub-portions arranged in the second direction, and the third bit line portion includes a plurality of third bit line sub-portions arranged in the second direction; the interconnect structure further includes a third interconnect structure, which is connected to the first bit line sub-portion and the third bit line sub-portion adjacent to it in the second direction, respectively; the second bit line portion includes a plurality of second bit line sub-portions arranged in the second direction, and the fourth bit line portion includes a plurality of fourth bit line sub-portions arranged in the second direction; the interconnect structure further includes a fourth interconnect structure, which is connected to the second bit line sub-portion and the fourth bit line sub-portion adjacent to it in the second direction, respectively.

[0014] In an exemplary embodiment, the first bit portion in the first bit structure adjacent to the third-upward first bit structure and the third bit portion in the second bit structure are connected to the first sensing amplifier, and the second bit portion in the first bit structure adjacent to the third-upward second bit structure and the fourth bit portion in the second bit structure are connected to the second sensing amplifier, wherein the first direction, the second direction and the third direction intersect each other.

[0015] In an exemplary embodiment, the semiconductor device further includes a first capacitor and a second capacitor. The first capacitor is located on the side of the first channel structure opposite to the first bit line structure; the second capacitor is located on the side of the second channel structure opposite to the second bit line structure.

[0016] In an exemplary embodiment, the first capacitor includes a first conductive portion, a first insulating layer, and a first conductive layer. The first conductive portion extends along a first direction and is connected to a first channel structure; the first insulating layer covers the first conductive portion; the first conductive layer covers the first insulating layer. The second capacitor includes a second conductive portion, a second insulating layer, and a second conductive layer. The second conductive portion extends along a first direction and is connected to a second channel structure; the second insulating layer covers the second conductive portion; the second conductive layer covers the second insulating layer.

[0017] In an exemplary embodiment, the first conductive layer connected to the first bit line portion and the second bit line portion is an integral structure, and the second conductive layer connected to the third bit line portion and the fourth bit line portion is an integral structure.

[0018] In an exemplary embodiment, the first conductive layer connected to the first bit line portion and the second bit line portion respectively is a separate structure, and the second conductive layer connected to the third bit line portion and the fourth bit line portion respectively is a separate structure.

[0019] In an exemplary embodiment, the first bit line portion and the second bit line portion are connected to the first conductive layer through a first channel structure, a first conductive portion and a first insulating layer, and the third bit line portion and the fourth bit line portion are connected to the second conductive layer through a second channel structure, a second conductive portion and a second insulating layer.

[0020] In an exemplary embodiment, the first channel structure includes a first main body, a first extension, and a second extension. The first main body extends along a first direction; the first extension is located at the end of the first main body away from the first bit structure; the second extension is located at the end of the first main body near the first bit structure, wherein, in a second direction, the first extension and the second extension extend in opposite directions. The second channel structure includes a second main body, a third extension, and a fourth extension. The second main body extends along the first direction; the third extension is located at the end of the second main body near the second bit structure; the fourth extension is located at the end of the second main body away from the second bit structure, wherein, in a second direction, the third extension and the fourth extension extend in opposite directions.

[0021] In an exemplary embodiment, two first extensions in adjacent first channel structures in the second direction have opposite extending directions; two fourth extensions in adjacent second channel structures in the second direction have opposite extending directions.

[0022] In an exemplary embodiment, in adjacent first main body portions in the second direction, the distance between the ends closer to the first bit structure is greater than the distance between the ends away from the first bit structure; in adjacent second main body portions in the second direction, the distance between the ends closer to the second bit structure is less than the distance between the ends away from the second bit structure.

[0023] In an exemplary embodiment, the materials of the first channel structure and the second channel structure include metal oxide semiconductor materials. For example, the metal oxide semiconductor material includes indium gallium zinc oxide.

[0024] In an exemplary embodiment, the first main body portion has a size of 3nm to 10nm in the second direction, and the second main body portion has a size of 3nm to 10nm in the second direction.

[0025] In an exemplary embodiment, the size of the first main body in the third direction is greater than the size of the first main body in the second direction, and the size of the second main body in the third direction is greater than the size of the second main body in the second direction, wherein the first direction, the second direction, and the third direction intersect each other.

[0026] In an exemplary embodiment, the semiconductor device further includes a first gate structure, a first gate dielectric layer, a second gate structure, and a second gate dielectric layer. The first gate structure is located on one side of the first channel structure in a second direction and extends along a third direction; the first gate dielectric layer is located between the first channel structure and the first gate structure; the second gate structure is located on one side of the second channel structure in a second direction and extends along a third direction; the second gate dielectric layer is located between the second gate structure and the second channel structure; wherein the first direction, the second direction, and the third direction intersect each other.

[0027] In an exemplary embodiment, the first gate structure includes a first adhesive layer and a first metal structure that are attached to each other, the first adhesive layer being located on one side of the first metal structure in a second direction, and the first metal structure being located on the side of the first metal structure that is away from the first bit line structure in the first direction; the second gate structure includes a second adhesive layer and a second metal structure that are attached to each other, the second adhesive layer being located on one side of the second metal structure in a second direction, and the second metal structure being located on the side of the second metal structure that is close to the second bit line structure in the first direction.

[0028] In an exemplary embodiment, the semiconductor device further includes a first isolation structure, a second isolation structure, a third isolation structure, and a fourth isolation structure. The first isolation structure is located between adjacent first channel structures in a second direction and extends along a third direction; the second isolation structure is located between adjacent first gate structures in a second direction and extends along a third direction, wherein the first isolation structure and the second isolation structure are alternately arranged in the second direction; the third isolation structure is located between adjacent second channel structures in a second direction and extends along a third direction; the fourth isolation structure is located between adjacent second gate structures in a second direction and extends along a third direction, wherein the third isolation structure and the fourth isolation structure are alternately arranged in the second direction.

[0029] In an exemplary embodiment, the first isolation structure includes a first conductive structure and a first dielectric layer. The first conductive structure extends in a third direction; the first dielectric layer is located between the first conductive structure and the first channel structure. The third isolation structure includes a second conductive structure and a second dielectric layer. The second conductive structure extends in a third direction; the second dielectric layer is located between the second conductive structure and the second channel structure.

[0030] In an exemplary embodiment, the first isolation structure and the third isolation structure are at least partially aligned in a first direction.

[0031] In an exemplary embodiment, the semiconductor device further includes a peripheral circuit structure. The peripheral circuit structure is located on the side of the first capacitor opposite to the first bit line structure, or on the side of the second capacitor opposite to the second bit line structure.

[0032] In an exemplary embodiment, the semiconductor device further includes a first connection structure and a second connection structure. The first connection structure extends along a first direction and is connected to an end of a first bit line portion or a third bit line portion in a second direction; the second connection structure extends along the first direction and is connected to an end of a second bit line portion or a fourth bit line portion in a second direction.

[0033] In an exemplary embodiment, the first trench structure and the second trench structure are formed by a thin film deposition process.

[0034] Secondly, some embodiments of this application provide a memory system. The memory system includes a memory and a controller. The memory includes semiconductor devices as mentioned in any of the embodiments described above. The controller is coupled to the memory and is used to control the storage of data.

[0035] Thirdly, some embodiments of this application provide a method for fabricating a semiconductor device. The method includes: forming a first channel structure extending along a first direction; sequentially forming a first bit line structure, an interconnect structure, and a second bit line structure on one side of the first channel structure in the first direction, wherein the first bit line structure extends in a second direction, and the second bit line structure extends in a second direction; forming a second channel structure extending along the first direction on the side of the second bit line structure opposite to the first channel structure; wherein the first direction intersects the second direction.

[0036] In an exemplary embodiment, forming a first bit line structure, an interconnect structure, and a second bit line structure sequentially on one side of the first channel structure in a first direction includes forming the first bit line structure, the interconnect structure, and the second bit line structure by a thin film deposition process.

[0037] In an exemplary embodiment, forming an interconnect structure on one side of the first channel structure in a first direction includes: alternately forming interconnect channels and interconnect lines, wherein the interconnect lines extend along a second direction and / or a third direction, and the interconnect channels are connected to a first line structure and a second line structure; wherein the first direction, the second direction, and the third direction intersect each other.

[0038] In an exemplary embodiment, the interconnect structure includes an interconnect channel extending along a first direction, wherein the end dimension of the interconnect channel near the first bit structure is smaller than the end dimension near the second bit structure.

[0039] In an exemplary embodiment, the fabrication method further includes: forming at least a portion of a first capacitor on the side of the first channel structure opposite to the first bit line structure; and forming a second capacitor on the side of the second channel structure opposite to the second bit line structure.

[0040] In an exemplary embodiment, forming at least a portion of a first capacitor on the side of the first channel structure away from the first bit line structure includes: forming a first conductive portion extending in a first direction, wherein the first conductive portion is connected to the first channel structure; forming a first insulating layer covering the first conductive portion; and forming a first conductive layer covering the first insulating layer. Forming a second capacitor on the side of the second channel structure away from the second bit line structure includes: forming a second conductive portion extending in a first direction, wherein the second conductive portion is connected to the second channel structure; forming a second insulating layer covering the second conductive portion; and forming a second conductive layer covering the second insulating layer.

[0041] In an exemplary embodiment, after the second conductive layer is formed, the first insulating layer and the first conductive layer are formed sequentially. Attached Figure Description

[0042] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0043] Figure 1 This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application;

[0044] Figure 2 This is a cross-sectional schematic diagram of the first channel structure, the first bit line structure, the second channel structure, and the second bit line structure in the semiconductor device provided in the embodiments of this application;

[0045] Figures 3 to 5 This is a three-dimensional schematic diagram of the first bit line structure, interconnect structure and second bit line structure in a semiconductor device provided in some embodiments of this application;

[0046] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application;

[0047] Figure 7 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application;

[0048] Figures 8A to 8G This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application during the fabrication process;

[0049] Figure 9 This is a schematic block diagram of a system with a memory system provided in the embodiments of this application; and

[0050] Figure 10A and Figure 10B This is a schematic block diagram of a memory system provided in an embodiment of this application. Detailed Implementation

[0051] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first channel structure discussed herein may also be referred to as the second channel structure, and the first bit line structure may also be referred to as the second bit line structure, and vice versa.

[0053] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0054] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0055] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0056] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0057] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0058] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0059] Some embodiments of this application provide a semiconductor device. Figure 1 This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application. Figure 2 This is a cross-sectional schematic diagram of the first channel structure, the first bit line structure, the second bit line structure, and the second channel structure in the semiconductor device provided in the embodiments of this application.

[0060] It should be noted that the D1 direction (corresponding to the first direction), D2 direction (corresponding to the second direction), and D3 direction (corresponding to the third direction) in the various figures illustrate the spatial relationship of the components in the semiconductor device. For example, the D1 direction may be the extension direction of the first channel structure (or the second channel structure), and the D2 and D3 directions may be two directions that intersect (e.g., are perpendicular to each other) on planes that intersect (e.g., are perpendicular to) the aforementioned extension directions. For example, the D2 direction may be the extension direction of the first bit line structure (or the second bit line structure). The same concepts will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0061] like Figure 1 As shown, the semiconductor device 100 may include a first channel structure 111, a first bit line structure 112, an interconnect structure 113, a second bit line structure 114, and a second channel structure 115 arranged sequentially in the D1 direction. The first channel structure 111 extends in the D1 direction, and the second channel structure 115 extends in the D1 direction. The first bit line structure 112 extends in the D2 direction, and the second bit line structure 114 extends in the D2 direction. The interconnect structure 113 is connected to the first bit line structure 112 and the second bit line structure 114. The interconnect structure 113 includes an interconnect channel 1135 extending in the D1 direction. The end dimension of the interconnect channel 1135 near the first bit line structure 112 is smaller than its end dimension near the second bit line structure 114.

[0062] In the semiconductor device 100, the first channel structure 111, the first bit line structure 112, the second bit line structure 114, and the second channel structure 115 are arranged in the D1 direction, which helps to improve the integration density of the semiconductor device 100 and save planar area. In addition, the interconnect channel 1135 in the interconnect structure 113 has a smaller end size near the first bit line structure 112 and a larger end size near the second bit line structure 114. This can be achieved by sequentially forming the first bit line structure 112, the interconnect structure 113, and the second bit line structure 114. Compared with alignment bonding to form the interconnect structure, this can reduce the structural complexity of the interconnect structure 113, improve the connection reliability of the interconnect structure 113, and improve the yield of the semiconductor device 100.

[0063] The following further combines Figure 2 The components of the semiconductor device 100 are described.

[0064] In some embodiments, the first channel structure 111 is larger in dimension in direction D1 than in dimension in direction D2 and larger in dimension in direction D3. Exemplarily, the first channel structure 111 may include a first body portion 1111, a first extension portion 1112, and a second extension portion 1113. The first body portion 1111 may extend along direction D1. The first extension portion 1112 may be located at the end of the first body portion 1111 opposite to the first line structure 112. The second extension portion 1113 may be located at the end of the first body portion 1111 near the first line structure 112. In direction D2, the first extension portion 1112 and the second extension portion 1113 extend in opposite directions. For example, viewed from direction D3, the first channel structure 111 may be approximately “Z” shaped. As another example, the extension dimensions of the first extension portion 1112 and the second extension portion 1113 in direction D2 may be the same or different; this application does not impose specific limitations in this regard.

[0065] In some embodiments, the second extension 1113 may be connected (e.g., in contact) to the first line structure 112, which helps to increase the connection area between the first channel structure 111 and the first line structure 112 and improve their electrical connection performance.

[0066] In some embodiments, the first main body portion 1111 has a larger dimension in the D1 direction than its dimension in the D2 direction and also larger dimension in the D3 direction. For example, the dimension of the first main body portion 1111 in the D2 direction may be 3 mm to 10 mm. Optionally, the dimensions of the first main body portion 1111 in the D2 direction, the first extension portion 1112 in the D1 direction, and the second extension portion 1113 in the D1 direction are substantially the same.

[0067] In some embodiments, the first main body portion 1111 has a larger dimension in the D3 direction than its dimension in the D2 direction. For example, the dimensions of the first main body portion 1111 in the D3 direction, the first extension portion 1112 in the D3 direction, and the second extension portion 1113 in the D3 direction are substantially the same.

[0068] In some embodiments, there may be multiple first channel structures 111. Multiple first channel structures 111 may be arranged in an array along the D2 and D3 directions. For example, several first channel structures 111 arranged in the D2 direction may be substantially aligned, and several first channel structures 111 arranged in the D3 direction may be substantially aligned.

[0069] In some embodiments, two first extensions 1112 in adjacent first channel structures 111 in the D2 direction may have opposite extending directions. In this case, two second extensions 1113 in adjacent first channel structures 111 in the D2 direction may also have opposite extending directions. For example, adjacent first channel structures 111 in the D2 direction may be approximately mirror-symmetrical.

[0070] In some embodiments, the formation process of the first channel structure 111 may include a thin-film deposition process. For example, the first main body 1111, the first extension 1112, and the second extension 1113 may be formed by the same thin-film deposition process. Forming the first channel structure 111 by a thin-film deposition process allows the first main body 1111 to have a smaller dimension in the D2 direction, which is beneficial for improving structural integration and miniaturization performance, reducing the need for high-performance manufacturing equipment, and also reducing manufacturing costs.

[0071] In some embodiments, the material of the first channel structure 111 may include a semiconductor material. For example, the first body portion 1111, the first extension portion 1112, and the second extension portion 1113 may be made of the same semiconductor material. When the three are made of the same material, there is no obvious interface between them, and they can be a single structure. The semiconductor material may include, but is not limited to, silicon (e.g., monocrystalline silicon, polycrystalline silicon, amorphous silicon), germanium silicon, metal oxide semiconductors (e.g., indium gallium zinc oxide), etc. When the semiconductor material is a metal oxide semiconductor, the first channel structure 111 can be formed by a low-temperature thin film deposition process, thereby reducing the thermal budget during its manufacturing process and reducing the impact of thermal stress on other formed components.

[0072] In some embodiments, the second channel structure 115 is larger in the D1 direction than in the D2 direction and larger in the D3 direction. Exemplarily, the second channel structure 115 may include a second body portion 1151, a third extension portion 1152, and a fourth extension portion 1153. The second body portion 1151 may extend along the D1 direction. The third extension portion 1152 may be located at the end of the second body portion 1151 near the second bit line structure 114. The fourth extension portion 1153 may be located at the end of the second body portion 1151 away from the second bit line structure 114. In the D2 direction, the third extension portion 1152 and the fourth extension portion 1153 extend in opposite directions. For example, viewed from the D3 direction, the second channel structure 115 may be approximately "Z"-shaped. As another example, the extension dimensions of the third extension portion 1152 and the fourth extension portion 1153 in the D2 direction may be the same or different; this application does not impose specific limitations in this regard.

[0073] In some embodiments, the third extension 1152 may be connected (e.g., in contact) to the second bit line structure 114, which helps to increase the connection area between the second channel structure 115 and the second bit line structure 114 and improve their electrical connection performance.

[0074] In some embodiments, the second main body portion 1151 may have a larger dimension in the D1 direction than its dimension in the D2 direction and also larger dimension in the D3 direction. For example, the dimension of the second main body portion 1151 in the D2 direction may be 3 mm to 10 mm. Optionally, the dimensions of the second main body portion 1151 in the D2 direction, the third extension portion 1152 in the D1 direction, and the fourth extension portion 1153 in the D1 direction may be substantially the same.

[0075] In some embodiments, the dimension of the second main body portion 1151 in the D3 direction may be larger than its dimension in the D2 direction. For example, the dimensions of the second main body portion 1151 in the D3 direction, the dimensions of the third extension portion 1152 in the D3 direction, and the dimensions of the fourth extension portion 1153 in the D3 direction are substantially the same.

[0076] In some embodiments, there may be multiple second channel structures 115. Multiple second channel structures 115 may be arranged in an array along the D2 and D3 directions. For example, several second channel structures 115 arranged in the D2 direction may be substantially aligned, and several second channel structures 115 arranged in the D3 direction may be substantially aligned.

[0077] In some embodiments, the two fourth extensions 1153 in adjacent second channel structures 115 in the D2 direction may have opposite extending directions. In this case, the two third extensions 1152 in adjacent second channel structures 115 in the D2 direction may also have opposite extending directions. For example, adjacent second channel structures 115 in the D2 direction may be approximately mirror-symmetrical.

[0078] In some embodiments, the formation process of the second channel structure 115 may include a thin-film deposition process. For example, the second main body portion 1151, the third extension portion 1152, and the fourth extension portion 1153 may be formed by the same thin-film deposition process. Forming the second channel structure 115 by a thin-film deposition process allows the second main body portion 1151 to have a smaller dimension in the D2 direction, which is beneficial for improving structural integration and miniaturization performance, reducing the need for high-performance manufacturing equipment, and also reducing manufacturing costs.

[0079] In some embodiments, the material of the second channel structure 115 may include a semiconductor material. For example, the second main body 1151, the third extension 1152, and the fourth extension 1153 may be made of the same semiconductor material. When the three are made of the same material, there is no obvious interface between them, and they can be a single structure. The semiconductor material may include, but is not limited to, silicon (e.g., monocrystalline silicon, polycrystalline silicon, amorphous silicon), germanium silicon, metal oxide semiconductors (e.g., indium gallium zinc oxide), etc. When the semiconductor material is a metal oxide semiconductor, the second channel structure 115 can be formed by a low-temperature thin film deposition process, thereby reducing the thermal budget during its manufacturing process and reducing the impact of thermal stress on other formed components.

[0080] In some embodiments, when there are multiple first channel structures 111 and multiple second channel structures 115, the multiple first channel structures 111 and multiple second channel structures 115 correspond one-to-one. For example, viewed from the D1 direction, the first channel structure 111 and its corresponding second channel structure 115 substantially overlap. As another example, viewed from the D1 direction, the first channel structure 111 and its corresponding second channel structure 115 substantially overlap in the D3 direction and have a gap in the D2 direction. In the above embodiments, the gap between the first channel structure 111 and its corresponding second channel structure 115 in the D2 direction increases the process margin and reduces the process difficulty.

[0081] In some embodiments, the semiconductor device 100 may further include a first gate structure 116, a first gate dielectric layer 117, a second gate structure 118, and a second gate dielectric layer 119. The first gate structure 116 may be located on one side of the first channel structure 111 in the D2 direction and extend along the D3 direction. The first gate dielectric layer 117 may be located between the first channel structure 111 and the first gate structure 116. The second gate structure 118 may be located on one side of the second channel structure 115 in the D2 direction and extend along the D3 direction. The second gate dielectric layer 119 may be located between the second gate structure 118 and the second channel structure 115. In this embodiment, multiple channel structures are "folded" in the D1 direction to form the first channel structure 111 and the second channel structure 115. When the number of channel structures arranged in the D2 direction is the same, the pitch of the "folded" first channel structure 111 and the second channel structure 115 in the D2 direction is increased, which is beneficial to reduce the process difficulty of the first gate structure 116, the first gate dielectric layer 117, the second gate structure 118 and the second gate dielectric layer 119. It is also beneficial to reduce the coupling effect between adjacent first gate structures 116 in the D2 direction and the coupling effect between adjacent second gate structures 118 in the D2 direction.

[0082] In some embodiments, the dimension of the first gate structure 116 in the D3 direction may be larger than its dimension in the D1 direction and may be larger than its dimension in the D2 direction. For example, viewed from the D3 direction, the first gate structure 116 may be located on one side of the first body portion 1111 in the D2 direction and close to the first extension portion 1112. The first gate structure 116 may have a spacing distance from the first first line structure 112 in the D1 direction.

[0083] In some embodiments, the first gate structure 116 may include a first adhesive layer 1161 and a first metal structure 1162 that are bonded to each other. For example, the first metal structure 1162 may be located on one side of the first body portion 1111 in the D2 direction and close to the first extension portion 1112. The dimension of the first metal structure 1162 in the D3 direction may be larger than its dimension in the D1 direction and may be larger than its dimension in the D2 direction. The first adhesive layer 1161 may be located on one side of the first metal structure 1162 in the D2 direction and on the side of the first metal structure 1162 facing away from the first first line structure 112 in the D1 direction. For example, the first adhesive layer 1161 may be located between the first body portion 1111 and the first extension portion 1112 in the first channel structure 111 and the first metal structure 1162. Viewed from the D3 direction, the first adhesive layer 1161 may be generally "L"-shaped, and the short side portion of the first adhesive layer 1161 faces away from the first first line structure 112.

[0084] In some embodiments, the material of the first metal structure 1162 may include one or more of tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable metallic material. The material of the first adhesive layer 1161 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, or any other suitable adhesive material. For example, the material of the first metal structure 1162 may be tungsten, and the material of the first adhesive layer 1161 may be titanium nitride. In other embodiments, the first gate structure 116 may be made of a single conductive material, and this application does not impose specific limitations on this.

[0085] In some embodiments, the first gate dielectric layer 117 may be sandwiched between the first gate structure 116 and the first channel structure 111, and contact both the first gate structure 116 and the first channel structure 111. For example, in the D2 direction, the first gate dielectric layer 117 may be located between the first body portion 1111 and the first adhesive layer 1161, and contact both the first body portion 1111 and the first adhesive layer 1161. In the D3 direction, the first gate dielectric layer 117 may be located between the first extension portion 1112 and the first adhesive layer 1161, and contact both the first extension portion 1112 and the first adhesive layer 1161. For example, viewed from the D3 direction, the first gate dielectric layer 117 may be approximately "L"-shaped, and the short side portion of the first gate dielectric layer 117 may be away from the first bit line structure 112.

[0086] In some embodiments, the material of the first gate dielectric layer 117 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating materials. The high dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc.

[0087] In some embodiments, there may be multiple first gate structures 116 and multiple first gate dielectric layers 117. Each of the multiple first gate structures 116 and multiple first gate dielectric layers 117 corresponds one-to-one. For example, adjacent first gate structures 116 in the D2 direction may be approximately mirror-symmetrical, and adjacent first gate dielectric layers 117 in the D2 direction may also be approximately mirror-symmetrical.

[0088] In some embodiments, the second gate structure 118 may have a larger dimension in the D3 direction than its dimension in the D1 direction and may also have a larger dimension in the D2 direction. For example, viewed from the D3 direction, the second gate structure 118 may be located on one side of the second main body portion 1151 in the D2 direction and close to the third extension portion 1152. The second gate structure 118 may have a spacing distance from the second conductive portion 128 in the D1 direction. The second conductive portion 128 will be described in detail below.

[0089] In some embodiments, the second gate structure 118 may include a second adhesive layer 1181 and a second metal structure 1182 that are bonded to each other. For example, the second metal structure 1182 may be located on one side of the second body portion 1151 in the D2 direction and close to the third extension portion 1152. The size of the second metal structure 1182 in the D3 direction may be larger than its size in the D1 direction and may be larger than its size in the D2 direction. The second adhesive layer 1181 may be located on one side of the second metal structure 1182 in the D2 direction and on the side of the second metal structure 1182 close to the second bit line structure 114 in the D1 direction. For example, the second adhesive layer 1181 may be located between the second body portion 1151 and the third extension portion 1152 and the second metal structure 1182 in the second channel structure 115. Viewed from the D3 direction, the second adhesive layer 1181 may be generally "L"-shaped, and the short side portion of the second adhesive layer 1181 is close to the second bit line structure 114.

[0090] In some embodiments, the material of the second metal structure 1182 may include one or more of tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable metallic material. The material of the second adhesive layer 1181 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, or any other suitable adhesive material. For example, the material of the second metal structure 1182 may be tungsten, and the material of the second adhesive layer 1181 may be titanium nitride. In other embodiments, the second gate structure 118 may be made of a single conductive material, and this application does not impose specific limitations on this.

[0091] In some embodiments, the second gate dielectric layer 119 may be sandwiched between the second gate structure 118 and the second channel structure 115, and contact the second gate structure 118 and the second channel structure 115, respectively. For example, in the D2 direction, the second gate dielectric layer 119 may be located between the second body portion 1151 and the second adhesive layer 1181, and contact the second body portion 1151 and the second adhesive layer 1181, respectively. In the D3 direction, the second gate dielectric layer 119 may be located between the third extension portion 1152 and the second adhesive layer 1181, and contact the third extension portion 1152 and the second adhesive layer 1181, respectively. For example, viewed from the D3 direction, the second gate dielectric layer 119 may be generally L-shaped, and the short side portion of the second gate dielectric layer 119 is close to the second bit line structure 114.

[0092] In some embodiments, the material of the second gate dielectric layer 119 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. The high dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc.

[0093] In some embodiments, there may be multiple second gate structures 118 and multiple second gate dielectric layers 119. Each of the multiple second gate structures 118 corresponds to one of the multiple second gate dielectric layers 119. For example, adjacent second gate structures 118 in the D2 direction may be approximately mirror-symmetrical, and adjacent second gate dielectric layers 119 in the D2 direction may also be approximately mirror-symmetrical.

[0094] In some embodiments, the first channel structure 111, the first gate structure 116, and the first gate dielectric layer 117 may constitute a first transistor T1. One end of the first channel structure 111 in the D1 direction may be a first electrode of the first transistor T1 (e.g., a source or drain electrode), and the other end of the first channel structure 111 in the D1 direction may be a second electrode of the first transistor T1 (e.g., a source or drain electrode). The first gate structure 116 may be a control electrode (e.g., a gate) of the first transistor T1. The first gate structure 116 extending along the D3 direction may be a first word line of the semiconductor device 100 and may be used to control a plurality of first transistors T1 arranged along the D3 direction.

[0095] In some embodiments, the second channel structure 115, the second gate structure 118, and the second gate dielectric layer 119 may constitute a second transistor T2. One end of the second channel structure 115 in the D1 direction may be the first terminal (e.g., one of the source or drain terminals) of the second transistor T2, and the other end of the second channel structure 115 in the D3 direction may be the second terminal (e.g., the other of the source or drain terminal) of the second transistor T2. The second gate structure 118 may be the control terminal (e.g., the gate) of the second transistor T2. The second gate structure 118 extending along the D3 direction may be a second word line of the semiconductor device 100 and may be used to control a plurality of second transistors T2 arranged along the D3 direction.

[0096] In some embodiments, the semiconductor device 100 may further include a first isolation structure 120 and a second isolation structure 121. The first isolation structure 120 may be located between adjacent first channel structures 111 in the D2 direction and extend along the D3 direction. The second isolation structure 121 may be located between adjacent first gate structures 116 in the D2 direction and extend along the D3 direction. The first isolation structure 120 and the second isolation structure 121 may be arranged alternately in the D2 direction. For example, the first channel structure 111 may be in contact with the first isolation structure 120. Adjacent first channel structures 111 in the D2 direction may be substantially mirror-symmetrical with respect to the first isolation structure 120. As another example, the first gate structure 116 may be in contact with the second isolation structure 121.

[0097] In some embodiments, the materials of the first isolation structure 120 and the second isolation structure 121 may include insulating materials. These insulating materials may include, but are not limited to, silicon oxide, silicon nitride, and silicon oxynitride. For example, the materials of the first isolation structure 120 and the second isolation structure 121 may be the same or different. As another example, the materials of the first isolation structure 120 and the second isolation structure 121 may be a single insulating material or a composite insulating material. The first isolation structure 120 may serve a supporting function during the formation of the first channel structure 111. The second isolation structure 121 may electrically isolate adjacent first gate structures 116 in the D2 direction.

[0098] In some embodiments, the first isolation structure 120 may include a first conductive structure 1201 and a first dielectric layer 1202. The first conductive structure 1201 may extend along the D3 direction. The first dielectric layer 1202 may be located between the first conductive structure 1201 and the first channel structure 111. For example, viewed from the D3 direction, the first conductive structure 1201 may be generally rectangular. The first conductive structure 1201 and the first first line structure 112 are spaced apart in the D1 direction, and the first extension 1112 and the surface of the first extension 1112 facing away from the first first line structure 112 are also spaced apart in the D1 direction. The first dielectric layer 1202 may be located on opposite sides of the first conductive structure 1201 in the D2 direction, and contact the first conductive structure 1201 and the first channel structure 111, respectively.

[0099] In some embodiments, the material of the first conductive structure 1201 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicide, or any other suitable conductive material. The material of the first dielectric layer 1202 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant material, or any other suitable insulating material. The high dielectric constant material may include, but is not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. In this embodiment, the first isolation structure 120 not only provides support during the formation of the first channel structure 111 but also provides shielding. For example, the coupling effect between adjacent first transistors T1 in the D2 direction can be improved by applying a voltage (e.g., a negative voltage or a ground voltage) to the first conductive structure 1201.

[0100] In some embodiments, the semiconductor device 100 may further include a third isolation structure 122 and a fourth isolation structure 123. The third isolation structure 122 may be located between adjacent second channel structures 115 in the D2 direction and extend along the D3 direction. The fourth isolation structure 123 may be located between adjacent second gate structures 118 in the D2 direction and extend along the D3 direction. The third isolation structure 122 and the fourth isolation structure 123 may be arranged alternately in the D2 direction. For example, the second channel structures 115 may contact the third isolation structure 122. Adjacent second channel structures 115 in the D2 direction may be substantially mirror-symmetrical with respect to the third isolation structure 122. As another example, the second gate structures 118 may contact the fourth isolation structure 123.

[0101] In some embodiments, the materials of the third isolation structure 122 and the fourth isolation structure 123 may include insulating materials. These insulating materials may include, but are not limited to, silicon oxide, silicon nitride, and silicon oxynitride. For example, the materials of the third isolation structure 122 and the fourth isolation structure 123 may be the same or different. As another example, the materials of the third isolation structure 122 and the fourth isolation structure 123 may be a single insulating material or a composite insulating material. The third isolation structure 122 may serve a supporting role during the formation of the second channel structure 115. The fourth isolation structure 123 may electrically isolate the adjacent second gate structures 118 in the D2 direction.

[0102] In some embodiments, the third isolation structure 122 may include a second conductive structure 1221 and a second dielectric layer 1222. The second conductive structure 1221 may extend along the D3 direction. The second dielectric layer 1222 may be located between the second conductive structure 1221 and the second channel structure 115. For example, viewed from the D3 direction, the second conductive structure 1221 may be generally rectangular. The second conductive structure 1221 and the second bit line structure 114 are spaced apart in the D1 direction, and the surface of the fourth extension 1153 facing away from the second bit line structure 114 is also spaced apart in the D1 direction. The second dielectric layer 1222 may be located on opposite sides of the second conductive structure 1221 in the D2 direction, and contact the second conductive structure 1221 and the second channel structure 115, respectively.

[0103] In some embodiments, the material of the second conductive structure 1221 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicide, or any other suitable conductive material. The material of the second dielectric layer 1222 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. The high dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. In this embodiment, the third isolation structure 122 not only provides support during the formation of the second channel structure 115 but also provides shielding. For example, the coupling effect between adjacent second transistors T2 in the D2 direction can be improved by applying a voltage (e.g., a negative voltage or a ground voltage) to the second conductive structure 1221.

[0104] In some embodiments, the first isolation structure 120 and the third isolation structure 122 are at least partially aligned in the D1 direction. Thus, as described above, the first channel structure 111 and its corresponding second channel structure 115 can have a gap in the D2 direction, thereby increasing the process margin and reducing the process difficulty.

[0105] In some embodiments, in adjacent first main body portions 1111 in the D2 direction, the distance l1 between the ends closer to the first first line structure 112 is greater than the distance l2 between the ends away from the first first line structure 112. For example, two adjacent first main body portions 1111 are distributed on opposite sides of the second isolation structure 121 in the D2 direction.

[0106] In some embodiments, in adjacent second body portions 1151 in the D2 direction, the distance l3 between the ends closer to the second bit line structure 114 is smaller than the distance l4 between the ends away from the second bit line structure 114. For example, two adjacent second body portions 1151 are distributed on opposite sides of the fourth isolation structure 123 in the D2 direction.

[0107] In some implementations, such as Figure 1 and Figure 2 As shown, the semiconductor device 100 may further include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may be located on the side of the first channel structure 111 opposite to the first bit line structure 112. The second capacitor C2 may be located on the side of the second channel structure 115 opposite to the second bit line structure 114. For example, the first capacitor C1 may be connected to the first transistor T1, and the second capacitor C2 may be connected to the second transistor T2. In this embodiment, since the pitch of the adjacent first channel structures 111 and the adjacent second channel structures 115 in the D2 direction is increased, it is possible to ensure that the first capacitor C1 and the second capacitor C2 have a large design size on the plane defined by the D2 and D3 directions, thus meeting the storage capacity requirements of the first capacitor C1 and the second capacitor C2.

[0108] In some embodiments, the first transistor T1 and the first capacitor C1 can constitute a first memory cell. For example, the first memory cell can be a DRAM memory cell. Multiple first memory cells can be arranged in an array along the D2 and D3 directions. The second transistor T2 and the second capacitor C2 can constitute a second memory cell. For example, the second memory cell can be a DRAM memory cell. Multiple second memory cells can be arranged in an array along the D2 and D3 directions.

[0109] In some embodiments, the first capacitor C1 may include a first conductive portion 125, a first insulating layer 126, and a first conductive layer 127. The first conductive portion 125 may extend along the D1 direction and be connected to the first channel structure 111. The first insulating layer 126 may cover the first conductive portion 125. The first conductive layer 127 may cover the first insulating layer 126.

[0110] Exemplarily, the first conductive portion 125 may be generally hollow and columnar. For example, a first support post 131 may be provided inside the first conductive portion 125. The first conductive portion 125 may be connected (e.g., in contact) to the first extension portion 1112. The first insulating layer 126 and the first conductive layer 127 may be sequentially disposed on the outside of the first conductive portion 125. For example, the first insulating layer 126 covering multiple first conductive portions 125 may be connected to each other. In other embodiments, the first conductive portion 125 may be generally solid and columnar, and the semiconductor device 100 may not have the first support post 131; this application does not impose specific limitations on this. In this embodiment, the first conductive portion 125 and the first conductive layer 127 may be two electrodes of the first capacitor C1, respectively. One electrode of the first capacitor C1 is connected to the first electrode (e.g., one of the source or drain electrodes) of the first transistor T1, and the other electrode of the multiple first capacitors C1 (i.e., the first conductive layer 127) is connected to each other.

[0111] In some embodiments, the material of the first conductive portion 125 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. For example, in the case where the semiconductor device 100 has a first support pillar 131, the material of the first conductive portion 125 may be titanium nitride. The material of the first support pillar 131 may be polycrystalline silicon. The material of the first insulating layer 126 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. The high dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The material of the first conductive layer 127 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, germanium silicon, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. In some examples, the first conductive layer 127 may be made of a composite material. For example, the material of the first conductive layer 127 may sequentially include titanium nitride, germanium silicon, and tungsten. In other examples, the first conductive layer 127 may be made of a single conductive material, and this application does not impose any specific limitations on this.

[0112] In some embodiments, the second capacitor C2 may include a second conductive portion 128, a second insulating layer 129, and a second conductive layer 130. The second conductive portion 128 may extend along the D1 direction and be connected to the second channel structure 115. The second insulating layer 129 may cover the second conductive portion 128. The second conductive layer 130 may cover the second insulating layer 129.

[0113] Exemplarily, the second conductive portion 128 may be generally hollow and columnar. For example, a second support post 132 may be provided inside the second conductive portion 128. The second conductive portion 128 may be connected (e.g., in contact) to the fourth extension 1153. The second insulating layer 129 and the second conductive layer 130 may be sequentially disposed on the outside of the second conductive portion 128. For example, the second insulating layer 129 covering multiple second conductive portions 128 may be connected to each other. In other embodiments, the second conductive portion 128 may be generally solid and columnar, and the semiconductor device 100 may not have the second support post 132; this application does not impose specific limitations on this. In this embodiment, the second conductive portion 128 and the second conductive layer 130 may be two electrodes of the second capacitor C2, respectively. One electrode of the second capacitor C2 is connected to the first electrode (e.g., one of the source or drain electrodes) of the second transistor T2, and the other electrode of the multiple second capacitors C2 (i.e., the second conductive layer 130) is connected to each other. In the above embodiments, the first conductive part 125 and the second conductive part 128 may be substantially columnar, and the first capacitor C1 and the second capacitor C2 may be referred to as columnar capacitors.

[0114] In some embodiments, the material of the second conductive portion 128 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. For example, when the semiconductor device 100 has a second support pillar 132, the material of the second conductive portion 128 may be titanium nitride. The material of the second support pillar 132 may be polycrystalline silicon. The material of the second insulating layer 129 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. The high dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The material of the second conductive layer 130 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, germanium silicon, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. In some examples, the second conductive layer 130 may be made of a composite material. For example, the material of the second conductive layer 130 may sequentially include titanium nitride, germanium silicon, and tungsten. In other examples, the second conductive layer 130 may be made of a single conductive material, and this application does not impose any specific limitations on this.

[0115] In some embodiments, the semiconductor device 100 may further include third insulating layers 133-1, 133-2, and 133-3. The third insulating layers 133-1 to 133-3 may surround at least a portion of the first conductive portion 125 and extend along the D2 and D3 directions. The first insulating layer 126 may also cover the third insulating layers 133-1 to 133-3 and the first conductive portion 125. The material of the third insulating layers 133-1 to 133-3 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the third insulating layers 133-1 to 133-3 may be silicon nitride. Exemplarily, the number of third insulating layers 133-1 to 133-3 may be multiple. Multiple third insulating layers 133-1 to 133-3 may be arranged in the D1 direction. For example, as... Figure 1 As shown, the three third insulating layers 133-1 to 133-3 can respectively surround the two ends and the middle of the first conductive portion 125 in the D1 direction. It should be noted that the specific number of the third insulating layers 133-1 to 133-3 is not limited in this application. In this embodiment, the third insulating layers 133-1 to 133-3 play a supporting role in the manufacturing process of the first capacitor C1.

[0116] In some embodiments, the semiconductor device 100 may further include fourth insulating layers 134-1, 134-2, and 134-3. The fourth insulating layers 134-1 to 134-3 may surround at least a portion of the second conductive portion 128 and extend along the D2 and D3 directions. The second insulating layer 129 may also cover the fourth insulating layers 134-1 to 134-3 and the second conductive portion 128. The material of the fourth insulating layers 134-1 to 134-3 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the fourth insulating layers 134-1 to 134-3 may be silicon nitride. Exemplarily, the number of fourth insulating layers 134-1 to 134-3 may be multiple. Multiple fourth insulating layers 134-1 to 134-3 may be arranged in the D1 direction. For example, as... Figure 1 As shown, the three fourth insulating layers 134-1 to 134-3 can respectively surround the two ends and the middle of the second conductive portion 128 in the D1 direction. It should be noted that the specific number of the fourth insulating layers 134-1 to 134-3 is not limited in this application. In this embodiment, the fourth insulating layers 134-1 to 134-3 play a supporting role in the manufacturing process of the second capacitor C2.

[0117] In some embodiments, in addition to the cylindrical capacitor described above, the first capacitor C1 and the second capacitor C2 may be implemented in other structural forms, such as cup capacitors, cylinder capacitors, stacked capacitors, etc., and this application does not impose specific limitations on them.

[0118] In some implementations, such as Figure 1 As shown, the first bit line structure 112 may include a first bit line portion 1121 and a second bit line portion 1122 arranged in the D2 direction. The second bit line structure 114 may include a third bit line portion 1141 and a fourth bit line portion 1142 arranged in the D2 direction. The connection method of each bit line portion in the first bit line structure 112 and the second bit line structure 114 will be described in detail below. In the semiconductor device 100, the first bit line portion 1121 and the second bit line portion 1122 are connected to the first conductive layer 127 through the first channel structure 111, the first conductive portion 125, and the first insulating layer 126. The first conductive layer 127 connected to the first bit line portion 1121 and the second bit line portion 1122 may be an integral structure. Similarly, the third bit line portion 1141 and the fourth bit line portion 1142 are connected to the second conductive layer 130 through the second channel structure 115, the second conductive portion 128, and the second insulating layer 129. The second conductive layer 130, connected to the third bit line portion 1141 and the fourth bit line portion 1142, is an integral structure. For example, the first memory cell connected to the first bit line structure 112 and the second memory cell connected to the second bit line structure 114 belong to the same memory block. When a predetermined number of memory cells are connected to the first bit line structure 112 (or the second bit line structure 114), Figure 1 The semiconductor device 100 shown has a more compact structure. For example, the first bit line portion 1121 and the second bit line portion 1122 may have a smaller spacing distance in the D2 direction, or the third bit line portion 1141 and the fourth bit line portion 1142 may have a smaller spacing distance in the D2 direction, which helps to reduce the planar area overhead of the semiconductor device 100 and improve the integration of the semiconductor device 100.

[0119] Figures 3 to 5 This is a three-dimensional schematic diagram of the first bit line structure, interconnect structure, and second bit line structure in a semiconductor device provided in some embodiments of this application. The following is in conjunction with... Figures 3 to 5 right Figure 1 The connection method of each bit line portion in the first bit line structure 112 and the second bit line structure 114 shown is illustrated by example.

[0120] In some implementations... Figure 3Six first bit line structures (e.g., 112-1, 112-2, 112-3, etc.) and six second bit line structures (e.g., 114-1, 114-2, 114-3, etc.) are exemplarily shown. For example, the first bit line structure 112-1 may include a first bit line portion 1121-1 and a second bit line portion 1122-1 arranged in the D2 direction. For example, both the first bit line portion 1121-1 and the second bit line portion 1122-1 extend continuously in the D2 direction. As another example, an insulating structure is provided between the first bit line portion 1121-1 and the second bit line portion 1122-1, such that the first bit line portion 1121-1 and the second bit line portion 1122-1 are electrically isolated. The second bit line structure 114-1 may include a third bit line portion 1141-1 and a fourth bit line portion 1142-1 arranged in the D2 direction. For example, both the third bit line portion 1141-1 and the fourth bit line portion 1142-1 extend continuously in the D2 direction. For example, an insulating structure is provided between the third bit line portion 1141-1 and the fourth bit line portion 1142-1, so that the third bit line portion 1141-1 and the fourth bit line portion 1142-1 are electrically isolated. The first bit line portion 1121-1 and the third bit line portion 1141-1 are stacked in the D1 direction, for example, when viewed from the D1 direction, the first bit line portion 1121-1 and the third bit line portion 1141-1 substantially overlap. Optionally, the second bit line portion 1122-1 and the fourth bit line portion 1142-1 are stacked in the D1 direction.

[0121] Similarly, the first bit line structure 112-2 may also include a first bit line portion 1121-2 and a second bit line portion 1122-2 arranged in the D2 direction. The second bit line structure 114-2 may also include a third bit line portion 1141-2 and a fourth bit line portion 1142-2 arranged in the D2 direction. The first bit line portion 1121-2 and the third bit line portion 1141-2 are stacked in the D1 direction. Optionally, the second bit line portion 1122-2 and the fourth bit line portion 1142-2 are stacked in the D1 direction.

[0122] The first interconnect structure 1131-1 in the interconnect structure is connected to the first bit line portion 1121-1 and the third bit line portion 1141-2, respectively. The first bit line portion 1121-1 and the third bit line portion 1141-2 are adjacent in the D3 direction. The first interconnect structure 1131-1 may be located at the end of the first bit line portion 1121-1 opposite to the second bit line portion 1122-1, and the first interconnect structure 1131-1 may also be located at the end of the third bit line portion 1141-2 opposite to the fourth bit line portion 1142-2.

[0123] The second interconnect structure 1132-1 in the interconnect structure is connected to the second bit line portion 1122-1 and the fourth bit line portion 1142-2, respectively. The second bit line portion 1122-1 and the fourth bit line portion 1142-2 are adjacent in the D3 direction. The second interconnect structure 1132-1 may be located at the end of the second bit line portion 1122-1 opposite to the first bit line portion 1121-1, and the second interconnect structure 1132-1 may also be located at the end of the fourth bit line portion 1142-2 opposite to the third bit line portion 1141-2.

[0124] Similarly, the first interconnect structure 1131-2 is connected to the first bit line portion 1121-2 and the third bit line portion 1141-1, respectively. The first bit line portion 1121-2 and the third bit line portion 1141-1 are adjacent in the D3 direction. The first interconnect structure 1131-2 may be located at the end of the first bit line portion 1121-2 away from the second bit line portion 1122-2, and the first interconnect structure 1131-2 may also be located at the end of the third bit line portion 1141-1 away from the fourth bit line portion 1142-1.

[0125] The second interconnect structure 1132-2 is connected to the second bit line portion 1122-2 and the fourth bit line portion 1142-1, respectively. The second bit line portion 1122-2 and the fourth bit line portion 1142-1 are adjacent in the D3 direction. The second interconnect structure 1132-2 may be located at the end of the second bit line portion 1122-2 away from the first bit line portion 1121-2, and the second interconnect structure 1132-2 may also be located at the end of the fourth bit line portion 1142-1 away from the third bit line portion 1141-1.

[0126] In some embodiments, the first interconnect structure 1131-1 may include interconnect channels 1135 and interconnect lines 1136 alternately arranged in the D1 direction. For example, two interconnect channels 1135 and one interconnect line 1136. One interconnect channel 1135 contacts a first bit line portion 1121-1, and the other interconnect channel 1135 contacts a third bit line portion 1141-2. The interconnect line 1136 may extend along the D3 direction to connect the two interconnect channels 1135. The interconnect channel 1135 may be generally columnar. As described above, the end dimension of the interconnect channel 1135 near, for example, the first bit line structure 112-1 is smaller than its end dimension near, for example, the second bit line structure 114-2. In this application, the end dimension of the interconnect channel 1135 may be a dimension (e.g., diameter) in a plane perpendicular to the D1 direction (or a plane defined by the D2 and D3 directions). In some practical applications, the dimension of the interconnect channel 1135 in the plane perpendicular to the D1 direction decreases along the D1 direction. As an example, the diameter of the interconnect channel 1135 gradually decreases from, for example, the second bit line structure 114-2 to, for example, the first bit line structure 112-1 in the D1 direction.

[0127] It should be noted that the second interconnect structure 1132-1 may have an internal structure similar to the first interconnect structure 1131-1, which will not be described in detail here. Furthermore, Figure 3 The number and / or arrangement of interconnect lines 1136 and interconnect channels 1135 included in the first interconnect structure 1131-1 or the second interconnect structure 1132-1 shown are merely examples. In other examples, interconnect lines 1136 may have other shapes in the direction perpendicular to D1, for example, interconnect lines 1136 may also extend along the D2 direction.

[0128] In this application, in order to clearly show the connection relationship of each line portion, the internal structure of the first interconnection structure 1131-2 and the second interconnection structure 1132-2 is omitted and replaced by the form of connecting lines. This application does not impose specific limitations on the internal structure of each interconnection structure.

[0129] Regarding the adjacent first bit line structures 112-1 and 112-2 in the D3 direction and the adjacent second bit line structures 114-1 and 114-2 in the D3 direction, the first bit line portion 1121-1 is electrically connected to the third bit line portion 1141-2 through the first interconnection structure 1131-1, and the first bit line portion 1121-2 is electrically connected to the third bit line portion 1141-1 through the first interconnection structure 1131-2. The second bit line portion 1122-1 is electrically connected to the fourth bit line portion 1142-2 through the second interconnection structure 1132-1, and the second bit line portion 1122-2 is electrically connected to the fourth bit line portion 1142-1 through the second interconnection structure 1132-2. For example, compared to an implementation where both the first bit line structure and the second bit line structure extend continuously along the D2 direction and an interconnection structure is provided at one end of the first bit line structure and the second bit line structure, in this implementation, the first bit line structure (e.g., 112-1 and 112-2) is broken into two parts, the second bit line structure (e.g., 114-1 and 114-2) is broken into two parts, and a part of the first bit line structure and a part of the second bit line structure are connected by an interconnection structure. This can shorten the bit line length used to transmit the same bit line signal, reduce RC delay, and increase sensing margin.

[0130] In some embodiments, the first bit line portions 1121-1 and 1121-2 of the adjacent first bit line structures 112-1 and 112-2 in the D3 direction, and the third bit line portions 1141-1 and 1141-2 of the second bit line structures 114-1 and 114-2, are connected to a first sensing amplifier. Through a “twisted” connection of the first interconnect structures 1131-1 and 1131-2, the first bit line portions 1121-1 and 1141-2 can be used to transmit a first bit line signal, and the first bit line portions 1121-2 and 1141-1 can be used to transmit a second bit line signal. For example, the first bit line signal may be greater than a reference bit line signal, and the second bit line signal may be less than a reference bit line signal; a readout operation is performed by sensing the change in either the first or second bit line signal. In this embodiment, the “twisted” connection of the interconnect structures improves the coupling effect between the bit line portions used to transmit different bit line signals, thus helping to improve the sensing margin.

[0131] In some embodiments, the second bit line portions 1122-1 and 1122-2 of the first bit line structures 112-1 and 112-2 adjacent in the D3 direction, and the fourth bit line portions 1142-1 and 1142-2 of the second bit line structures 114-1 and 114-2, are connected to the second sense amplifier. The “twisted” connection of the second interconnect structures 1132-1 and 1132-2 improves the coupling effect between the bit line portions used to transmit different bit line signals, thus contributing to increased sensing margin.

[0132] In some embodiments, the first bit line structure 112-3 may include a first bit line portion 1121-3 and a second bit line portion 1122-3 arranged in the D2 direction. The second bit line structure 114-3 may include a third bit line portion 1141-3 and a fourth bit line portion 1142-3 arranged in the D2 direction. The first bit line portion 1121-3 and the third bit line portion 1141-3 are stacked in the D1 direction. Optionally, the second bit line portion 1122-3 and the fourth bit line portion 1142-3 are stacked in the D2 direction. The first interconnect structure 1131-3 is connected to the first bit line portion 1121-3 and the third bit line portion 1141-3, respectively. For example, the first bit line portion 1121-3 and the third bit line portion 1141-3 are aligned in the D1 direction. The second interconnect structure 1132-2 is connected to the second bit line portion 1122-3 and the fourth bit line portion 1142-3, respectively. For example, the second bit line portion 1122-3 and the fourth bit line portion 1142-3 are aligned in the D1 direction.

[0133] For example, neither the first interconnect structure 1131-3 nor the second interconnect structure 1132-3 includes interconnect lines. For instance, both the first interconnect structure 1131-3 and the second interconnect structure 1132-3 are implemented as a single interconnect channel. The dimension of this interconnect channel near, for example, the first bit line structure 112-3 is smaller than its dimension near, for example, the second bit line structure 114-3. In some practical applications, the dimension of this interconnect channel decreases along the D1 direction in a plane perpendicular to the D1 direction. In this embodiment, breaking the first bit line structure (e.g., 112-3) into two parts and the second bit line structure (e.g., 114-3) into two parts, and connecting a portion of the first bit line structure and a portion of the second bit line structure via interconnect structures, can shorten the bit line length used to transmit the same bit line signal, reduce RC delay, and increase sensing margin.

[0134] In some embodiments, each interconnect channel 1135 decreases in size along the D1 direction in a plane perpendicular to the D1 direction. For example, this can be achieved by sequentially fabricating the first bit line structure, the interconnect structure, and the second bit line structure, which helps to reduce fabrication difficulty, improve connection reliability, and increase the yield of the semiconductor device 100.

[0135] In some embodiments, the materials of the first bit line structure (e.g., 112-1 to 112-3), the second bit line structure (e.g., 114-1 to 114-3), the first interconnect structure (e.g., 1131-1 to 1131-3), and the second interconnect structure (e.g., 1132-1 to 1132-3) may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicide, or any other suitable conductive material.

[0136] exist Figure 4 In order to clearly show the connection relationship of each bit line part (or bit line sub-part), the internal structure of the third interconnection structure and the fourth interconnection structure is omitted and replaced by the form of connecting lines. This application does not impose specific restrictions on the internal structure of each interconnection structure (e.g., the number, shape and arrangement of interconnection channels and interconnection lines).

[0137] In some embodiments, the first line portion 1121-1 may include a plurality (e.g., two) first line sub-portions 11211a-1, 11211b-1 arranged in the D2 direction. The third line portion 1141-1 may include a plurality (e.g., two) third line sub-portions 11411a-1, 11411b-1 arranged in the D2 direction. Exemplarily, each first line sub-portion 11211a-1, 11211b-1 and each third line sub-portion 11411a-1, 11411b-1 corresponds one-to-one. For example, viewed from the D1 direction, the first line sub-portion 11211a-1 and its corresponding third line sub-portion 11411a-1 substantially overlap. For example, an insulating structure can be provided between each of the first-position wire sub-sections 11211a-1 and 11211b-1 to achieve electrical isolation between them. Similarly, an insulating structure can be provided between each of the third-position wire sub-sections 11411a-1 and 11411b-1 to achieve electrical isolation between them.

[0138] In the interconnect structure, a third interconnect structure 1133-1 (e.g., a single solid line connection) is connected to both the first line sub-part 11211a-1 and the third line sub-part 11411b-1. The first line sub-part 11211a-1 and the third line sub-part 11411b-1 are adjacent in the D2 direction. Another third interconnect structure 1133-3 (e.g., a single solid line connection) is also connected to both the first line sub-part 11211b-1 and the third line sub-part 11411a-1. The first line sub-part 11211b-1 and the third line sub-part 11411a-1 are also adjacent in the D2 direction.

[0139] The second bit line portion 1122-1 may include a plurality (e.g., two) of second bit line sub-portions 11221a-1 and 11221b-1 arranged in the D2 direction. The fourth bit line portion 1142-1 may include a plurality (e.g., two) of fourth bit line sub-portions 11421a-1 and 11421b-1 arranged in the D2 direction. Exemplarily, each of the second bit line sub-portions 11221a-1 and 11221b-1 and each of the fourth bit line sub-portions 11421a-1 and 11421b-1 corresponds one-to-one. For example, viewed from the D1 direction, the second bit line sub-portion 11221a-1 and its corresponding fourth bit line sub-portion 11421a-1 substantially overlap. For example, an insulating structure may be provided between each of the second-position wire sections 11221a-1 and 11221b-1 to achieve electrical isolation between them. Similarly, an insulating structure may be provided between each of the fourth-position wire sections 11421a-1 and 11421b-1 to achieve electrical isolation between them.

[0140] One fourth interconnect structure 1134-1 (e.g., a single solid line connection) is connected to both the second bit sub-part 11221a-1 and the fourth bit sub-part 11421b-1 in the interconnect structure. The second bit sub-part 11221a-1 and the fourth bit sub-part 11421b-1 are adjacent in the D2 direction. Another fourth interconnect structure 1134-1 (e.g., a single solid line connection) is also connected to both the second bit sub-part 11221b-1 and the fourth bit sub-part 11421a-1. The second bit sub-part 11221b-1 and the fourth bit sub-part 11421a-1 are adjacent in the D2 direction.

[0141] In some embodiments, the first interconnect structure 1131-1 is connected to the first bit sub-partition 11211a-1 and the third bit sub-partition 11411a-1, respectively. The second interconnect structure 1132-1 is connected to the second bit sub-partition 11221b-1 and the fourth bit sub-partition 11421b-1, respectively. In other embodiments, the first interconnect structure may be connected to the third bit sub-partition of the first bit sub-partition 11211a-1 and the third bit sub-partition 1141-2, respectively. The third bit sub-partitions of the first bit sub-partition 11211a-1 and the third bit sub-partition 1141-2 are adjacent in the D3 direction. The second interconnect structure may be connected to the fourth bit sub-partition of the second bit sub-partition 11221b-1 and the fourth bit sub-partition 1142-2, respectively. The fourth bit sub-partitions of the second bit sub-partition 11221b-1 and the fourth bit sub-partition 1142-2 are adjacent in the D3 direction.

[0142] In some implementations, similar to the first bit line structure 112-1 and the second bit line structure 114-1, the first bit line structure 112-2 and the second bit line structure 114-2 have the same internal structure and connection method.

[0143] In some embodiments, the first bit line portions 1121-1 and 1121-2 of the adjacent first bit line structures 112-1 and 112-2 in the D3 direction, and the third bit line portions 1141-1 and 1141-2 of the second bit line structures 114-1 and 114-2, are connected to the first sensing amplifier. The “twisted” connection of the third interconnect structure (e.g., 1133-1) improves the coupling effect between the bit line portions (or bit line sub-portions) used to transmit different bit line signals, thus contributing to improved sensing margin.

[0144] In some embodiments, the second bit line portions 1122-1 and 1122-2 of the first bit line structures 112-1 and 112-2 adjacent in the D3 direction, and the fourth bit line portions 1142-1 and 1142-2 of the second bit line structures 114-1 and 114-2, are connected to the second sense amplifier. The “twisted” connection of the fourth interconnect structure (e.g., 1134-1) improves the coupling effect between the bit line portions (or bit line sub-portions) used to transmit different bit line signals, thus contributing to improved sensing margin.

[0145] In some embodiments, the materials of the third interconnect structure (e.g., 1133-1) and the fourth interconnect structure (e.g., 1134-1) may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicides or any other suitable conductive materials.

[0146] It should be noted that, Figure 4 The number of bit line sub-parts included in each bit line portion shown is merely an example. In other examples, each bit line portion may include more (e.g., more than two) bit line sub-parts. This application does not limit the specific number of bit line sub-parts included in each bit line portion.

[0147] In some implementations, such as Figure 5As shown, in the adjacent first line portions 1121-1 and 1121-2 in the D3 direction, and the adjacent third line portions 1141-1 and 1141-2 in the D3 direction, the third interconnection structure 1133-1 (e.g., a single solid line connection) is connected to the first line sub-portion 11211a-1 and the third line sub-portion 11411b-1, respectively. The first line sub-portion 11211a-1 and the third line sub-portion 11411b-1 are adjacent in the D2 direction. The third interconnection structure 1133-2 (e.g., a single solid line connection) is connected to the first line sub-portion 11211b-2 and the third line sub-portion 11411a-2, respectively. The first line sub-portion 11211b-2 and the third line sub-portion 11411a-2 are adjacent in the D2 direction.

[0148] In the adjacent second bit line portions 1122-1 and 1122-2 in the D3 direction, and the adjacent fourth bit line portions 1142-1 and 1142-2 in the D3 direction, the fourth interconnection structure 1134-1 (e.g., a single solid line connection) is connected to the second bit line sub-portion 11221a-1 and the fourth bit line sub-portion 11421b-1, respectively. The second bit line sub-portion 11221a-1 and the fourth bit line sub-portion 11421b-1 are adjacent in the D2 direction. The fourth interconnection structure 1134-2 (e.g., a single solid line connection) is connected to the second bit line sub-portion 11221b-2 and the fourth bit line sub-portion 11421a-2, respectively. The second bit line sub-portion 11221b-2 and the fourth bit line sub-portion 11421a-2 are adjacent in the D2 direction.

[0149] In some embodiments, the first bit line portions 1121-1 and 1121-2 of the adjacent first bit line structures 112-1 and 112-2 in the D3 direction, and the third bit line portions 1141-1 and 1141-2 of the second bit line structures 114-1 and 114-2, are connected to the first sensing amplifier. The “twisted” connection of the third interconnect structure (e.g., 1133-1 and 1133-2) improves the coupling effect between the bit line portions (or bit line sub-portions) used to transmit different bit line signals, thus contributing to improved sensing margin.

[0150] In some embodiments, the second bit line portions 1122-1 and 1122-2 of the first bit line structures 112-1 and 112-2 adjacent in the D3 direction, and the fourth bit line portions 1142-1 and 1142-2 of the second bit line structures 114-1 and 114-2, are connected to the second sense amplifier. The “twisted” connection of the fourth interconnect structure (e.g., 1134-1 and 1134-2) improves the coupling effect between the bit line portions (or bit line sub-portions) used to transmit different bit line signals, thus contributing to improved sensing margin.

[0151] In some implementations, refer again Figure 1 The semiconductor device 100 may also include a peripheral circuit structure 135. The peripheral circuit structure 135 may be located on the side of the second capacitor C2 away from the second bit line structure 114, or on the side of the first capacitor C1 away from the first bit line structure 112 (not shown).

[0152] Exemplarily, the peripheral circuit structure 135 may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for controlling the operation of the memory cell array (e.g., an array consisting of a first memory cell and a second memory cell). For example, this peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0153] In some embodiments, the semiconductor device 100 may further include a first connection structure 136 and a second connection structure 137. The first connection structure 136 may extend along the D1 direction and connect to the end of the third bit line portion 1141 or the first bit line portion 1121 in the D2 direction. The second connection structure 137 may extend along the D1 direction and connect to the end of the fourth bit line portion 1142 or the second bit line portion 1122 in the D2 direction. Leading the first bit line structure 112 or the second bit line structure 114 from the end helps to reduce the difficulty of winding.

[0154] In some embodiments, the materials of the first connection structure 136 and the second connection structure 137 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, polycrystalline silicon, amorphous silicon, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicides or any other suitable conductive materials.

[0155] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application. For the purpose of brevity, the parts that are the same as those in the previous embodiment will not be repeated here.

[0156] like Figure 6 As shown above, the first bit line structure 112 may include a first bit line portion 1121 and a second bit line portion 1122 arranged in the D2 direction. The second bit line structure 114 may include a third bit line portion 1141 and a fourth bit line portion 1142 arranged in the D2 direction.

[0157] In the semiconductor device 100, the first bit line portion 1121 and the second bit line portion 1122 are connected to the first conductive layer 127 via a first channel structure 111, a first conductive portion 125, and a first insulating layer 126. The first conductive layer 127 connected to the first bit line portion 1121 and the second bit line portion 1122 can be a separate structure. For example, the first conductive layer 127 connected to the first bit line portion 1121 and the first conductive layer 127 connected to the second bit line portion 1122 are independent structures and are not connected to each other.

[0158] The third bit line portion 1141 and the fourth bit line portion 1142 are connected to the second conductive layer 130 through the second channel structure 115, the second conductive portion 128, and the second insulating layer 129. The second conductive layer 130 connected to the third bit line portion 1141 and the fourth bit line portion 1142 is a separate structure. For example, the second conductive layer 130 connected to the third bit line portion 1141 and the second conductive layer 130 connected to the fourth bit line portion 1142 are independent structures and are not connected to each other. For example, the first memory cell and the second memory cell connected to the first bit line portion 1121 and the third bit line portion 1141 belong to one memory block. The first memory cell and the second memory cell connected to the second bit line portion 1122 and the fourth bit line portion 1142 belong to another memory block.

[0159] When a predetermined number of memory cells are connected to the first bit line structure 112 (or the second bit line structure 114), the first bit line portion 1121 and the second bit line portion 1122 have a large spacing distance in the D2 direction, or the third bit line portion 1141 and the fourth bit line portion 1142 have a large spacing distance in the D2 direction. This is more favorable for the process of the first conductive layer 127 and the second conductive layer 130, and is beneficial to improving the yield of the semiconductor device 100.

[0160] Some embodiments of this application also provide a method for fabricating a semiconductor device. Figure 7 This is a schematic flowchart illustrating the fabrication method of the semiconductor device provided in this application. Figure 7 As shown, the semiconductor device fabrication method 200 (hereinafter referred to as fabrication method 200) may include the following steps.

[0161] S210, forming a first channel structure extending along the first direction.

[0162] S220, a first bit line structure, an interconnect structure and a second bit line structure are sequentially formed on one side of the first channel structure in the first direction, wherein the first bit line structure extends in the second direction and the second bit line structure extends in the second direction.

[0163] S230, a second channel structure extending in the first direction is formed on the side of the second channel structure that is away from the first channel structure.

[0164] According to the fabrication method provided in the embodiments of this application, by forming a first channel structure, a first bit line structure, a second bit line structure, and a second channel structure arranged in a first direction, it is helpful to improve the integration density of semiconductor devices and save planar area overhead. In addition, compared with alignment bonding to form interconnect structures, by sequentially forming the first bit line structure, the interconnect structure, and the second bit line structure, the process difficulty and structural complexity of the interconnect structure can be reduced, and the connection reliability can be improved, thereby increasing the yield of semiconductor devices.

[0165] Figures 8A to 8G This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application during the fabrication process. Figure 8A An intermediate structure 300a is shown after the formation of the first conductive part and the first channel structure. Figure 8B The intermediate structure 300b is shown after the formation of the interconnect structure and the second bit line structure. Figure 8C The intermediate structure 300c is shown after the formation of the second channel structure. Figure 8D The intermediate structure 300d after the formation of the second capacitor is shown. Figure 8E The intermediate structure 300e is shown after the external circuit structure is connected. Figure 8F The intermediate structure 300f after the substrate has been removed is shown. Figure 8G The semiconductor device 300 after the formation of the first capacitor is shown. The following is in conjunction with... Figures 8A to 8G The preparation method 200, which includes steps S210 to S230, will be described by way of example.

[0166] In some implementations, such as Figure 8A As shown, before forming the first channel structure 311, the fabrication method 200 may include the step of forming a portion of the first capacitor, for example, forming a first conductive portion 325 extending along the D1 direction in the first capacitor.

[0167] Exemplarily, the first sacrificial layers 340-1 and 340-2 extending along the D2 and D3 directions can be formed using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, during the formation of the first sacrificial layers 340-1 and 340-2, a stepwise deposition method can be used, forming a third insulating layer 333-2 between two depositions. Furthermore, the third insulating layers 333-1 and 333-3 can be formed before the first deposition and after the last deposition, respectively. Thus, the third insulating layers 333-1 to 333-3 can be located on opposite sides of the first sacrificial layers 340-1 and 340-2 in the D1 direction, and embedded within the first sacrificial layers 340-1 and 340-2. The third insulating layers 333-1 to 333-3 can extend along the D2 and D3 directions.

[0168] For example, the material of the first sacrificial layers 340-1 and 340-2 may include silicon oxide, polycrystalline silicon, carbon, or any other suitable removable material. When the third insulating layers 333-1 to 333-3 are formed, the material of the third insulating layers 333-1 to 333-3 may differ from the material of the first sacrificial layers 340-1 and 340-2. The third insulating layers 333-1 to 333-3 can serve a supporting function after the first sacrificial layers 340-1 and 340-2 have been removed.

[0169] Exemplarily, first sacrificial layers 340-1 and 340-2 may be formed on one side (e.g., the surface) of substrate 341. For example, substrate 341 may include a semiconductor substrate. The material of the semiconductor substrate may include silicon, germanium, germanium-silicon, gallium arsenide, indium phosphide, silicon-on-insulator (SiI) substrate, or germanium-on-insulator (CHI) substrate, etc. For example, substrate 341 may be a composite layer structure or composed of a single material. Substrate 341 may serve a supporting function and is removed in subsequent processes.

[0170] Exemplarily, an etching process (e.g., dry etching and / or wet etching) can be used to form a first conductive hole (corresponding to the outer contour of the first conductive portion 325) penetrating the first sacrificial layers 340-1, 340-2 (or further penetrating the third insulating layers 333-1 to 333-3). Next, an initial first conductive portion can be formed on the inner wall of the first conductive hole, and a first support post 331 can be formed inside the initial first conductive portion. For example, the first conductive portion 325 can be formed by etching back the first support post 331 and filling the end face of the first support post 331 facing away from the substrate 341 with conductive material. Alternatively, after forming the first conductive hole, conductive material can be directly filled into the first conductive hole to form the first conductive portion (not shown).

[0171] In some embodiments, the fabrication method 200 may further include the step of forming a first isolation structure 320 before forming the first channel structure 311. The first channel structure 311 may be formed based on the first isolation structure 320.

[0172] For example, a first isolation structure 320 may be formed on one side of the first conductive portion 325 in the D1 direction. The first isolation structure 320 may extend in the D3 direction. For example, the first isolation structure 320 may also extend in the D1 direction. In other words, the dimensions of the first isolation structure 320 in both the D1 and D3 directions are larger than its dimensions in the D2 direction. For example, in the D2 direction, the first isolation structure 320 may be located between adjacent first conductive portions 325; or it may partially overlap with one of the adjacent first conductive portions 325 and have a gap distance from the other. In the case where multiple first isolation structures 320 are formed, in the D2 direction, two adjacent first isolation structures 320 may be spaced apart by two first conductive portions 325.

[0173] As an example, the first isolation structure 320 may be made of an insulating material. As another example, the first isolation structure 320 may include a first conductive structure 3201 and a first dielectric layer 3202. The first conductive structure 3201 may extend along the D3 direction, and the first dielectric layer 3202 may be formed on opposite sidewalls of the first conductive junction 3201 in the D2 direction. For example, the first conductive structure 3201 may have a spaced distance from the first conductive portion 325 in the D1 direction.

[0174] S210

[0175] In some embodiments, an initial first channel structure (not shown) covering the first isolation structure 320 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Next, an etching process (e.g., dry etching and / or wet etching) can be used to periodically break the initial first channel structure in the D3 direction and also periodically break it in the D2 direction, thereby forming a plurality of first channel structures 311. Each of the plurality of first channel structures 311 can be connected (e.g., contacted) to the first conductive portion 325. The portion covering the sidewall of the first isolation structure 320 can be the first main body portion 3111 of the first channel structure 311. For example, during the process of periodically breaking the initial first channel structure in the D2 direction, a portion of the initial first channel structure covering the first conductive portion 325 can be retained, and this portion can be the first extension portion 3112 of the first channel structure 311. Thus, the first extension portion 3112 in the first channel structure 311 is connected (e.g., contacted) to the first conductive portion 325.

[0176] For example, the portion of the first isolation structure 320 located at the end face in the D3 direction of two adjacent first channel structures 311 in the D2 direction can be disconnected. The disconnected portion can be a second extension 3113 of a first channel structure 311. It should be noted that the first isolation structure 320 having the first conductive structure 3201 and the first dielectric layer 3202 can be formed after the second extension 3113 is formed, while the initial first channel structure can be formed based on the first isolation structure 320 made of insulating material. Furthermore, if the first isolation structure 320 having the first conductive structure 3201 and the first dielectric layer 3202 has already been formed before the first channel structure 311 is formed, the step of forming the second extension 3113 described above can be omitted, thus allowing the opposing second extensions 3113 in adjacent first channel structures 311 in the D2 direction to connect with each other.

[0177] In some embodiments, the fabrication method 200 may further include the steps of forming a first gate structure 316 and a first gate dielectric layer 317. For example, the first gate dielectric layer 317 may be formed on the surface of the first body portion 3111 opposite to the first isolation structure 320 and on the surface of the first extension portion 3112 opposite to the first conductive portion 325. Subsequently, a first adhesive layer 3161 may be formed on the surface of the first gate dielectric layer 317, and a first metal structure 3162 may be formed on the side of the first adhesive layer 3161 opposite to the first body portion 3111 and the first extension portion 3112. The first adhesive layer 3161 and the first metal structure 3162 may constitute the first gate structure 316. Alternatively, a first gate structure (not shown) made of a single conductive material may be formed on the side of the first gate dielectric layer 317 opposite to the first body portion 3111 and the first extension portion 3112.

[0178] S220

[0179] like Figure 8A and Figure 8B As shown, a first bit line structure 312, an interconnect structure 313, and a second bit line structure 314 can be sequentially formed on one side of the first channel structure 311 in the D1 direction. The first bit line structure 312 extends in the D2 direction, and the second bit line structure 314 extends in the D2 direction.

[0180] In some embodiments, a conductive material layer may be formed on one side of the first channel structure 311 in the D1 direction using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. This conductive material layer may be used to form the first line structure 312. Next, etching (e.g., dry etching and / or wet etching) may be used to remove the portion of the conductive material layer other than the first line structure 312 to be formed. Optionally, the voids after the removal of the conductive material layer may be filled with an insulating material, which may be used to form an isolation structure between the first line structures 312.

[0181] In other embodiments, an insulating material layer may be formed on one side of the first channel structure 311 in the D1 direction using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. This insulating material layer may be used to form an isolation structure between the first line structures 312. Next, a portion of the insulating material layer may be removed by etching (e.g., dry etching and / or wet etching) to form a plurality of trenches. Subsequently, a conductive material may be filled into the trenches using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form the first line structure 312.

[0182] It should be noted that the first bit line structure 312 may include a first bit line portion 3121 and a second bit line portion 3122. For example, the first bit line portion 3121 may include multiple first bit line sub-portions (not shown), and the second bit line portion 3122 may include multiple second bit line sub-portions (not shown). The various portions or sub-portions included in the first bit line structure 312 can be obtained through patterning design using an etching process.

[0183] In some embodiments, the formation process of interconnect structure 313 is described using a first interconnect structure 3131 and a second interconnect structure 3132 in interconnect structure 313 as examples. For example, the first interconnect structure 3131 and the second interconnect structure 3132 may include a single interconnect channel 3135. Exemplarily, an insulating material layer may be formed on one side of the first interconnect structure 312 in the D1 direction using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. Then, an interconnect channel hole penetrating the insulating material layer may be formed using etching (e.g., dry etching and / or wet etching). Subsequently, a conductive material may be filled into the interconnect channel hole using a thin film deposition process of CVD, PVD, ALD, or any combination thereof to form the interconnect channel 3135.

[0184] It should be noted that the position of the interconnect channel 3135, which serves as the first interconnect structure 3131 and the second interconnect structure 3132, can be determined by patterning design through etching process.

[0185] In some embodiments, the interconnect structure 313 may further include interconnect lines (not shown) extending along the D2 and / or D3 directions. During the formation of the interconnect structure 313, interconnect channels and interconnect lines may be formed alternately. The interconnect channels may be connected (e.g., contacted) to the first bit line structure 312 and the second bit line structure 314.

[0186] In some embodiments, similar to the formation of the first bit line structure 312, during the formation of the second bit line structure 314, the second bit line structure 314 can be formed first, followed by the formation of the isolation structure between the second bit line structures 314; or the isolation structure between the second bit line structures 314 can be formed first, followed by the formation of the second bit line structure 314. For example, the second bit line structure 314 can be formed by a thin film deposition process.

[0187] In step S220, the first bit line structure 312, the interconnect structure 313, and the second bit line structure 314 are formed sequentially in the D1 direction. During the formation of the interconnect channel 3135 of the interconnect structure 313, as the depth of the interconnect channel hole increases, the size of the interconnect channel hole decreases in the plane perpendicular to the D1 direction. Therefore, the end size of the interconnect channel 3135 near the first bit line structure 312 is smaller than the end size near the second bit line structure 314.

[0188] In some implementations, such as Figure 8C As shown, before forming the second channel structure 315, the preparation method 200 may further include the step of forming a third isolation structure 322. The second channel structure 315 may be formed based on the third isolation structure 322.

[0189] For example, a third isolation structure 322 may be formed on the side of the second bit line structure 314 opposite to the first bit line structure 312. The third isolation structure 322 may extend along the D3 direction. For example, the third isolation structure 322 may also extend along the D1 direction. In other words, the dimensions of the third isolation structure 322 in both the D1 and D3 directions are larger than its dimensions in the D2 direction.

[0190] As an example, the third isolation structure 322 may be made of an insulating material. As another example, the third isolation structure 322 may include a second conductive structure 3221 and a second dielectric layer 3222. The second conductive structure 3221 may extend along the D3 direction, and the second dielectric layer 3222 may be formed on the opposite sidewall of the second conductive structure 3221 in the D2 direction.

[0191] S230

[0192] In some implementations, such as Figure 8C As shown, an initial second channel structure (not shown) covering the third isolation structure 322 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Next, an etching process (e.g., dry etching and / or wet etching) can be used to break the initial second channel structure at intervals in the D3 direction, break the portion located between two third isolation structures 322 in the D2 direction, and break the portion located at the end face of one third isolation structure 322 in the D3 direction in the D2 direction. The portion covering the sidewall of the third isolation structure 322 can be the second main body portion 3151 of the second channel structure 315. The portion covering the second bit line structure 314 can be the third extension portion 3152 of the second channel structure 315. The portion covering the end face of the third isolation structure 322 in the D3 direction can be the fourth extension portion 3153 of the second channel structure 315.

[0193] Alternatively, the step of forming the fourth extension 3153 can be omitted, such that the fourth extensions 3153 extending toward each other in adjacent second channel structures 315 in the D2 direction are connected to each other.

[0194] It should be noted that the third isolation structure 322 having the second conductive structure 3221 and the second dielectric layer 3222 can be formed after the fourth extension 3153 is formed, and the initial second channel structure can be formed based on the third isolation structure 322 made of insulating material.

[0195] In some embodiments, the fabrication method 200 may further include the step of forming a second gate structure 318 and a second gate dielectric layer 319. For example, the second gate dielectric layer 319 may be formed on the surface of the second body portion 3151 opposite to the third isolation structure 322 and on the surface of the third extension portion 3152 opposite to the second bit line structure 314. Subsequently, a second adhesive layer 3181 may be formed on the surface of the second gate dielectric layer 319, and a second metal structure 3182 may be formed on the side of the second adhesive layer 3181 opposite to the second body portion 3151 and the third extension portion 3152. The second adhesive layer 3181 and the second metal structure 3182 may constitute the second gate structure 318. Alternatively, a second gate structure (not shown) made of a single conductive material may be formed on the side of the second gate dielectric layer 319 opposite to the second body portion 3151 and the third extension portion 3152.

[0196] In some implementations, such as Figure 8D As shown, the fabrication method 200 may further include the step of forming a second capacitor C2 on the side of the second channel structure 315 opposite to the second bit line structure 314. Exemplarily, a second conductive portion 328 may be formed, connected to the second channel structure 315 and extending along the D1 direction. Next, a second insulating layer 329 covering the second conductive portion 328 may be formed using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. Subsequently, a second conductive layer 330 covering the second insulating layer 329 may be formed using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. After the above process, the second conductive portion 328, the second insulating layer 329, and the second conductive layer 330 constitute the second capacitor C2.

[0197] In some implementations, such as Figure 8E As shown, the fabrication method 200 may further include the step of connecting the peripheral circuit structure 335. Exemplarily, the peripheral circuit structure 335 may be connected (e.g., bonded) to a side near the second capacitor C2. For example, the peripheral circuit structure 335 may be connected to... Figure 8DThe intermediate structure 300d shown is manufactured in parallel to improve efficiency. Optionally, a first connection structure 336 and a second connection structure 337 may be formed before connecting to the peripheral circuit structure 335. As an example, a first connection structure 336 may be formed extending along the D1 direction to the end of the third bit line portion 3141. Since the third bit line portion 3141 is connected to the first bit line portion 3121 via a first interconnect structure 3131, the first connection structure 336 can be used to lead either the third bit line portion 3141 or the first bit line portion 3121 out from the D1 direction, thereby connecting to the peripheral circuit structure 335. As an example, a second connection structure 337 may be formed extending along the D1 direction to the end of the fourth bit line portion 3142. Since the fourth bit line portion 3142 is connected to the second bit line portion 3122 via a second interconnect structure 3132, the second connection structure 337 can be used to lead either the fourth bit line portion 3142 or the second bit line portion 3122 out from the D1 direction, thereby connecting to the peripheral circuit structure 335.

[0198] In some implementations, such as Figures 8E to 8G As shown, the fabrication method 200 further includes the step of forming another portion of the first capacitor C1. For example, forming a first insulating layer 326 and a first conductive layer 327 of the first capacitor C1.

[0199] For example, such as Figure 8E and Figure 8F As shown, after connecting the peripheral circuit structure 335, the intermediate structure 300e can be flipped 180°. When the intermediate structure 300e is in the position shown... Figure 8F In the shown placement, the peripheral circuit structure 335 is at the bottom. Further, the substrate 341 can be removed using chemical mechanical polishing (CMP) and / or etching processes. For example, the third insulating layer 333-1 is exposed. Subsequently, the first sacrificial layers 340-1 and 340-2 can be removed using etching (e.g., wet etching) processes, exposing the first conductive portion 325. After removing the first sacrificial layers 340-1 and 340-2, the third insulating layers 333-1 to 333-3 can serve a supporting function. Next, as... Figure 8F and Figure 8G As shown, a first insulating layer 326 covering the first conductive portion 325 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and a first conductive layer 327 covering the first insulating layer 326 can also be formed. The first insulating layer 326 may further cover third insulating layers 333-1 to 333-3. After the above processing, the first conductive portion 325, the first insulating layer 326, and the first conductive layer 327 can constitute a first capacitor C1.

[0200] This application also provides a memory system. Figure 9 This is a schematic block diagram of a system with a memory system provided in the embodiments of this application. Figure 10A and Figure 10B This is a schematic block diagram of a memory system provided in an embodiment of this application.

[0201] like Figure 9 As shown, system 40 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 41 located therein). Figure 9 As shown, system 40 may include a host 44 and a memory system 41, the memory system 41 having one or more memories 42 and a controller 43. The host 44 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 44 may be configured to send or receive data to and from the memory 42.

[0202] Memory 42 may include the semiconductor device 100 described in any embodiment of this application. According to some embodiments, controller 43 is coupled to memory 42 and host 44 and is configured to control memory 42. Controller 43 may manage data stored in memory 42 and communicate with host 44. In some embodiments, controller 43 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 43 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 43 may be configured to control operations of memory 42, such as read, erase, and program operations. Controller 43 may also be configured to manage various functions related to data stored in or to be stored in memory 42, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 43 is further configured to process error correction codes (ECCs) related to data read from or written to memory 42. Controller 43 may also perform any other appropriate functions, such as formatting memory 42. Controller 43 may communicate with external devices (e.g., host 44) according to a specific communication protocol. For example, controller 43 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0203] The controller 43 and one or more memories 42 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 41 can be implemented and packaged into different types of end electronic products. Figure 10AIn one example shown, the controller 43 and a single memory 42 may be integrated into a memory card 45. The memory card 45 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 45 may further include a connector for connecting the memory card 45 to a host computer (e.g., Figure 9 The host 44) is coupled to the memory card connector 46. In such a way... Figure 10B In another example shown, the controller 43 and multiple memories 42 may be integrated into the SSD 47. The SSD 47 may further include a connection between the SSD 47 and the host (e.g., Figure 9 The SSD connector 48 is coupled to the host 44. In some embodiments, the storage capacity and / or operating speed of the SSD 47 is higher than that of the memory card 45.

[0204] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device comprising a first channel structure, a first bit line structure, an interconnect structure, a second bit line structure, and a second channel structure arranged sequentially in a first direction, wherein, The first channel structure extends along the first direction, the second channel structure extends along the first direction, the first bit line structure extends in the second direction, the second bit line structure extends in the second direction, and the interconnect structure is connected to the first bit line structure and the second bit line structure. The interconnect structure includes an interconnect channel extending along the first direction, wherein the end dimension of the interconnect channel near the first bit line structure is smaller than the end dimension near the second bit line structure, and the first direction intersects the second direction.

2. The semiconductor device according to claim 1, wherein, The end dimension of the interconnect channel is the dimension in a plane perpendicular to the first direction.

3. The semiconductor device according to claim 1 or 2, wherein, Along the first direction, the dimensions of the interconnecting channels decrease in a plane perpendicular to the first direction.

4. The semiconductor device according to claim 3, wherein, Along the first direction, the dimensions of each interconnect channel decrease in a plane perpendicular to the first direction.

5. The semiconductor device according to claim 1, wherein, The interconnection structure further includes interconnect lines extending along the second direction and / or the third direction, the interconnection channels and the interconnect lines being alternately arranged in the first direction, wherein the first direction, the second direction and the third direction intersect each other.

6. The semiconductor device according to claim 1, wherein, The first bit line structure includes a first bit line portion and a second bit line portion arranged in the second direction, and the second bit line structure includes a third bit line portion and a fourth bit line portion arranged in the second direction, with the first bit line portion and the third bit line portion overlapping in the first direction. The interconnection structure includes a first interconnection structure and a second interconnection structure. The first interconnection structure is connected to the first bit line portion and the third bit line portion, respectively, and the second interconnection structure is connected to the second bit line portion and the fourth bit line portion, respectively.

7. The semiconductor device according to claim 6, wherein, The first interconnect structure is connected to the end of the first bit line portion that is away from the second bit line portion and the end of the third bit line portion that is adjacent to it in the third direction that is away from the fourth bit line portion. The second interconnect structure is connected to the end of the second bit line portion that is away from the first bit line portion and the end of the fourth bit line portion that is adjacent to it in the third direction that is away from the third bit line portion. The first direction, the second direction, and the third direction intersect each other.

8. The semiconductor device according to claim 7, wherein, The first bit line portion, the second bit line portion, the third bit line portion, and the fourth bit line portion all extend continuously along the second direction.

9. The semiconductor device according to claim 6, wherein, The first interconnect structure is connected to the end of the first bit line portion that is away from the second bit line portion and the end of the third bit line portion that is aligned with it in the first direction that is away from the fourth bit line portion. The second interconnect structure is connected to the end of the second bit line portion that is away from the first bit line portion and the end of the fourth bit line portion that is aligned with it in the first direction that is away from the third bit line portion.

10. The semiconductor device according to claim 7 or 9, wherein, The first bit line portion includes a plurality of first bit line sub-portions arranged in the second direction, and the third bit line portion includes a plurality of third bit line sub-portions arranged in the second direction; The interconnection structure further includes a third interconnection structure, which is connected to the first bit line sub-part and the third bit line sub-part adjacent to it in the second direction, respectively. The second bit line portion includes a plurality of second bit line sub-portions arranged in the second direction, and the fourth bit line portion includes a plurality of fourth bit line sub-portions arranged in the second direction; The interconnect structure further includes a fourth interconnect structure, which is connected to the second bit line sub-part and the fourth bit line sub-part adjacent to it in the second direction.

11. The semiconductor device according to claim 1, wherein, The first bit line portion in the first bit line structure adjacent to the third direction and the third bit line portion in the second bit line structure are connected to the first sensing amplifier, and the second bit line portion in the first bit line structure adjacent to the third direction and the fourth bit line portion in the second bit line structure are connected to the second sensing amplifier, wherein the first direction, the second direction and the third direction intersect each other.

12. The semiconductor device according to claim 6, wherein, The semiconductor device further includes: A first capacitor is located on the side of the first channel structure opposite to the first bit line structure; and The second capacitor is located on the side of the second channel structure that is away from the second bit line structure.

13. The semiconductor device according to claim 12, wherein, The first capacitor includes: A first conductive portion extends along the first direction and is connected to the first channel structure; A first insulating layer covers the first conductive portion; and A first conductive layer covers the first insulating layer; The second capacitor includes: The second conductive portion extends along the first direction and is connected to the second channel structure; A second insulating layer covers the second conductive portion; and The second conductive layer covers the second insulating layer.

14. The semiconductor device according to claim 13, wherein, The first conductive layer connected to the first bit line portion and the second bit line portion is an integral structure, and the second conductive layer connected to the third bit line portion and the fourth bit line portion is an integral structure.

15. The semiconductor device according to claim 13, wherein, The first conductive layer, which is connected to the first bit line portion and the second bit line portion respectively, is a separate structure, and the second conductive layer, which is connected to the third bit line portion and the fourth bit line portion respectively, is a separate structure.

16. The semiconductor device according to claim 14 or 15, wherein, The first bit line portion and the second bit line portion are connected to the first conductive layer through the first channel structure, the first conductive portion and the first insulating layer, and the third bit line portion and the fourth bit line portion are connected to the second conductive layer through the second channel structure, the second conductive portion and the second insulating layer.

17. The semiconductor device according to claim 1, wherein, The first channel structure includes: The first main body extends along the first direction; A first extension portion is located at the end of the first main body portion that is away from the first bit line structure; and The second extension is located at the end of the first main body near the first bit line structure, wherein, in the second direction, the extension directions of the first extension and the second extension are opposite; The second channel structure includes: The second main body extends along the first direction; The third extension is located at the end of the second main body near the second bit line structure; and The fourth extension is located at the end of the second main body that is away from the second bit line structure, wherein, in the second direction, the extension directions of the third extension and the fourth extension are opposite.

18. The semiconductor device according to claim 17, wherein, Two first extensions in adjacent first channel structures in the second direction have opposite extension directions; The two fourth extensions in the second channel structures that are adjacent in the second direction have opposite extension directions.

19. The semiconductor device according to claim 17, wherein, In adjacent first main body portions in the second direction, the distance between the ends closer to the first bit line structure is greater than the distance between the ends away from the first bit line structure; In the adjacent second main body portions in the second direction, the distance between the ends closer to the second bit line structure is smaller than the distance between the ends away from the second bit line structure.

20. The semiconductor device according to claim 1 or 17, wherein, The materials of the first channel structure and the second channel structure include metal oxide semiconductor materials.

21. The semiconductor device according to claim 20, wherein, The metal oxide semiconductor material includes indium gallium zinc oxide.

22. The semiconductor device according to claim 17, wherein, The first main body portion has a size of 3nm to 10nm in the second direction, and the second main body portion has a size of 3nm to 10nm in the second direction.

23. The semiconductor device according to claim 17, wherein, The first main body portion has a larger dimension in the third direction than the first main body portion in the second direction, and the second main body portion has a larger dimension in the third direction than the second main body portion in the second direction, wherein the first direction, the second direction, and the third direction intersect each other.

24. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A first gate structure is located on one side of the first channel structure in the second direction and extends along a third direction; The first gate dielectric layer is located between the first channel structure and the first gate structure; The second gate structure is located on one side of the second channel structure in the second direction and extends along the third direction; The second gate dielectric layer is located between the second gate structure and the second channel structure; The first direction, the second direction, and the third direction intersect each other.

25. The semiconductor device according to claim 24, wherein, The first gate structure includes a first adhesive layer and a first metal structure that are bonded to each other. The first adhesive layer is located on one side of the first metal structure in the second direction and on the side of the first metal structure opposite to the first bit line structure in the first direction. The second gate structure includes a second adhesive layer and a second metal structure that are bonded together, the second adhesive layer being located on one side of the second metal structure in the second direction, and the second metal structure being located on the side of the second metal structure close to the second bit line structure in the first direction.

26. The semiconductor device according to claim 24, wherein, The semiconductor device further includes: A first isolation structure is located between adjacent first channel structures in the second direction and extends along the third direction; A second isolation structure is located between adjacent first gate structures in the second direction and extends along the third direction, wherein the first isolation structure and the second isolation structure are arranged alternately in the second direction; A third isolation structure is located between adjacent second channel structures in the second direction and extends along the third direction; and A fourth isolation structure is located between adjacent second gate structures in the second direction and extends along the third direction, wherein the third isolation structure and the fourth isolation structure are arranged alternately in the second direction.

27. The semiconductor device according to claim 26, wherein, The first isolation structure includes: A first conductive structure extends along the third direction; and A first dielectric layer is located between the first conductive structure and the first channel structure; The third isolation structure includes: A second conductive structure extends along the third direction; and The second dielectric layer is located between the second conductive structure and the second channel structure.

28. The semiconductor device according to claim 26, wherein, In the first direction, the first isolation structure and the third isolation structure are at least partially aligned.

29. The semiconductor device according to claim 12, wherein, The semiconductor device further includes: The peripheral circuit structure is located on the side of the first capacitor away from the first bit line structure, or on the side of the second capacitor away from the second bit line structure.

30. The semiconductor device according to claim 29, wherein, The semiconductor device further includes: A first connection structure extends along the first direction and connects to the end of the first bit line portion or the third bit line portion in the second direction; and The second connection structure extends along the first direction and connects to the end of the second bit line portion or the fourth bit line portion in the second direction.

31. The semiconductor device according to claim 1 or 17, wherein, The first channel structure and the second channel structure are formed by a thin film deposition process.

32. A memory system, comprising: The memory includes the semiconductor device as described in any one of claims 1 to 31; as well as A controller, coupled to the memory, is used to control the memory to store data.

33. A method for fabricating a semiconductor device, comprising: Forming a first channel structure extending along a first direction; A first bit line structure, an interconnect structure, and a second bit line structure are sequentially formed on one side of the first channel structure in the first direction, wherein the first bit line structure extends in the second direction, and the second bit line structure extends in the second direction; and A second channel structure extending along the first direction is formed on the side of the second line structure that is opposite to the first channel structure; Wherein, the first direction intersects with the second direction.

34. The preparation method according to claim 33, wherein, The first bit line structure, the interconnect structure, and the second bit line structure are sequentially formed on one side of the first channel structure in the first direction, including: The first bit line structure, the interconnect structure, and the second bit line structure are formed by a thin film deposition process.

35. The preparation method according to claim 33 or 34, wherein, Forming an interconnect structure on one side of the first channel structure in the first direction includes: The interconnect channels and interconnect lines are alternately formed, wherein the interconnect lines extend along the second direction and / or the third direction, and the interconnect channels are connected to the first bit line structure and the second bit line structure; The first direction, the second direction, and the third direction intersect each other.

36. The preparation method according to claim 33 or 34, wherein, The interconnect structure includes an interconnect channel extending along the first direction, wherein the end dimension of the interconnect channel near the first bit line structure is smaller than the end dimension near the second bit line structure.

37. The preparation method according to claim 33, wherein, The preparation method further includes: At least a portion of the first capacitor is formed on the side of the first channel structure opposite to the first bit line structure; and A second capacitor is formed on the side of the second channel structure that is away from the second bit line structure.

38. The preparation method according to claim 37, wherein, At least a portion of the first capacitor is formed on the side of the first channel structure opposite to the first bit line structure, including: A first conductive portion is formed extending along the first direction, wherein the first conductive portion is connected to the first channel structure; Forming a first insulating layer covering the first conductive portion; and A first conductive layer is formed covering the first insulating layer; The second capacitor is formed on the side of the second channel structure opposite to the second bit line structure, including: A second conductive portion is formed extending along the first direction, wherein the second conductive portion is connected to the second channel structure; Forming a second insulating layer covering the second conductive portion; and A second conductive layer is formed that covers the second insulating layer.

39. The preparation method according to claim 38, wherein, After the second conductive layer is formed, the first insulating layer and the first conductive layer are formed sequentially.

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