3D MIM capacitor structure and preparation method thereof

Abstract

The invention provides a 3D MIM capacitor structure and a preparation method thereof, and the method comprises the steps: firstly depositing a first TiN lower electrode layer with a (200) crystal face under a low-temperature deposition condition of a TiN material through a low-temperature template method, and then depositing a second TiN lower electrode layer at a temperature required by the deposition of a TiN material with a (111) crystal face, thereby forming a TiN lower electrode layer of the 3D MIM capacitor structure, and finally, annealing the TiN lower electrode by adopting a nitrogen-containing supercritical fluid to finally obtain a TiN lower electrode layer with low surface roughness and ensure small impedance Rs of the TiN lower electrode layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a 3D MIM capacitor structure and its fabrication method. Background Technology

[0002] MIM (Metal-Insulator-Metal) capacitors, also known as plate capacitors, have precise capacitance values ​​that do not change with bias voltage. In semiconductor devices, MIM capacitor structures are typically formed by a lower metal layer, an insulating dielectric layer, and an upper metal layer.

[0003] With the miniaturization of semiconductor devices, 3D MIM capacitor structures have emerged, enabling higher capacitance densities. However, in 3D MIM capacitor structures, the introduction of high aspect ratio trenches leads to varying degrees of gas diffusion and concentration at different locations during the deposition process of the TiN electrode plate. The interface treatment of the TiN electrode plate cannot be uniformly controlled like that of a flat plate, resulting in reduced step coverage of the high aspect ratio film and uneven film thickness at different locations. Surface defects in the film have a significant impact on the overall capacitor performance. Therefore, it is necessary to reduce the roughness of the upper surface of the lower electrode plate in the deep trench to reduce the leakage risk of the capacitor structure. Simultaneously, the impedance Rs of the TiN electrode affects the high-frequency performance of the device; a higher impedance is detrimental to the device's operation at high frequencies. Therefore, reducing the electrode impedance is also crucial.

[0004] For planar TiN electrodes, a low-resistivity TiN electrode layer can generally be obtained through high-temperature deposition. The resulting surface roughness can be mitigated by using an Asher (N2 / O2 plasma) process to oxidize the TiN electrode layer to TiON at the interface, thus reducing the risk of leakage. However, in 3D MIM capacitor structures, as the aspect ratio gradually increases, the film surface at the bottom of the trench cannot be effectively treated by Asher, thus failing to effectively reduce roughness.

[0005] Therefore, it is necessary to propose a 3D MIM capacitor structure and its fabrication method to reduce the impedance of the capacitor structure while ensuring the low surface roughness of the electrode under titanium nitride. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a 3D MIM capacitor structure and its fabrication method, which solves the problem in the prior art that the TiN electrode layer in a high aspect ratio 3D MIM capacitor structure cannot simultaneously satisfy the requirements of reducing surface roughness while maintaining low resistance.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a 3D MIM capacitor structure, the method comprising:

[0008] A substrate is provided, on which a dielectric layer is formed, and trenches are formed in the dielectric layer;

[0009] A first TiN lower electrode layer with (200) crystal planes is deposited on the bottom wall and sidewalls of the trench;

[0010] A second TiN lower electrode layer is deposited on the surface of the first TiN lower electrode layer; wherein the temperature at which the second TiN lower electrode layer is deposited is the temperature required to deposit a TiN material with a (111) crystal plane, and the ratio of the thickness D1 of the first TiN lower electrode layer to the thickness D2 of the second TiN lower electrode layer satisfies D1 / D2≥1 / 3;

[0011] The first TiN lower electrode layer and the second TiN lower electrode layer were annealed using a nitrogen-containing supercritical fluid.

[0012] Optionally, the temperature at which the first TiN under electrode layer is deposited is 300℃~320℃.

[0013] Optionally, the temperature for depositing the second TiN lower electrode layer is 360℃~390℃.

[0014] Optionally, the nitrogen-containing supercritical fluid is an N2O supercritical fluid or a NO supercritical fluid.

[0015] Furthermore, the nitrogen-containing supercritical fluid is an N2O supercritical fluid, and the annealing temperature using the nitrogen-containing supercritical fluid is 100℃~130℃, and the annealing time is 30min~60min.

[0016] Optionally, the first TiN lower electrode layer and the second TiN lower electrode layer are deposited using an ALD process.

[0017] Furthermore, the precursors used for depositing the first TiN lower electrode layer and the second TiN lower electrode layer using the ALD process include TiCl4 and NH3.

[0018] Optionally, after forming the second TiN lower electrode layer, the method further includes the step of sequentially depositing an insulating dielectric layer and a TiN upper electrode layer on the second TiN lower electrode layer.

[0019] Furthermore, the insulating dielectric layer is a stacked composite structure of ZrO2 / Al2O3 / ZrO2.

[0020] The present invention also provides a 3D MIM capacitor structure, which is prepared by the preparation method of the 3D MIM capacitor structure described in any one of the above claims.

[0021] As described above, the method for fabricating the 3D MIM capacitor structure of the present invention uses a low-temperature template method. First, a first TiN lower electrode layer with (200) crystal planes is deposited under low-temperature deposition conditions of TiN material. Then, a second TiN lower electrode layer is deposited at the temperature required for depositing TiN material with (111) crystal planes (i.e., under relatively high-temperature conditions), thereby forming the TiN lower electrode layer of the 3D MIM capacitor structure. Finally, the TiN lower electrode is annealed using a nitrogen-containing supercritical fluid. Since the first TiN lower electrode layer has (200) crystal planes, based on the face-centered cubic crystal structure characteristics of TiN material, the surface roughness of the first TiN lower electrode layer dominated by (200) crystal planes can be significantly reduced. This can be used as a template for the subsequent deposition of the second TiN lower electrode layer. This template enables the subsequent deposition of the second TiN lower electrode layer to preferentially grow according to the (200) crystal plane arrangement, resulting in a thin film with lower roughness. Furthermore, the deposition of the second TiN lower electrode layer uses the temperature required for depositing TiN material with (111) crystal planes, thereby obtaining a second TiN with low impedance Rs. Although the impedance Rs of the first TiN lower electrode layer with (200) crystal plane is relatively high, the equivalent impedance Rs of the entire TiN lower electrode layer increases slightly after combining it with the second TiN lower electrode layer with low impedance Rs. At this time, it is annealed with nitrogen-containing supercritical fluid. Under supercritical conditions, it can diffuse into the interior of the TiN lower electrode layer, eliminate nitrogen vacancies in the film, reduce film defects, reduce electron scattering, thereby reducing the impedance Rs of the TiN lower electrode layer, and finally obtain a TiN lower electrode layer with low surface roughness and ensure a small TiN lower electrode layer impedance Rs. Attached Figure Description

[0022] Figure 1 The diagram shows a cross-sectional view of an example MIM capacitor structure where the rough surface of the electrode layer causes leakage current in the capacitor structure.

[0023] Figures 2 to 5 The diagram shows cross-sectional structural schematics of each step in the fabrication method of the 3D MIM capacitor structure of the present invention, wherein... Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure of the TiN lower electrode layer along the deposition direction.

[0024] Component designation explanation

[0025] 10 substrate 11 Dielectric layer 110 trench 12 TiN under electrode layer 120 First TiN under-electrode layer 121 Second TiN under-electrode layer 13 Insulating dielectric layer 14 TiN top electrode layer Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0028] like Figure 1 As shown in the background section, 3D MIM capacitor structures are typically implemented using trenches. First, trenches are formed in the dielectric layer, and then the lower electrode layer 12, insulating dielectric layer 13, and upper electrode layer 14 of the 3D MIM capacitor structure are sequentially filled in the trenches. Therefore, the roughness of the contact surface between the lower electrode layer 12 and the insulating dielectric layer 13 (i.e., the upper surface of the lower electrode layer 12) has a significant impact on the leakage current of the MIM capacitor structure. The greater the roughness of the surface of the lower electrode layer 12, the greater the risk of leakage current in the MIM capacitor structure. In addition, in order to ensure the high-frequency characteristics of the MIM capacitor structure, a low-impedance Rs electrode layer is also crucial. However, for high aspect ratio 3D MIM capacitor structures, the high-temperature deposition combined with Asher process of planar MIM capacitor structure to form a TiN electrode layer with low impedance Rs and low roughness is not suitable. Due to the large aspect ratio of the trenches in the 3D MIM capacitor structure, the diffusion degree and concentration of gas flow are different at different positions when the high-temperature deposition process and Asher process are used to prepare the TiN electrode plate. The interface treatment of the TiN electrode plate cannot be uniformly controlled like that of a flat plate. This leads to a reduction in the step coverage of the high aspect ratio film, resulting in uneven film thickness at different positions. Furthermore, during the Asher process, the closer to the bottom of the trench, the more difficult it is for the Asher gas to penetrate, thus failing to effectively reduce roughness. Ultimately, this results in a high surface roughness of the TiN electrode layer.

[0029] Based on this, this embodiment provides a method for fabricating a 3D MIM capacitor structure. This method can reduce the impedance Rs of the TiN under electrode layer while maintaining low surface roughness, thereby improving the overall performance of the 3D MIM capacitor structure. The fabrication method includes the following steps:

[0030] S1, a substrate is provided, on which a dielectric layer is formed, and trenches are formed in the dielectric layer;

[0031] S2, deposit a first TiN lower electrode layer having a (200) crystal plane on the bottom wall and sidewall of the trench;

[0032] S3, deposit a second TiN lower electrode layer on the surface of the first TiN lower electrode layer; wherein, the temperature for depositing the second TiN lower electrode layer is the temperature required for depositing a TiN material with a (111) crystal plane, and the ratio of the thickness D1 of the first TiN lower electrode layer to the thickness D2 of the second TiN lower electrode layer satisfies D1 / D2≥1 / 3;

[0033] S4, the first TiN lower electrode layer and the second TiN lower electrode layer are annealed using a nitrogen-containing supercritical fluid.

[0034] The method for fabricating the 3D MIM capacitor structure in this embodiment uses a low-temperature template method. First, a first TiN lower electrode layer with (200) crystal planes is deposited under low-temperature deposition conditions of TiN material. Then, a second TiN lower electrode layer is deposited at the temperature required for depositing TiN material with (111) crystal planes (i.e., under relatively high temperature conditions), thereby forming the TiN lower electrode layer of the 3D MIM capacitor structure. Finally, the TiN lower electrode is annealed using a nitrogen-containing supercritical fluid. Since the first TiN lower electrode layer has (200) crystal planes, based on the face-centered cubic crystal structure characteristics of TiN material, the surface roughness of the first TiN lower electrode layer dominated by (200) crystal planes can be significantly reduced. This can be used as a template for the subsequent deposition of the second TiN lower electrode layer. This template enables the subsequent deposition of the second TiN lower electrode layer to preferentially grow according to the (200) crystal plane arrangement, resulting in a thin film with low roughness. Furthermore, the deposition of the second TiN lower electrode layer uses the temperature required for depositing TiN material with (111) crystal planes, thereby obtaining a second TiN with low impedance Rs. Although the impedance Rs of the first TiN lower electrode layer with (200) crystal plane is relatively high, the equivalent impedance Rs of the entire TiN lower electrode layer increases slightly after combining it with the second TiN lower electrode layer with low impedance Rs. At this time, it is annealed with nitrogen-containing supercritical fluid. Under supercritical conditions, it can diffuse into the interior of the TiN lower electrode layer, eliminate nitrogen vacancies in the film, reduce film defects, reduce electron scattering, thereby reducing the impedance Rs of the TiN lower electrode layer, and finally obtain a TiN lower electrode layer with low surface roughness and ensure a small TiN lower electrode layer impedance Rs.

[0035] The fabrication method of the 3D MIM capacitor structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0036] like Figure 2 As shown, step S1 is performed first, a substrate 10 is provided, on which a dielectric layer 11 is formed, and trenches 110 are formed in the dielectric layer 11.

[0037] It should be noted here that the focus of this embodiment is on the fabrication of a trench-type 3D MIM capacitor structure, therefore Figure 2 The specific structure of substrate 10 is not shown. In practice, the structure of substrate 10 is designed according to specific needs. It may be that the functional areas have already been manufactured, such as the source, drain and gate circuits, the circuit interconnection structure, the isolation structure, etc., which have already been designed in substrate 10. No excessive restrictions are imposed here.

[0038] The substrate 10 may comprise a single-layer semiconductor structure, such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, or a silicon-on-germanium insulating substrate, etc.; it may also comprise a multilayer structure, such as a silicon / silicon-germanium multilayer, etc. In this embodiment, the more commonly used silicon substrate is used as an example for illustration.

[0039] As an example, an electrical connection structure (not shown in the figure) is also formed in the substrate 10, which serves as the electrical lead-out structure of the TiN lower electrode layer in the subsequently formed 3D MIM capacitor structure.

[0040] The number of trenches 110, as well as the depth and diameter of each trench 110, are set according to actual needs and are not excessively limited here. When there are multiple trenches 110, the MIM capacitor structure therein is formed simultaneously using the fabrication method of this embodiment.

[0041] like Figure 3 and combined Figure 4 As shown, step S2 is then performed, where a first TiN lower electrode layer 120 having a (200) crystal plane is deposited on the bottom and sidewalls of the trench 110.

[0042] As a preferred example, the temperature for depositing the first TiN lower electrode layer 120 is in the range of 300℃ to 320℃, including the endpoint value, and 300℃ is preferred in this embodiment. TiN material has a face-centered cubic crystal structure. When TiN is deposited in the relatively low temperature range of 300℃ to 320℃, the (200) crystal plane of TiN is dominant. At this time, the roughness of the deposited TiN layer is greatly reduced, but the impedance will increase.

[0043] The first TiN lower electrode layer 120 can be deposited using existing conventional and applicable deposition processes, such as PVD deposition, CVD deposition, or ALD deposition. In this embodiment, ALD deposition is preferred to further improve the surface smoothness of the film.

[0044] like Figure 3 and combined Figure 4As shown, step S3 is then performed, whereby a second TiN lower electrode layer 121 is deposited on the surface of the first TiN lower electrode layer 120, so that the first TiN lower electrode layer 120 and the second TiN lower electrode layer 121 together constitute the TiN lower electrode layer 12 of the 3D MIM capacitor structure; wherein, the temperature for depositing the second TiN lower electrode layer 121 is the temperature required for depositing TiN material with (111) crystal plane, and the ratio of the thickness D1 of the first TiN lower electrode layer 120 to the thickness D2 of the second TiN lower electrode layer 121 satisfies D1 / D2≥1 / 3, that is, compared with the thickness of the first TiN lower electrode layer 120, the thickness of the second TiN lower electrode layer 121 cannot be too thick. If it is too thick, the template clamping effect of the first TiN lower electrode layer 120 on the second TiN lower electrode layer 121 will be worse, causing the second TiN lower electrode layer 121 to grow closer to the (111) crystal plane, resulting in an increase in surface roughness.

[0045] As a preferred example, the deposition temperature of the second TiN under electrode layer 121 is in the range of 360°C to 390°C, including the endpoint value, and 360°C is preferred in this embodiment. TiN material has a face-centered cubic crystal structure. When TiN is deposited in the relatively high temperature range of 360°C to 390°C, the (111) crystal plane of TiN is dominant. At this time, the deposited TiN layer has high roughness but low impedance. This embodiment is based on the characteristics of the face-centered cubic crystal structure of TiN material and utilizes the mechanism that different TiN material crystal planes can be obtained by deposition at different temperatures. The first TiN under electrode layer 120 with low roughness is used as the deposition template of the second TiN under electrode layer 121 to obtain a second TiN under electrode layer 121 with low roughness surface and low impedance within a reasonable thickness range. Moreover, the resistance of the TiN under electrode layer composed of the first and second TiN under electrode layers is not too high.

[0046] The second TiN lower electrode layer 121 can be deposited using existing conventional and applicable deposition processes, such as PVD deposition, CVD deposition, or ALD deposition. In this embodiment, ALD deposition is preferred to further improve the surface smoothness of the film. More preferably, both the first TiN lower electrode layer 1201 and the second TiN lower electrode layer 121 are prepared using ALD deposition. Furthermore, the precursors used for depositing the first TiN lower electrode layer 1201 and the second TiN lower electrode layer 121 are selected based on the deposition process used. For example, when both are prepared using ALD deposition, the precursors include TiCl4 and NH3.

[0047] As a specific example, the thickness of the first TiN lower electrode layer 120 is selected to be about 50 Å; the thickness of the second TiN lower electrode layer 121 is selected to be about 150 Å.

[0048] Finally, in step S4, the first TiN lower electrode layer 120 and the second TiN lower electrode layer 121 are annealed using a nitrogen-containing supercritical fluid.

[0049] Supercritical fluids are fluids whose temperature and pressure are both above their critical temperature (T). n ) and critical pressure (P) n The fluid in question exhibits neither the diffusivity of a gas nor the fluidity of a liquid; rather, it exists in a special state between gas and liquid, lacking a distinct phase interface and possessing the advantages of both, such as the solubility of a liquid and the diffusion coefficient of a gas. Therefore, using a nitrogen-containing supercritical fluid effectively utilizes its high diffusion coefficient and low viscosity, facilitating diffusion to the bottom of the trench and eliminating N vacancies in the TiN under-electrode layer 12. This reduces film defects, decreases electron scattering, and ultimately lowers impedance.

[0050] As an example, the nitrogen-containing supercritical fluid can be selected as either N2O supercritical fluid or NO supercritical fluid. Furthermore, when N2O supercritical fluid is selected, the annealing temperature using the nitrogen-containing supercritical fluid is 100℃~130℃, and the annealing time is 30min~60min. In this embodiment, an annealing temperature of 110℃ is preferred, and the annealing time is preferably 60min.

[0051] like Figure 5 As shown, as a specific example, after forming the second TiN lower electrode layer 121, the method further includes the step of sequentially depositing an insulating dielectric layer 13 and a TiN upper electrode layer 14 on the second TiN lower electrode layer 121. Further, the insulating dielectric layer 13 can be selected as a ZrO2 / Al2O3 / ZrO2 ZAZ stacked composite structure, but it is not limited to this; other materials suitable as insulating dielectric layers for capacitor structures can also be used. Additionally, when the TiN lower electrode layer 12, the insulating dielectric layer 13, and the TiN upper electrode layer 14 are also formed on the surface of the dielectric layer 11, the method further includes a step of removing them using a CMP process.

[0052] This embodiment also provides a 3D MIM capacitor structure, which can be prepared by the 3D MIM capacitor structure preparation method described above. The beneficial effects it can achieve can be found in the detailed description of the preparation method, and will not be repeated here.

[0053] In summary, this invention provides a 3D MIM capacitor structure and its fabrication method. Using a low-temperature template method, a first TiN lower electrode layer with (200) crystal planes is deposited under low-temperature deposition conditions of TiN material. Then, a second TiN lower electrode layer is deposited at the temperature required for depositing TiN material with (111) crystal planes (i.e., under relatively high-temperature conditions), thereby forming the TiN lower electrode layer of the 3D MIM capacitor structure. Finally, the TiN lower electrode is annealed using a nitrogen-containing supercritical fluid. Since the first TiN lower electrode layer has (200) crystal planes, based on the face-centered cubic crystal structure of TiN material, the surface roughness of the first TiN lower electrode layer dominated by (200) crystal planes can be significantly reduced. This serves as a template for the subsequent deposition of the second TiN lower electrode layer. This template enables the subsequently deposited second TiN lower electrode layer to preferentially grow according to the (200) crystal plane arrangement, resulting in a thin film with lower roughness. Furthermore, the deposition of the second TiN lower electrode layer uses the temperature required for depositing TiN material with (111) crystal planes, thereby obtaining a second TiN with low impedance Rs. Although the first TiN lower electrode layer with a (200) crystal plane has a relatively high impedance Rs, the equivalent impedance Rs of the entire TiN lower electrode layer increases slightly after combining it with a second TiN lower electrode layer with a low impedance Rs. At this point, annealing with a nitrogen-containing supercritical fluid allows the nitrogen to diffuse into the interior of the TiN lower electrode layer in a supercritical state, eliminating nitrogen vacancies in the film, reducing film defects, and decreasing electron scattering, thereby reducing the impedance Rs of the TiN lower electrode layer. Ultimately, a TiN lower electrode layer with low surface roughness and a low TiN lower electrode layer impedance Rs is obtained. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a 3D MIM capacitor structure, characterized in that, The preparation method includes: A substrate is provided, on which a dielectric layer is formed, and trenches are formed in the dielectric layer; A first TiN lower electrode layer with (200) crystal planes is deposited on the bottom wall and sidewalls of the trench; A second TiN lower electrode layer is deposited on the surface of the first TiN lower electrode layer; wherein the temperature at which the second TiN lower electrode layer is deposited is the temperature required to deposit a TiN material with a (111) crystal plane, and the ratio of the thickness D1 of the first TiN lower electrode layer to the thickness D2 of the second TiN lower electrode layer satisfies D1 / D2≥1 / 3; The first TiN lower electrode layer and the second TiN lower electrode layer were annealed using a nitrogen-containing supercritical fluid.

2. The method for fabricating the 3D MIM capacitor structure according to claim 1, characterized in that: The temperature at which the first TiN lower electrode layer is deposited is 300℃~320℃.

3. The method for fabricating the 3D MIM capacitor structure according to claim 1 or 2, characterized in that: The deposition temperature of the second TiN lower electrode layer is 360℃~390℃.

4. The method for fabricating the 3D MIM capacitor structure according to claim 1, characterized in that: The nitrogen-containing supercritical fluid is either N2O supercritical fluid or NO supercritical fluid.

5. The method for fabricating the 3D MIM capacitor structure according to claim 4, characterized in that: The nitrogen-containing supercritical fluid is N2O supercritical fluid, and the annealing temperature using nitrogen-containing supercritical fluid is 100℃~130℃, and the annealing time is 30min~60min.

6. The method for fabricating the 3D MIM capacitor structure according to claim 1, characterized in that: The first TiN lower electrode layer and the second TiN lower electrode layer were deposited using the ALD process.

7. The method for fabricating the 3D MIM capacitor structure according to claim 6, characterized in that: The precursors used for depositing the first TiN lower electrode layer and the second TiN lower electrode layer using the ALD process include TiCl4 and NH3.

8. The method for fabricating a 3D MIM capacitor structure according to claim 1, characterized in that: After forming the second TiN lower electrode layer, the method further includes the step of sequentially depositing an insulating dielectric layer and a TiN upper electrode layer on the second TiN lower electrode layer.

9. The method for fabricating the 3D MIM capacitor structure according to claim 8, characterized in that: The insulating dielectric layer is a stacked composite structure of ZrO2 / Al2O3 / ZrO2.

10. A 3D MIM capacitor structure, characterized in that, The 3D MIM capacitor structure is prepared using the method for preparing a 3D MIM capacitor structure as described in any one of claims 1 to 9.

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