Semiconductor structure and forming method thereof
By combining VFET technology with back-side power rail technology, a back-side dielectric layer and metal interconnect structure are formed on the back side of the semiconductor substrate, solving the problem of VFET device integration limitations and realizing a VFET structure with high integration and high performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2026-04-14
AI Technical Summary
The device integration density in VFET technology is limited and cannot meet the requirements of processes below 5nm.
By combining VFET technology with back-side power rail technology, three-dimensional device integration is achieved by forming a back-side dielectric layer and metal interconnect structure on the back side of the semiconductor substrate.
It improves the device integration of VFETs, meets the requirements of sub-5nm process, reduces the area of standard cells, and enhances chip performance.
Smart Images
Figure CN121865644A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] The increased integration density of integrated circuits is due to the miniaturization of the underlying field-effect transistors (FETs). However, in recent years, with the evolution of process nodes, lateral fin field-effect transistors (FinFETs) can no longer meet the process requirements below 5nm. The new generation of vertical field-effect transistors (VFETs) overcomes the limitations of lateral gate spacing and can meet the requirements of sub-5nm processes, making them an ideal replacement for lateral FinFETs.
[0003] VFET is a novel type of field-effect transistor device. Its channel is perpendicular to the wafer surface, with the source and drain terminals located on the top and bottom sides of the channel. The gate surrounds the channel. When the VFET is turned on, current flows through the channel from top to bottom or bottom to top, perpendicular to the wafer surface. This structure of the VFET is not limited by the gate spacing in FinFET and is considered a potential replacement for FinFET in the future.
[0004] Back power rails are an emerging interconnect technology. In traditional processes, devices are located on the wafer surface, and all interconnects are laid out on top of the devices. Back power rail technology, however, places some of the traces that would otherwise be on top of the devices on the back of the chip. Back power rails can increase trace resources, reduce the area of standard cells, and improve chip performance.
[0005] Current VFET technology limits device integration. Therefore, it is necessary to provide a more efficient and reliable technical solution that combines VFET technology with back-side power rail technology to improve VFET device integration. Summary of the Invention
[0006] This application provides a semiconductor structure and its formation method, which combines VFET process with back power rail technology to improve the device integration of VFET.
[0007] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including opposing front and back sides, the front side of the semiconductor substrate having an etch stop layer, a plurality of fin structures located on the etch stop layer, and a hard mask layer located on the top surface of the fin structures; forming an isolation structure in the etch stop layer and the semiconductor substrate on both sides of the fin structures; forming a bottom spacer layer on the front side of the etch stop layer on both sides of the fin structures; removing the semiconductor substrate and the etch stop layer to form an opening exposing the bottom spacer layer and the bottom surface of the fin structures; forming a lower source drain in the opening, the back side of the lower source drain being not lower than the back side of the isolation structure; forming a back dielectric layer and a back metal interconnect structure electrically connecting the lower source drain in the back dielectric layer on the back side of the lower source drain and the isolation structure.
[0008] In some embodiments of this application, the step of forming the bottom spacer layer precedes the step of forming the isolation structure.
[0009] In some embodiments of this application, after forming a bottom spacer layer on the front side of the etch stop layer on both sides of the fin structure, the method further includes: forming a gate structure and an interfin dielectric layer on the surface of the bottom spacer layer, the sidewall of the fin structure, and the sidewall of the hard mask layer; etching the gate structure and the hard mask layer so that the top surface of the gate structure is lower than the top surface of the fin structure and removing the hard mask layer; forming a top spacer layer on a portion of the sidewall of the fin structure and the top surface of the gate structure; forming an upper source drain on the top surface of the fin structure and the top spacer layer; forming a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain in the front dielectric layer on the surface of the upper source drain and the interfin dielectric layer.
[0010] In some embodiments of this application, the gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer, the fin structure, and the sidewall of the hard mask layer.
[0011] In some embodiments of this application, the method of removing the semiconductor substrate and the etch stop layer to form an opening exposing the bottom spacer layer and the bottom surface of the fin structure includes: thinning the back side of the semiconductor substrate to expose the bottom surface of the isolation structure; etching the back side of the semiconductor substrate to expose the etch stop layer; and removing the etch stop layer to expose the bottom spacer layer and the bottom surface of the fin structure.
[0012] In some embodiments of this application, the bottom surface of the fin structure is not lower than the bottom surface of the bottom spacer layer.
[0013] Another aspect of this application provides a semiconductor structure, including: a lower source drain, wherein a plurality of fin structures are formed on the front side of the lower source drain, and isolation structures for isolating adjacent lower source drains are formed on both sides of the fin structures, and the back side of the lower source drain is not lower than the back side of the isolation structures; a bottom spacer layer is formed on the front side of the lower source drains and the isolation structures on both sides of the fin structures; a back dielectric layer and a back metal interconnect structure electrically connected to the lower source drain are formed on the back side of the lower source drains and the isolation structures.
[0014] In some embodiments of this application, a gate structure is further formed on the surface of the bottom spacer layer and part of the sidewalls of the fin structure, the top surface of the gate structure being lower than the top surface of the fin structure; a top spacer layer is further formed on part of the sidewalls of the fin structure and the top surface of the gate structure; an interfinite dielectric layer is formed on the surface of the gate structure, the top surface of the interfinite dielectric layer being higher than the top surface of the fin structure; an upper source drain is formed on the top surface of the fin structure and the top spacer layer; a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain are formed on the surface of the upper source drain and the interfinite dielectric layer.
[0015] In some embodiments of this application, the gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer, the fin structure, and the sidewall of the hard mask layer.
[0016] In some embodiments of this application, the bottom surface of the fin structure is not lower than the bottom surface of the bottom spacer layer.
[0017] This application provides a semiconductor structure and its formation method, which combines VFET process with back power rail technology to improve the device integration of VFET. Attached Figure Description
[0018] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0019] in:
[0020] Figures 1 to 11 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation
[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0023] Figures 1 to 11 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.
[0024] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a front side and a back side opposite to each other, the front side of the semiconductor substrate 100 having an etch stop layer 101, a plurality of fin structures 110 located on the etch stop layer 101, and a hard mask layer 111 located on the top surface of the fin structures 110.
[0025] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0026] It should be noted that the terms "front side," "back side," "top surface," and "bottom surface" used in the embodiments of this application refer to the accompanying drawings of the embodiments of this application. Specifically, "front side" and "top surface" refer to the upward direction in the drawings, that is, the surface on the semiconductor substrate 100 in the direction in which the fin structure 110 is formed; conversely, "back side" and "bottom surface" refer to the downward direction in the drawings, that is, the surface on the semiconductor substrate 100 in the direction opposite to the fin structure 110.
[0027] In some embodiments of this application, the etch stop layer 101 is required to be a material with a high etch selectivity (e.g., greater than 10) for the semiconductor substrate 100 and the subsequent isolation structure, such as a germanium silicide with a different germanium content than the initial channel layer, or a dielectric material such as a nitrogen-containing silicide, an oxygen-containing silicide, or a silicon oxynitride.
[0028] In some embodiments of this application, the fin structure 110 can be formed by etching an epitaxial layer after forming an epitaxial layer on the surface of the etch stop layer 101. The hard mask layer 111 serves as a mask during the etching process to form the fin structure 110. There can be multiple fin structures 110; for simplicity, only one fin structure 110 is shown here as an example.
[0029] refer to Figure 2 As shown, an isolation structure 120 is formed in the etch stop layer 101 and the semiconductor substrate 100 on both sides of the fin structure 110.
[0030] In some embodiments of this application, the material of the isolation structure 120 includes insulating materials such as silicon oxide or silicon nitride. The isolation structure 120 is used to isolate adjacent active regions.
[0031] refer to Figure 3 As shown, a bottom spacer layer 130 is formed on the front side of the etching stop layer 101 and the isolation structure 120 on both sides of the fin structure 110.
[0032] In some embodiments of this application, the bottom spacer layer 130 is made of a dielectric material, such as SiN, SiO, SiON, etc.
[0033] In some embodiments of this application, reference is made to Figure 2 and Figure 3 As shown, the step of forming the bottom spacer layer 130 is after the step of forming the isolation structure 120, that is, the isolation structure 120 is formed first and then the bottom spacer layer 130 is formed. Therefore, the isolation structure 120 is located in the semiconductor substrate 100 and the etch stop layer 101.
[0034] In other embodiments of this application, reference is made to Figure 4 As shown, the step of forming the bottom spacer layer 130 occurs before the step of forming the isolation structure 120; that is, the bottom spacer layer 130 is formed first, and then the isolation structure 120 is formed. Therefore, the isolation structure 120 is located in the semiconductor substrate 100, the etch stop layer 101, and the bottom spacer layer 130.
[0035] refer to Figure 5 As shown (in order) Figure 3 (as shown in the steps), a gate structure 150 and an interfin dielectric layer 160 are formed on the surface of the bottom spacer layer 130, the sidewall of the fin structure 110, and the sidewall of the hard mask layer 111.
[0036] In some embodiments of this application, the gate structure 150 includes conventional gate structure layers such as a gate dielectric layer, a work function layer, and a gate metal layer, sequentially located on the surface of the bottom spacer layer 130, the sidewall of the fin structure 110, and the sidewall of the hard mask layer 111. The gate dielectric layer is composed of multiple layers of high-dielectric-constant dielectric materials such as silicon oxide and hafnium oxide. The work function layer is made of materials such as titanium nitride. The gate metal layer is made of materials such as titanium.
[0037] In some embodiments of this application, the material of the interfin dielectric layer 160 includes insulating materials such as silicon oxide or silicon nitride.
[0038] refer to Figure 6 As shown, the gate structure 150 and the hard mask layer 111 are etched so that the top surface of the gate structure 150 is lower than the top surface of the fin structure 110, and the hard mask layer 111 is removed. The height difference between the top surfaces of the gate structure 150 and the fin structure 110 defines the height of the subsequently formed top spacer layer. This height difference can be set according to specific needs.
[0039] refer to Figure 7 As shown, a top spacer layer 141 is formed on the sidewalls of a portion of the fin structure 110 and on the top surface of the gate structure 150. The top surface of the top spacer layer 141 is flush with the top surface of the fin structure 110. The material of the top spacer layer 141 can be the same as the material of the bottom spacer layer 130.
[0040] refer to Figure 8 As shown, an upper source drain 171 is formed on the top surface of the fin structure 110 and the top spacer layer 141. The top surface of the upper source drain 171 may be higher than, lower than or flush with, the top surface of the interfin dielectric layer 160.
[0041] In some embodiments of this application, the upper source drain 171 is formed using an in-situ doping epitaxial growth process on the fin structure 110 as a substrate. The doping type of the upper source drain 171 is set according to device requirements and can be P-type or N-type.
[0042] The method for forming the semiconductor structure described in this application further includes: forming a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain in the front dielectric layer on the surface of the upper source drain 171 and the interfin dielectric layer 160. For the sake of brevity, the front dielectric layer and the front metal interconnect structure are omitted here.
[0043] In some embodiments of this application, the surface of the upper source drain 171 may be formed with metal silicide for electrically connecting the front metal interconnect structure.
[0044] refer to Figure 9As shown, removing the semiconductor substrate 100 and the etch stop layer 101 from the back side of the semiconductor substrate forms an opening 181 that exposes the bottom spacer layer 130 and the bottom surface of the fin structure 110.
[0045] In some embodiments of this application, the method of removing the semiconductor substrate 100 and the etch stop layer 101 to form an opening 181 exposing the bottom spacer layer 130 and the bottom surface of the fin structure 110 includes: thinning the back side of the semiconductor substrate 100 to expose the bottom surface of the isolation structure 120; etching the back side of the semiconductor substrate 100 to expose the etch stop layer 101; and etching away the etch stop layer 101 to expose the bottom spacer layer 130 and the bottom surface of the fin structure 110. The material of the etch stop layer 101 has a high etch selectivity greater than 10 for the bottom spacer layer 130, so etching can stop at the bottom spacer layer 130, and the bottom spacer layer 130 can serve as an etch stop signal.
[0046] In some embodiments of this application, the bottom surface of the fin structure 110 is not lower than (higher than or flush with) the bottom surface of the bottom spacer layer 130.
[0047] refer to Figure 10 As shown, a lower source drain 170 is formed in the opening 181, and the back side of the lower source drain 170 is not lower than the back side of the isolation structure 120.
[0048] In some embodiments of this application, the lower source / drain 170 is formed using an in-situ doped epitaxial growth process on the fin structure 110 as a substrate. The doping type of the lower source / drain 170 is set according to device requirements and can be P-type or N-type.
[0049] refer to Figure 11 As shown, a back dielectric layer 190 and a back metal interconnect structure 191 electrically connected to the lower source drain 170 are formed on the back side of the lower source drain 170 and the isolation structure 120.
[0050] In some embodiments of this application, the material of the back dielectric layer 190 includes silicon oxide or a low-k dielectric material, etc.
[0051] In some embodiments of this application, the material of the back metal interconnect structure 191 includes copper or tungsten, etc.
[0052] In some embodiments of this application, the surface of the lower source drain 170 may be formed with metal silicide for electrically connecting the back metal interconnect structure 191.
[0053] This application provides a method for forming a semiconductor structure that combines VFET process with back-side power rail technology, thereby improving the device integration density of VFET.
[0054] Embodiments of this application also provide a semiconductor structure, referencing Figure 11 As shown, it includes: a lower source drain 170, the lower source drain 170 having a plurality of fin structures 110 formed on its front side, and isolation structures 120 forming on both sides of the fin structures 110 to isolate adjacent lower source drains 170, the back side of the lower source drain 170 being not lower than the back side of the isolation structures 120; a bottom spacer layer 130 forming on the front side of the lower source drains 170 and the isolation structures 120 on both sides of the fin structures 110; a back dielectric layer 190 forming on the back side of the lower source drains 170 and the isolation structures 180, and a back metal interconnect structure 191 electrically connected to the lower source drains 170 in the back dielectric layer 190.
[0055] It should be noted that the terms "front side," "back side," "top side," and "bottom side" used in the embodiments of this application refer to the accompanying drawings of the embodiments of this application. Specifically, "front side" and "top side" refer to the upward direction in the drawings, that is, the surface on the lower source drain 170 in the direction in which the fin structure 110 is formed; conversely, "back side" and "bottom side" refer to the downward direction in the drawings, that is, the surface on the lower source drain 170 in the direction opposite to the fin structure 110.
[0056] In some embodiments of this application, the number of fin structures 110 may be multiple. For the sake of brevity, only one fin structure 110 is shown here as an example.
[0057] In some embodiments of this application, the material of the isolation structure 120 includes insulating materials such as silicon oxide or silicon nitride. The isolation structure 120 is used to isolate adjacent lower source drains 170.
[0058] In some embodiments of this application, the bottom spacer layer 130 is made of a dielectric material, such as SiN, SiO, SiON, etc.
[0059] Continue to refer to Figure 11 As shown, a gate structure 150 is also formed on the surface of the bottom spacer layer 130 and part of the sidewall of the fin structure 110, and the top surface of the gate structure 150 is lower than the top surface of the fin structure 110.
[0060] In some embodiments of this application, the gate structure 150 includes conventional gate structure layers such as a gate dielectric layer, a work function layer, and a gate metal layer, sequentially located on the surface of the bottom spacer layer 130, the sidewall of the fin structure 110, and the sidewall of the hard mask layer 111. The gate dielectric layer is made of high- or low-dielectric-constant dielectric materials such as silicon oxide or hafnium oxide. The work function layer is made of materials such as titanium nitride. The gate metal layer is made of materials such as titanium.
[0061] Continue to refer toFigure 11 As shown, a top spacer layer 141 is also formed on the sidewall of part of the fin structure 110 and the top surface of the gate structure 150.
[0062] In some embodiments of this application, the top surface of the top spacer layer 141 is flush with the top surface of the fin structure 110. The material of the top spacer layer 141 may be the same as the material of the bottom spacer layer 130.
[0063] Continue to refer to Figure 11 As shown, an interfin dielectric layer 160 is formed on the surface of the gate structure 150, and the top surface of the interfin dielectric layer 160 is higher than the top surface of the fin structure 110.
[0064] In some embodiments of this application, the material of the interfin dielectric layer 160 includes insulating materials such as silicon oxide or silicon nitride.
[0065] Continue to refer to Figure 11 As shown, an upper source drain 171 is formed on the top surface of the fin structure 110 and the top spacer layer 141.
[0066] In some embodiments of this application, the top surface of the upper source drain 171 may be higher than, lower than or flush with the top surface of the interfin dielectric layer 160.
[0067] In some embodiments of this application, the upper source drain 171 is formed using an in-situ doping epitaxial growth process on the fin structure 110 as a substrate. The doping type of the upper source drain 171 is set according to device requirements and can be P-type or N-type.
[0068] In embodiments of this application, a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain 171 are further formed on the surfaces of the upper source drain 171 and the interfin dielectric layer 160. For the purpose of brevity, the front dielectric layer and the front metal interconnect structure are omitted here.
[0069] In some embodiments of this application, the surface of the upper source drain 171 may be formed with metal silicide for electrically connecting the front metal interconnect structure.
[0070] In some embodiments of this application, the bottom surface of the fin structure 110 is not lower than (higher than or flush with) the bottom surface of the etch stop layer 130.
[0071] In some embodiments of this application, the lower source / drain 170 is formed using an in-situ doped epitaxial growth process on the fin structure 110 as a substrate. The doping type of the lower source / drain 170 is set according to device requirements and can be P-type or N-type.
[0072] Continue to refer to Figure 11As shown, a back dielectric layer 190 and a back metal interconnect structure 191 electrically connected to the lower source drain 170 are formed on the back side of the lower source drain 170 and the isolation structure 120.
[0073] In some embodiments of this application, the material of the back dielectric layer 190 includes silicon oxide or silicon nitride, etc.
[0074] In some embodiments of this application, the material of the back metal interconnect structure 191 includes copper or tungsten, etc.
[0075] In some embodiments of this application, the surface of the lower source drain 170 may be formed with metal silicide for electrically connecting the back metal interconnect structure 191.
[0076] This application provides a semiconductor structure and its formation method, which combines VFET process with back power rail technology to improve the device integration of VFET.
[0077] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0078] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0079] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0080] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0081] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a front side and a back side opposite to each other, the front side of the semiconductor substrate having an etch stop layer and a plurality of fin structures located on the etch stop layer; An isolation structure is formed in the etch stop layer and the semiconductor substrate on both sides of the fin structure; A bottom spacer layer is formed on the front side of the etching stop layer on both sides of the fin structure; The semiconductor substrate and the etch stop layer are removed from the back side of the semiconductor substrate to form an opening that exposes the bottom spacer layer and the bottom surface of the fin structure; A lower source drain is formed in the opening; A back dielectric layer and a back metal interconnect structure electrically connecting the lower source drain are formed on the back side of the lower source drain and the isolation structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the bottom spacer layer occurs before the step of forming the isolation structure.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the bottom spacer layer on the front side of the etching stop layer on both sides of the fin structure, the method further includes: A gate structure and an interfin dielectric layer are formed on the surface of the bottom spacer layer and on the sidewalls of the fin structure; The gate structure is etched so that the top surface of the gate structure is lower than the top surface of the fin structure; A top spacer layer is formed on the sidewalls of some fin structures and on the top surface of the gate structure; An upper source drain is formed on the top surface of the fin structure and the top spacer layer; A front dielectric layer and a front metal interconnect structure electrically connecting the upper source drain are formed on the surface of the upper source drain and the interfin dielectric layer.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer and the sidewall of the fin structure.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for removing the semiconductor substrate and the etch stop layer to form an opening exposing the bottom spacer layer and the bottom surface of the fin structure includes: Thin the back side of the semiconductor substrate to expose the bottom surface of the isolation structure; Etch the back side of the semiconductor substrate until the etch stop layer is exposed; Remove the etching stop layer to expose the bottom spacer layer and the bottom surface of the fin structure.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The bottom surface of the fin structure is not lower than the bottom surface of the bottom spacer layer.
7. A semiconductor structure, characterized in that, include: The lower source drain has a plurality of fin structures formed on its front side, and isolation structures that isolate adjacent lower source drains are formed on both sides of the fin structures. The lower source drain and the front of the isolation structure on both sides of the fin structure have bottom spacer layers formed. The lower source drain and isolation structure have a back dielectric layer formed on the back side and a back metal interconnect structure electrically connected to the lower source drain in the back dielectric layer.
8. The semiconductor structure as described in claim 7, characterized in that, A gate structure is also formed on the surface of the bottom spacer layer and part of the sidewalls of the fin structure, with the top surface of the gate structure being lower than the top surface of the fin structure; a top spacer layer is also formed on part of the sidewalls of the fin structure and the top surface of the gate structure; an interfinite dielectric layer is formed on the surface of the gate structure, with the top surface of the interfinite dielectric layer being higher than the top surface of the fin structure; an upper source drain is formed on the top surface of the fin structure and the top spacer layer; a front dielectric layer and a front metal interconnect structure electrically connected to the upper source drain are formed on the surface of the upper source drain and the interfinite dielectric layer.
9. The semiconductor structure as described in claim 8, characterized in that, The gate structure includes a gate dielectric layer, a work function layer, and a gate metal layer, which are sequentially located on the surface of the bottom spacer layer and the sidewall of the fin structure.
10. The semiconductor structure as claimed in claim 7, characterized in that, The bottom surface of the fin structure is not lower than the bottom surface of the bottom spacer layer.