Carbon-based CMOS semiconductor structure and integrated circuit

Abstract

The invention provides a carbon-based CMOS semiconductor structure and an integrated circuit. The structure comprises a substrate, an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor) structure are formed on the substrate, and the NMOS structure comprises an NMOS channel layer which is positioned on the substrate and is made of a carbon nanotube; the NMOS grid electrode is positioned on the NMOS channel layer; the NMOS drain electrode covers and makes contact with one end of the NMOS channel layer, is located on one side of the NMOS grid electrode and comprises an NMOS drain electrode interface contact layer and a drain electrode conductive filling layer, and the NMOS drain electrode interface contact layer is a semi-metal type metal nitride and can conduct N-type doping on the carbon nano tube; the NMOS source electrode covers and is in contact with the other end of the NMOS channel layer and is located on the other side of the NMOS grid electrode, the NMOS source electrode comprises an NMOS source electrode interface contact layer and an NMOS source electrode conductive filling layer, the NMOS source electrode interface contact layer is a semi-metal type metal nitride and can perform N-type doping on the carbon nano tube, and the thickness of the NMOS drain electrode interface contact layer and the NMOS source electrode interface contact layer is 5-20 nm.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a carbon-based CMOS semiconductor structure and integrated circuit. Background Technology

[0002] The contact points between the source and drain electrodes and the channel in carbon-based devices are the core interface for current transmission. This interface affects the magnitude of contact resistance and the stability of the contact interface. Excessive contact resistance increases device power consumption and causes heat generation, thus limiting switching speed and energy efficiency. The stability of the contact interface affects the device's lifespan; poor contact can lead to signal attenuation and failure. Current carbon-based NMOS devices mostly use scandium (Sc) metal for channel contact, but this metal is easily oxidized, causing contact resistance to spike. Furthermore, for carbon-based PMOS devices, palladium (Pd) metal is often used for channel contact. This metal's coefficient of thermal expansion is mismatched with that of carbon nanotubes, resulting in relatively poor device reliability. These problems are particularly pronounced in small devices.

[0003] Therefore, a solution is needed that can achieve carbon-based devices with low contact resistance and stable contact interfaces, while meeting industrialization requirements. Summary of the Invention

[0004] This disclosure provides a carbon-based CMOS semiconductor structure and integrated circuit.

[0005] According to one aspect of this disclosure, a carbon-based CMOS semiconductor structure is provided, including a substrate on which an NMOS semiconductor structure and a PMOS semiconductor structure are formed. The NMOS semiconductor structure includes: an NMOS channel layer located on the substrate, the NMOS channel layer being made of carbon nanotubes; an NMOS gate located on the NMOS channel layer; an NMOS drain covering and contacting one end of the NMOS channel layer and located on one side of the NMOS gate, the NMOS drain including an NMOS drain interface contact layer and an NMOS drain conductive filling layer, wherein the NMOS drain interface contact layer is a half-metallic metal nitride capable of N-type doping of the carbon nanotubes; and an NMOS source covering and contacting the other end of the NMOS channel layer. The NMOS source includes an NMOS source interface contact layer and an NMOS source conductive filling layer, wherein the NMOS source interface contact layer is a half-metallic metal nitride capable of N-type doping of carbon nanotubes, and the thickness of the NMOS drain interface contact layer and the NMOS source interface contact layer is 5-20 nm; the PMOS semiconductor structure includes: a PMOS channel layer located on the substrate, the material of the PMOS channel layer being carbon nanotubes; and a PMOS gate, a PMOS drain, and a PMOS source, wherein the PMOS gate is located on the PMOS channel layer, and the PMOS drain and PMOS source are located on both sides of the PMOS gate and at least on both ends of the PMOS channel layer.

[0006] According to one aspect of the technical solution disclosed herein, both the NMOS source and drain interface contact layers are made of half-metallic metal nitrides, possessing both N-type doping capabilities for carbon nanotubes and contact transport capabilities. During fabrication, doping is achieved through the inherent properties of the material, resulting in higher doping uniformity and significantly improved contact interface stability. No additional ion implantation doping step is required, avoiding damage caused by ion implantation. The NMOS source and drain interface contact layers can be fabricated using atomic layer deposition (ALD) technology, which is particularly suitable for small-size devices (source / drain widths of 100–400 nm) and high aspect ratio contact holes. The thickness of the NMOS source and drain interface contact layers is 5–20 nm, ensuring sufficient doping and low contact resistance, thus guaranteeing excellent device performance.

[0007] According to at least one embodiment of the carbon-based CMOS semiconductor structure of this disclosure, the lengths of the NMOS gate and the PMOS gate are less than or equal to 90 nm, the widths of the NMOS gate and the PMOS gate are 150–500 nm, the widths of the NMOS source and the PMOS source are 100–400 nm, and the widths of the NMOS drain and the PMOS drain are 100–400 nm, wherein the length is the dimension along the source-drain current direction, and the width is the dimension perpendicular to the source-drain current direction.

[0008] According to the technical solution of this embodiment, the gate length design can significantly reduce the area occupied by a single device, enabling high-density device array integration. The gate width design can ensure sufficient drive current and avoid excessive width leading to an increase in the area of ​​a single device. In addition, the source and drain widths are designed to match the gate width, effectively controlling the parasitic resistance and capacitance of the source and drain, and improving the switching speed and frequency response characteristics of the device.

[0009] According to at least one embodiment of the carbon-based CMOS semiconductor structure of the present disclosure, the NMOS drain interface contact layer covers the upper surface and side surface of one end of the NMOS channel layer, and the NMOS source interface contact layer covers the upper surface and side surface of the other end of the NMOS channel layer.

[0010] According to the technical solution of this embodiment, the effective contact area between the NMOS drain interface contact layer and the NMOS source interface contact layer and the channel layer is increased, thereby significantly reducing the contact resistance. This can greatly reduce energy loss during carrier transport and meet the low power consumption requirements of small-size devices. In addition, it can also enhance the interfacial bonding force between the interface contact layer and the channel, thereby ensuring the stability of the contact interface.

[0011] According to at least one embodiment of the carbon-based CMOS semiconductor structure of this disclosure, the material of the NMOS drain interface contact layer and the NMOS source interface contact layer is tantalum nitride, and the material of the NMOS drain conductive filling layer and the NMOS source conductive filling layer is copper or ruthenium.

[0012] According to at least one embodiment of the carbon-based CMOS semiconductor structure of this disclosure, the NMOS drain interface contact layer and the NMOS source interface contact layer are formed simultaneously by an atomic layer deposition process.

[0013] In the technical solution of this embodiment, the interface contact layer between the drain and source of NMOS is formed simultaneously using the same atomic layer deposition process. This ensures that the thickness uniformity, composition consistency and film density of the two are exactly the same, avoiding the process parameter fluctuations caused by batch deposition. This ensures that the key performance parameters such as the contact resistance and doping efficiency of the source and drain are highly matched, improves the current transmission symmetry of the NMOS device, and reduces signal distortion during the switching process.

[0014] According to at least one embodiment of the carbon-based CMOS semiconductor structure of this disclosure, the NMOS gate and the PMOS gate are a stacked structure formed of the same material, the stacked structure including a hafnium dioxide layer, a titanium nitride layer and a tantalum nitride layer.

[0015] In this embodiment, the NMOS and PMOS gates are formed using a stacked structure made of the same material, eliminating the need for different gate material systems and deposition processes for the two devices. A global gate thin film can be fabricated simultaneously in the same process, followed by photolithography etching to pattern the gates of both types of devices. This reduces process steps and significantly lowers the production cost and process complexity of large-scale integration.

[0016] According to at least one embodiment of the carbon-based CMOS semiconductor structure of this disclosure, the thickness of the hafnium dioxide layer is 3-5 nm.

[0017] According to at least one embodiment of the carbon-based CMOS semiconductor structure of this disclosure, the PMOS drain includes a PMOS drain interface contact layer and a PMOS drain conductive filling layer, the PMOS drain interface contact layer covers and contacts one end of the PMOS channel layer, and the PMOS drain conductive filling layer fills the hollow space formed by the PMOS drain interface contact layer; the PMOS source includes a PMOS source interface contact layer and a PMOS source conductive filling layer, the PMOS source interface contact layer covers and contacts the other end of the PMOS channel layer, and the PMOS source conductive filling layer fills the hollow space formed by the PMOS source interface contact layer.

[0018] According to the technical solution of this embodiment, both the PMOS source and drain interface contact layers are made of half-metallic metal oxides, possessing both p-type doping capabilities for carbon nanotubes and contact transport capabilities. During fabrication, doping is achieved through the inherent properties of the material, resulting in higher doping uniformity and significantly improved contact interface stability. No additional ion implantation doping step is required, avoiding damage caused by ion implantation. The PMOS source and drain interface contact layers can be fabricated using atomic layer deposition (ALD) technology, which is particularly suitable for small-sized devices (source / drain widths of 100–400 nm) and high aspect ratio contact holes.

[0019] According to at least one embodiment of the carbon-based CMOS semiconductor structure of this disclosure, the materials of the PMOS drain interface contact layer and the PMOS source interface contact layer are both ruthenium dioxide or iridium dioxide; the materials of the PMOS drain conductive filling layer and the PMOS source conductive filling layer are both ruthenium.

[0020] According to at least one embodiment of the carbon-based CMOS semiconductor structure of this disclosure, the thickness of the PMOS drain interface contact layer and the PMOS source interface contact layer is 5 to 20 nm.

[0021] According to the technical solution of this embodiment, the thickness of the PMOS source interface contact layer and the PMOS drain interface contact layer is 5-20nm, which ensures sufficient doping and low contact resistance, thus ensuring excellent device performance.

[0022] According to another aspect of this disclosure, an integrated circuit is provided, comprising: a plurality of NMOS semiconductor structures and a plurality of PMOS semiconductor structures in a carbon-based CMOS semiconductor structure as described in any of the preceding claims; and a metal interconnect for connecting the plurality of NMOS semiconductor structures and the plurality of PMOS semiconductor structures. Attached Figure Description

[0023] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0024] Figure 1 This is a schematic diagram of an N-type semiconductor structure of a carbon-based CMOS semiconductor structure according to an embodiment of the present disclosure.

[0025] Figure 2 This is a schematic diagram of an N-type semiconductor structure of a carbon-based CMOS semiconductor structure according to an embodiment of the present disclosure.

[0026] Figure 3 This is a schematic diagram of a P-type semiconductor structure of a carbon-based CMOS semiconductor structure according to an embodiment of the present disclosure.

[0027] Figure 4 This is a schematic diagram of a P-type semiconductor structure of a carbon-based CMOS semiconductor structure according to an embodiment of the present disclosure.

[0028] Figure 5 This is a schematic diagram of a carbon-based CMOS semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0029] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0030] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0032] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0033] This application provides a carbon-based CMOS semiconductor structure. This carbon-based CMOS semiconductor structure may include an NMOS semiconductor structure and a PMOS semiconductor structure.

[0034] Figure 1 A schematic diagram of an NMOS semiconductor structure according to an embodiment of the present disclosure is shown. Figure 1 As shown, the NMOS semiconductor structure 100 may include a substrate 110, an NMOS channel layer 120, an NMOS gate 130, an NMOS source 140, and an NMOS drain 150.

[0035] The substrate 110 is made of one or more combinations of semiconductors, rigid insulating materials, or high-temperature resistant flexible insulating materials that are compatible with the channel layer and fabrication process. For example, rigid materials such as silicon, silicon oxide, silicon nitride, quartz, glass, and alumina can be used, or flexible materials such as PET (polyethylene terephthalate), PEN (polyethylene naphthalate), and polyimide can be used. The surface of the substrate 110 has good flatness, providing a stable support interface for the transfer or growth of the NMOS channel layer 120 above. The NMOS channel layer 120 is formed on the upper surface of the substrate 110 and is the core region for carrier transport in the device. Its material is preferably undoped carbon nanotubes. Specifically, it can be a carbon nanotube thin film, carbon nanotube array, carbon nanotube network thin film (such as a neatly arranged self-assembled thin film), or a composite thin film of the above forms with a purity of 90% to 99.9999%. The thickness of the NMOS channel layer 120 is controlled within the range of greater than 0 nm and ≤10 nm. This thickness design ensures both the intrinsic high carrier mobility of carbon nanotubes and the integration requirements of small-sized devices.

[0036] The NMOS gate 130 is located above the NMOS channel layer 120, and the two ends of the NMOS channel layer 120 are in contact with the NMOS source 140 and the NMOS drain 150, respectively.

[0037] In the process of forming the NMOS gate structure, after depositing gate stack material on the substrate and channel layer, a hard mask layer is deposited on the gate stack material, and a basically vertical NMOS gate 130 is formed by photolithography and etching.

[0038] The NMOS semiconductor structure described in this application is a small-size device structure. The gate length is less than or equal to 90 nm, the gate width is between 150 and 500 nm, the source width is between 100 and 400 nm, and the drain width is between 100 and 400 nm. The length mentioned here refers to the dimension in the source-drain current direction, and the width refers to the dimension perpendicular to the source-drain current direction (deep into the paper in the figure). The gate length design can significantly reduce the area occupied by a single device, enabling high-density device array integration. The gate width design ensures sufficient drive current and avoids an increase in the area of ​​a single device due to excessive width. Furthermore, the source-drain width is designed to match the gate width, effectively controlling the parasitic resistance and capacitance of the source and drain, and improving the switching speed and frequency response characteristics of the device.

[0039] The NMOS gate 130 of the NMOS semiconductor structure may include an NMOS gate dielectric layer and an NMOS gate electrode layer. The NMOS gate dielectric layer may be an insulating dielectric layer made of a high-k material, such as hafnium dioxide (HfO2). The NMOS gate electrode layer may be made of titanium nitride (TiN) or tantalum nitride (TaN). Thus, the NMOS gate 130 is a stacked structure consisting of a hafnium dioxide layer 131, a titanium nitride layer 132, and a tantalum nitride layer 133.

[0040] The NMOS source 140 can be formed on the upper surface of the NMOS channel layer 120, that is, on the carbon nanotubes of the NMOS channel layer 120. The NMOS source 140 is formed on one side of the NMOS gate 130 and can be insulated from the NMOS gate 130 through an interlayer dielectric layer 160, wherein the interlayer dielectric layer 160 can be an insulating material such as silicon dioxide (SiO2). In this application, the NMOS source 140 directly contacts the NMOS channel layer 120. The NMOS source 140 may include an NMOS source interface contact layer 141 and an NMOS source conductive filling layer 142, which form a stacked structure. The NMOS source interface contact layer 141 is in direct contact with the NMOS channel layer 120, and the undoped carbon nanotubes are N-type doped through the NMOS source interface contact layer 141. Therefore, in this application, the NMOS source interface contact layer 141 can be deposited by atomic layer deposition (ALD) process, and the carbon nanotubes can be N-type doped by a half-metal type metal nitride material of the NMOS source interface contact layer 141.

[0041] The NMOS source interface contact layer 141 can be made of tantalum nitride (TaN). During the formation of the NMOS source 140, a source contact hole with substantially vertical sidewalls can be formed using photolithography and etching processes, and the NMOS source interface contact layer 141 of tantalum nitride material is deposited within the source contact hole. The NMOS source interface contact layer 141 is deposited at the bottom of the source contact hole and in direct contact with the channel layer 120, and is also deposited on the sidewalls of the source contact hole. The thickness of the NMOS source interface contact layer 141 is 5 nm to 20 nm. If this thickness is too thin, the polarization will be insufficient during the interface charge transfer and built-in electric field establishment process after the NMOS source interface contact layer 141 contacts the carbon nanotube. If the thickness is too thick, the series resistance of the NMOS source interface contact layer 141 will increase significantly, leading to increased device power consumption. The NMOS source interface contact layer 141 covers the sidewalls and bottom of the source contact hole, and the bottom of the NMOS source interface contact layer 141 is in direct contact with the carbon nanotube channel layer. In the hollow space formed by the NMOS source interface contact layer 141, copper is deposited using chemical vapor deposition (CVD) or ruthenium is deposited using physical vapor deposition (PVD) / atomic layer deposition (ALD) until the hollow space is filled, thus forming the NMOS source conductive filling layer 142 with copper or ruthenium. In this application, the carbon nanotubes used in the formation of the channel layer can be undoped carbon nanotubes, but rather the undoped carbon nanotubes are N-type doped using the material of the NMOS source interface contact layer 141 above.

[0042] The NMOS drain 150 can be formed on the upper surface of the NMOS channel layer 120, i.e., on the carbon nanotubes of the NMOS channel layer 120. The NMOS drain 150 is formed on one side of the NMOS gate 130 and can be insulated from the NMOS gate 130 by an interlayer dielectric layer 160, which can be an insulating material such as silicon dioxide (SiO2). In this application, the NMOS drain 150 directly contacts the NMOS channel layer 120. The NMOS drain 150 may include an NMOS drain interface contact layer 151 and an NMOS drain conductive filling layer 152, forming a stacked structure. The NMOS drain interface contact layer 151 is in direct contact with the NMOS channel layer 120, and the undoped carbon nanotubes are N-type doped through the NMOS drain interface contact layer 151. The material of the NMOS drain interface contact layer 151 can be tantalum nitride (TaN). During the formation of the NMOS drain 150, a drain contact hole with substantially vertical sidewalls can be formed using photolithography and etching processes, and an NMOS drain interface contact layer 151 of tantalum nitride material can be deposited in the drain contact hole. The NMOS drain interface contact layer 151 is deposited at the bottom of the drain contact hole and in direct contact with the channel layer 120, and is also deposited on the sidewalls of the drain contact hole. The thickness of the NMOS drain interface contact layer 151 is 5 nm to 20 nm. If this thickness is too thin, the polarization will be insufficient during the interface charge transfer and built-in electric field establishment process after the NMOS drain interface contact layer 151 contacts the carbon nanotube; if the thickness is too thick, the series resistance of the NMOS drain interface contact layer 151 will increase significantly, leading to increased device power consumption. Therefore, in this application, the NMOS drain interface contact layer 151 can be deposited using atomic layer deposition (ALD) technology, and the carbon nanotubes can be N-type doped using a half-metallic metal nitride material in the NMOS drain interface contact layer 151. Furthermore, the NMOS drain interface contact layer 151 and the NMOS source interface contact layer 141 can be fabricated simultaneously using the same process and materials. The NMOS drain interface contact layer 151 covers the sidewalls and bottom of the drain contact hole, and the bottom of the NMOS drain interface contact layer 151 directly contacts the carbon nanotube channel layer. In the hollow space formed by the NMOS drain interface contact layer 151, copper is deposited using chemical vapor deposition (CVD), or ruthenium is deposited using physical vapor deposition (PVD) / atomic layer deposition (ALD) until the hollow space is filled, thus forming the NMOS drain conductive filling layer 152 with copper or ruthenium. In this application, the carbon nanotubes used in the formation of the channel layer can be undoped carbon nanotubes, but rather the undoped carbon nanotubes are N-type doped using the material of the NMOS drain interface contact layer 151.

[0043] In this application, the NMOS source interface contact layer 141 and the NMOS drain interface contact layer 151 are formed using the same material, and the NMOS source conductive filling layer 142 and the NMOS drain conductive filling layer 152 are also formed using the same material. Both the NMOS source and drain interface contact layers are made of a half-metal type metal nitride, possessing both N-type doping functionality and contact transport functionality for carbon nanotubes. During fabrication, doping is achieved through the inherent properties of the material, resulting in higher doping uniformity and significantly improved contact interface stability. No additional ion implantation doping step is required, avoiding damage caused by ion implantation. The NMOS source and drain interface contact layers can be fabricated using atomic layer deposition (ALD) technology, which is particularly suitable for small-size devices (source / drain widths of 100–400 nm) and high aspect ratio contact holes. The thickness of the NMOS source and drain interface contact layers is 5–20 nm, ensuring sufficient doping and low contact resistance, thus guaranteeing excellent device performance.

[0044] Figure 2 An NMOS semiconductor structure according to a further embodiment of the present disclosure is shown. Figure 2 The NMOS semiconductor structure of the embodiment and Figure 1 The difference in the NMOS semiconductor structure shown in the embodiment is that the NMOS drain 150 covers the upper and side surfaces of one end of the NMOS channel layer, and the NMOS source 140 covers the upper and side surfaces of the other end of the NMOS channel layer.

[0045] For example Figure 2 The portion shown in circles. For the NMOS drain 150, its NMOS drain interface contact layer 151 covers the upper surface 121 and side surface 122 of the channel layer 120. For the NMOS source 140, its NMOS source interface contact layer 141 covers the upper surface 121 and side surface 122 of the channel layer 120. This allows the NMOS drain 150 and NMOS source 140 to have a larger contact area with the channel. Since contact resistance is inversely proportional to contact area, increasing the contact area will reduce the contact resistance. In addition, the side surface can also provide additional transport paths for charge carriers. Furthermore, uniform N-type doping of carbon nanotubes can be achieved, improving performance consistency. For small-size devices, Figure 2 The source-drain contact area of ​​the embodiment can solve the problem of current concentration caused by small size.

[0046] Figure 2The illustrated embodiment increases the effective contact area between the NMOS drain interface contact layer and the NMOS source interface contact layer and the channel layer, thereby significantly reducing contact resistance. This can greatly reduce energy loss during carrier transport, meeting the low-power requirements of small-size devices. Furthermore, it enhances the interfacial bonding force between the interface contact layer and the channel, ensuring the stability of the contact interface.

[0047] Figure 3 A schematic diagram of a PMOS semiconductor structure according to an embodiment of the present disclosure is shown. Figure 3 As shown, the PMOS semiconductor structure 200 may include a substrate 210, a PMOS channel layer 220, a PMOS gate 230, a PMOS source 240, and a PMOS drain 250.

[0048] Substrate 210 is as described with reference to the NMOS semiconductor structure. The PMOS and NMOS semiconductor structures are formed on the same substrate. Furthermore, during the formation of the NMOS channel layer 120 and the PMOS channel layer, undoped carbon nanotubes can be transferred to the surface of the substrate. Through subsequent processing, only the carbon nanotubes used for the NMOS channel layer 120 and the PMOS channel layer 220 are retained, while the remaining carbon nanotubes are removed. The thickness of the NMOS channel layer 120 and the PMOS channel layer 220 ranges from greater than 0 nm to less than or equal to 10 nm.

[0049] The PMOS gate 230 is located above the PMOS channel layer 220, and the two ends of the PMOS channel layer 220 are in contact with the PMOS source 240 and the PMOS drain 250, respectively.

[0050] During the formation of the PMOS gate structure, a hard mask layer can be deposited on the PMOS gate structure, and a basically vertical PMOS gate 230 can be formed by photolithography and etching.

[0051] The PMOS semiconductor structure of this application is a small-size device structure, with a gate length of less than or equal to 90 nm, a gate width between 150 and 500 nm, a source width between 100 and 400 nm, and a drain width between 100 and 400 nm. The length mentioned here refers to the dimension in the source-drain current direction, and the width refers to the dimension perpendicular to the source-drain current direction (in the figure, extending into the paper).

[0052] The PMOS gate 230 of the PMOS semiconductor structure may include a PMOS gate dielectric layer and a PMOS gate electrode layer. The PMOS gate dielectric layer can be an insulating dielectric layer made of a high-k material, such as hafnium dioxide (HfO2). The PMOS gate electrode layer can be made of titanium nitride (TiN) or tantalum nitride (TaN). Thus, the PMOS gate 230 is a stacked structure composed of a hafnium dioxide layer 231, a titanium nitride layer 232, and a tantalum nitride layer 233. In this application, the structure and materials of the PMOS gate are the same as those of the NMOS gate. The NMOS gate and PMOS gate are formed using the same material in a stacked structure, eliminating the need for different gate material systems and deposition processes for the two devices. A global gate thin film can be fabricated simultaneously in the same process, followed by photolithography etching to pattern the gates of both types of devices, reducing process steps and significantly lowering the production cost and process complexity of large-scale integration.

[0053] The PMOS source 240 can be formed on the upper surface of the PMOS channel layer 220, i.e., on the carbon nanotubes of the PMOS channel layer 220. The PMOS source 240 is formed on one side of the PMOS gate 230 and can be insulated from the PMOS gate 230 by an interlayer dielectric layer 260, which can be an insulating material such as silicon dioxide (SiO2). In this application, the PMOS source 240 directly contacts the PMOS channel layer 220. The PMOS source 240 can include a PMOS source interface contact layer 241 and a PMOS source conductive filling layer 242, forming a stacked structure. The PMOS source interface contact layer 241 is in direct contact with the PMOS channel layer 220, and the undoped carbon nanotubes are p-type doped through the PMOS source interface contact layer 241. The material of the PMOS source interface contact layer 241 can be ruthenium dioxide (RuO2) or iridium dioxide (IrO2). During the formation of the PMOS source 240, a source contact hole with substantially vertical sidewalls can be formed using photolithography and etching processes. A PMOS source interface contact layer 241 made of ruthenium dioxide or iridium dioxide is deposited within the source contact hole. The PMOS source interface contact layer 241 is deposited at the bottom of the source contact hole and in direct contact with the channel layer 220, and is also deposited on the sidewalls of the source contact hole. The thickness of the PMOS source interface contact layer 241 is 5 nm to 20 nm. If this thickness is too thin, the polarization will be insufficient during the interface charge transfer and built-in electric field establishment process after the PMOS source interface contact layer 241 contacts the carbon nanotube. If the thickness is too thick, the series resistance of the PMOS source interface contact layer 241 will increase significantly, leading to increased device power consumption. The PMOS source interface contact layer 241 covers the sidewalls and bottom of the source contact hole, and the bottom of the PMOS source interface contact layer 241 is in direct contact with the carbon nanotube channel layer. In the hollow space formed by the PMOS source interface contact layer 241, ruthenium (Ru) is deposited using a physical vapor deposition (PVD) / atomic layer deposition (ALD) process until the hollow space is filled, thus forming the PMOS source conductive filling layer 242 through ruthenium. In this application, the carbon nanotubes used in the formation of the channel layer can be undoped carbon nanotubes, but the undoped carbon nanotubes are p-type doped using the material of the PMOS source interface contact layer 241. Therefore, in this application, the PMOS source interface contact layer 241 can be deposited using an atomic layer deposition (ALD) process, and the carbon nanotubes can be p-type doped using a half-metallic metal oxide material of the PMOS source interface contact layer 241.

[0054] The PMOS drain 250 can be formed on the upper surface of the PMOS channel layer 220, i.e., on the carbon nanotubes of the PMOS channel layer 220. The PMOS drain 250 is formed on one side of the PMOS gate 230 and can be insulated from the PMOS gate 230 by an interlayer dielectric layer 260, which can be an insulating material such as silicon dioxide (SiO2). In this application, the PMOS drain 250 directly contacts the PMOS channel layer 220. The PMOS drain 250 can include a PMOS drain interface contact layer 251 and a PMOS drain conductive filling layer 252, forming a stacked structure. The PMOS drain interface contact layer 251 is in direct contact with the PMOS channel layer 220, and the undoped carbon nanotubes are p-type doped through the PMOS drain interface contact layer 251. The material of the PMOS drain interface contact layer 251 can be ruthenium dioxide (RuO2) or iridium dioxide (IrO2). Therefore, in this application, the PMOS drain interface contact layer 251 can be deposited using atomic layer deposition (ALD) technology, and the carbon nanotubes can be p-type doped using a half-metallic metal oxide material in the PMOS drain interface contact layer 251. Furthermore, the PMOS drain interface contact layer 251 and the PMOS source interface contact layer 241 can be fabricated simultaneously using the same process and the same materials.

[0055] During the formation of the PMOS drain 250, a drain contact hole with substantially vertical sidewalls can be formed using photolithography and etching processes. A PMOS drain interface contact layer 251 made of ruthenium dioxide or iridium dioxide is deposited within the drain contact hole. The PMOS drain interface contact layer 251 is deposited at the bottom of the drain contact hole and in direct contact with the channel layer 220, and is also deposited on the sidewalls of the drain contact hole. The thickness of the PMOS drain interface contact layer 251 is 5 nm to 20 nm. If this thickness is too thin, the polarization will be insufficient during the interface charge transfer and built-in electric field establishment process after the PMOS drain interface contact layer 251 contacts the carbon nanotube. If the thickness is too thick, the series resistance of the PMOS drain interface contact layer 251 will increase significantly, leading to increased device power consumption. The PMOS drain interface contact layer 251 covers the sidewalls and bottom of the drain contact hole, and the bottom of the PMOS drain interface contact layer 251 is in direct contact with the carbon nanotube channel layer. Ruthenium is deposited in the hollow space formed by the PMOS drain interface contact layer 251 using a physical vapor deposition (PVD) / atomic layer deposition (ALD) process until the hollow space is filled, thus forming the PMOS drain conductive filling layer 252 through ruthenium. In this application, the carbon nanotubes used in the formation of the channel layer can be undoped carbon nanotubes, but the undoped carbon nanotubes are p-type doped using the material of the PMOS drain interface contact layer 251 above.

[0056] In this application, the PMOS source interface contact layer 241 and the PMOS drain interface contact layer 251 are formed using the same material, and the PMOS source conductive filling layer 242 and the PMOS drain conductive filling layer 252 are also formed using the same material. Both the PMOS source and drain interface contact layers are made of a half-metal type metal oxide, possessing both p-type doping functionality for carbon nanotubes and contact transport functionality. During fabrication, doping is achieved through the inherent properties of the material, resulting in higher doping uniformity and significantly improved contact interface stability. No additional ion implantation doping step is required, avoiding damage caused by ion implantation. The PMOS source and drain interface contact layers can be fabricated using atomic layer deposition (ALD) technology, which is particularly suitable for small-size devices (source / drain widths of 100–400 nm) and high aspect ratio contact holes.

[0057] Figure 4 A PMOS semiconductor structure according to a further embodiment of the present disclosure is shown. Figure 4 The PMOS semiconductor structure of the embodiment and Figure 3 The difference in the PMOS semiconductor structure shown in the embodiment is that the PMOS drain 250 covers the upper and side surfaces of one end of the PMOS channel layer, and the PMOS source 240 covers the upper and side surfaces of the other end of the PMOS channel layer.

[0058] For example Figure 4 The portion shown in circles. For the PMOS drain 250, its PMOS drain interface contact layer 251 covers the upper surface 221 and side surface 222 of the channel layer 220. For the PMOS source 240, its PMOS source interface contact layer 241 covers the upper surface 221 and side surface 222 of the channel layer 220. This allows the PMOS drain 250 and PMOS source 240 to have a larger contact area with the channel. Since contact resistance is inversely proportional to contact area, increasing the contact area will reduce the contact resistance. In addition, the side surface can also provide additional transport paths for charge carriers. Furthermore, uniform P-type doping of carbon nanotubes can be achieved, improving performance consistency. For small-size devices, Figure 4 The source-drain contact area of ​​the embodiment can solve the problem of current concentration caused by small size.

[0059] exist Figure 5 The image shows including Figure 1 The NMOS semiconductor structure of the embodiment and Figure 3 A schematic diagram of the CMOS semiconductor structure of the PMOS semiconductor structure in this embodiment. Those skilled in the art will understand that the CMOS semiconductor structure may include a suitable number of NMOS semiconductor structures and PMOS semiconductor structures. Additionally, it can be... Figures 1 to 4The semiconductor structures of the embodiments can be arbitrarily combined to form CMOS semiconductor structures.

[0060] The carbon-based CMOS semiconductor structure of this application is fabricated using a monolithic integration process, ensuring performance matching and process compatibility between NMOS and PMOS. Hard insulating materials such as silicon oxide or flexible insulating materials such as polyimide are selected as substrates. The substrate surface is pretreated to provide a clean and flat support interface for carbon nanotube transfer. An undoped carbon nanotube film is transferred to the pretreated substrate surface using a transfer printing process, patterning the carbon nanotube film. Only the carbon nanotube areas of the NMOS channel layer 120 and PMOS channel layer 220 are retained, while the remaining carbon nanotubes are completely removed. After patterning the carbon nanotube film, a gate stack material composed of HfO2, TiN, and TaN is sequentially deposited using a deposition process to form a continuous gate film. Subsequently, a hard mask layer is deposited, and the gate structure is patterned using photolithography and dry etching processes to form the NMOS gate 130 and PMOS gate 230, respectively. The etching vertical deviation is ≤2° to ensure precise coverage of the channels by the gates. After etching, the hard mask layer can be removed or retained to obtain a structured gate array. Further, a dielectric barrier layer can be deposited, which covers the substrate surface, the channel layer surface corresponding to the source and drain, and the gate surface. Then, an interlayer dielectric layer can be deposited to cover the dielectric barrier layer, and subsequently, the surface of the interlayer dielectric layer is planarized using a CMP process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the gate.

[0061] The contact hole positions of NMOS source 140, NMOS drain 150, PMOS source 240, and PMOS drain 250 are defined by photolithography. The interlayer dielectric layer is etched by dry etching until the surface of the corresponding carbon nanotube channel layer is exposed.

[0062] NMOS source and drain electrodes are fabricated, and NMOS source interface contact layers and NMOS drain interface contact layers are deposited in the NMOS source contact holes and NMOS drain contact holes, respectively, to achieve conformal coverage (covering the bottom and sidewalls). If... Figure 2 When etching the NMOS source and drain contact holes, the etching process must extend to the side of the channel layer to ensure that the NMOS source and drain interface contact layers can cover the upper and side surfaces of the channel after deposition. Subsequently, a conductive filling layer is deposited to fill the contact holes of the NMOS source and drain.

[0063] PMOS source and drain electrodes are fabricated, and PMOS source and drain interface contact layers are deposited in the PMOS source and drain contact holes, respectively, achieving conformal coverage. If... Figure 4When etching the PMOS source and drain contact holes, the etching process must extend to the side of the channel layer to ensure that the PMOS source and drain interface contact layers can cover the upper and side surfaces of the channel after deposition. Subsequently, a conductive filling layer is deposited to fill the contact holes.

[0064] The deposited NMOS source, NMOS drain, PMOS source, and PMOS drain are planarized using CMP (chemical mechanical polishing) (e.g., the surface of the formed device is planarized) to remove excess material.

[0065] Throughout the entire fabrication process of CMOS semiconductor structures, low-temperature processes can be used to avoid problems such as carbon nanotube oxidation, lattice damage, or decreased carrier mobility caused by high temperatures. The stacked structure of NMOS gate and PMOS gate can use the same materials and the same deposition process, which simplifies the process steps and reduces manufacturing costs.

[0066] According to a further embodiment of this disclosure, a carbon-based integrated circuit is also provided, constructed based on the carbon-based CMOS semiconductor structure described above, and capable of large-scale monolithic integration. The carbon-based integrated circuit may include a substrate layer, which is the substrate described above. Additionally, the carbon-based integrated circuit may also include a carbon-based CMOS device array, wherein the carbon-based CMOS semiconductor structure described above is employed, and can be arranged from multiple carbon-based NMOS semiconductor structures (NMOS devices) and carbon-based PMOS semiconductor structures (PMOS devices) described above according to circuit logic requirements.

[0067] Carbon-based integrated circuits may also include metal interconnects, such as using suitable metal wiring like copper, which can be formed through photolithography, etching, and deposition processes to connect the various NMOS and PMOS devices in the carbon-based integrated circuit.

[0068] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0069] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0070] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A carbon-based CMOS semiconductor structure, characterized by, Includes a substrate, on which NMOS semiconductor structures and PMOS semiconductor structures are formed. The NMOS semiconductor structure includes: An NMOS channel layer is located on the substrate, and the material of the NMOS channel layer is carbon nanotubes; The NMOS gate is located above the NMOS channel layer; An NMOS drain, covering and contacting one end of the NMOS channel layer and located on one side of the NMOS gate, comprises an NMOS drain interface contact layer and an NMOS drain conductive filling layer, wherein the NMOS drain interface contact layer is a half-metallic metal nitride capable of N-type doping of carbon nanotubes; and The NMOS source electrode covers and contacts the other end of the NMOS channel layer and is located on the other side of the NMOS gate. The NMOS source electrode includes an NMOS source interface contact layer and an NMOS source conductive filling layer. The NMOS source interface contact layer is a half-metallic metal nitride capable of N-type doping of carbon nanotubes. The thickness of both the NMOS drain interface contact layer and the NMOS source interface contact layer is 5–20 nm. The PMOS semiconductor structure includes: A PMOS channel layer, located on the substrate, wherein the material of the PMOS channel layer is carbon nanotubes; and The PMOS gate, PMOS drain, and PMOS source are located on the PMOS channel layer, with the PMOS gate situated above the PMOS channel layer, and the PMOS drain and PMOS source situated on both sides of the PMOS gate and at least above both ends of the PMOS channel layer.

2. The carbon-based CMOS semiconductor structure of claim 1, wherein, The lengths of the NMOS gate and the PMOS gate are less than or equal to 90 nm, the widths of the NMOS gate and the PMOS gate are 150–500 nm, the widths of the NMOS source and the PMOS source are 100–400 nm, and the widths of the NMOS drain and the PMOS drain are 100–400 nm, wherein the length is the dimension along the source-drain current direction, and the width is the dimension perpendicular to the source-drain current direction.

3. The carbon-based CMOS semiconductor structure as described in claim 1, characterized in that, The NMOS drain interface contact layer covers the upper and side surfaces of one end of the NMOS channel layer, and the NMOS source interface contact layer covers the upper and side surfaces of the other end of the NMOS channel layer.

4. The carbon-based CMOS semiconductor structure of claim 1, wherein, The NMOS drain interface contact layer and the NMOS source interface contact layer are made of tantalum nitride, and the NMOS drain conductive filling layer and the NMOS source conductive filling layer are made of copper or ruthenium.

5. The carbon-based CMOS semiconductor structure of claim 1, wherein, The NMOS drain interface contact layer and the NMOS source interface contact layer are formed simultaneously through an atomic layer deposition process.

6. The carbon-based CMOS semiconductor structure of claim 1, wherein, The NMOS gate and the PMOS gate are a stacked structure made of the same material, and the stacked structure includes a hafnium dioxide layer, a titanium nitride layer and a tantalum nitride layer.

7. The carbon-based CMOS semiconductor structure as described in claim 1, characterized in that, The PMOS drain includes a PMOS drain interface contact layer and a PMOS drain conductive filling layer. The PMOS drain interface contact layer covers and contacts one end of the PMOS channel layer, and the PMOS drain conductive filling layer fills the hollow space formed by the PMOS drain interface contact layer. The PMOS source includes a PMOS source interface contact layer and a PMOS source conductive filling layer. The PMOS source interface contact layer covers and contacts the other end of the PMOS channel layer, and the PMOS source conductive filling layer fills the hollow space formed by the PMOS source interface contact layer.

8. The carbon-based CMOS semiconductor structure as described in claim 7, characterized in that, The materials of the PMOS drain interface contact layer and the PMOS source interface contact layer are both ruthenium dioxide or iridium dioxide; the materials of the PMOS drain conductive filling layer and the PMOS source conductive filling layer are both ruthenium.

9. The carbon-based CMOS semiconductor structure as described in claim 1, characterized in that, The thickness of the PMOS drain interface contact layer and the PMOS source interface contact layer is 5–20 nm.

10. An integrated circuit, characterized in that, include: The carbon-based CMOS semiconductor structure comprising a plurality of NMOS semiconductor structures and a plurality of PMOS semiconductor structures as described in any one of claims 1 to 9; as well as Metal interconnects are used to connect the plurality of NMOS semiconductor structures and the plurality of PMOS semiconductor structures.

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