Table-top type PIN photoelectric detector based on epitaxial Ge on Si and preparation method of table-top type PIN photoelectric detector

Abstract

The invention discloses a mesa type PIN photoelectric detector based on epitaxial Ge on Si and a preparation method, and relates to the technical field of semiconductor photoelectric devices. The detector comprises an N-type silicon Si substrate, a mesa structure formed by an intrinsic Ge layer and a P-type heavily-doped Ge layer which are sequentially and epitaxially arranged on the N-type silicon Si substrate, a passivation layer covering a mesa, and a metal electrode respectively connected with the P-type heavily-doped Ge layer and the N-type silicon Si substrate. According to the invention, the size of a germanium active region is greatly reduced by adopting a structure that a thin layer Ge is extended on the Si substrate and mesa isolation is combined, and generation and recombination of carriers are inhibited by cooperation of a Si / Ge heterojunction and side wall passivation, so that the dark current of the device is remarkably reduced. Meanwhile, by accurately controlling the thickness of the intrinsic Ge layer, flexible optimization can be carried out between high responsivity and high bandwidth, and the requirements of different near-infrared application scenes are met.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic device technology, specifically relating to a mesa-type PIN photodetector based on Si epitaxial Ge and its fabrication method. Background Technology

[0002] Near-infrared photodetectors are core components in modern optoelectronic systems, enabling optical communication, sensing, and imaging. Currently, in the 1550 nm communication band and other near-infrared applications, indium gallium arsenide (InGaAs) is the mainstream material for high-performance detectors. InGaAs detectors are widely used due to their high responsivity and sensitivity in this band. However, InGaAs detectors are expensive to fabricate, rely on complex heteroepitaxial growth techniques, and are difficult to integrate with mainstream silicon-based complementary metal-oxide-semiconductor (CMOS) processes. These factors severely limit the application of InGaAs detectors in low-cost, miniaturized, and large-scale optoelectronic integrated systems.

[0003] In recent years, colloidal quantum dot (such as PbS quantum dot) detectors have attracted attention due to their advantages such as solution-handleability and low cost. However, they have problems such as poor stability, low carrier mobility, and difficulty in integration with silicon processes, and their performance and reliability are still difficult to meet commercial requirements.

[0004] In contrast, germanium (Ge), as a classic semiconductor material, exhibits excellent light absorption characteristics in the near-infrared band (especially at 1550 nm), and its fabrication process is highly compatible with silicon-based CMOS processes, making it considered one of the ideal candidate materials for achieving low-cost, high-performance on-chip optoelectronic integration. Currently, there are various detector structures based on germanium materials, among which the PIN structure has been widely studied due to its ability to effectively separate photogenerated carriers through its internal electric field.

[0005] However, traditional Ge-based PIN photodetectors face significant challenges. For PIN detectors fabricated using bulk germanium, the intrinsic region (I-region) is typically thick, resulting in very high dark current levels under reverse bias, severely degrading the signal-to-noise ratio and detection sensitivity. Excessive thinning or the absence of an I-region to reduce dark current significantly increases the recombination probability of photogenerated carriers, leading to a substantial decrease in the device's quantum efficiency and responsivity. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a mesa-type PIN photodetector based on Ge epitaxial growth on Si and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a mesa-type PIN photodetector based on Si-epitaxy Ge, comprising: N-type Si substrate; An intrinsic Ge layer is located on the upper surface of the N-type Si substrate; A p-type heavily doped Ge layer is located on the upper surface of the intrinsic Ge layer; The intrinsic Ge layer and the p-type heavily doped Ge layer form a mesa structure; The first metal electrode is located on the upper surface of the P-type heavily doped Ge layer and forms an ohmic contact with the P-type heavily doped Ge layer; The second metal electrode is located on the surface of the N-type Si substrate and forms an ohmic contact with the N-type Si substrate; A passivation layer is disposed on the sidewall of the mesa structure, on the uncovered upper surface of the p-type heavily doped Ge layer and the upper surface of the N-type Si substrate.

[0007] In one embodiment of the present invention, the resistivity of the N-type Si substrate is no more than 0.005 Ω·cm and the thickness is 300 μm-500 μm.

[0008] In one embodiment of the present invention, the thickness of the intrinsic Ge layer is 0.1-2 μm.

[0009] In one embodiment of the present invention, the doping concentration of the p-type heavily doped Ge layer is 1 × 10⁻⁶. 18 -5×10 19 cm -3 .

[0010] In one embodiment of the present invention, the thickness of the p-type heavily doped Ge layer is 10-200 nm.

[0011] In one embodiment of the present invention, the width of the tabletop structure does not exceed 500 μm.

[0012] In one embodiment of the present invention, the material of the passivation layer is at least one of Al2O3, SiO2, and SiN, and the thickness is 1-500 nm.

[0013] In one embodiment of the present invention, the materials of the first metal electrode and the second metal electrode are gold, silver or aluminum.

[0014] In one embodiment of the present invention, the second metal electrode is an electrode located on the lower surface of the N-type Si substrate; or, the second metal electrode is an annular electrode located on the upper surface of the N-type Si substrate, the annular electrode being disposed around the mesa structure.

[0015] This invention provides a method for fabricating a mesa-type PIN photodetector based on Ge epitaxial growth on Si, applicable to the mesa-type PIN photodetector based on Ge epitaxial growth on Si described in any of the above embodiments. The fabrication method includes: Step 1: Select an N-type Si substrate; Step 2: Intrinsic Ge layer and P-type heavily doped Ge layer are epitaxially grown sequentially on the N-type Si substrate; Step 3: Pattern the intrinsic Ge layer and the p-type heavily doped Ge layer into a mesa structure using photolithography and etching processes; Step 4: Deposit a passivation layer on the device surface; Step 5: Define and etch contact windows on the passivation layer to expose part of the p-type heavily doped Ge layer and part of the n-type Si substrate; Step 6: Form a metal electrode within the contact window to form ohmic contacts with the p-type heavily doped Ge layer and the n-type Si substrate, respectively.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The mesa-type PIN photodetector based on epitaxial Ge on Si of the present invention significantly reduces the effective volume of Ge material by employing a thin layer of Ge epitaxially grown on a Si substrate and forming a mesa, thereby reducing the bulk dark current at its source. Simultaneously, the presence of the Si / Ge heterojunction further suppresses carrier diffusion and recombination. By precisely controlling the thickness of the intrinsic Ge layer, an optimized design can be achieved between high responsivity and high bandwidth to meet the needs of different application scenarios.

[0017] 2. The mesa-type PIN photodetector based on Ge epitaxy on Si of the present invention uses a passivation layer to effectively passivate the mesa sidewalls, reducing the surface state density, further suppressing surface leakage current, and improving the long-term reliability of the device. In addition, the epitaxial, photolithography, etching, and deposition processes involved in the entire fabrication process are all compatible with standard silicon-based CMOS processes, which facilitates monolithic integration with readout circuits, etc., and reduces system cost and complexity.

[0018] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a mesa-type PIN photodetector based on Si epitaxial Ge provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another mesa-type PIN photodetector based on Si epitaxial Ge provided in an embodiment of the present invention; Figure 3This is a schematic diagram of a method for fabricating a mesa-type PIN photodetector based on epitaxial Ge on Si, provided in an embodiment of the present invention.

[0020] Icons: 1-N-type Si substrate; 2-Intrinsic Ge layer; 3-P-type heavily doped Ge layer; 4-First metal electrode; 5-Second metal electrode; 6-Passivation layer. Detailed Implementation

[0021] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of a mesa-type PIN photodetector based on Si epitaxial Ge and its fabrication method according to the present invention.

[0022] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0023] In a first aspect, embodiments of the present invention provide a mesa-type PIN photodetector based on epitaxial Ge on Si. By introducing a Si / Ge heterojunction and forming a mesa on the Ge layer, the effective volume of the device and the carrier recombination interface are effectively reduced, thereby significantly reducing dark current while maintaining high photoresponsivity and detection sensitivity. Moreover, the process is compatible with silicon-based CMOS technology and is suitable for large-scale, low-cost manufacturing.

[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of a mesa-type PIN photodetector based on Si epitaxial Ge provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the mesa-type PIN photodetector based on Si-based epitaxial Ge in this embodiment includes: an N-type Si substrate 1, an intrinsic Ge layer 2, a P-type heavily doped Ge layer 3, a first metal electrode 4, a second metal electrode 5, and a passivation layer 6. The intrinsic Ge layer 2 is located on the upper surface of the N-type Si substrate 1; the P-type heavily doped Ge layer 3 is located on the upper surface of the intrinsic Ge layer 2; the intrinsic Ge layer 2 and the P-type heavily doped Ge layer 3 form a mesa structure; the first metal electrode 4 is located on the upper surface of the P-type heavily doped Ge layer 3 and forms an ohmic contact with it; the second metal electrode 5 is located on the surface of the N-type Si substrate 1 and forms an ohmic contact with it; the passivation layer 6 is disposed on the sidewall of the mesa structure, covering the uncovered upper surface of the P-type heavily doped Ge layer 3 and the upper surface of the N-type Si substrate 1.

[0025] Optionally, the second metal electrode 5 is an electrode located on the lower surface of the N-type Si substrate 1, such as... Figure 1 As shown. In other alternative embodiments, the second metal electrode 5 is a ring electrode located on the upper surface of the N-type Si substrate 1, and the ring electrode is disposed around the mesa structure, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of another mesa-type PIN photodetector based on Si epitaxial Ge provided in an embodiment of the present invention.

[0026] In this embodiment, the resistivity of the N-type Si substrate 1 does not exceed 0.005 Ω·cm, for example, it can be 0.0002 Ω·cm or 0.004 Ω·cm.

[0027] Optionally, the thickness of the N-type Si substrate 1 can be 300μm-500μm. For example, it can be 300μm, 400μm or 500μm.

[0028] In this embodiment, a high-quality intrinsic (i-type) germanium layer can be grown on the upper surface of the N-type Si substrate 1 by epitaxial processes such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) to form an intrinsic Ge layer 2.

[0029] Optionally, the thickness of the intrinsic Ge layer 2 is 0.1-2 μm. For example, it can be 100 nm, 200 nm, 1.5 μm, or 2 μm. The intrinsic Ge layer 2 is used to absorb near-infrared light and generate photogenerated carriers.

[0030] It is understandable that when a photodetector pursues a large bandwidth, in order to reduce the carrier transit time, the thickness of the intrinsic Ge layer 2 needs to be reduced, and its thickness can be controlled at around 100-500nm; while when a photodetector pursues high absorption efficiency, the thickness of the intrinsic Ge layer 2 needs to be increased to improve the detector's responsivity.

[0031] For example, when the thickness of the intrinsic Ge layer 2 is 200 nm, this thickness can ensure a certain initial light absorption at a communication wavelength of 1550 nm, while the core objective is to minimize the transit time of photogenerated carriers. Although the intrinsic Ge layer is very thin, the conduction band shift at the N-Si / i-Ge heterojunction interface can still effectively suppress the reverse injection of electrons from N-Si to the i-Ge region. This heterojunction barrier allows the device in this embodiment to achieve high-speed performance while its dark current is still much lower than that of a homojunction Ge photodiode.

[0032] For example, when the thickness of the intrinsic Ge layer 2 is 1.5 μm, this thickness is slightly greater than the absorption depth of Ge at a wavelength of 1550 nm, aiming to ensure that incident photons are fully absorbed. A thicker intrinsic Ge layer does not linearly increase the dark current because the depletion region width is primarily determined by the bias voltage and doping concentration. Thanks to the barrier effect of the N-Si / i-Ge heterojunction and the lower defect density of the intrinsic Ge layer compared to bulk Ge, the photodetector of this embodiment achieves high responsivity while maintaining a low dark current, thus ensuring excellent signal-to-noise ratio in low-light environments.

[0033] In this embodiment, the doping concentration of the p-type heavily doped Ge layer 3 is 1×10⁻⁶. 18 -5×10 19 cm -3 .

[0034] Optionally, the P-type heavily doped Ge layer 3 can also be formed by epitaxial growth, with a growth thickness of 10-200 nm. The P-type heavily doped Ge layer 3, together with the underlying intrinsic Ge layer 2 and the N-type Si substrate 1, constitutes a PIN junction.

[0035] In other alternative embodiments, the p-type heavily doped Ge layer 3 can also be achieved by ion implantation of the intrinsic Ge layer 2 to a depth of 100-200 nm. For example, boron (B) ions are implanted into the upper surface region of the intrinsic Ge layer 2 to form a doping concentration of 5 × 10⁻⁶ nm. 19 cm -3 A 150 nm deep P-type Ge region is formed as the P-type heavily doped Ge layer 3. It should be noted that rapid thermal annealing (RTA) is required after ion implantation to activate the dopant and repair lattice damage.

[0036] In this embodiment, the intrinsic Ge layer 2 and the P-type heavily doped Ge layer 3 are patterned into a mesa structure by an etching process. The width of the mesa structure is no more than 500 μm, and its sidewalls are perpendicular to the substrate surface.

[0037] For example, the intrinsic Ge layer 2 and the p-type heavily doped Ge layer 3 can be patterned into a cylindrical mesa structure with a diameter of 100 μm by an etching process. It is understandable that if the P-type heavily doped Ge layer 3 is achieved by ion implantation into the intrinsic Ge layer 2, the implantation pattern of the P-type Ge region will not exceed the mesa area of ​​the intrinsic Ge layer 2.

[0038] In this embodiment, the first metal electrode 4 and the second metal electrode 5 are made of gold, silver or aluminum.

[0039] For example, a Ti / Au multilayer metal can be deposited on the upper surface of the heavily doped p-type Ge layer 3 using electron beam evaporation or thermal evaporation processes to form an ohmic contact with the heavily doped p-type Ge layer 3. A Ti / Au multilayer metal can also be deposited on the lower surface of the n-type Si substrate 1 to form an ohmic contact.

[0040] In this embodiment, the passivation layer 6 is made of at least one of Al2O3, SiO2, and SiN, and has a thickness of 1-500 nm. The passivation layer 6 can be formed by plasma-enhanced chemical vapor deposition (PECVD) to reduce the surface state density and suppress surface leakage current.

[0041] Traditional Ge-based PIN detectors typically employ bulk germanium or a thick epitaxial Ge layer as the intrinsic absorption region (I-region). Within this region, due to the high intrinsic carrier concentration of germanium at room temperature and the presence of a certain density of bulk defects (such as dislocations and point defects), a significant bulk dark current is generated under reverse bias. This invention presents a mesa-type PIN photodetector based on epitaxial Ge on Si. This is achieved by epitaxially growing a thin Ge layer (the thickness of the intrinsic Ge layer can be as low as below 500 nm) on an N-type Si substrate and then laterally confining the Ge active region to a tiny size (500 μm) using a mesa etching process. This significantly reduces the effective volume of the Ge material. The bulk generation component of the dark current is positively correlated with the active region volume, thus directly reducing the absolute value of the dark current physically.

[0042] Furthermore, the Si / Ge heterojunction formed between the N-type Si substrate and the intrinsic Ge layer exhibits a significant band shift (especially a large valence band shift). This heterojunction can be equivalent to an additional energy barrier, effectively blocking the diffusion and injection of minority carriers (holes on the N-Si side) from Si to the Ge region, while also suppressing the diffusion and loss of minority carriers generated within the Ge region to the Si substrate. This is equivalent to reducing the carrier density effectively participating in the generation-recombination process, thereby further suppressing the diffusion current component. Since the Ge sidewalls exposed after mesa etching have a high surface state density, they are the main channels for surface leakage current. This invention effectively saturates surface dangling bonds and reduces the interface state density by depositing high-quality passivation layers such as Al2O3, SiO2, and SiN, thereby significantly suppressing surface generation-recombination current and edge leakage current.

[0043] The responsivity and bandwidth of a photodetector are two inherently related performance parameters. Responsivity mainly depends on light absorption efficiency and carrier collection efficiency, while bandwidth is limited by carrier transit time and RC time constant. This invention achieves continuous tunability of the intrinsic Ge layer thickness within the range of 0.1-2 μm through precise control of the epitaxial growth process. This provides flexible performance optimization space. For applications such as optical power detection and weak light sensing, a thicker intrinsic Ge layer (I-region) can be selected, such as 1000-1500 nm. For applications such as high-speed optical communication and lidar, a thinner intrinsic Ge layer (I-region) can be selected, such as 200-500 nm. Furthermore, by optimizing the mesa diameter to reduce junction capacitance, high-frequency response is further improved. A balance is achieved between responsivity and bandwidth; for example, an intrinsic Ge layer (I-region) thickness of 600-800 nm can be selected to meet the needs of most medium-speed systems.

[0044] This invention achieves customizable detector performance through a single structure and adjustable process parameters. Without redesigning the device layout or changing the material system, detectors suitable for different application scenarios can be fabricated on the same technology platform simply by adjusting the key process variable of the intrinsic Ge layer epitaxial thickness, greatly improving design flexibility and product applicability.

[0045] Secondly, embodiments of the present invention provide a method for fabricating a mesa-type PIN photodetector based on epitaxial Ge on Si, applicable to the mesa-type PIN photodetector based on epitaxial Ge on Si provided in the first aspect.

[0046] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating a method for fabricating a mesa-type PIN photodetector based on epitaxial Ge on Si, provided by an embodiment of the present invention. Figure 2 As shown, the fabrication method of the mesa-type PIN photodetector based on Ge epitaxial growth on Si in this embodiment includes the following steps: Step 1: Select an N-type Si substrate.

[0047] In this embodiment, the resistivity of the N-type Si substrate does not exceed 0.005 Ω·cm. This low-resistivity substrate facilitates the formation of low-resistivity ohmic contacts with the metal electrodes, reducing the series resistance of the device. Optionally, the thickness of the N-type Si substrate is 300-500 μm to provide sufficient mechanical support strength for subsequent processing. The use of a highly doped N-type substrate provides an ideal electron collection terminal for the device, and its low-resistivity characteristics are fundamental to achieving efficient charge extraction and low-power operation.

[0048] After selecting an N-type Si substrate, the silicon wafer is cleaned using a standard RCA cleaning process to remove surface organic matter, metal particles, and the natural oxide layer, resulting in a clean, hydrophilic surface.

[0049] Step 2: Intrinsic Ge layer and P-type heavily doped Ge layer are epitaxially grown sequentially on N-type Si substrate.

[0050] In this embodiment, the cleaned N-type Si substrate is placed in a chemical vapor deposition (CVD) reaction chamber. First, under appropriate temperature and pressure conditions, an intrinsic Ge layer with a thickness of 0.1-2 μm is epitaxially grown on the N-type Si substrate. Subsequently, a boron (B) precursor is introduced, and in-situ doping epitaxy is continued to form a layer with a thickness of 10-200 nm and a doping concentration of approximately 1 × 10⁻⁶. 18 -5×10 19 cm -3 The p-type heavily doped Ge layer.

[0051] Step 3: Pattern the intrinsic Ge layer and the P-type heavily doped Ge layer into a mesa structure using photolithography and etching processes.

[0052] In this embodiment, photoresist is spin-coated onto the surface of a heavily doped p-type Ge layer. The layer is then exposed and developed using photolithography to define a pattern with a width not exceeding 500 μm. Using the photoresist as a mask, reactive ion etching (RIE) is employed to anisotropically etch the unprotected heavily doped p-type Ge layer and the intrinsic Ge layer until the underlying N-type Si substrate surface is exposed, thus forming a mesa structure. Residual photoresist is removed using a photoresist remover.

[0053] Step 4: Deposit a passivation layer on the device surface.

[0054] Alternatively, a silicon dioxide (SiO2) film with a thickness not exceeding 500 nm can be uniformly deposited on the entire device surface (including mesa sidewalls, top and exposed substrate area) as a passivation layer using a plasma-enhanced chemical vapor deposition (PECVD) device.

[0055] Step 5: Define and etch contact windows on the passivation layer to expose part of the P-type heavily doped Ge layer and part of the N-type Si substrate.

[0056] In this embodiment, photoresist is spin-coated again onto the passivation layer surface, and the first electrode contact window (located at the center of the top of the mesa) and the second electrode contact window (located at the edge region of the front side of the substrate) are defined by photolithography. The SiO2 passivation layer in the window region is etched away using buffered oxide etching (BOE) solution or dry etching process, exposing the surface of the underlying P-type heavily doped Ge layer and the surface of the N-type Si substrate.

[0057] Step 6: Form metal electrodes within the contact window to form ohmic contacts with the P-type heavily doped Ge layer and the N-type Si substrate, respectively.

[0058] Specifically, without cleaning the photoresist after the previous etching process, an approximately 20 nm thick layer of titanium (Ti) is directly deposited on the device surface as an adhesion layer using electron beam evaporation, followed by an approximately 200 nm thick layer of gold (Au) as a conductive layer. The device is then immersed in acetone for ultrasonic lift-off to remove the photoresist and the metal covering it, leaving only the metal within the contact window to form the first electrode with ohmic contact to the P-type heavily doped Ge layer and the second electrode with ohmic contact to the N-type Si substrate.

[0059] In other alternative embodiments, the second electrode may also be deposited and patterned separately on the back side of the N-type Si substrate.

[0060] It should be noted that after the metal electrode is fabricated, alloying annealing (e.g., annealing at 400°C in a nitrogen atmosphere for 30 seconds) can be performed as needed to optimize the ohmic characteristics of the metal-semiconductor contact. Finally, subsequent processes such as dicing and packaging can be performed to complete the device fabrication.

[0061] This invention discloses a method for fabricating a mesa-type PIN photodetector based on Si-based epitaxial Ge layer. CVD epitaxy allows for precise control of the Ge layer thickness and doping concentration, while photolithography and RIE precisely control the mesa dimensions and morphology. The process exhibits good repeatability and is suitable for large-scale manufacturing. All process steps are performed at low or medium temperatures, and the PECVD, RIE, and electron beam evaporation equipment used are commonly used in standard silicon process lines, requiring no special process modules. This facilitates fabrication on existing CMOS production lines or integration with front-end circuitry. While achieving a high-performance device structure (low dark current, good responsivity), it avoids the use of expensive InGaAs materials or complex bonding processes, significantly reducing manufacturing costs. PECVD SiO2 passivation is a mature process with good film density, effectively passivating the mesa sidewalls and serving as a dielectric layer for subsequent metal interconnects.

[0062] For details regarding the fabrication method of the mesa-type PIN photodetector based on Si epitaxial Ge and its corresponding beneficial effects, please refer to the relevant content on the mesa-type PIN photodetector based on Si epitaxial Ge provided in the first aspect, which will not be repeated here.

[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0064] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0065] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A mesa-type PIN photodetector based on Si-based epitaxial Ge, characterized in that, include: N-type Si substrate (1); The intrinsic Ge layer (2) is located on the upper surface of the N-type Si substrate (1); A p-type heavily doped Ge layer (3) is located on the upper surface of the intrinsic Ge layer (2); The intrinsic Ge layer (2) and the P-type heavily doped Ge layer (3) form a mesa structure; The first metal electrode (4) is located on the upper surface of the P-type heavily doped Ge layer (3) and forms an ohmic contact with the P-type heavily doped Ge layer (3); The second metal electrode (5) is located on the surface of the N-type Si substrate (1) and forms an ohmic contact with the N-type Si substrate (1); A passivation layer (6) is disposed on the sidewall of the mesa structure, on the upper surface of the uncovered P-type heavily doped Ge layer (3) and the upper surface of the N-type Si substrate (1).

2. The mesa-type PIN photodetector based on Si epitaxial Ge according to claim 1, characterized in that, The resistivity of the N-type Si substrate (1) is no more than 0.005 Ω·cm and the thickness is 300 μm-500 μm.

3. The mesa-type PIN photodetector based on Si epitaxial Ge according to claim 1, characterized in that, The thickness of the intrinsic Ge layer (2) is 0.1-2 μm.

4. The mesa-type PIN photodetector based on Si epitaxial Ge according to claim 1, characterized in that, The doping concentration of the heavily doped p-type Ge layer (3) is 1×10⁻⁶. 18 -5×10 19 cm -3 .

5. The mesa-type PIN photodetector based on Si-epitaxy Ge as described in claim 1, characterized in that, The thickness of the p-type heavily doped Ge layer (3) is 10-200 nm.

6. The mesa-type PIN photodetector based on Si-epitaxy Ge as described in claim 1, characterized in that, The width of the platform structure does not exceed 500 μm.

7. The mesa-type PIN photodetector based on Si epitaxial Ge according to claim 1, characterized in that, The passivation layer (6) is made of at least one of Al2O3, SiO2, and SiN, and has a thickness of 1-500 nm.

8. The mesa-type PIN photodetector based on Si-epitaxy Ge as described in claim 1, characterized in that, The materials of the first metal electrode (4) and the second metal electrode (5) are gold, silver or aluminum.

9. The mesa-type PIN photodetector based on Si-epitaxy Ge as described in claim 1, characterized in that, The second metal electrode (5) is an electrode located on the lower surface of the N-type Si substrate (1); or, the second metal electrode (5) is an annular electrode located on the upper surface of the N-type Si substrate (1), the annular electrode being arranged around the mesa structure.

10. A method for fabricating a mesa-type PIN photodetector based on Ge epitaxial growth on Si, characterized in that, The method for fabricating the mesa-type PIN photodetector based on Si epitaxial Ge as described in any one of claims 1-9 includes: Step 1: Select an N-type Si substrate; Step 2: Intrinsic Ge layer and P-type heavily doped Ge layer are epitaxially grown sequentially on the N-type Si substrate; Step 3: Pattern the intrinsic Ge layer and the p-type heavily doped Ge layer into a mesa structure using photolithography and etching processes; Step 4: Deposit a passivation layer on the device surface; Step 5: Define and etch contact windows on the passivation layer to expose part of the P-type heavily doped Ge layer and part of the N-type Si substrate; Step 6: Form a metal electrode within the contact window to form ohmic contacts with the p-type heavily doped Ge layer and the n-type Si substrate, respectively.

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