Automatic chip testing method and device and storage medium

Abstract

The invention discloses an automatic chip testing method and device and a storage medium. The method comprises the steps that a placement instruction is sent to a mechanical arm to place a chip to a testing position; after the response signal is received, a test instruction is sent to the lower computer to complete a verification process; after verification is passed, different test instructions are sent in sequence, and test results are received; when the test item passes, adding a quality label to the chip; and a target application scene of the chip is determined according to the multiple quality labels, and a sorting instruction is sent to enable a manipulator to place the chip in a corresponding area. According to the method, full-process automation of chip testing, analysis and grading is achieved, multi-dimensional feature evaluation is achieved through a quality label system, accurate butt joint of the chip and a target application scene is achieved based on label matching, and the testing efficiency and the chip value utilization rate are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to an automated chip testing method, equipment, and storage medium. Background Technology

[0002] In the semiconductor manufacturing field, with the continuous increase in chip process complexity, especially the mass production of high-performance memory chips such as LPDDR5, process fluctuations during manufacturing lead to significant natural distribution characteristics in parameters such as chip performance, power consumption, and reliability. Traditional chip testing methods mainly focus on basic functional verification and parameter testing, which are increasingly inadequate to meet the sophisticated testing needs of the modern semiconductor industry.

[0003] In existing technologies, testing systems often employ a segmented processing model, separating test data acquisition from grading decisions. The testing system typically outputs raw test data, while the decision to match chips to specific application scenarios relies on engineers' experience or offline data analysis. This human-interventional grading method is not only inefficient but also prone to subjective judgment errors, leading to inconsistent and unrepeatable grading results. More significantly, existing testing systems lack complete automated closed-loop management capabilities. The physical handling, electrical testing, and final sorting of chips are usually managed by multiple independent control systems, resulting in low efficiency in coordination between these systems and hindering the formation of efficient and seamless automated production lines. For example, after a robotic arm places a chip, the testing system often requires manual triggering to start the testing program; after testing, operator intervention is needed to classify and place the chips into different storage areas. This fragmented processing severely restricts the improvement of overall testing efficiency. Furthermore, traditional grading methods are usually based on single parameters or simple rules, failing to fully utilize multi-dimensional test data for comprehensive evaluation and refined grading. For example, classifying chips solely based on their highest operating frequency while ignoring other important performance indicators such as power consumption, signal integrity, and temperature adaptability results in a large number of chips being unable to be matched to application scenarios that best suit their characteristic combinations, thus wasting the potential value of the chips. Summary of the Invention

[0004] This invention provides an automated chip testing method, equipment, and storage medium to solve the problems of disconnect between testing and grading, non-closed-loop process, and simple and rigid grading logic in the prior art.

[0005] Firstly, an automated chip testing method is provided, including: Send placement instructions to the robotic arm so that the robotic arm can place the chip from the loading area to the corresponding test position according to the placement instructions; After receiving the response signal returned by the robot arm after completing the placement action, send the instruction carrying the test information to the lower computer corresponding to the test position so that the lower computer can complete the verification process according to the test information; After the verification process is completed, different test commands are sent to the lower-level machine in sequence, and the test results fed back by the lower-level machine are received. Once the test results confirm that the test item has passed, add the corresponding quality label to the chip. Based on the quality labels contained in the multiple test results of the chip, the target application scenario of the chip is determined, and a placement instruction carrying the target application scenario is sent to the robot arm so that the robot arm can place the chip from the test position to the placement area corresponding to the target application scenario.

[0006] Secondly, a host computer is provided, including: The robot control module is used to send placement instructions to the robot, so that the robot can place the chip from the loading area to the corresponding test position according to the placement instructions; The verification module is used to receive the response signal returned by the robot after completing the placement action, and send the instruction carrying the test information to the lower computer corresponding to the test position so that the lower computer can complete the verification process according to the test information. The testing module is used to send different test commands to the lower-level machine in sequence after the verification process is passed, and to receive the test results fed back by the lower-level machine. The tagging module is used to add corresponding quality tags to the chip when the test results confirm that the test items have passed. The scenario allocation module is used to determine the target application scenario of the chip based on the quality tags contained in the multiple test results of the chip, and send a placement instruction carrying the target application scenario to the robot arm so that the robot arm can place the chip from the test position to the placement area corresponding to the target application scenario.

[0007] Thirdly, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described automated chip testing method.

[0008] Fourthly, a computer-readable storage medium is provided, which stores a computer program that, when executed by a processor, implements the steps of the aforementioned automated chip testing method.

[0009] The aforementioned automated chip testing methods, devices, equipment, and storage media achieve a complete closed-loop system of testing-decision-sorting by coordinating hardware resources such as robotic arms and slave computers through a host computer system. This organically integrates previously scattered and independent testing processes into a continuous and smooth automated workflow, completely eliminating delays and inconsistencies caused by manual intervention and significantly improving testing efficiency. Furthermore, by introducing a quality labeling system, the performance of chips in different test items is semantically described and quantitatively evaluated, achieving refined grading based on multi-dimensional features. This multi-dimensional, fine-grained feature description method enables the system to accurately identify the unique performance characteristics of each chip, laying a solid data foundation for precise scenario matching. In addition, by establishing an intelligent mapping relationship between quality labels and application scenarios, a data-driven grading decision-making mechanism is realized. This system can comprehensively consider the chip's performance, power consumption, reliability, and other characteristics, automatically allocating it to the target application where it can best realize its value, significantly improving chip utilization efficiency and the overall value of the product. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating an automated chip testing method according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram of the structure of a host computer in one embodiment of the present invention.

[0013] Figure 3 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Please see Figure 1 As shown, Figure 1 A flowchart illustrating an automated chip testing method provided in an embodiment of the present invention includes the following steps: Step S1: Send a placement command to the robot arm so that the robot arm can place the chip from the loading area to the corresponding test position according to the placement command.

[0016] Specifically, sending placement instructions to the robotic arm is the starting point of the automated testing process, and its key is to ensure that the chip can be accurately and reliably placed at the predetermined test position. In actual implementation, the host computer generates a structured placement instruction data packet. This data packet not only contains the three-dimensional coordinate information of the target test station, but also includes rich information such as chip batch identifier, task priority, robotic arm grasping parameters (such as nozzle selection, grasping force, placement speed, etc.), and security check codes. The host computer establishes a real-time communication connection with the robotic arm controller through an industrial Ethernet protocol (such as EtherCAT or PROFINET). This communication method provides deterministic real-time communication capabilities, ensuring the timeliness and reliability of instruction transmission. After receiving the instruction, the robotic arm will grasp the chip from the designated position in the loading area, calculate the optimal movement trajectory according to the built-in path planning algorithm, and finally accurately place the chip at the target test station. To ensure placement accuracy, the system can also be equipped with force sensors and vision systems for real-time verification. In practical applications, a machine vision system can also be introduced for chip positioning calibration, an anti-collision detection algorithm can be implemented to ensure the safety of the robotic arm's movement, or a chip posture detection and correction mechanism can be added to ensure the reliability of test contact.

[0017] Furthermore, in step S1, the step of sending placement instructions to the robot arm specifically includes: communicating with the robot arm's controller via the industrial Ethernet protocol to send placement instructions, which include the coordinates of the target test position, the chip batch number, and the task ID.

[0018] Specifically, the implementation details of the Industrial Ethernet protocol include the use of the EtherCAT protocol, support for distributed clock synchronization with clock jitter less than 1 microsecond, implementation of periodic heartbeat detection, automatic triggering of safety mechanisms in the event of communication interruption, and the use of priority frame scheduling to ensure real-time transmission of motion control commands. Structured instruction data packets employ binary encoding to reduce transmission overhead, include sequence numbers and timestamps to support command tracking and duplicate detection, and implement dual protection of data integrity through XOR and CRC checks. This communication mechanism ensures precise synchronization of the robot's movements, reliable command transmission reduces production interruptions caused by communication errors, standardized protocols facilitate system integration and maintenance, and structured data packets support the transmission of complex control parameters, adapting to diverse testing needs.

[0019] Step S2: Receive the response signal returned by the robot after completing the placement action, and send an instruction carrying test information to the lower-level machine corresponding to the test position so that the lower-level machine can complete the verification process according to the test information.

[0020] Specifically, after the robotic arm completes chip placement, it sends a response signal containing detailed status information to the host computer. This signal not only simply confirms the completion of the operation but also includes the operation result (success / failure), the deviation data between the actual placement position and the target position, any abnormal information detected during the placement process (such as vacuum loss, exceeding positioning deviation limits, etc.), and key information such as the timestamp and task ID. Upon receiving the successful response signal, the host computer immediately sends instructions carrying test information to the corresponding lower-level machine at the test station. These test instructions use a carefully designed structured frame format, including a frame header (containing synchronization characters and protocol version), the target lower-level machine address, the instruction type (e.g., test start, test stop, parameter configuration, etc.), the test parameter set (e.g., voltage, frequency, timing parameters, etc.), the expected firmware version and board ID, and a data integrity check code (e.g., CRC32). The transmission of test commands can utilize different communication protocols depending on the specific testing environment requirements: for scenarios with high real-time requirements, dedicated buses (such as PXI, PXIe) can be used; for distributed testing systems, TCP / IP can be used; and for specific testing devices, device-specific protocols (such as GPIB, USB) can be used. Furthermore, command encryption and digital signatures can be implemented to prevent unauthorized access, command priority management mechanisms can be added to handle concurrent test requests, or command retransmission and timeout handling mechanisms can be introduced to enhance communication reliability.

[0021] Furthermore, in step S2, the step of sending an instruction carrying test information to the lower-level machine corresponding to the test location specifically includes: sending a structured instruction frame to the lower-level machine corresponding to the test location via TCP / IP protocol or dedicated bus. The instruction frame is an encrypted frame, including a frame header, target address, instruction type, test parameters, and frame tail checksum.

[0022] Specifically, the TCP / IP protocol implementation adopts a client-server architecture, with the host computer acting as the client and the slave computers as the server. It uses a custom application layer protocol to define command formats and response mechanisms, and implements connection pool management to support concurrent connections from multiple slave computers. The dedicated bus implementation uses the PXIe bus to provide high-bandwidth, low-latency data transmission, employs DMA transfer mode to reduce CPU overhead, and implements a bus arbitration mechanism to ensure fair access for multiple devices. The structured command frame design includes a frame header (containing synchronization characters and protocol version information), an address field (supporting unicast, multicast, and broadcast communication modes), and a data field (using TLV encoding to support flexible expansion). This diverse communication method adapts to different testing environment requirements. The structured command frame improves the system's scalability and maintainability, the reliable communication mechanism ensures the accurate execution of test commands, and the encrypted command frame guarantees the security of the testing system, effectively preventing unauthorized access. To ensure the communication security of the test system, the command frame is encrypted before transmission. In a preferred embodiment, the AES (Advanced Encryption Standard) symmetric encryption algorithm is used to encrypt the payload of the command frame (including key information such as test parameters), and the key is distributed to the authorized lower-level machine through a secure channel.

[0023] Furthermore, the verification process includes: 1. Receive the verification result from the lower-level machine. The verification result is generated by the lower-level machine after receiving the test information by comparing its own firmware version number and hardware board ID with the expected version number and board ID carried in the test information.

[0024] 2. Determine whether the verification passes based on the verification results.

[0025] Specifically, during firmware version verification, the lower-level device reads the firmware version number from non-volatile memory. The version number follows a semantic versioning specification (major version.minor version.revision number), and the comparison algorithm supports flexible strategies: strict matching requires all version number parts to be completely identical; lenient matching only requires the major and minor version numbers to be identical; and backward compatibility allows new firmware versions to replace older versions. Board ID verification obtains the hardware ID through a DIP switch or a unique internal chip identifier. An ID whitelist mechanism is implemented, allowing only authorized boards to participate in the test. ID mask configuration is supported to achieve batch authorization of board groups. The error handling mechanism implements a tiered handling strategy for different error types: recoverable errors (such as temporary communication interruptions) trigger an automatic retry mechanism; unrecoverable errors (such as hardware failures) trigger system alarms and abort the test. This strict verification mechanism ensures the consistency of the test environment, flexible version management supports smooth system upgrades, comprehensive error handling improves system robustness and availability, and the whitelist mechanism enhances the security of the test system, preventing unauthorized devices from accessing the system.

[0026] Step S3: After the verification process is completed, send different test commands to the lower-level machine in sequence and receive the test results fed back by the lower-level machine.

[0027] Specifically, after the verification process is completed, the system enters the test sequence execution and quality label management phase. The test sequence is executed in a predefined order and typically includes multiple items such as contact detection, DC parameter testing, functional testing, performance testing, and reliability testing. Contact detection mainly verifies the electrical connection reliability between the chip pins and the test socket; DC parameter testing is responsible for measuring basic parameters such as quiescent current, input leakage current, and output high and low level voltages; functional testing verifies the correctness of the chip's logic function by running test vectors; performance testing measures key performance indicators such as operating frequency, power consumption, and analog accuracy; and reliability testing conducts stress tests in high and low temperature environments to evaluate the long-term stability of the chip.

[0028] The specific execution flow of the test sequence is as follows: the host computer issues test instructions sequentially according to the order defined in the test program set. Each instruction contains specific test parameters and pass / fail criteria; the slave computer executes the test and returns structured test results; the host computer receives the results and performs real-time analysis and decision-making.

[0029] Test result analysis and process control follow intelligent principles: For each test item, the host computer compares the measured data with preset specification limits and determines the direction of the test process based on the comparison results. If the test passes, the system adds a corresponding quality tag to the test item and automatically triggers the next test item; if the test fails, it decides, according to the preset configuration, whether to immediately stop the test or continue to collect more data. For critical test items (such as power short-circuit tests), failure usually leads to immediate stoppage; while for non-critical items, it can be configured to continue execution in order to collect complete chip characteristic data.

[0030] Furthermore, in step S3, the step of sequentially sending different test commands to the lower-level machine includes: sequentially sending at least two test commands corresponding to test items to the lower-level machine corresponding to the test position according to a predefined test sequence. The test items include: contact detection, DC parameter test, functional test, performance test, and reliability test.

[0031] Specifically, the test sequence adopts a modular design, including multiple items such as contact detection, DC parameter testing, functional testing, performance testing, and reliability testing. Contact detection implements four-wire Kelvin connection measurements to eliminate the influence of contact resistance, measures the impedance to ground of all power pins, detects short circuits / open circuits, and verifies the termination resistance of signal pins to ensure impedance matching. DC parameter testing covers static power consumption testing (measuring power supply current in standby mode), input leakage current testing (measuring leakage current at input pins when voltage is applied), and output drive capability testing (measuring the voltage tolerance of output high and low levels). Functional testing runs the test mode set provided by the manufacturer, implements the March C-algorithm to detect memory cell faults, and verifies address decoding logic and read / write functions. Performance testing includes transfer rate testing (measuring data throughput at different operating frequencies), access latency testing (measuring the time interval from command issuance to data output), and power consumption performance testing (measuring dynamic power consumption under different workloads). Reliability testing covers high and low temperature cycling testing (verifying functional stability under extreme temperature conditions), data retention testing (evaluating the charge retention capability of memory cells under specific conditions), and endurance testing (measuring the number of erase / write cycles of memory cells). This comprehensive and well-organized testing arrangement ensures the integrity of chip quality assessment. The modular design allows for flexible configuration of test content according to product type, and the reasonable test sequence optimizes test time and improves overall efficiency. Furthermore, the requirement of at least two test items ensures the acquisition of multi-dimensional data, laying a solid foundation for refined grading.

[0032] Step S4: When the test results confirm that the test item has passed, add the corresponding quality label to the chip.

[0033] Specifically, quality tags are essentially semantic performance descriptors used to accurately characterize a chip's performance in specific test items. Tag generation is based on comparisons between test data and preset thresholds. The tag system adopts a hierarchical structure, including basic tags and composite tags. These quality tags are systematically stored in the chip's test records and are continuously enriched and improved as the testing process progresses. Furthermore, adaptive testing strategies can be introduced to dynamically adjust subsequent test parameters based on previous test results; statistical process control can be implemented to monitor the stability of the testing process in real time; or test data mining functions can be added to discover potential product trends or process issues.

[0034] Furthermore, step S4 specifically includes: 1. Determine whether the test item passes based on the test results.

[0035] 2. If the test items pass, a quality label is added to the chip to identify the characteristics of the test items.

[0036] 3. If the test item fails, the testing process will be terminated.

[0037] Specifically, the test process control adopts an advanced state machine model, encompassing multiple states such as test preparation (initializing test parameters and resources), test execution (sending test commands and receiving results), result evaluation (analyzing test data and generating decisions), state transition (determining the next state based on the evaluation results), and test completion (normal termination or abnormal termination). The quality labeling mechanism varies depending on the test type: for pass / fail tests, binary labels (such as PASS_DC, FAIL_FT) are added; for parameterized tests, level labels (such as SPEED_FAST, POWER_LOW) are added based on the numerical range. All these labels are stored in the chip test record as key-value pairs (such as {"perf_speed": "fast", "power": "low"}) for easy subsequent analysis and processing. This intelligent test process management significantly improves test efficiency. The refined quality labeling system provides a rich data foundation for subsequent grading decisions, dynamic process control effectively reduces invalid test time, improves test throughput, and the timely test termination mechanism avoids wasting valuable test resources on known defective chips.

[0038] Furthermore, step S4, which involves adding the corresponding quality label to the chip, specifically includes: 1. For test results with specific test data, compare the test data with preset thresholds and generate corresponding performance level quality labels based on the comparison results.

[0039] 2. For test items that pass or fail, add a quality label to the chip indicating that the test item has passed, and trigger the next test instruction.

[0040] Specifically, the performance level quality label generation process includes extracting numerical results from the test items (such as transmission rate and power consumption values), comparing them with multiple preset thresholds, determining the performance level based on the threshold range, and finally generating the corresponding semantic label. For example, in the transmission rate test, a "SPEED_ULTRA_FAST" label can be added when the rate is greater than 6000 Mbps; a "SPEED_FAST" label can be added when the rate is between 4800 Mbps and 6000 Mbps; a "SPEED_STANDARD" label can be added when the rate is between 3600 Mbps and 4800 Mbps; and a "SPEED_SLOW" label can be added when the rate is less than or equal to 3600 Mbps. In power consumption testing, a "POWER_ULTRA_LOW" label is added for power consumption below 100 mW; a "POWER_LOW" label is added for power consumption between 100 mW and 200 mW; a "POWER_STANDARD" label is added for power consumption between 200 mW and 300 mW; and a "POWER_HIGH" label is added for power consumption above or equal to 300 mW. This data transformation mechanism converts raw test data into meaningful performance descriptions, greatly improving data interpretability, providing intuitive input for tiering decisions, reducing decision complexity, ensuring consistency across different test items through a unified labeling system, and enabling more refined performance differentiation and supporting more precise scenario matching through multi-level tiering.

[0041] Step S5: Based on the quality labels contained in the multiple test results of the chip, determine the target application scenario of the chip, and send a placement instruction carrying the target application scenario to the robot arm so that the robot arm can place the chip from the test position to the placement area corresponding to the target application scenario.

[0042] Specifically, after all tests are completed, the system enters the target application scenario decision-making and sorting execution phase. The target application scenario decision-making process uses accumulated quality tags for intelligent grading: First, it collects the quality tags obtained by the chip in all the passed tests; then, it matches the tag combinations with predefined application scenario requirements; application scenario requirements are defined in the form of scenario quality tags, accurately representing the specific requirements of the scenario for chip characteristics; the matching algorithm calculates the matching degree between the chip tag set and each scenario requirement; finally, it selects the scenario with the highest matching degree as the target application scenario. Exemplary matching rules include: server and supercomputing applications require tags such as "ultra-fast transmission rate" and "lowest access latency"; mobile devices and IoT applications require tags such as "optimal power consumption" and "good transmission rate"; consumer electronics applications require tags such as "cost optimization" and "complete basic functions"; downgrading is applicable to chips whose parameters are not optimal but within the allowable range. In the sorting execution phase, the host computer sends sorting instructions containing the target scenario identifier to the robotic arm. The robotic arm accurately transports the chip from the test station to the storage area corresponding to the target scenario according to the instructions. At the same time, the system updates the chip status record, including test results, quality tags, and final grading information. The possibilities for expansion in this stage include introducing multi-objective optimization algorithms to balance multiple dimensions such as performance, cost, and reliability; adding customized tiering rules to meet specific customer needs; or implementing tiering confidence assessments to handle boundary cases specially.

[0043] Furthermore, step S5, which involves determining the target application scenario of the chip based on the quality labels contained in the multiple test results of the chip, specifically includes: 1. Match the multiple quality tags carried by the chip with the scene quality tags corresponding to multiple preset application scenarios.

[0044] 2. Based on the matching results, the chips are assigned to the corresponding target application scenarios.

[0045] Specifically, application scenario matching employs a rule-based decision-making system. The process includes defining essential and optional labels for each application scenario, calculating the match between the chip label set and the requirements of each scenario, applying a weighted scoring algorithm (considering the differences in importance of different labels), and finally selecting the scenario with the highest overall score as the target application scenario. For example, the matching rules for server and supercomputing applications require essential labels to include SPEED_ULTRA_FAST and LATENCY_ULTRA_LOW, high-weight labels to include RELIABILITY_HIGH, and a minimum matching threshold of 90%. For mobile devices and IoT applications, the essential labels to include POWER_ULTRA_LOW and POWER_LOW, high-weight labels to include SPEED_FAST and SPEED_STANDARD, and a minimum matching threshold of 85%. The requirements for downgraded applications are relatively lenient; the only essential label is FUNCTIONAL_PASS, optional labels include any non-optimal performance labels, and certain parameters are allowed to deviate from standard values ​​within a safe range. This intelligent matching mechanism enables intelligent tiering decisions based on multi-dimensional data. By configuring weights, it flexibly adapts to the priorities of different application scenarios. Clear matching rules ensure the consistency and transparency of tiering decisions, while multi-scenario support maximizes the application value of each chip.

[0046] This embodiment establishes a complete closed-loop system of testing, decision-making, and sorting by coordinating hardware resources such as robotic arms and slave devices through a host computer system. This organically integrates the originally scattered and independent testing processes into a continuous and smooth automated workflow, completely eliminating delays and inconsistencies caused by manual intervention and significantly improving testing efficiency. Furthermore, by introducing a quality tagging system, the performance of chips in different test items is semantically described and quantitatively evaluated, achieving fine-grained grading based on multi-dimensional features. This multi-dimensional, fine-grained feature description method enables the system to accurately identify the unique performance characteristics of each chip, laying a solid data foundation for precise scenario matching. In addition, by establishing an intelligent mapping relationship between quality tags and application scenarios, a data-driven grading decision-making mechanism is realized. This system can comprehensively consider the chip's performance, power consumption, reliability, and other characteristics, automatically allocating it to the target application where it can best realize its value, significantly improving chip utilization efficiency and the overall value of the product.

[0047] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0048] In one embodiment, a host computer is provided, which corresponds one-to-one with the automated chip testing method described in the above embodiments. For example... Figure 2 As shown, the host computer includes a robotic arm control module 11, a verification module 12, a testing module 13, a marking module 14, and a scene allocation module 15.

[0049] The robot control module 11 is used to send placement instructions to the robot, so that the robot can place the chip from the loading area to the corresponding test position according to the placement instructions. Verification module 12 is used to receive the response signal returned by the robot after completing the placement action, and send the instruction carrying the test information to the lower computer corresponding to the test position so that the lower computer can complete the verification process according to the test information. The test module 13 is used to send different test commands to the lower-level machine in sequence after the verification process is passed, and to receive the test results fed back by the lower-level machine. The tagging module 14 is used to add a corresponding quality tag to the chip when the test results confirm that the test item has passed. The scenario allocation module 15 is used to determine the target application scenario of the chip based on the quality tags contained in the multiple test results of the chip, and send a placement instruction carrying the target application scenario to the robot arm so that the robot arm can place the chip from the test position to the placement area corresponding to the target application scenario.

[0050] Optionally, the test module 13 performs the operation of sequentially sending different test commands to the lower-level machine, specifically including: According to the predefined test sequence, at least two test instructions corresponding to the test items are sent sequentially to the lower-level machine corresponding to the test position. The test items include: contact detection, DC parameter test, functional test, performance test, and reliability test.

[0051] Optionally, the marking module 14 performs the operation of adding a corresponding quality label to the chip when the test results confirm that the test item has passed, specifically including: Determine whether the test item passes based on the test results; If the test is passed, a quality label is added to the chip to identify the characteristics of the test. If a test item fails, the testing process will be terminated.

[0052] Optionally, the marking module 14 performs the operation of adding a corresponding quality label to the chip, specifically including: For test results with specific test data, the test data is compared with a preset threshold, and a corresponding performance level quality label is generated based on the comparison result; For test items that pass or fail, a quality label indicating that the test item has passed is added to the chip, and the next test instruction is triggered.

[0053] Optionally, the scenario allocation module 15 performs the operation of determining the target application scenario of the chip based on the quality labels contained in multiple test results of the chip, specifically including: Match the multiple quality tags carried by the chip with the scene quality tags corresponding to multiple preset application scenarios; Based on the matching results, the chips are assigned to the corresponding target application scenarios.

[0054] Optionally, the robot control module 11 performs the operation of sending placement instructions to the robot, specifically including: The robot communicates with its controller via the Industrial Ethernet protocol to send placement instructions, which include the coordinates of the target test location, the chip batch number, and the task ID.

[0055] Optionally, the verification module 12 performs the operation of sending an instruction carrying test information to the lower-level machine corresponding to the test location, specifically including: Structured instruction frames are sent to the lower-level machine corresponding to the test location via TCP / IP protocol or dedicated bus. The instruction frames are encrypted and include frame header, target address, instruction type, test parameters and frame tail check code.

[0056] Optionally, the verification module 12 performs the verification process operations, specifically including: The lower-level machine receives the verification result from the lower-level machine. The verification result is generated by the lower-level machine after receiving the test information and comparing its own firmware version number and hardware board ID with the expected version number and board ID carried in the test information. Determine whether the verification passes based on the verification results.

[0057] For specific limitations regarding the host computer, please refer to the limitations of the automated chip testing method mentioned above, which will not be repeated here. Each module in the aforementioned host computer can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the computer device in hardware form or independent of it, or they can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0058] In one embodiment, a computer device is provided, the internal structure of which can be shown in the following diagram. Figure 3As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used to communicate with external clients via a network connection. When the computer program is executed by the processor, it performs the following steps: Send placement instructions to the robotic arm so that the robotic arm can place the chip from the loading area to the corresponding test position according to the placement instructions; After receiving the response signal returned by the robot arm after completing the placement action, send the instruction carrying the test information to the lower computer corresponding to the test position so that the lower computer can complete the verification process according to the test information; After the verification process is completed, different test commands are sent to the lower-level machine in sequence, and the test results fed back by the lower-level machine are received. Once the test results confirm that the test item has passed, add the corresponding quality label to the chip. Based on the quality labels contained in the multiple test results of the chip, the target application scenario of the chip is determined, and a placement instruction carrying the target application scenario is sent to the robot arm so that the robot arm can place the chip from the test position to the placement area corresponding to the target application scenario.

[0059] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor: Send placement instructions to the robotic arm so that the robotic arm can place the chip from the loading area to the corresponding test position according to the placement instructions; After receiving the response signal returned by the robot arm after completing the placement action, send the instruction carrying the test information to the lower computer corresponding to the test position so that the lower computer can complete the verification process according to the test information; After the verification process is completed, different test commands are sent to the lower-level machine in sequence, and the test results fed back by the lower-level machine are received. Once the test results confirm that the test item has passed, add the corresponding quality label to the chip. Based on the quality labels contained in the multiple test results of the chip, the target application scenario of the chip is determined, and a placement instruction carrying the target application scenario is sent to the robot arm so that the robot arm can place the chip from the test position to the placement area corresponding to the target application scenario.

[0060] It should be noted that the functions or steps that can be implemented by the computer-readable storage medium or computer device described above can be referred to the relevant descriptions in the foregoing method embodiments. To avoid repetition, they will not be described one by one here.

[0061] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other storage media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0063] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An automated chip testing method, characterized in that, It is applied to a host computer, and the method includes: Send a placement command to the robotic arm so that the robotic arm can place the chip from the loading area to the corresponding test position according to the placement command; After receiving the response signal returned by the robot arm after completing the placement action, send an instruction carrying test information to the lower-level machine corresponding to the test position so that the lower-level machine can complete the verification process according to the test information; After the verification process is completed, different test commands are sent to the lower-level machine in sequence, and the test results fed back by the lower-level machine are received. When the test results confirm that the test item has passed, a corresponding quality label is added to the chip. Based on the quality labels contained in the multiple test results of the chip, the target application scenario of the chip is determined, and a placement instruction carrying the target application scenario is sent to the robot arm so that the robot arm can place the chip from the test position to the placement area corresponding to the target application scenario.

2. The automated chip testing method according to claim 1, characterized in that, The step of sequentially sending different test commands to the lower-level machine includes: According to the predefined test sequence, at least two test instructions corresponding to the test items are sent sequentially to the lower-level machine corresponding to the test position. The test items include: contact detection, DC parameter test, functional test, performance test, and reliability test.

3. The automated chip testing method according to claim 1, characterized in that, When the test results confirm that the test item has passed, a corresponding quality label is added to the chip, including: Determine whether the test item passes based on the test results; If the test item passes, a quality label is added to the chip to identify the characteristics of the test item. If the test item fails, the testing process will be terminated.

4. The automated chip testing method according to claim 1, characterized in that, Adding a corresponding quality label to the chip includes: For test results with specific test data, the test data is compared with a preset threshold, and a corresponding performance level quality label is generated based on the comparison result. For test items that pass or fail, a quality label indicating that the test item has passed is added to the chip, and the next test instruction is triggered.

5. The automated chip testing method according to claim 1, characterized in that, The step of determining the target application scenario of the chip based on the quality labels contained in multiple test results of the chip includes: The chip carries multiple quality tags that are matched with the scene quality tags corresponding to multiple preset application scenarios. The chip is assigned to the corresponding target application scenario based on the matching results.

6. The automated chip testing method according to claim 1, characterized in that, Sending placement instructions to the robotic arm includes: The robot communicates with the controller of the robotic arm via the Industrial Ethernet protocol to send the placement instructions, which include the coordinates of the target test position, the chip batch number, and the task ID.

7. The automated chip testing method according to claim 1, characterized in that, Sending the instruction carrying test information to the lower-level machine corresponding to the test location includes: Structured instruction frames are sent to the lower-level machine corresponding to the test location via TCP / IP protocol or dedicated bus. The instruction frames are encrypted frames and include frame header, target address, instruction type, test parameters and frame tail check code.

8. The automated chip testing method according to claim 1, characterized in that, The verification process includes: The lower-level machine receives the verification result fed back by the lower-level machine. The verification result is generated by the lower-level machine after receiving the test information by comparing its own firmware version number and hardware board ID with the expected version number and board ID carried in the test information. Determine whether the verification passes based on the verification results.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the chip automated testing method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the chip automated testing method as described in any one of claims 1 to 8.

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