Wafer production control method, device, equipment and system and storage medium
By acquiring wafer inspection data and production context information, the inference strategy of the defect identification model is dynamically adjusted, solving the problem of high misjudgment rate of ADC system in dynamic production environment, and realizing precise control and cost optimization of wafer production process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-04-14
AI Technical Summary
Existing automated defect classification (ADC) systems cannot be effectively integrated with the wafer manufacturing process, resulting in a high misclassification rate in dynamic production environments, an inability to adapt to production changes in real time, and increased ineffective processing costs.
By acquiring wafer inspection data and production context information, the inference strategy of the defect identification model is dynamically adjusted to generate control commands to adapt to the dynamic production environment, reduce the false judgment rate, and optimize the processing.
It effectively reduced the misjudgment rate caused by changes in the production environment, reduced ineffective processing costs, and achieved precise control over the real-time production process.
Smart Images
Figure CN121865897A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a control method, apparatus, equipment, system, and storage medium for wafer production. Background Technology
[0002] The wafer manufacturing process includes processes such as crystal pulling, dicing, lapping, double-disk surface grinding (DDSG), and chemical mechanical polishing (CMP). These processes can all introduce defects onto the wafer surface.
[0003] In relevant solutions, an Automatic Defect Classification (ADC) system is typically used to extract visual features from wafer surface images, identify wafer defects using the extracted visual features, and classify the identified defects.
[0004] However, ADC systems typically operate as standalone detection tools, lacking integration with the wafer fabrication process. This prevents ADC systems from sensing the real-time dynamic production environment, leading to misjudgments. Summary of the Invention
[0005] This disclosure provides a control method, apparatus, equipment, system, and storage medium for wafer fabrication; it enables the ADC system to adapt to dynamic production environments, reduces the probability of misjudgments, and allows control of the current real-time production process, thereby reducing ineffective processing costs.
[0006] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a method for controlling wafer fabrication, including: Acquire the testing data and production context information of the wafer under test; Adjust the inference strategy of the defect identification model based on the production context information of the wafer under test; The modified defect identification model is used to analyze the detection data to obtain the defect classification results of the wafer under test; Based on the defect classification results of the wafer under test, control instructions are generated.
[0007] Secondly, this disclosure provides a control device for wafer fabrication, comprising: an acquisition module, an adjustment module, an analysis module, and a control module; wherein, The acquisition module is configured to acquire the inspection data and production context information of the wafer under test; The adjustment module is configured to adjust the inference strategy of the defect identification model based on the production context information of the wafer under test. The analysis module is configured to analyze the detection data using the adjusted defect identification model to obtain the defect classification results of the wafer under test; The control module is configured to generate control commands based on the defect classification results of the wafer under test.
[0008] Thirdly, this disclosure provides a computing device, including: a processor; and a memory storing a computer program; wherein the processor is configured to, when executing the computer program, implement the control method for wafer production as described in the first aspect.
[0009] Fourthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the control method for wafer production as described in the first aspect.
[0010] Fifthly, this disclosure provides a semiconductor manufacturing control system, comprising: Processing equipment is used to perform processing procedures on wafers to be tested; The production execution system is used to record maintenance status information of processing equipment and manage wafer flow; And, as described in the second aspect, a control device for wafer production, which is communicatively connected to the processing equipment and the production execution system, respectively.
[0011] This disclosure provides a control method, apparatus, equipment, system, and storage medium for wafer manufacturing; it utilizes wafer manufacturing context information to dynamically adjust a defect identification model, enabling the defect identification model to shift from static identification to dynamic perception, thereby adapting to the dynamic production environment and reducing the probability of misjudgment due to changes in the production environment; furthermore, it controls the current real-time production process based on the defect classification results output by the defect identification model, reducing ineffective processing costs. Attached Figure Description
[0012] Figure 1 This is a schematic diagram of the architecture of a semiconductor manufacturing control system provided in this disclosure.
[0013] Figure 2 This is a flowchart illustrating a control method for wafer fabrication provided in this disclosure.
[0014] Figure 3 This is a schematic diagram of a hierarchical storage structure provided in this disclosure.
[0015] Figure 4 This is a schematic diagram of the composition of a control device for wafer production provided in this disclosure.
[0016] Figure 5 This is a schematic diagram of the structure of a computing device provided in this disclosure. Detailed Implementation
[0017] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.
[0018] Figure 1 This is a schematic diagram of the architecture of the semiconductor manufacturing control system provided in this disclosure. See also... Figure 1 The semiconductor manufacturing control system 100 is logically divided into an edge sensing layer L1, a data transmission layer L2, a core computing layer L3, and a business execution layer L4.
[0019] exist Figure 1 In this process, the edge sensing layer L1 includes processing equipment 101 and inspection equipment 102. Specifically, processing equipment 101 includes all equipment covering the entire wafer manufacturing process, such as wire saw equipment for cutting single-crystal silicon rods, chamfering equipment for trimming wafer edge contours, double-disk surface grinding (DDSG) equipment for planarizing wafers, and polishing equipment for chemical mechanical polishing of wafers. Inspection equipment 102 includes a surface inspection system, a geometry station, a nanotopography instrument, and an electron microscope (SEM). These inspection devices utilize laser scattering, optical interference, or electron beam imaging principles to acquire microscopic morphology image data, nanotopography maps, defect distribution maps, and profile data of the wafer surface.
[0020] In this disclosure, the data transmission layer L2 employs a high-throughput, low-latency distributed architecture to handle the surge of large amounts of data generated during wafer fabrication. For example... Figure 1 As shown, the data transmission layer L2 includes: Object Storage Service (OSS) 104 and message middleware (Kafka) 105. Specifically, this disclosure employs an object storage cluster, enabling unstructured data generated by the detection device 102, such as images and waveforms, to be directly written to the buckets of OSS 104 via the mounted network file interface.
[0021] In some examples, when the inspection device 102 completes scanning a wafer and uploads the image, an inspection completion event is generated. This event contains metadata such as wafer identifier ID, processing device identifier ID, and image path. This event will be pushed to a topic in Kafka 105.
[0022] In some examples, structured data in the MES database, such as wafer batch transfer records and preventive maintenance (PM) records of processing equipment 101, can be incrementally synchronized to the ADC database in real time using data synchronization tools, such as Oracle GoldenGate (OGG) technology, to ensure the timeliness of production context information.
[0023] In this disclosure, the core computing layer L3 includes a wafer fabrication control device, which can typically be deployed in a private cloud or high-performance computing cluster. This control device receives wafer detection data and production context information from the data transmission layer L2, generates control commands using the wafer fabrication control method provided in this disclosure, and finally transmits the control commands to the business execution layer L4.
[0024] In this disclosure, the business execution layer L4 may include a Manufacturing Execution System (MES), an Equipment Engineering System (EES), and a Yield Management System (YMS), etc. After the control commands output by the core computing layer L3 are transmitted to these systems, these systems perform corresponding operations based on the control commands, such as instructing the MES to detain a batch of wafers or instructing the EES to lock a processing device, etc.
[0025] based on Figure 1 The semiconductor manufacturing control system 100 shown in this disclosure provides a control method for wafer production. Figure 2 This is a flowchart illustrating the control method. In this disclosure, the control method is executed by a wafer production control device in the core computing layer L3, which is equipped with a defect identification model for identifying wafer defect types.
[0026] See Figure 2 In step S210, the detection data and production context information of the wafer under test are obtained.
[0027] In this disclosure, the wafer fabrication control unit receives a detection completion message by subscribing to a Kafka 104 topic. The message body contains the URL of the object storage. The wafer fabrication control unit retrieves the detection data based on the URL. Taking image-based detection data as an example, the wafer fabrication control unit preprocesses the image detection data upon receiving it.
[0028] Specifically, this preprocessing can include operations such as cropping, scaling, enhancement, and mapping. Specifically, the wafer fabrication control unit removes invalid background at the edges of image data through cropping to extract the Region of Interest (ROI). The wafer fabrication control unit scales image data of different resolutions to a size that can be input into the defect recognition model, such as 512x512 or 1024x1024, through scaling. The wafer fabrication control unit enhances the image data through operations such as Gaussian blurring to smooth noise, histogram equalization to enhance contrast, or grayscale conversion to reduce computational load. The wafer fabrication control unit maps the coordinate data into an intuitive wafer map or a full-wafer profile curve, facilitating input into the defect recognition model, such as a convolutional neural network (CNN), to extract global features.
[0029] In some examples, the wafer manufacturing control unit initiates a query request to the MES system or database using the wafer ID of the wafer under test to obtain the wafer's production context information. Specifically, the production context information includes: equipment history, material history, and associated data. For example, equipment history includes the identifier of the current processing equipment, the timestamp of the most recent PM (Processing Part) for that equipment, the currently used consumables (such as the cumulative processing time of polishing pads), and the current alarm code of the processing equipment. Material history includes the block ID of the wafer under test, the growth parameters of the ingot to which the wafer under test belongs (such as pulling speed and dopant concentration), and the position of the wafer under test within the ingot (such as head, middle, or tail). Associated data includes the inspection results of other wafers in the same lot as the wafer under test, and the defect distribution characteristics of wafers belonging to the same block as the wafer under test in previous lots.
[0030] In step S220, the inference strategy of the defect identification model is adjusted based on the production context information of the wafer under test.
[0031] In this disclosure, the operating parameters of the defect identification model, such as the confidence threshold and classification set, are modified based on the production context information of the wafer under test to adjust the inference strategy of the defect identification model. Thus, the adjusted inference strategy is more suitable for dynamically changing production environments, avoiding the increase in false positive rates caused by static operating parameters in dynamically changing production environments.
[0032] In step S230, the adjusted defect identification model is used to analyze the detection data to obtain the defect classification results of the wafer under test.
[0033] In this disclosure, preprocessed detection data is input into an adjusted defect identification model, and the adjusted defect identification model outputs the defect classification results of the wafer under test. Specifically, the defect identification model may include a large visual model based on architectures such as Faster R-CNN, YOLOv5, or Mask R-CNN, or a time-series analysis model for non-image data, such as one-dimensional convolutional networks (1D-CNN) or LSTM used for profile curves.
[0034] In step S240, control instructions are generated based on the defect classification results of the wafer under test.
[0035] In this disclosure, control commands for controlling processing equipment are generated based on the defect classification results of the wafer under test and in combination with preset instruction rules, and then sent to the corresponding processing equipment through MES, thereby realizing real-time closed-loop control of the production process.
[0036] pass Figure 2 The technical solution shown utilizes wafer production context information to dynamically adjust the defect identification model, enabling the model to shift from static identification to dynamic perception, thereby adapting to the dynamic production environment and reducing the probability of misjudgment due to changes in the production environment. Furthermore, the current real-time production process is controlled based on the defect classification results output by the defect identification model, reducing ineffective processing costs.
[0037] In some examples, preventive maintenance (PM) events of wafer processing equipment have a significant impact on process stability. For example, in the polishing process, after replacing a new polishing pad and a retainer ring, the polishing equipment needs to go through a break-in period. During this break-in period, the micro-texture on the surface of the polishing pad is not yet stable, and it is easy to leave extremely shallow lines on the wafer surface. These lines are visible under extremely sensitive nano-topography detection equipment. Conventional ADC systems, due to the fixed decision threshold, usually misjudge these wafers with lines as qualified wafers during the break-in period after PM, resulting in a large number of defective wafers being misjudged as qualified.
[0038] Based on this, in the present disclosure, the production context information includes the maintenance status information of the equipment for processing the wafer to be measured. Thus, adjusting the inference strategy of the defect recognition model according to the production context information of the wafer to be measured includes: When the current processing time point or processing batch of the equipment is within a preset monitoring window after a maintenance event occurs, the confidence threshold for the defect recognition model to determine the qualified category is increased from the first threshold to the second threshold.
[0039] Specifically, the control device for wafer production subscribes to the device status change messages published by MES to learn that the equipment maintenance event is completed. After obtaining the detection data of the wafer to be measured, the control device for wafer production queries the last PM time T_pm of the processing equipment for this wafer to be measured, and calculates the time difference Δt between the current time T_now and T_pm, or queries the cumulative number of processed batches N_lot of this processing equipment since the last PM.
[0040] The control device for wafer production can preset a monitoring window. For example, set a time monitoring window Window_Time = 4 hours for the time difference Δt, or set a batch monitoring window Window_Lot = 10 Lots for the cumulative number of processed batches N_lot since the last PM.
[0041] After calculating the time difference Δt or querying the cumulative number of processed batches N_lot of this processing equipment since the last PM, the control device for wafer production can compare Δt or N_lot with the time monitoring window Window_Time and the batch monitoring window Window_Lot respectively.
[0042] In the case where Δt < Window_Time or N_lot < Window_Lot, the control device for wafer production determines that the wafer to be measured is in the break-in period after PM.
[0043] When the wafer manufacturing control system determines that the wafer under test is in the break-in period after part defect detection (PM), it increases the confidence threshold for the defect identification model, such as the nanoMap model, to determine whether it is acceptable. Specifically, under normal circumstances, the confidence threshold for the nanoMap model to determine that a wafer is acceptable (OK) is the first threshold, for example, 0.5. That is, as long as the nanoMap model believes that the inspection data of the wafer, such as the nanoMap image, has a greater than 50% probability of being OK, then the wafer is considered acceptable.
[0044] However, during the break-in period after PM (partial polishing), the background noise caused by the patterns left by the polishing pads on the wafer surface is significant. To prevent potential defects from being missed, the confidence threshold for classifying wafers as OK in the NanoMap model during the break-in period after PM can be increased from 0.5 to 0.8, i.e., the second threshold. This means that during the break-in period after PM, the defect identification model deployed in the wafer production control device has a stricter standard for classifying wafers as OK. This is because during the unstable break-in period, any tiny abnormal signal may indicate that PM is not in place; therefore, increasing the confidence threshold for classifying as OK can effectively prevent batch accidents.
[0045] After raising the confidence threshold for the defect identification model to determine OK, when the confidence level for the wafer under test to be determined to be OK is set to 0.7, since it is less than the second threshold, i.e. 0.8, the wafer under test is not directly determined to be qualified (OK), but can be marked as suspicious (Suspect), and a review instruction is generated to prompt manual intervention for confirmation.
[0046] In some examples, the physicochemical reactions during crystal growth determine the intrinsic properties of the wafer. Take intrinsic defects as an example, such as crystal-originated particles (COPs), which are tiny octahedral voids formed by the aggregation of vacancies during the pulling process of a single-crystal silicon rod. In images, COP defects typically appear as tiny black or bright spots, and their morphological characteristics are extremely similar to "particles" or "stains" introduced during processing.
[0047] However, when a COP defect occurs, since it is a material characteristic, its acceptance is usually determined by customer specifications. Even if the wafer under test is identified as having a COP defect, it is not necessary to stop the machine for inspection. On the other hand, particle or stain defects are considered process abnormalities, which often mean that the cavity of the processing equipment is contaminated and must be stopped for cleaning. In other words, misclassifying a COP defect as a particle or stain defect will lead to frequent false alarms on the production line, severely impacting the equipment uptime (OEE).
[0048] Because the distribution of COP defects along the length of the crystal ingot is continuous during crystal production, meaning that for a crystal block cut from a crystal ingot, if the crystal block has COP defects, then all wafers cut from that crystal block will have COP defects. Based on this, in this disclosure, the production context information includes the detection information of the crystal block to which the wafer under test belongs. Accordingly, adjusting the inference strategy of the defect identification model based on the production context information of the wafer under test includes: Obtain the target native defects of associated wafers belonging to the same crystal block; Based on the target native defects, a target classification set for the wafer under test is determined from the original defect category set of the defect identification model; wherein, the target classification set includes the target native defects and excludes non-native defects.
[0049] Specifically, the wafer production control device can query the block identifier ID of the wafer to be tested from the MES system or database, and query the inspection history of wafers previously processed in that block from the database, or query the quality inspection report of the ingot growth.
[0050] If this is the first time a block is being processed, the wafer production control unit will wait for the inspection data from the previous few wafers of this block, such as the first five associated wafers. It will then perform an overlay operation on the defect maps of these five associated wafers. This is because COP defects on the wafer typically exhibit a ring-like or centrally concentrated distribution related to crystal growth zones. In contrast, processing defects, such as particles and contaminants, are usually randomly distributed or exhibit a linear distribution related to the mechanical movement trajectory.
[0051] Based on this, if the overlay results show that the defects exhibit obvious concentric circle distribution characteristics, or if the historical record of the block shows that it is a "COP-rich crystal rod", it indicates that the block has a tendency to have COP defects, and similar defects on the wafer under test belonging to the block are highly likely to be COP.
[0052] Therefore, to avoid misclassifying COP defects as particle or stain defects, the wafer manufacturing control system adjusts the output space of the defect identification model. For example, the initial defect category set includes: COP defects, scratch defects, particle defects, chemical contamination defects, and OK. In other words, the defect classification result of the wafer under test output by the defect identification model is usually generated only from the initial defect category set. However, when a block is prone to having COP defects, the wafer manufacturing control system retains only COP defects and OK from the initial defect category set to form the target classification set, excluding non-native defects such as scratch defects, particle defects, and chemical contamination defects.
[0053] For the testing data of the wafer under test, the conventional storage structure is usually organized according to the asset hierarchy, for example... This storage structure is convenient for equipment maintenance, but it reduces retrieval efficiency for wafer inspection.
[0054] Specifically, wafer quality issues are often highly correlated. For example, several wafers cut from the same block or ingot will still retain block characteristics, such as COP defect distribution and resistivity stripes, after being processed by different equipment. If the inspection data is stored using a conventional storage structure, the wafer production control device will have to search through hundreds of different device folders in the database when analyzing the inspection data of all wafers from a single ingot or block, resulting in a large number of I / O operations and extremely low retrieval efficiency.
[0055] Based on this, in this disclosure, the test data of the wafer under test is stored in a set hierarchical storage structure. In this set hierarchical storage structure, the identifier of the block to which the wafer under test belongs is the top-level index, the process type of the wafer under test is the second-level index, and the production batch of the wafer under test is the third-level index.
[0056] In detail, Figure 3 In the hierarchical storage structure 300 shown, the first-level index 301, or top-level index, is specifically the Block ID or Ingot ID. This is the source identifier of the wafer under test. All test data from wafers originating from the same ingot or the same block are grouped under this directory. This allows the wafer production control device to locate all relevant data in O(1) time complexity when performing defect analysis on the entire ingot or block, without having to traverse multiple device folders.
[0057] The second level, index 302, represents the process type. Examples include DDSG, Polishing, and Cleaning. This level categorizes wafer inspection data according to their lifecycle stages.
[0058] The third-level index 303 is the production lot ID. A lot is the basic logistics unit in the production flow, typically containing 25 wafers.
[0059] In this disclosure, the hierarchical storage structure may also include a fourth-level index 304, namely the wafer ID. This index points to all images, maps, and profile data of the wafer in the current process.
[0060] The hierarchical storage structure provided in this disclosure allows for faster retrieval of historical data from the block to which the wafer belongs, such as residual defects from previous processes and test results of other related wafers in the same block, compared to conventional storage structures, during the acquisition of production context information for the wafer under test. This improves the response speed of the wafer production control device.
[0061] exist Figure 2 In the technical solution shown, the control commands can be used to control both the wafer products and the processing equipment.
[0062] For wafer products, in some examples, generating control instructions based on the defect classification results of the wafer under test includes: When the defect classification result indicates an anomaly, a target handling instruction is generated from the candidate handling instructions based on the level of the anomaly.
[0063] The candidate disposal instructions include: single-wafer disposal instructions for the wafer under test, batch disposal instructions for the batch to which the wafer under test belongs, or disposal instructions for the wafer block to which the wafer under test belongs and wafers of the batch derived from that block.
[0064] Specifically, the control devices in wafer production can classify the handling of wafer products into the following three levels based on the severity and density of defects: The first level is the single wafer level. At this level, disposal instructions can include: Hold, which means that when a single wafer has an undetermined defect, the single wafer hold instruction is sent to the automated handling system (OHT) to place the single wafer in the review stocker for manual review; Scrap, which means that when a fatal defect is detected, such as a large crack or edge chipping, the single wafer is directly marked as scrapped to prevent it from flowing into subsequent processes and causing equipment damage, such as fragments causing vacuum chamber contamination; Rework, which means that for repairable defects, such as surface dirt or watermarks, a rework instruction is generated to route the single wafer back to the cleaner for cleaning again; Downgrade, which means that for single wafers with excessively high COP density but which do not affect mechanical properties, they are downgraded to monitor wafers or dummy wafers for debugging of processing equipment to maximize the value of the material.
[0065] The second level is the batch level. For example, if more than 30% of the wafers in a batch are deemed defective, the wafer production control device can trigger a hold-lot disposal instruction, which usually indicates that the batch of wafers has experienced a process fluctuation.
[0066] The third level is the block level. For example, if multiple consecutive batches (lots) of wafers belonging to the same block exhibit abnormalities, such as excessive resistivity or high COP defect density, the wafer production control device can issue disposal instructions for the block or the wafers derived from that block. Upon receiving the disposal instruction, the MES will freeze all remaining wafers in the block's inventory, prohibiting them from being put into production to avoid batch loss.
[0067] For processing equipment, in some examples, generating control instructions based on the defect classification results of the wafer under test includes: Based on the defect classification results, a status adjustment instruction is sent to the production execution system for the equipment processing the wafer under test. This status adjustment instruction includes locking the upstream processing equipment or triggering the calibration of the equipment process parameters.
[0068] Specifically, during the production process, in addition to handling defective wafers, adjustments to the processing equipment are necessary to eliminate the root causes of defective wafers. For example, when the wafer production control device detects defects with obvious equipment characteristics, such as periodic scratches or severe grinding marks, it immediately sends an equipment lock (EQP_LOCK) command to the MES (Manufacturing Execution System). Upon receiving this command, the MES will switch the status of the processing equipment in the preceding process of the wafer under test to a locked state and cut off the load port of that processing equipment, forcing a shutdown. This prevents the processing equipment from continuing to operate with potential defects.
[0069] Furthermore, for non-fatal parameter drifts, such as when the wafer fabrication control unit detects an overall wafer thickness deviation that is too large but still within specifications through geometric parameter measurements, the control unit calculates the deviation value, generates a process parameter calibration command, and feeds it back to the polishing machine. The polishing machine automatically adjusts process parameters such as polishing pressure or time parameters for the next batch, achieving closed-loop automatic calibration of the process.
[0070] See Figure 4 This illustration shows the composition of a wafer fabrication control device 400 provided in this disclosure. The control device 400 includes: an acquisition module 410, an adjustment module 420, an analysis module 430, and a control module 440; wherein, The acquisition module 410 is configured to acquire the detection data and production context information of the wafer under test; The adjustment module 420 is configured to adjust the inference strategy of the defect identification model based on the production context information of the wafer under test. Analysis module 430 is configured to analyze the detection data using the adjusted defect identification model to obtain the defect classification results of the wafer under test; The control module 440 is configured to generate control commands based on the defect classification results of the wafer under test.
[0071] In some examples, the production context information includes maintenance status information of the equipment that processes the wafer under test; Adjustment module 420 is configured as follows: When the current processing time or batch of the equipment is within the preset monitoring window after a maintenance event occurs, the confidence threshold for the defect identification model to be classified as qualified is raised from the first threshold to the second threshold.
[0072] In some examples, the production context information includes detection information for the block to which the wafer under test belongs; Adjustment module 420 is configured as follows: Obtain the target native defects of associated wafers belonging to the same crystal block; Based on the target native defects, a target classification set for the wafer under test is determined from the original defect category set of the defect identification model; wherein, the target classification set includes the target native defects and excludes non-native defects.
[0073] In some examples, the target native defect includes crystal native grain COP defects, and the non-native defect includes at least scratch defects, dirt defects, or grain defects.
[0074] In some examples, the test data of the wafer under test is stored in a hierarchical structure, which uses the identifier of the block to which the wafer under test belongs as the top-level index, the process type of the wafer under test as the second-level index, and the production batch of the wafer under test as the third-level index.
[0075] In some examples, control module 440 is configured as follows: When the defect classification result indicates an anomaly, a target disposal instruction is generated from the candidate disposal instructions according to the level of the anomaly; wherein, the candidate disposal instructions include: a single-wafer disposal instruction for the wafer under test, a batch disposal instruction for the batch to which the wafer under test belongs, or a disposal instruction for the die block to which the wafer under test belongs and wafers of the batch derived from the die block.
[0076] In some examples, control module 440 is configured as follows: Based on the defect classification results, a status adjustment instruction is sent to the production execution system for the equipment processing the wafer under test. This status adjustment instruction includes locking the upstream processing equipment or triggering the calibration of the equipment process parameters.
[0077] In some examples, the detection data includes microscopic topographic images of the surface of the wafer under test; the defect identification model includes a visual classification model based on a convolutional neural network or a defect detection model based on nanoscale topographic images.
[0078] In some examples, module 410 is configured as follows: Listen for data collection events using a message broker; The detection data is read in real time from the object storage service using the mounted network file interface.
[0079] Please refer to Figure 5This diagram illustrates a structural block diagram of a computing device provided in an exemplary embodiment of this disclosure. In some examples, the control device 400 for wafer fabrication can be implemented by the computing device 50. The computing device 50 can be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The computing device 50 has communication capabilities and can access wired or wireless networks. The computing device 50 can refer to one of multiple terminals, and those skilled in the art will understand that the number of such terminals can be more or less. In some examples, the computing device 50 can receive data based on the accessed wired or wireless network. It is understood that the computing device 50 undertakes the calculation and processing work of the technical solution of this disclosure, and this disclosure does not limit it in this regard.
[0080] like Figure 5 As shown, the computing device in this disclosure may include one or more of the following components: processor 510 and memory 520.
[0081] Optionally, the processor 510 connects various parts within the computing device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 520, and by calling data stored in the memory 520. Optionally, the processor 510 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 510 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used for wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 510, but may be implemented using a separate chip.
[0082] The memory 520 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 520 may include a non-transitory computer-readable storage medium. The memory 520 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 520 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created according to the use of the computing device, etc.
[0083] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation on the computing device. The computing device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the computing device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.
[0084] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the wafer fabrication control method described in the various embodiments above.
[0085] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the control method for wafer production described in the above embodiments.
[0086] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.
[0087] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.
[0088] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A control method for wafer fabrication, characterized in that, The control method includes: Acquire the testing data and production context information of the wafer under test; The reasoning strategy of the defect identification model is adjusted based on the production context information of the wafer under test. The detection data is analyzed using the adjusted defect identification model to obtain the defect classification results of the wafer under test; Based on the defect classification results of the wafer under test, control instructions are generated.
2. The control method according to claim 1, characterized in that, The production context information includes the maintenance status information of the equipment used to process the wafer under test; The step of adjusting the inference strategy of the defect identification model based on the production context information of the wafer under test includes: When the current processing time or batch of the equipment is within a preset monitoring window after a maintenance event occurs, the confidence threshold for the defect identification model to be classified as qualified is raised from the first threshold to the second threshold.
3. The control method according to claim 1, characterized in that, The production context information includes the detection information of the wafer to be tested belonging to the wafer block; The step of adjusting the inference strategy of the defect identification model based on the production context information of the wafer under test includes: Obtain the target native defects of associated wafers belonging to the same crystal block; Based on the target native defect, a target classification set is determined for the wafer under test from the original defect category set of the defect identification model; wherein the target classification set includes the target native defect and excludes non-native defects.
4. The control method according to claim 3, characterized in that, The target native defects include crystal native particle COP defects, and the non-native defects include at least scratch defects, dirt defects, or particle defects.
5. The control method according to claim 1, characterized in that, The detection data of the wafer under test is stored in a hierarchical structure. The hierarchical storage structure uses the identifier of the block to which the wafer under test belongs as the top-level index, the process type of the wafer under test as the second-level index, and the production batch of the wafer under test as the third-level index.
6. The method according to claim 1, characterized in that, The step of generating control instructions based on the defect classification results of the wafer under test includes: When the defect classification result indicates an anomaly, a target disposal instruction is generated from the candidate disposal instructions according to the level of the anomaly; wherein, the candidate disposal instructions include: a single-wafer disposal instruction for the wafer under test, a batch disposal instruction for the batch to which the wafer under test belongs, or a disposal instruction for the die block to which the wafer under test belongs and wafers of the batch derived from the die block.
7. The method according to claim 1, characterized in that, The step of generating control instructions based on the defect classification results of the wafer under test includes: Based on the defect classification results, a status adjustment instruction is sent to the production execution system for the equipment processing the wafer under test. The status adjustment instruction includes locking the upstream processing equipment or triggering the calibration of the equipment process parameters.
8. The method according to claim 1, characterized in that, The detection data includes microscopic morphology image data of the surface of the wafer under test; the defect recognition model includes a visual classification model based on convolutional neural networks or a defect detection model based on nanoscale morphology images.
9. The method according to claim 1, characterized in that, The acquisition of the test data of the wafer under test includes: Listen for data collection events using a message broker; The detection data is read in real time from the object storage service using the mounted network file interface.
10. A control device for wafer fabrication, characterized in that, The control device includes: an acquisition module, an adjustment module, an analysis module, and a control module; wherein... The acquisition module is configured to acquire the detection data and production context information of the wafer under test; The adjustment module is configured to adjust the inference strategy of the defect identification model based on the production context information of the wafer under test. The analysis module is configured to analyze the detection data using an adjusted defect identification model to obtain the defect classification result of the wafer under test; The control module is configured to generate control commands based on the defect classification results of the wafer under test.
11. A computing device, characterized in that, The computing device includes: a processor; and a memory in which a computer program is stored. When the processor is configured to execute the computer program, it implements the control method for wafer production as described in any one of claims 1 to 9.
12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the control method for wafer production as described in any one of claims 1 to 9.
13. A semiconductor manufacturing control system, characterized in that, The control system includes: Processing equipment is used to perform processing procedures on wafers to be tested; The production execution system is used to record the maintenance status information of the processing equipment and manage the wafer flow. And, as described in claim 10, the wafer production control device is communicatively connected to both the processing equipment and the production execution system.