Three-dimensional memory device including multi-layer trench bridge structure and method of forming same

Abstract

A semiconductor structure includes a first layer structure including a pair of first alternating stacks of first insulating layers and first conductive layers; a memory opening including a memory opening fill structure extending vertically through the first layer structure; a lateral isolation cavity located between the pair of first alternating stacks and having a pair of lengthwise sidewalls, each having first vertically straight and laterally concave surface sections of the first layer structure adjoining one another at a first vertically extending edge; and a perforated first layer bridge structure comprising a different material than the insulating layer located in the lateral isolation cavity.

Description

Cross-reference to related applications

[0001] This application claims the benefit and priority of U.S. Patent Application Serial No. 18 / 598,782, filed on March 7, 2024. Technical Field

[0002] This disclosure relates in general to the field of semiconductor devices, and more specifically to three-dimensional memory devices including multilayer trench bridging structures and methods for forming the same. Background Technology

[0003] A three-dimensional vertical NAND string with one bit per cell is disclosed in the article entitled “Novel Ultra High Density Memory With AStacked-Surrounding Gate Transistor (S-SGT) Structured Cell” by T. Endoh et al. (2001), pages 33-36. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor structure includes: a first layer structure including a pair of first alternating stacks of a first insulating layer and a first conductive layer; a memory opening extending vertically through the first layer structure; a memory opening filling structure located in the memory opening, wherein each memory opening filling structure includes a vertical semiconductor channel and a memory film; a lateral isolation trench located between the pair of first alternating stacks and including a lateral isolation cavity having a pair of longitudinally extending sidewalls generally along a first horizontal direction, wherein each longitudinally extending sidewall of the lateral isolation cavity includes a first vertically straight and laterally concave surface segment of the first layer structure adjacent to each other at a first vertically extending edge; and a lateral isolation trench filling structure located in the lateral isolation trench. The transverse isolation trench filling structure includes: a first bridging structure comprising a material different from the insulating layer, wherein each of the first bridging structures has at least one vertically extending perforation through a corresponding set therethrough; and an insulating spacer extending continuously above the sidewall of the transverse isolation cavity.

[0005] According to another aspect of this disclosure, a method of forming a semiconductor structure includes: forming a first alternating stack of a first insulating layer and a first sacrificial material layer; forming a first memory aperture and a first isolation aperture through the first alternating stack; forming a first sacrificial memory aperture filling structure and a first sacrificial isolation aperture filling structure in the first memory aperture and the first isolation aperture, respectively; forming a first bridging structure around a subset of the first sacrificial isolation aperture filling structures; forming a second alternating stack of a second insulating layer and a second sacrificial material layer above the first alternating stack; forming a second memory aperture and a second isolation aperture through the second alternating stack; and removing the first sacrificial memory aperture filling structure. The structure includes a memory opening formed within the volume of a first layer memory opening and a second layer memory opening; a memory opening filling structure formed within the memory opening, wherein each memory opening filling structure includes a corresponding vertical semiconductor channel and a vertical memory film; removal of a first layer sacrificial isolation opening filling structure, wherein a layer spacer exit is formed within the volume of the first layer isolation opening and the volume of the second layer isolation opening; and laterally extending the layer spacer exit to form a lateral isolation cavity by performing a first isotropic etching process that selectively isotropically etches a first alternating stack and a second alternating stack relative to the first layer bridging structure. Attached Figure Description

[0006] Figure 1 This is a schematic vertical cross-sectional view of an exemplary structure for forming a memory die after a first alternating stack of a first insulating layer and a first sacrificial material layer and a first insulating cap layer are formed on a carrier substrate, according to a first embodiment of the present disclosure.

[0007] Figure 2 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the first stepped surface and the first stepped dielectric material portion, according to an embodiment of the present disclosure.

[0008] Figure 3A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the first layer memory opening, the first layer support opening, and the first layer isolation opening, according to an embodiment of the present disclosure.

[0009] Figure 3B yes Figure 3A The top-down view of the exemplary structure. Vertical plane A-A' is... Figure 3A The cutting plane of the vertical cross-section.

[0010] Figure 4 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the first layer of sacrificial opening filler material portion, according to an embodiment of this disclosure.

[0011] Figure 5A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the first-layer bridging structure, according to an embodiment of the present disclosure.

[0012] Figure 5B yes Figure 5A A top-down view of an exemplary structure. Vertical plane A-A' is... Figure 5A The cutting plane of the vertical cross-section.

[0013] Figure 6A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the first-layer bridging structure, according to an embodiment of the present disclosure.

[0014] Figure 6B yes Figure 6A A top-down view of an exemplary structure. Vertical plane A-A' is... Figure 6A The cutting plane of the vertical cross-section.

[0015] Figure 7 This is a schematic vertical cross-sectional view of an exemplary structure following the formation of a second alternating stack of a second insulating layer and a second sacrificial material layer, a second insulating cap layer, a second stepped surface, and a second stepped dielectric material portion, according to an embodiment of this disclosure.

[0016] Figure 8A This is a schematic vertical cross-sectional view of an exemplary structure following the formation of the second layer of sacrificial opening filler material and the second layer of bridging structure, according to an embodiment of this disclosure.

[0017] Figure 8B yes Figure 8A A top-down view of an exemplary structure. Vertical plane A-A' is... Figure 8A The cutting plane of the vertical cross-section.

[0018] Figure 9A This is a schematic vertical cross-sectional view of an exemplary structure following the formation of a third alternating stack of a third insulating layer and a third sacrificial material layer, a third insulating cap layer, a third stepped surface, a third stepped dielectric material portion, a third layer sacrificial opening-filling material portion, and a third layer bridging structure, according to an embodiment of this disclosure.

[0019] Figure 9B yes Figure 9A A top-down view of an exemplary structure. Vertical plane A-A' is... Figure 9A The cutting plane of the vertical cross-section.

[0020] Figure 10 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of interlayer support openings according to an embodiment of the present disclosure.

[0021] Figure 11 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the support column structure, according to an embodiment of the present disclosure.

[0022] Figure 12 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of an interlayer memory opening, according to an embodiment of the present disclosure.

[0023] Figures 13A to 13D This is a sequential vertical cross-sectional view of the regions surrounding the multilayer memory opening during the formation of the memory opening filling structure according to an embodiment of the present disclosure.

[0024] Figure 14A This is a vertical cross-sectional view of an exemplary structure after the formation of the memory opening filling structure according to an embodiment of the present disclosure.

[0025] Figure 14B yes Figure 14A A top-down view of an exemplary structure. Vertical plane A-A' is... Figure 14A The cutting plane of the vertical cross-section.

[0026] Figure 15A This is a vertical cross-sectional view of an exemplary structure after the contact level dielectric layer and contact level openings have been formed and patterned, according to an embodiment of the present disclosure.

[0027] Figure 15B yes Figure 15A A top-down view of an exemplary structure. The hinged vertical plane A-A' is... Figure 15A The cutting plane of the vertical cross-section.

[0028] Figure 16A This is a vertical cross-sectional view of an exemplary structure after the opening of the forming layer spacer, according to an embodiment of the present disclosure.

[0029] Figure 16B yes Figure 16A A top-down view of an exemplary structure. The hinged vertical plane A-A' is... Figure 16A The cutting plane of the vertical cross-section.

[0030] Figure 17A This is a vertical cross-sectional view of an exemplary structure after the formation of a transverse isolation trench, according to an embodiment of the present disclosure.

[0031] Figure 17B It is along Figure 17A The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane B-B'. The hinged vertical plane A-A' is... Figure 17A The cutting plane of the vertical cross-section.

[0032] Figure 17CIt is along Figure 17A A horizontal cross-sectional view of an exemplary structure in the horizontal plane C-C'. The hinged vertical plane A-A' is... Figure 17A The cutting plane of the vertical cross-section.

[0033] Figure 17D It is along Figure 17A A horizontal cross-sectional view of an exemplary structure in the horizontal plane D-D'. The hinged vertical plane A-A' is... Figure 17A The cutting plane of the vertical cross-section.

[0034] Figure 17E It is based on the implementation scheme of this disclosure. Figure 17B A vertical cross-sectional view of an exemplary structure of the vertical plane E-E'.

[0035] Figure 18A This is a vertical cross-sectional view of an exemplary structure after the formation of the lateral extension cavity, according to an embodiment of the present disclosure.

[0036] Figure 18B It is along Figure 18A The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane B-B'. The hinged vertical plane A-A' is... Figure 18A The cutting plane of the vertical cross-section.

[0037] Figure 19A This is a vertical cross-sectional view of an exemplary structure after the formation of a conductive layer, according to an embodiment of the present disclosure.

[0038] Figure 19B yes Figure 19A A top-down view of an exemplary structure. The hinged vertical plane A-A' is... Figure 19A The cutting plane of the vertical cross-section.

[0039] Figure 20A This is a vertical cross-sectional view of an exemplary structure after the formation of the transverse isolation trench filling structure according to an embodiment of the present disclosure.

[0040] Figure 20B It is along Figure 20A The horizontal cross-sectional view of the exemplary structure is taken by the horizontal plane B-B'. The hinged vertical plane A-A' is... Figure 20A The cutting plane of the vertical cross-section.

[0041] Figure 20C It is along Figure 20A A horizontal cross-sectional view of an exemplary structure in the horizontal plane C-C'. The hinged vertical plane A-A' is... Figure 20A The cutting plane of the vertical cross-section.

[0042] Figure 20D It is along Figure 20AA horizontal cross-sectional view of an exemplary structure in the horizontal plane D-D'. The hinged vertical plane A-A' is... Figure 20A The cutting plane of the vertical cross-section.

[0043] Figure 20E It is based on the implementation scheme of this disclosure. Figure 20B A vertical cross-sectional view of an exemplary structure of the vertical plane E-E'.

[0044] Figure 21 This is a vertical cross-sectional view of an exemplary structure after various contact via structures have been formed, according to an embodiment of this disclosure.

[0045] Figure 22 This is a vertical cross-sectional view of an exemplary structure according to an embodiment of the present disclosure, which involves forming a memory-side dielectric material layer and a memory-side metal interconnect structure to form a memory die, and attaching a logic die to the memory die.

[0046] Figure 23 This is a vertical cross-sectional view of an exemplary structure after the carrier substrate has been removed and the source layer has been formed, according to an embodiment of the present disclosure.

[0047] Figures 24 to 31 This is a vertical cross-sectional view of an alternative configuration of an exemplary structure according to various embodiments of the present disclosure. Detailed Implementation

[0048] As discussed above, embodiments of this disclosure relate to a three-dimensional memory device including a multilayer trench bridging structure and a method for forming the same, various aspects of which are now described in detail. Embodiments of this disclosure can be used to form semiconductor devices, such as three-dimensional memory devices comprising multiple memory strings.

[0049] The accompanying drawings are not to scale. Multiple instances of an element may be reproduced where only a single instance is illustrated, unless otherwise explicitly described or clearly indicated that a reproduction of the element does not exist. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0050] Like reference numerals denote the same or similar elements. Unless otherwise specified, elements with the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements providing an edge or surface shared by these elements. If two or more elements are not in direct contact with each other or with each other, the two elements are “separated” from each other or “separated from each other”. As used herein, a first element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the surfaces of the second element, the first element is “directly” located “on” the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure whose shape or composition is subsequently modified.

[0051] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the first continuous structure. For example, a layer may be located between the top and bottom surfaces of the first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0052] As used herein, the first and second surfaces are “vertically coincident” if the second surface overlies or lies beneath the first surface and a vertical or substantially vertical plane comprising the first and second surfaces is present. A substantially vertical plane is a plane extending in a straight line along an angle less than 5 degrees deviating from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0053] As used herein, a “memory level” or “memory array level” refers to a level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) of the topmost surface of the array of memory elements and a second horizontal plane of the bottommost surface of the array of memory elements. As used herein, a “through-stack” element refers to an element that extends vertically through the memory level.

[0054] As used in this article, "semiconductor material" refers to a material in which electrical conductivity is greater than 1.0 × 10⁻⁶ in the absence of electrical dopants. -5 Materials with electrical conductivity ranging from S / m to 1.0 S / m, and which, after appropriate doping with an electrical dopant, can produce conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶. 7 Doped materials in the S / m range. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material with a conductivity greater than 1.0 × 10⁻⁶. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a conductivity less than 1.0 × 10⁻⁶. -5 Materials with a S / m ratio. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a value greater than 1.0 × 10⁻⁶. 5 The conductivity is S / m. "Doped semiconductor material" can be a heavily doped semiconductor material, or it can be a semiconductor material comprising electrically dopants (i.e., p-type dopants and / or n-type dopants) at a concentration of 1.0 × 10⁻⁶. -5 S / m to 1.0×10 7 Conductivity in the S / m range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrically conductive agent. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrically conductive agent therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element. All conductivity measurements were performed under standard conditions.

[0055] Generally speaking, a semiconductor package (or "package") refers to a single semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or "chip") or multiple semiconductor chips fully bonded together, for example, through flip-chip bonding or chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit capable of independently executing external commands or reporting status. Typically, a package or chip with multiple dies can execute as many external commands simultaneously as the total number of dies contained therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but some limitations may exist. When the die is a memory die (i.e., a die containing memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased in a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0056] refer to Figure 1 This illustrates an exemplary structure according to embodiments of the present disclosure. The exemplary structure includes a base material layer, over which a layer stack is subsequently formed. In one embodiment, the base material layer includes a carrier substrate 9, which may be a semiconductor substrate. For example, the carrier substrate 9 may include a commercially available silicon wafer. Alternatively, the carrier substrate 9 may include any material that can be selectively removed relative to the material of the subsequently formed overlay material.

[0057] A first alternating stack of a first insulating layer 132 and a first spacer material layer may be formed on a carrier substrate 9. In one embodiment, the first spacer material layer may include a first sacrificial material layer 142. In this case, a first alternating stack (132, 142) of the first insulating layer 132 and the first sacrificial material layer 142 may be formed on the carrier substrate 9. The first insulating layer 132 comprises an insulating material such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, and the first sacrificial material layer 142 comprises a sacrificial material such as silicon nitride or silicon germanium. In one embodiment, the first insulating layer 132 may include a silicon oxide layer, and the first sacrificial material layer 142 may include a silicon nitride layer. The first alternating stack (132, 142) may include multiple repetitions of a unit layer stack including the first insulating layer 132 and the first sacrificial material layer 142. The total number of repetitions of the unit layer stack within the first alternating stack (132, 142) may be, for example, in the range of 8 to 1,024 (e.g., 32 to 256), but fewer and more repetitions may also be used.

[0058] The thickness of each first insulating layer in the first insulating layer 132 may be in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), but smaller and larger thicknesses may also be used. The thickness of each first sacrificial material layer in the first sacrificial material layer 142 may be in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), but smaller and larger thicknesses may also be used.

[0059] A first insulating capping layer 170 may be formed over a first alternating stack (132, 142). In one embodiment, the first insulating capping layer 170 has a homogeneous material composition. In one embodiment, the first insulating capping layer 170 comprises, and / or is substantially composed of, a dielectric material selected from undoped and doped silicate glasses. In one embodiment, the thickness of the first insulating capping layer 170 may be in the range of 60 nm to 400 nm (e.g., 100 nm to 300 nm), but smaller and larger thicknesses are also possible.

[0060] The first insulating capping layer 170 can be formed by chemical vapor deposition. In one embodiment, the first insulating capping layer 170 comprises a silicon oxide material formed by the decomposition of a precursor material (such as tetraethyl orthosilicate (TEOS)) used for silicon oxide deposition. In one embodiment, the first insulating capping layer 170 may contain residual carbon atoms and / or residual hydrogen atoms. In one embodiment, the carbon concentration in the first insulating capping layer 170 may be in the range of 2 ppm to 5,000 ppm, such as 10 ppm to 1,000 ppm. In one embodiment, the hydrogen concentration in the first insulating capping layer 170 may be in the range of 100 ppm to 10,000 ppm, such as 300 ppm to 5,000 ppm.

[0061] An exemplary structure includes a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will subsequently be formed, and in the contact region, a layer contact via structure for contact word lines will subsequently be formed.

[0062] refer to Figure 2 A first stepped surface is formed in the contact area 300. As used herein, a “stepped surface” refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. The first stepped cavity is formed within the volume from which portions of the first alternating stack (132, 142) and the first insulating cap layer 170 are removed by the formation of the first stepped surface. A “stepped cavity” refers to a cavity having a stepped surface.

[0063] The first stepped cavity may have various first stepped surfaces, such that the horizontal profile shape of the first stepped cavity changes stepwise as a function of the vertical distance from the top surface of the supporting substrate 9. In one embodiment, the first stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the depth of the cavity by one or more levels, and the second type of etching process laterally extending the area vertically etched in a subsequent first type of etching process. As used herein, a “level” comprising alternating plurality of structures is defined as the relative position of a pair of first and second material layers within the structure.

[0064] Each first sacrificial material layer 142 within the first alternating stack (132, 142), except for the topmost first sacrificial material layer 142, extends laterally further than any overlying first sacrificial material layer 142 within the stepped region of the first alternating stack (132, 142). The first stepped surface of the first alternating stack (132, 142) extends continuously from the bottom layer within the first alternating stack (132, 142) to the first insulating cap layer 170. Typically, the first stepped surface extends continuously from the bottom layer within the first alternating stack (132, 142) to at least the top layer within the first alternating stack (132, 142).

[0065] A first stepped dielectric material portion 165 (i.e., an insulating filler portion) can be formed in a first stepped cavity by depositing a dielectric material therein. For example, a dielectric material (such as silicon dioxide) can be deposited in the first stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from the top surface of the first insulating cap layer 170 by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the first stepped cavity constitutes the first stepped dielectric material portion 165. As used herein, a “stepped” element refers to an element having a first stepped surface and a horizontal cross-sectional area that monotonically increases as a function of the vertical distance from the top surface of the substrate on which the element is situated. If silicon dioxide is used for the first stepped dielectric material portion 165, the silicon dioxide of the first stepped dielectric material portion 165 may be doped with or may not be doped with dopants such as B, P, and / or F. In one embodiment, a first stepped dielectric material portion 165 is overlaid on and in contact with a first stepped surface, and has a top surface that is coplanar with the top surface of the first insulating cap layer 170.

[0066] refer to Figure 3A and Figure 3BA first etch mask layer (not shown) may be formed over a first insulating cap layer 170. The first etch mask layer may comprise a carbon-based material, such as amorphous carbon or diamond-like carbon. A photoresist layer (not shown) may be formed over the first etch mask layer and may be photolithographically patterned to form various openings therein. A first anisotropic etch process may be performed to transfer the pattern of the openings in the photoresist layer through the first etch mask layer, the first insulating cap layer 170, and the upper portion of the combination of the first alternating stack (132, 142) and the first stepped dielectric material portion 165. The various openings may include a first layer memory opening 149 formed in the memory array region 100, a first layer support opening 129 formed in the contact region 300, and a first layer lateral isolation opening 179 optionally extending laterally across the memory array region 100 and the contact region 300 along a first horizontal direction hd1. Each of the first layer memory opening 149, the first layer support opening 129, and the first layer lateral isolation opening 179 may extend vertically through the first alternating stack (132, 142). Alternatively, the first layer lateral isolation opening 179 may be formed separately from the first layer memory opening 149 and the first layer support opening 129 during separate photolithography and etching steps.

[0067] The first layer support opening 129 may have a maximum diameter in the range of 50 nm to 400 nm (e.g., 70 nm to 300 nm), but smaller and larger maximum diameters are also possible. The first layer memory opening 149 may have a maximum diameter in the range of 50 nm to 400 nm (e.g., 70 nm to 300 nm), but smaller and larger maximum diameters are also possible. The width of the first layer lateral isolation opening 179 may be in the range of 150 nm to 600 nm (e.g., 200 nm to 400 nm), but smaller and larger widths are also possible. Each of the first layer memory opening 149, the first layer support opening 129, and the first layer lateral isolation opening 179 may have a corresponding tapered sidewall, such that the upper portion has a larger lateral dimension (e.g., diameter) than the lower portion.

[0068] In one embodiment, the memory array region 100 may be laterally spaced from the contact region 300 along a first horizontal direction hd1. The first layer memory openings 149 may include multiple rows of first layer memory openings 149 arranged along the first horizontal direction hd1 and laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2. Multiple clusters of first layer memory openings 149 may be formed in the memory array region 100, each cluster containing a corresponding two-dimensional periodic array of first layer memory openings 149. The clusters of first layer memory openings 149 may be laterally spaced along the second horizontal direction hd2. The first layer lateral isolation openings 179 may be formed as multiple rows of first layer lateral isolation openings 179. Each row of first layer lateral isolation openings 179 may be arranged along the first horizontal direction hd1.

[0069] refer to Figure 4 An optional etch-stop liner (not shown) and a first sacrificial filler material may be deposited in the first layer memory opening 149, the first layer support opening 129, and the first layer lateral isolation opening 179. The optional etch-stop liner (if present) comprises a thin silicon oxide layer with a thickness ranging from 1 nm to 6 nm. The first sacrificial filler material may comprise a carbon-based material, such as amorphous carbon or diamond-like carbon.

[0070] The first etch mask layer can be selectively removed relative to the material of the first insulating cap layer 170. A planarization process can be performed to remove portions of the first sacrificial filler material from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portions of the first sacrificial filler material filling the first layer memory opening 149, the first layer support opening 129, and the first layer lateral isolation opening 179 constitute the first layer sacrificial opening filler material portions (147, 127, 177). The first layer sacrificial opening filler material portions (147, 127, 177) include the first layer sacrificial memory opening filler material portion 147 formed in the first layer memory opening 149, the first layer sacrificial support opening filler material portion 127 formed in the first layer support opening 129, and the first layer sacrificial isolation opening filler material portion 177 formed in the first layer lateral isolation opening 179.

[0071] refer to Figure 5A and Figure 5BA photoresist layer (not shown) may be applied over the first insulating cap layer 170 and may be photolithographically patterned to form discrete openings on a corresponding subset of the first layer sacrificial isolation opening-fill material portions 177. Each discrete opening may have a periphery that encloses a corresponding subset of the first layer sacrificial isolation opening-fill material portions 177 in a plan view. In the illustrated example, each discrete opening may enclose a corresponding set of three first layer sacrificial isolation opening-fill material portions 177 in a plan view. However, each discrete opening may enclose fewer than or more than three of the first layer sacrificial isolation opening-fill material portions 177.

[0072] A selective anisotropic etching process can be performed to selectively etch the materials of the first insulating cap layer 170, the first sacrificial material layer 142, and the first insulating layer 132 relative to the material of the first sacrificial isolation opening-fill material portion 177. In an exemplary example, if the first insulating cap layer 170 and the first insulating layer 132 comprise silicon oxide, if the first sacrificial material layer 142 comprises silicon nitride, and if the first sacrificial isolation opening-fill material portion 177 comprises amorphous carbon, a reactive ion etching process employing a mixture of CF4 and CHF3 can be performed to selectively etch the materials of the first insulating cap layer 170, the first sacrificial material layer 142, and the first insulating layer 132 relative to the material of the first sacrificial isolation opening-fill material portion 177.

[0073] A cavity is formed in the volume from which the material of the first insulating cap layer 170, the first sacrificial material layer 142, and the first insulating layer 132 is removed; this cavity is referred to herein as a first-layer bridging cavity 171. Each first-layer bridging cavity 171 laterally surrounds the upper portion of a corresponding set of first-layer sacrificial isolation openings filled with material portions 177. Although Figure 5BThe illustration shows an embodiment in which each first-layer bridging cavity 171 laterally surrounds three first-layer sacrificial isolation opening-fill material portions 177. However, in alternative embodiments, each first-layer bridging cavity 171 may laterally surround fewer or more than three first-layer sacrificial isolation opening-fill material portions 177. The bottom surface of each first-layer bridging cavity 171 may be formed at the level of the first insulating cap layer 170, or at the level of one of the first sacrificial material layers 142 or one of the first insulating layers 132. In one embodiment, the bottom surface of each first-layer bridging cavity 171 may be formed below the topmost first sacrificial material layer 142 or at the level below the Nth first sacrificial material layer 142 from the top, where N is an integer from 2 to 10. The height of the first bridging cavity 171 can be in the range of 0.5% to 10% of the thickness of the first layer structure, which is the sum of the thickness of the first alternating stack (132, 142) and the thickness of the first insulating cap layer 170.

[0074] In one embodiment, the portion of the first sacrificial material layer 142 exposed in the first bridging cavity 171 is oxidized to form a first lateral fin spacer 144, which extends laterally from the sidewall of the first bridging cavity 171 and contacts the remaining portion of the first sacrificial layer 142. Oxidation may include plasma and / or thermal oxidation in an oxygen-containing environment (e.g., in an oxygen gas, air, or nitrous oxide (N₂O) environment). If the first sacrificial material layer 142 comprises silicon nitride, the first lateral fin spacer 144 comprises silicon oxide or silicon oxynitride.

[0075] refer to Figure 6A and Figure 6B A first cavity filler material can be deposited into the first layer bridging cavity 171. The first cavity filler material comprises a material different from the material of the first alternating stack (132, 142) and the first layer sacrificial isolation opening filler portion 177. For example, the first cavity filler material may comprise a semiconductor material, such as amorphous silicon or polycrystalline silicon. Excess portions of the first cavity filler material can be removed from above a horizontal plane including the top surface of the first insulating cap layer 170 by performing a planarization process that may include a chemical mechanical polishing process and / or a recess etching process. Each remaining portion of the first cavity filler material filling a corresponding first layer bridging cavity in the first layer bridging cavity 171 constitutes a first layer bridging structure 172. In one embodiment, the top surface of the first layer bridging structure 172 may be coplanar with the top surface of the first insulating cap layer 170, i.e., may be formed in a horizontal plane including the top surface of the first insulating cap layer 170. Typically, the first layer bridging structure 172 surrounds a subset of the first layer sacrificial isolation opening fill structure 177. Although Figure 6BAn embodiment is illustrated in which each first-layer bridging structure 172 laterally surrounds three first-layer sacrificial isolation opening-fill material portions 177. However, in an alternative embodiment, each first-layer bridging structure 172 may laterally surround fewer or more than three first-layer sacrificial isolation opening-fill material portions 177. Figure 6B In one embodiment shown, each first-layer bridging structure 172 includes a pair of length-direction sidewalls 172L extending laterally along a first horizontal direction (e.g., word line direction) hd1, and a pair of width-direction sidewalls 172W extending laterally along a second horizontal direction (e.g., bit line direction) hd2, which may be perpendicular to the first horizontal direction hd1. Each first-layer bridging structure 172 contacts a cylindrical surface segment of a subset of the first-layer sacrificial isolation opening-fill structure 177 and has a top surface in the same horizontal plane as the top surface of the first-layer sacrificial isolation opening-fill structure 177. A first lateral fin-shaped spacer 144 prevents contact between the first-layer bridging structure 172 and the first sacrificial material layer 142.

[0076] refer to Figure 7 Optionally, the reference can be implemented with any desired changes. Figure 1 and Figure 2 The described processing steps form a second alternating stack of a second insulating layer 232 and a second sacrificial material layer 242, a second insulating cap layer 270, a second stepped surface, and a second stepped dielectric material portion 265. The second stepped surface may be laterally offset relative to the first stepped surface toward the memory array region 100.

[0077] refer to Figure 8A and Figure 8B The reference can be implemented with any necessary changes. Figures 3A to 6B The described processing steps are to form a second layer opening, a second layer sacrificial opening filler portion (247, 227, 277), a second lateral fin spacer 244, and a second layer bridging structure 272. The second layer sacrificial opening filler portion (247, 227, 277) may include a second layer sacrificial memory opening filler portion 247 formed in the second layer memory opening, a second layer sacrificial support opening filler portion 227 formed in the second layer support opening, and a second layer sacrificial isolation opening filler portion 277 formed in the second layer lateral isolation opening.

[0078] In a top-down view, a second bridging cavity may be formed above the region of the first bridging structure 172. In other words, in a top-down view, the region of the second bridging cavity may be the same as the region of the first bridging structure 172. A second cavity filler material may be deposited in the second bridging cavity. The second cavity filler material comprises a material different from the material of the second alternating stack (232, 242) and the second sacrificial isolation opening filler portion 277. For example, the second cavity filler material may comprise a semiconductor material, such as amorphous silicon or polycrystalline silicon. Excess portions of the second cavity filler material may be removed from above a horizontal plane including the top surface of the second insulating cap layer 270 by performing a planarization process that may include a chemical mechanical polishing process and / or a recess etching process. Each remaining portion of the second cavity filler material filling a corresponding second bridging cavity in the second bridging cavity constitutes the second bridging structure 272. In one embodiment, the top surface of the second bridging structure 272 may be coplanar with the top surface of the second insulating cap layer 270, i.e., it may be formed in a horizontal plane including the top surface of the second insulating cap layer 270. The second bridging structure 272 may be formed around a subset of the second sacrificial isolation opening-filling structures 277 (e.g., fewer than three, exactly three, or more than three). In one embodiment, each second bridging structure 272 includes a pair of length-direction sidewalls extending laterally along a first horizontal direction hd1, and a pair of width-direction sidewalls extending laterally along a second horizontal direction hd2, which may be perpendicular to the first horizontal direction hd1. Each second bridging structure 272 contacts a cylindrical surface segment of the subset of the second sacrificial isolation opening-filling structures 277 and has a top surface in the same horizontal plane as the top surface of the second sacrificial isolation opening-filling structures 277.

[0079] refer to Figure 9A and Figure 9B Optionally, the reference can be implemented with any desired changes. Figure 1 and Figure 2 The described processing steps form a third alternating stack of a third insulating layer 332 and a third sacrificial material layer 342, a third insulating cap layer 370, a third stepped surface, and a third stepped dielectric material portion 365. The third stepped surface may be laterally offset relative to the second stepped surface toward the memory array region 100.

[0080] The reference can be implemented with any necessary changes. Figures 3A to 6BThe described processing steps form a third-layer opening, a third-layer sacrificial opening filling material portion (347, 327, 377), a third lateral fin spacer 344, and a third-layer bridging structure 372. The third-layer sacrificial opening filling material portion (347, 327, 377) may include a third-layer sacrificial memory opening filling material portion 347 formed in the third-layer memory opening, a third-layer sacrificial support opening filling material portion 327 formed in the third-layer support opening, and a third-layer sacrificial isolation opening filling material portion 377 formed in the third-layer lateral isolation opening.

[0081] In a top-down view, a third-layer bridging cavity may be formed above the region of the second-layer bridging structure 272. In other words, in a top-down view, the region of the third-layer bridging cavity may be the same as the region of the second-layer bridging structure 272. A third-layer cavity filler material may be deposited in the third-layer bridging cavity. The third-layer cavity filler material comprises a material different from the material of the third alternating stack (332, 342) and the third-layer sacrificial isolation opening filler portion 377. For example, the third-layer cavity filler material may comprise a semiconductor material, such as amorphous silicon or polycrystalline silicon. Excess portions of the third-layer cavity filler material may be removed from above a horizontal plane including the top surface of the third insulating cap layer 370 by performing a planarization process that may include a chemical mechanical polishing process and / or a recess etching process. Each remaining portion of the third-layer cavity filler material filling a corresponding third-layer bridging cavity in the third-layer bridging cavity constitutes the third-layer bridging structure 372. In one embodiment, the top surface of the third bridging structure 372 may be coplanar with the top surface of the third insulating cap layer 370, i.e., may be formed in a horizontal plane including the top surface of the third insulating cap layer 370. The third bridging structure 372 may be formed around a subset of the third sacrificial isolation opening-filling structures 377 (e.g., fewer than three, exactly three, or more than three). In one embodiment, each third bridging structure 372 includes a pair of length-direction sidewalls extending laterally along a first horizontal direction hd1, and a pair of width-direction sidewalls extending laterally along a second horizontal direction hd2, which may be perpendicular to the first horizontal direction hd1. Each third bridging structure 372 contacts a cylindrical surface segment of the subset of the third sacrificial isolation opening-filling structures 377 and has a top surface in the same horizontal plane as the top surface of the third sacrificial isolation opening-filling structures 377. A drain selection layer isolation structure (e.g., silicon oxide filled trench) 72 extending laterally along the first horizontal direction hd1 can be formed through a subset of the uppermost third sacrificial material layer 342 that will replace the drain-side selected gate electrode.

[0082] Although the memory device is illustrated as having three layers, in alternative embodiments, there may be one, two, or more than three layers. Furthermore, while an embodiment is illustrated in which each layer includes a corresponding bridging structure, in alternative embodiments, the bridging structure may be omitted in one or more layers. For example, in a three-layer memory device, the third-layer bridging structure 372 may be omitted. In a two-layer memory device, the second-layer bridging structure 272 may be omitted.

[0083] refer to Figure 10 A photoresist layer (not shown) may be applied over the third insulating cap layer 170 and the third stepped dielectric material portion 365, and may be photolithographically patterned to cover the third sacrificial memory aperture fill material portion 347 and the third sacrificial isolation aperture fill material portion 377, but not the third sacrificial support aperture fill material portion 327. An ashing process may be performed to remove the various sacrificial support aperture fill material portions (327, 227, 127). An interlayer support opening 19 (also referred to as support opening 19) may be formed in the volume from which the sacrificial support aperture fill material portions (327, 227, 127) are removed.

[0084] Each interlayer support opening 19 includes a first tapered sidewall extending vertically through the first layer structure, a second tapered sidewall extending vertically through the second layer structure, a third tapered sidewall extending vertically through the third layer structure, a first annular flat surface located in a first horizontal plane including the top surface of the first layer structure and having an inner periphery adjacent to the bottom periphery of the second tapered sidewall and an outer periphery adjacent to the top periphery of the first tapered sidewall, and a second annular flat surface located in a second horizontal plane including the top surface of the second layer structure and having an inner periphery adjacent to the bottom periphery of the third tapered sidewall and an outer periphery adjacent to the top periphery of the second tapered sidewall.

[0085] refer to Figure 11 Dielectric filler material (such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass) may be conformally deposited in the interlayer support openings 19. Excess portions of the dielectric filler material can be removed from above a third horizontal plane, including the topmost surface of the third insulating cap layer 370, by performing a planarization process. The planarization process may include a chemical mechanical polishing process and / or a recessed etching process. Each remaining portion of the dielectric filler material filling the respective interlayer support opening 19 constitutes a dielectric pillar structure 20.

[0086] Each dielectric pillar structure in the dielectric pillar structure 20 includes a first tapered sidewall extending vertically through the first layer structure, an optional second tapered sidewall extending vertically through the second layer structure, an optional third tapered sidewall extending vertically through the third layer structure, a first annular flat surface located in a first horizontal plane including the top surface of the first layer structure and having an inner periphery adjacent to the bottom periphery of the second tapered sidewall and an outer periphery adjacent to the top periphery of the first tapered sidewall, and an optional second annular flat surface located in a second horizontal plane including the top surface of the second layer structure and having an inner periphery adjacent to the bottom periphery of the third tapered sidewall and an outer periphery adjacent to the top periphery of the second tapered sidewall.

[0087] refer to Figure 12 A photoresist layer (not shown) may be applied over a third insulating cap layer 170 and a third stepped dielectric material portion 365, and may be photolithographically patterned to cover a third sacrificial isolation opening-fill material portion 377 but not a third sacrificial memory opening-fill material portion 347. An ashing process may be performed to remove the various sacrificial memory opening-fill material portions (347, 247, 147). An interlayer memory opening 49 (also referred to as memory opening 49) may be formed in the volume of material from which the sacrificial memory opening-fill material portions (347, 247, 147) are removed. The memory opening 49 is formed by creating a void within the volume of the first layer memory opening 149, an optional second layer memory opening, and an optional third layer memory opening.

[0088] Each interlayer memory opening 49 includes a first tapered sidewall extending vertically through the first layer structure, an optional second tapered sidewall extending vertically through the second layer structure, an optional third tapered sidewall extending vertically through the third layer structure, a first annular flat surface located in a first horizontal plane including the top surface of the first layer structure and having an inner periphery adjacent to the bottom periphery of the second tapered sidewall and an outer periphery adjacent to the top periphery of the first tapered sidewall, and an optional second annular flat surface located in a second horizontal plane including the top surface of the second layer structure and having an inner periphery adjacent to the bottom periphery of the third tapered sidewall and an outer periphery adjacent to the top periphery of the second tapered sidewall.

[0089] Figures 13A to 13D This is a sequential vertical cross-sectional view of the regions surrounding the multilayer memory opening during the formation of the memory opening filling structure according to an embodiment of the present disclosure.

[0090] refer to Figure 13A Examples are shown in Figure 12 The memory opening 49 follows the processing steps. (See reference.) Figure 13BA layer stack including a memory material layer 54 can be conformally deposited. In an exemplary example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric pad 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing changes in resistivity, ferroelectric polarization, or any other measurable physical property. Where the memory material layer 54 includes a charge storage material, the optional dielectric pad 56 may include a tunneling dielectric layer.

[0091] The semiconductor channel material layer 60L can be deposited on top of the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, it can have a first conductivity type of doping, which can be p-type or n-type. In one embodiment, the first semiconductor material comprises a first doped silicon material having a first conductivity type of doping. In an exemplary example, the atomic concentration of the first conductivity type of dopant in the semiconductor channel material layer 60L can be 1.0 × 10⁻⁶. 13 / cm 3 Up to 3.0×10 17 / cm 3 Within the range, such as 1.0 × 10 14 / cm 3 Up to 3.0×10 16 / cm 3 However, smaller and larger atomic concentrations can also be used. A dielectric core layer 62L, including a dielectric filling material (e.g., silicon oxide), can be deposited in the remaining volume of the memory opening 49 and deposited over the alternating stack (32, 42).

[0092] refer to Figure 13C The dielectric core layer 62L may be vertically recessed, such that each remaining portion of the dielectric core layer 62L has a top surface at or near a horizontal plane including the bottom surface of the insulating cap layer 370. Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62.

[0093] refer to Figure 13D A doped semiconductor material having a second conductivity type can be deposited in each recessed region above the dielectric core 62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be 5.0 × 10⁻⁶. 18 / cm 3 Up to 2.0×10 21 / cm3 Within the range, but smaller or larger dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material having dopant of a second conductivity type and a horizontal portion of the semiconductor channel layer 60L can be removed (e.g., by chemical mechanical planarization (CMP) or recess etching processes) above a horizontal plane including the top surface of the insulating cap layer 370. Each remaining portion of the doped semiconductor material having dopant of a second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L (having dopant of a first conductivity type) constitutes a vertical semiconductor channel 60.

[0094] Each portion of the stack of layers, including the memory material layer 54 retained in the respective memory opening 49, constitutes a memory film 50. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, the memory material layer 54, and an optional dielectric pad 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a respective vertical stack of memory elements, which may include a portion of the memory material layer 54 located at the level of the sacrificial material layer 42.

[0095] In an alternative embodiment, the interlayer support opening 19 and the memory opening 49 can be formed in the same step by simultaneously removing the sacrificial support opening filler material portions (327, 227, 127) and the sacrificial memory opening filler material portions (347, 247, 147). In this embodiment, in Figures 13A to 13D During the same deposition and patterning steps shown, the interlayer support opening 19 and memory opening 49 are filled with the same set of materials. In this embodiment, the support pillar structure 20 includes a dummy memory opening filling structure having the same composition as the memory opening filling structure 58, but not electrically connected to the corresponding bit line.

[0096] refer to Figure 14A and Figure 14B Examples are shown in the reference Figure 13DThe exemplary structure following the described processing steps. A memory aperture filling structure 58 is formed in the memory aperture 49. Each memory aperture filling structure in the memory aperture filling structure includes a corresponding vertical semiconductor channel 60. Each memory aperture filling structure in the memory aperture filling structure 58 includes a first tapered sidewall extending vertically through the first layer structure, an optional second tapered sidewall extending vertically through the second layer structure, an optional third tapered sidewall extending vertically through the third layer structure, a first annular flat surface located in a first horizontal plane including the top surface of the first layer structure and having an inner periphery adjacent to the bottom periphery of the second tapered sidewall and an outer periphery adjacent to the top periphery of the first tapered sidewall, and an optional second annular flat surface located in a second horizontal plane including the top surface of the second layer structure and having an inner periphery adjacent to the bottom periphery of the third tapered sidewall and an outer periphery adjacent to the top periphery of the second tapered sidewall.

[0097] refer to Figure 15A and Figure 15B The contact-level dielectric layer 80 may be deposited over the third insulating cap layer 370. The contact-level dielectric layer 80 includes a dielectric material (such as silicon oxide) and may have a thickness in the range of 100 nm to 800 nm, but smaller and larger thicknesses are also possible.

[0098] A photoresist layer 77 may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form strip-shaped openings overlying the sacrificial isolation opening-fill material portions (177, 277, 377) of the corresponding row. An anisotropic etching process may be performed to form slit-shaped openings through the contact-level dielectric layer 80 over the regions of the sacrificial isolation opening-fill material portions (177, 277, 377). These slit-shaped openings are referred to herein as contact-level openings 87.

[0099] refer to Figure 16A and Figure 16BAn ashing or selective etching process can be performed to remove various sacrificial isolation opening filler portions (177, 277, 377). Vertically extending through-holes 73 and interlayer spacer openings 75 (also referred to as isolation openings 75) can be formed in the volume of material from which the sacrificial isolation opening filler portions (377, 277, 177) are removed. The vertically extending through-holes 73 extend through bridging structures (172, 272, 372), while the interlayer spacer openings 75 are located between laterally adjacent and vertically adjacent bridging structures (172, 272, 372). However, the bridging structures (172, 272, 372) were not removed and remained laterally positioned between, above, and below the interlayer spacer exit 75 because the bridging structures (172, 272, 372) included semiconductor material that was not removed by ashing or selective etching of the sacrificial isolation opening fill material portions (377, 277, 177).

[0100] Each of the layer spacing exits 75 includes a first tapered sidewall extending vertically through the first layer structure, an optional second tapered sidewall extending vertically through the second layer structure, and an optional third tapered sidewall extending vertically through the third layer structure.

[0101] refer to Figures 17A to 17E It can perform at least one selective isotropic etching process to selectively etch the materials of the insulating layer (132, 232, 332), the sacrificial material layer (142, 242, 342), and the insulating cap layer (170, 270, 370) relative to the semiconductor material of the bridging structure (172, 272, 372) and the carrier substrate 9. For example, if the insulating layers (132, 232, 332) and the insulating cap layers (170, 270, 370) comprise silicon oxide, and if the sacrificial material layers (142, 242, 342) comprise silicon nitride, a wet etching process using a buffered oxide etch (BOE) solution (containing a mixture of about 5% to 7% by volume hydrofluoric acid, about 25% to 40% by volume ammonium hydroxide, and deionized water) can be used to isotropically etch the materials of the insulating layers (132, 232, 332), the sacrificial material layers (142, 242, 342), and the insulating cap layers (170, 270, 370) at approximately the same etch rate. The duration of at least one selective isotropic etching process can be selected such that each row of layers merges at the opening 75 to form a corresponding lateral isolation cavity 79.

[0102] Typically, the interlayer spacer openings 75 can be isotropically extended by performing a first isotropic etching process that selectively and isotropically etches a first alternating stack (132, 142), a second alternating stack (232, 242), and a third alternating stack (332, 342) relative to the first interlayer bridging structure 172, the second interlayer bridging structure 272, and the third interlayer bridging structure 372. A continuous lateral isolation cavity 79 is formed in each volume formed by merging the interlayer spacer openings 75 of a corresponding row.

[0103] Usually, in Figure 16A and 16B The combination of a first alternating stack (132, 142), an optional second alternating stack (232, 242), and an optional third alternating stack (332, 342) provided after the processing steps can be divided into a plurality of laterally spaced layer stacks (e.g., memory blocks) laterally spaced from each other by lateral isolation trenches. The lateral isolation trenches (172, 272, 372, 79) include the volume of bridging structures (172, 272, 372) and lateral isolation cavities 79. In other words, each lateral isolation trench (172, 272, 372, 79) includes the volume of a lateral isolation cavity 79, and also includes the volume of a subset of bridging structures (172, 272, 372) located within the respective lateral isolation cavity 79. Therefore, each transverse isolation trench (172, 272, 372, 79) is filled with a first-layer bridging structure 172 of the corresponding row, a second-layer bridging structure 272 of the corresponding row, and a third-layer bridging structure 372 of the corresponding row.

[0104] The lateral isolation cavities 79 are located between adjacent pairs of first alternating stacks (132, 142), adjacent pairs of second alternating stacks (232, 242), and adjacent pairs of third alternating stacks (332, 342). Each lateral isolation trench (172, 272, 372, 79) includes a pair of longitudinal sidewalls extending transversely generally along a first horizontal direction hd1. Each longitudinal sidewall of the lateral isolation trench (172, 272, 372, 79) includes a first vertically straight and laterally concave surface section of a first layer structure adjacent to each other at a first vertically extending edge, an optional second vertically straight and laterally concave surface section of a second layer structure adjacent to each other at a second vertically extending edge, and an optional third vertically straight and laterally concave surface section of a third layer structure adjacent to each other at a third vertically extending edge. As used herein, a “vertically straight” surface section refers to a surface section having a straight vertical cross-sectional profile. As used in this article, a "transverse concave" surface section refers to a surface section with a concave horizontal cross-sectional profile.

[0105] In one embodiment, a first subset of a first vertically straight and laterally concave surface segment of the first layer structure extends vertically from the top surface of the first layer structure to a first horizontal plane including the bottom surface of the first layer bridging structure 172. A second subset of the first vertically straight and laterally concave surface segment of the first layer structure lies entirely below the horizontal plane including the bottom surface of the first layer bridging structure 172. In one embodiment, a first subset of a second vertically straight and laterally concave surface segment of the second layer structure extends vertically from the top surface of the second layer structure to a second horizontal plane including the bottom surface of the second layer bridging structure 272. A second subset of the second vertically straight and laterally concave surface segment of the second layer structure lies entirely below the horizontal plane including the bottom surface of the second layer bridging structure 272. In one embodiment, a first subset of a third vertically straight and laterally concave surface segment of the second layer structure extends vertically from the top surface of the third layer structure to a third horizontal plane including the bottom surface of the third layer bridging structure 372. The second subset of the third vertical and horizontally concave surface section of the third layer structure lies entirely below the horizontal plane of the bottom surface including the third layer bridging structure 372.

[0106] In one embodiment, the center of curvature of the pair of first vertically straight and laterally concave surface segments facing each other in the first layer structure lies on a vertical line passing through the geometric center of one of the vertically extending perforations 73 in the first layer bridging structure 172. In one embodiment, the center of curvature of the pair of second vertically straight and laterally concave surface segments facing each other in the second layer structure 272 lies on a vertical line passing through the geometric center of one of the vertically extending perforations 73 in the second layer bridging structure 272. In one embodiment, the center of curvature of the pair of third vertically straight and laterally concave surface segments facing each other in the third layer structure 372 lies on a vertical line passing through the geometric center of one of the vertically extending perforations 73 in the third layer bridging structure 372.

[0107] refer to Figure 18A and Figure 18BAn isotropic etching process can be performed to selectively remove the sacrificial material layer (142, 242, 342) relative to the insulating layer (132, 232, 332), the insulating cap layer (170, 270, 370), the contact-level dielectric layer 80, the bridging structure (372, 272, 172), the lateral fin spacers (144, 244, 344), the memory opening filling structure 58, the support pillar structure 20, and the carrier substrate 9. In an exemplary example, the insulating layer (132, 232, 332) and the lateral fin spacers (144, 244, 344) may comprise silicon oxide, the sacrificial material layer (142, 242, 342) may comprise silicon nitride, and the carrier substrate 9 and the bridging structure (372, 272, 172) may comprise silicon. In this configuration, the isotropic etching process for removing the sacrificial material layers (142, 242, 342) may include a wet etching process using hot phosphoric acid, which is supplied through the lateral isolation cavity 79 to the alternating stacks. Lateral extension cavities (143, 243, 343) may be formed within the volume from which the sacrificial material layers (142, 242, 342) are removed. The lateral extension cavities (143, 243, 343) may include: a first lateral extension cavity 143 formed within the volume from which the first sacrificial material layer 142 is removed; a second lateral extension cavity 243 formed within the volume from which the second sacrificial material layer 242 is removed; and a third lateral extension cavity 343 formed within the volume from which the third sacrificial material layer 342 is removed. Sidewall surface segments of the memory opening filling structure 58 may be physically exposed to the lateral extension cavities (143, 243, 343).

[0108] refer to Figure 19A and Figure 19BAn external barrier dielectric layer (not shown) (such as an alumina layer) may optionally be formed in the lateral extension cavities (143, 243, 343) via a conformal deposition process. At least one conductive material (such as at least one metallic material) may be conformally deposited in the lateral extension cavities (143, 243, 343). This at least one conductive material may include, for example, a combination of a metallic barrier material and a metallic filler material. The metallic barrier material may include, for example, TiN, TaN, WN, MoN, TiC, TaC, WC, or combinations thereof. The metallic filler material may include, for example, Ti, Ta, Mo, Co, Ru, W, Cu, other transition metals, and / or alloys or stacks thereof. Excess portions of the at least one conductive material deposited in the lateral isolation trench 79 or above the contact-level dielectric layer 80 may be removed by performing an etch-back process, which may include isotropic etching and / or anisotropic etching processes. Each remaining portion of a corresponding lateral extension cavity (143, 243, 343) filled with at least one conductive material constitutes a conductive layer (146, 246, 346). The conductive layers (146, 246, 346) comprise a first conductive layer 146 interwoven with a first insulating layer 132, a second conductive layer 246 interwoven with a second insulating layer 232, and a third conductive layer 346 interwoven with a third insulating layer 332. Alternating stacks of the insulating layers (132, 232, 332) and the conductive layers (146, 246, 346) may be formed between each pair of adjacent lateral isolation trenches (172, 272, 372, 79) above the carrier substrate 9. Multiple alternating stacks of insulating layers (132, 232, 332) and conductive layers (146, 246, 346) can be laterally spaced apart from each other by lateral isolation trenches (172, 272, 372, 79). Typically, the conductive layers (146, 246, 346) can be formed in the lateral extension cavities (143, 243, 343) by performing an isotropic conductive material deposition process, which provides reactants to the lateral extension cavities (143, 243, 343) through the lateral isolation cavities 79 and deposits conductive material in the lateral extension cavities (143, 243, 343), and isotropically recessing the deposited conductive material. Lateral fin spacers (144, 244, 344) prevent short circuits between the conductive layers (146, 246, 346) and the semiconductor bridging structures (172, 272, 372).

[0109] refer to Figures 20A to 20EAn insulating material layer may be conformally deposited on the physically exposed surfaces of the lateral isolation cavities 79 and the bridging structures (172, 272, 372). The insulating material layer comprises an insulating material, such as silicon oxide. In one embodiment, the thickness of the insulating material layer may be greater than the radius of each perforation 73 through the bridging structures (172, 272, 372). In one embodiment, the insulating material may have a thickness less than half the minimum spacing of each lateral isolation cavity 79 along the second horizontal direction hd2, and may only partially fill each lateral isolation cavity 79. In another embodiment, the insulating material may have a thickness greater than half the minimum spacing of each lateral isolation cavity 79 along the second horizontal direction hd2, and may completely fill each lateral isolation cavity 79.

[0110] If the insulating material does not completely fill the lateral isolation cavity 79, an optional conductive filler material (such as a metallic filler material) may be deposited in the remaining volume of the lateral isolation cavity 79. Excess portions of the conductive filler material and insulating material layers can be removed from a horizontal plane above the top surface of the contact-level dielectric layer 80 by performing a planarization process, which may employ chemical mechanical polishing or recess etching. Each remaining portion of the insulating material layer filling a portion of a corresponding lateral isolation trench in the lateral isolation trench constitutes an insulating spacer 74. Each remaining portion of the conductive filler material filling a portion of a corresponding lateral isolation trench in the lateral isolation trench constitutes a trench-filling material portion 76. Alternatively, if the insulating material completely fills the lateral isolation cavity 79, the insulating spacer 74 completely fills the lateral isolation cavity 79 and the through-hole 73.

[0111] Typically, the insulating spacer 74 can be formed at least in the peripheral region of the corresponding lateral isolation cavity 79 by performing a conformal deposition process. In one embodiment, an optional trench filling material portion 76 may be formed within the unfilled volume of the lateral isolation cavity 79 containing the insulating spacer 74. In one embodiment, each insulating spacer 74 extends continuously below the bottom surface of a row of first-layer bridging structures 172, below the bottom surface of a row of second-layer bridging structures 272, and below the bottom surface of a row of third-layer bridging structures 372. In one embodiment, the insulating spacer 74 extends continuously into each vertically extending perforation 73 in the row of first-layer bridging structures 172, into each vertically extending perforation in the row of second-layer bridging structures 272, and into each vertically extending perforation in the row of third-layer bridging structures 372.

[0112] Typically, lateral isolation trenches (172, 272, 372, 79) may be provided between each pair of adjacent first alternating stacks (132, 146), between each pair of adjacent second alternating stacks (232, 246), and between each pair of adjacent third alternating stacks (332, 342). Each lateral isolation trench (172, 272, 372, 79) includes a pair of longitudinal sidewalls extending laterally generally along a first horizontal direction hd1. In one embodiment, each longitudinal sidewall of the lateral isolation trench (172, 272, 372, 79) includes a first vertically straight and laterally concave surface section of a first layer structure adjacent to each other at a first vertically extending edge, a second vertically straight and laterally concave surface section of a second layer structure adjacent to each other at a second vertically extending edge, and a third vertically straight and laterally concave surface section of a third layer structure adjacent to each other at a third vertically extending edge.

[0113] Lateral isolation trench filling structures (172, 272, 372, 74, 76) may be located in each lateral isolation trench (172, 272, 372, 79). In one embodiment, the lateral isolation trench filling structures (172, 272, 372, 74, 76) are located within each lateral isolation trench (172, 272, 372, 79). 76) may include: a first bridging structure 172, each of the first bridging structures having at least one vertically extending perforation 73 through a corresponding set therethrough and having a corresponding top surface located within a first horizontal plane including the top surface of the first layer structure (such as a horizontal plane including the top surface of the first insulating cap layer 170); a second bridging structure 272, each of the second bridging structures having at least one vertically extending perforation 73 through a corresponding set therethrough and having a corresponding top surface located within a second horizontal plane including the top surface of the second layer structure (such as a horizontal plane including the top surface of the second insulating cap layer 270); a third bridging structure 372, each of the third bridging structures having at least one vertically extending perforation 73 through a corresponding set therethrough and having a corresponding top surface located within a third horizontal plane including the top surface of the third layer structure (such as a horizontal plane including the top surface of the third insulating cap layer 370); and an insulating spacer 74, the insulating spacer being in the transverse isolation trenches (172, 272, 372, ... 79) extends continuously above the sidewall and fills the perforation 73; and an optional groove filling material portion 76 fills an optional volume laterally defined by the insulating spacer 74.

[0114] In one embodiment, the first bridging structure 172 includes a length-direction sidewall extending laterally along a first horizontal direction hd1 and a width-direction sidewall extending laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1; the second bridging structure 272 includes a length-direction sidewall extending laterally along the first horizontal direction hd1 and a width-direction sidewall extending laterally along the second horizontal direction hd2; and the third bridging structure 372 includes a length-direction sidewall extending laterally along the first horizontal direction hd1 and a width-direction sidewall extending laterally along the second horizontal direction hd2.

[0115] In one embodiment, the insulating spacer 74 contacts each width-direction sidewall of the first layer bridging structure 172 in the transverse isolation trench, contacts each width-direction sidewall of the second layer bridging structure 272 in the transverse isolation trench, and contacts each width-direction sidewall of the third layer bridging structure 372 in the transverse isolation trench.

[0116] In one embodiment, the first layer structure includes a first insulating cap layer 170 covering the pair of first alternating stacks (132, 146) and having a top surface in a first horizontal plane. In one embodiment, the first insulating cap layer 170 has a thickness greater than the sum of the thicknesses of the first insulating layers 132 and the first conductive layers 146. In one embodiment, the second layer structure includes a second insulating cap layer 270 covering the pair of second alternating stacks (232, 246) and having a top surface in a second horizontal plane. In one embodiment, the second insulating cap layer 270 has a thickness greater than the sum of the thicknesses of the second insulating layers 232 and the second conductive layers 246. In one embodiment, the third layer structure includes a third insulating cap layer 370 covering the pair of third alternating stacks (332, 346) and having a top surface in a third horizontal plane. In one embodiment, the third insulating cap layer 370 has a thickness greater than the sum of the thickness of one of the third insulating layers 332 and the thickness of one of the third conductive layers 346.

[0117] exist Figure 20AIn one embodiment shown, the width of the bridging structures (172, 272, 372) along the second horizontal direction hd2 may be greater than the width of the overlying portion of the transverse isolation trench, which is at least partially filled by the insulating spacer 74 (i.e., greater than the overlying portion of the transverse isolation cavity 79). In one embodiment, each top surface of the first-layer bridging structure 172 includes a central portion 172C contacted by the insulating spacer 74 and a pair of peripheral strip portions 172S contacted by a bottom surface segment of the second-layer structure. In one embodiment, each top surface of the second-layer bridging structure 272 includes a central portion contacted by the insulating spacer 74 and a pair of peripheral strip portions contacted by a bottom surface segment of the third-layer structure. In one embodiment, each top surface of the third-layer bridging structure 372 includes a central portion contacted by the insulating spacer 74 and a pair of peripheral strip portions contacted by a bottom surface segment of the contact layer dielectric layer 80.

[0118] In one embodiment, the center of curvature of the facing pair of first vertically straight and laterally concave surface segments of the first layer structure lies on a vertical line passing through the geometric center of one of the vertically extending perforations in the first layer bridging structure 172. In one embodiment, the center of curvature of the facing pair of second vertically straight and laterally concave surface segments of the second layer structure lies on a vertical line passing through the geometric center of one of the vertically extending perforations in the second layer bridging structure 272. In one embodiment, the center of curvature of the facing pair of third vertically straight and laterally concave surface segments of the third layer structure lies on a vertical line passing through the geometric center of one of the vertically extending perforations in the third layer bridging structure 372.

[0119] refer to Figure 21 A via cavity can be formed through the contact layer dielectric layer 80 and through the stepped dielectric material portion (365, 265, 165). A drain contact via cavity can be formed above the drain region 63 of the memory opening-fill structure 58. The layer contact via structure can be formed above the conductive layer (146, 246, 346) underlying the stepped surface.

[0120] At least one conductive material (such as a combination of a conductive barrier material and a conductive filler material) may be deposited in the drain contact via cavity and the layer contact via cavity. Excess of the at least one conductive material can be removed from above a horizontal plane including the top surface of the contact layer dielectric layer 80 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of the at least one conductive material filling the drain contact via cavity constitutes a drain contact via structure 88, which contacts the top surface of the drain region 63. The remaining portion of the at least one conductive material filling the layer contact via cavity constitutes a layer contact via structure 86, which contacts the top surface of the conductive layers (146, 246, 346).

[0121] refer to Figure 22 Additional dielectric material layers and additional metal interconnect structures may be formed over the contact-level dielectric layer 80. The additional dielectric material layer may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structures may include metal via structures, metal line structures, and / or integrated metal line and via structures. The additional dielectric material layer formed over the contact-level dielectric layer 80 is referred to herein as memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as memory-side dielectric material layer 960. Memory-side dielectric material layer 960 includes bit-line level dielectric material layers with embedded bit lines, which are a subset of memory-side metal interconnect structures 980.

[0122] Metal bonding pads (referred to herein as memory-side bonding pads 988) may be formed at the top layer of the memory-side dielectric material layer 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structure 980 and various nodes of the three-dimensional memory array, the nodes comprising alternating stacks of insulating layers (132, 232, 332) and conductive layers (146, 246, 346) and memory opening-filling structures 58. Through the above steps, a memory die 900 is formed.

[0123] In one embodiment, the memory die 900 may include: a three-dimensional memory array comprising alternating stacks of insulating layers (132, 232, 332) and conductive layers (146, 246, 346); a two-dimensional array extending vertically through alternating stacked memory openings 49; a two-dimensional array of memory opening-filling structures 58 located in the two-dimensional array of memory openings 49 and comprising corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; a two-dimensional array of drain contact via structures 88 electrically connected via corresponding drain regions 63 to corresponding vertical semiconductor channels 60; and a two-dimensional array of layer contact via structures 86 electrically connected to corresponding conductive layers (146, 246, 346), a subset of which serves as word lines of the three-dimensional memory array.

[0124] A logic die 700 may be provided. For example, peripheral circuitry 720 may be formed on a logic-side substrate 709, which may be a semiconductor substrate. The peripheral circuitry 720 may be configured to control the operation of a memory array within the memory die 900. A logic-side metal interconnect structure 780 embedded within a logic-side dielectric material layer 760 may be formed over the logic-side substrate 709 (which may include a semiconductor substrate) to form the logic die 700. The logic die 700 also includes logic-side bonding pads 788 embedded within the logic-side dielectric material layer 760.

[0125] A bonded assembly can be formed by bonding logic die 700 to memory die 900. For example, logic die 700 can be attached to memory die 900 by bonding logic-side bonding pads 788 to memory-side bonding pads 988. The bonding between memory die 900 and logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of memory die 900 is bonded to a two-dimensional array of logic die 700), a die-to-die bonding process, or a die-to-die bonding process. Logic-side bonding pads 788 within each logic die 700 can be bonded to memory-side bonding pads 988 within the corresponding memory die 900.

[0126] refer to Figure 23 The carrier substrate 9 can be optionally removed, for example, by grinding, polishing, cleaving, isotropic etching, and / or anisotropic etching. The end portions of the memory film 50 can be selectively removed from each memory aperture-filled structure 58 relative to the vertical semiconductor channel 60, for example, by performing an etching process that selectively etches the material of the memory film 50 relative to the material of the vertical semiconductor channel 60. At least one heavily doped semiconductor layer and / or conductive material layer can be deposited on the physically exposed surface of the vertical semiconductor channel 60 and subsequently patterned to form the source layer 6.

[0127] Figures 24 to 31 This is a vertical cross-sectional view of an alternative configuration of an exemplary structure according to various embodiments of the present disclosure.

[0128] refer to Figure 24 This illustrates a first alternative configuration of the exemplary structure, which can be achieved by omitting the formation of the third-layer bridging structure 372. Figure 23 This is derived from the exemplary structure illustrated.

[0129] refer to Figure 25 This illustrates a second alternative configuration of the exemplary structure, which can be achieved by omitting the formation of the second-layer bridging structure 272. Figure 23 This is derived from the exemplary structure illustrated.

[0130] refer to Figure 26 This illustrates a third alternative configuration of the exemplary structure, which can be achieved by omitting the formation of the first-layer bridging structure 172. Figure 23 This is derived from the exemplary structure illustrated.

[0131] refer to Figure 27 This illustrates a fourth alternative configuration of the exemplary structure, which can be achieved by omitting the formation of the second-layer bridging structure 272 and the third-layer bridging structure 372. Figure 23 This is derived from the exemplary structure illustrated.

[0132] refer to Figure 28 This illustrates a fifth alternative configuration of the exemplary structure, which can be achieved by omitting the formation of the first bridging structure 172 and the second bridging structure 272. Figure 23 This is derived from the exemplary structure illustrated.

[0133] refer to Figure 29 This illustrates a sixth alternative configuration of the exemplary structure, which can be achieved by omitting the formation of the first-layer bridging structure 172 and the third-layer bridging structure 372. Figure 23 This is derived from the exemplary structure illustrated.

[0134] refer to Figure 30 The illustration shows a seventh alternative configuration of the exemplary structure, which can be derived from omitting the formation of the third layer structure. Figure 23 This is derived from the exemplary structure illustrated. In this case, the contact-level dielectric layer 80 can be formed directly on the top surface of the second insulating cap layer 270.

[0135] refer to Figure 31 An eighth alternative configuration of the exemplary structure is illustrated, which can be derived from omitting the formation of the second-layer bridging structure 272. Figure 30The seventh alternative configuration of the exemplary structure illustrated is derived.

[0136] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, the semiconductor structure includes: a first layer structure comprising a first alternating stack (132, 146) of a pair of first insulating layers 132 and first conductive layers 146; a memory opening 49 extending vertically through the first layer structure; a memory opening filling structure 58 located within the memory opening, wherein each memory opening filling structure 58 comprises a vertical semiconductor channel 60 and a memory film 50; a lateral isolation trench (172, 79) located between the pair of first alternating stacks and including a lateral isolation cavity 79 having a pair of longitudinally extending sidewalls extending laterally in a generally horizontal direction, wherein each longitudinally extending sidewall of the lateral isolation cavity comprises a first vertically straight and laterally concave surface segment of the first layer structure adjacent to each other at a first vertically extending edge; and a lateral isolation trench filling structure (172, 74) located within the lateral isolation trench (172, 79). The transverse isolation trench filling structure (172, 74) includes: a first bridging structure 172 comprising a material different from the insulating layer 132, wherein each of the first bridging structures 172 has at least one vertically extending perforation 72 through a corresponding set thereof; and an insulating spacer 74 extending continuously above the sidewall of the transverse isolation cavity 79.

[0137] In one embodiment, the first bridging structure 172 includes a semiconductor material, such as amorphous silicon or polycrystalline silicon.

[0138] In one embodiment, the insulating spacer 74 extends continuously below the bottom surface of the first bridging structure 172 and enters each vertically extending through-hole 73 in the first bridging structure 172. In one embodiment, the first bridging structure 172 includes a length-direction sidewall 172L and a width-direction sidewall 172W, the length-direction sidewall extending laterally in a first horizontal direction hd1 without any laterally concave surface sections, and the width-direction sidewall extending laterally in a second horizontal direction hd2 perpendicular to the first horizontal direction hd1; and an insulating spacer 74 that contacts each width-direction sidewall 172W of the first bridging structure 172.

[0139] In one embodiment, the semiconductor structure further includes a second layer structure that contacts the top surface of the first layer structure in a first horizontal plane and includes a pair of second alternating stacks of a second insulating layer 232 and a second conductive layer 246. A memory opening further extends vertically through the second layer structure; lateral isolation trenches (172, 79) are also located between the pair of second alternating stacks; each longitudinal sidewall of the lateral isolation cavity 79 also includes a second vertically straight and laterally concave surface segment of the second layer structure, the second vertically straight and laterally concave surface segments being adjacent to each other at a second vertically extending edge; and the first layer bridging structure 172 has a corresponding top surface located in the first horizontal plane.

[0140] In one embodiment, each memory opening in the memory opening 49 includes: a first tapered sidewall extending vertically through a first layer structure; a second tapered sidewall extending vertically through a second layer structure; and an annular flat surface located in a first horizontal plane and having an inner periphery adjacent to the bottom periphery of the second tapered sidewall.

[0141] In one embodiment, the lateral isolation trench filling structure (172, 272, 74) further includes a semiconductor second-layer bridging structure 272, each of which has at least one vertically extending through-hole 73 of a respective set therethrough and a respective top surface located in a second horizontal plane including the top surface of the second-layer structure.

[0142] In one embodiment, the semiconductor structure further includes a third layer structure that contacts the top surface of the second layer structure in a second horizontal plane and includes a pair of third alternating stacks (332, 346) of a third insulating layer 332 and a third conductive layer 346, wherein: a memory opening 49 further extends vertically through the third layer structure; and a lateral isolation trench is also located between the pair of third alternating stacks (332, 346). In one embodiment, the lateral isolation trench filling structure (172, 272, 372, 74, 76) further includes: a trench filling material portion 76 that fills a volume laterally defined by an insulating spacer 74; and additional semiconductor bridging structures (such as a third layer bridging structure 372), each of which has at least one vertically extending through-hole of a corresponding set therethrough and a corresponding top surface located in a third horizontal plane including the top surface of the third layer structure.

[0143] In one embodiment, each top surface of the first bridging structure 172 includes a central portion contacted by an insulating spacer 74 and a pair of peripheral strip portions contacted by bottom surface segments of the second layer structure. In one embodiment, the center of curvature of the pair of first vertically straight and laterally concave surface segments of the first layer structure lies on a vertical line passing through the geometric center of one of the vertically extending perforations in the first bridging structure 172.

[0144] Various embodiments of this disclosure provide bridging structures (172, 272, 372) that provide structural support and reduce or prevent tilting and buckling of alternating stacked layers into the transverse isolation cavity 79. The methods for forming the bridging structures are simpler and cheaper than various prior art methods.

[0145] While the foregoing relates to specific preferred embodiments, it should be understood that this disclosure is not limited thereto. Those skilled in the art will envision various modifications that can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” envision that the words “substantially constitute…” or “consist of…” replace all embodiments for which the words “comprising” or “including” are used. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “capable” is used in this disclosure to describe the formation of an element or the execution of a processing step, it is also clearly envisioned that embodiments in which such element or such processing step is not performed are included, provided that the resulting apparatus or device is capable of providing equivalent results. Therefore, whenever omitting such an element or the formation of such a processing step can provide the same or equivalent result, the auxiliary verb "can" applied to the formation of an element or the execution of a processing step should also be interpreted as "can" or "may, or may not," with these equivalent results including slightly superior and slightly inferior results. In cases where embodiments employing specific structures and / or configurations are illustrated in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible for a person skilled in the art. If any publications, patent applications, and / or patents are cited herein, each of such documents is incorporated herein by reference in its entirety.

Claims

1. A semiconductor structure, the semiconductor structure comprising: The first layer structure includes a pair of first alternating stacks of a first insulating layer and a first conductive layer; A memory opening that extends vertically through the first layer structure; A memory aperture filling structure, wherein the memory aperture filling structure is located in the memory aperture, and each memory aperture filling structure in the memory aperture filling structure includes a vertical semiconductor channel and a memory film; A transverse isolation trench located between the pair of first alternating stacks and including a transverse isolation cavity having a pair of longitudinal sidewalls extending transversely generally along a first horizontal direction, wherein each longitudinal sidewall of the transverse isolation cavity includes a first vertically straight and transversely concave surface section of the first layer structure adjacent to each other at a first vertically extending edge. as well as A transverse isolation trench filling structure, wherein the transverse isolation trench filling structure is located in the transverse isolation trench, and wherein the transverse isolation trench filling structure comprises: A first bridging structure comprising a material different from the insulating layer, wherein each of the first bridging structures has a corresponding set of at least one vertically extending perforation passing through it. as well as An insulating spacer that extends continuously above the sidewall of the transverse isolation cavity.

2. The semiconductor structure according to claim 1, wherein the first bridging structure comprises a semiconductor material.

3. The semiconductor structure according to claim 2, wherein the first bridging structure comprises amorphous silicon or polycrystalline silicon.

4. The semiconductor structure of claim 1, wherein the insulating spacer extends continuously below the bottom surface of the first bridging structure and extends into each of the vertically extending through-holes in the first bridging structure.

5. The semiconductor structure according to claim 1, wherein: The first bridging structure includes a sidewall along its length and a sidewall along its width. The sidewall along its length extends horizontally in a straight line along the first horizontal direction, excluding the surface section with the transverse concave surface. The sidewall along its width extends horizontally in a second horizontal direction perpendicular to the first horizontal direction. The insulating spacer contacts each of the width-direction sidewalls of the first bridging structure.

6. The semiconductor structure of claim 1, further comprising a second layer structure, the second layer structure contacting the top surface of the first layer structure in a first horizontal plane and comprising a pair of second alternating stacks of a second insulating layer and a second conductive layer. in: The memory opening extends vertically further through the second layer structure; The lateral isolation trench is also located between the pair of second alternating stacks; Each longitudinal sidewall of the transverse isolation cavity further includes a second vertically straight and laterally concave surface segment of the second layer structure, the second vertically straight and laterally concave surface segments being adjacent to each other at the second vertically extending edge; and The first bridging structure has a corresponding top surface located in the first horizontal plane.

7. The semiconductor structure of claim 6, wherein each memory opening in the memory opening comprises: A first tapered sidewall extends vertically through the first layer of structure; The second tapering sidewall extends vertically through the second layer structure; as well as An annular flat surface, the annular flat surface being located in the first horizontal plane and having an inner periphery adjacent to the bottom periphery of the second tapering sidewall.

8. The semiconductor structure of claim 6, wherein the lateral isolation trench filling structure further comprises a semiconductor second layer bridging structure, each of the semiconductor second layer bridging structures having at least one vertically extending through-hole of a corresponding set therethrough and having a corresponding top surface located in a second horizontal plane including the topmost surface of the second layer structure.

9. The semiconductor structure of claim 6, further comprising a third layer structure, the third layer structure contacting the top surface of the second layer structure in a second horizontal plane and comprising a pair of third alternating stacks of a third insulating layer and a third conductive layer, wherein: The memory opening extends vertically further through the third layer structure; and The lateral isolation trench is also located between the pair of third alternating stacks.

10. The semiconductor structure according to claim 9, wherein the lateral isolation trench filling structure further comprises: The trench filling material portion fills the volume laterally defined by the insulating spacer; as well as Additional semiconductor bridging structures, each having at least one vertically extending through-hole of a corresponding set therethrough and having a corresponding top surface located in a third horizontal plane including the top surface of the third layer structure.

11. The semiconductor structure of claim 6, wherein each top surface of the first bridging structure includes a central portion contacted by the insulating spacer and a pair of peripheral strip portions contacted by a bottom surface segment of the second layer structure.

12. The semiconductor structure of claim 1, wherein the center of curvature of the pair of first vertically straight and laterally concave surface segments facing each other in the first layer structure lies on a vertical line passing through the geometric center of one of the vertically extending through-holes in the first layer bridging structure.

13. A method for forming a semiconductor structure, the method comprising: A first alternating stack of a first insulating layer and a first sacrificial material layer is formed; A first layer of memory opening and a first layer of isolation opening are formed through the first alternating stack; A first sacrificial memory opening filling structure and a first sacrificial isolation opening filling structure are formed in the first layer memory opening and the first layer isolation opening, respectively. A first layer of bridging structure is formed around a subset of the first layer of sacrificial isolation opening-filled structure; A second alternating stack of a second insulating layer and a second sacrificial material layer is formed on top of the first alternating stack; A second layer of memory opening and a second layer of isolation opening are formed through the second alternating stack; Remove the first sacrificial memory opening filling structure, wherein the memory opening is formed within the volume of the first layer memory opening and the volume of the second layer memory opening; A memory opening filling structure is formed in the memory opening, wherein each memory opening filling structure includes a corresponding vertical semiconductor channel and a vertical memory film; Remove the first layer of sacrificial isolation opening filling structure, wherein a layer spacer is formed within the volume of the first layer of isolation opening and the volume of the second layer of isolation opening; as well as The first isotropic etching process is performed to laterally extend the layer spacer opening to form a lateral isolation cavity, wherein the first isotropic etching process selectively and isotropically etches the first alternating stack and the second alternating stack relative to the first layer bridging structure.

14. The method of claim 13, further comprising performing a second isotropic etching process by supplying an isotropic etchant into the lateral isolation cavity, the isotropic etchant selectively etching the materials of the second sacrificial material layer and the first sacrificial material layer relative to the materials of the first insulating layer, the second insulating layer and the first layer bridging structure, to form a lateral extension cavity within the volume of the second sacrificial material layer and the volume of the first sacrificial material layer.

15. The method of claim 14, further comprising forming a conductive layer by: performing an isotropic conductive material deposition process, the isotropic conductive material deposition process providing reactants into the lateral extension cavity through the lateral isolation cavity and depositing conductive material in the lateral extension cavity, and isotropically recessing the deposited conductive material.

16. The method according to claim 15, further comprising: Insulating spacers are formed in the peripheral region of the transverse isolation trench by performing a conformal deposition process; as well as A groove filling material portion is formed within the volume of the transverse isolation cavity that is not filled with the insulating spacer.

17. The method of claim 13, wherein the first bridging structure contacts a cylindrical surface segment of the subset of the first sacrificial isolation opening-filling structure and has a top surface in the same horizontal plane as the top surface of the first sacrificial isolation opening-filling structure.

18. The method of claim 13, wherein the first bridging structure comprises a semiconductor material, the semiconductor material including vertically extending through-holes.

19. The method according to claim 13, further comprising: A second sacrificial memory opening filling structure and a second sacrificial isolation opening filling structure are formed in the second layer memory opening and the second layer isolation opening, respectively. as well as A second bridging structure is formed around a subset of the second sacrificial isolation opening filling structure, wherein the first isotropic etching process is selective for the second bridging structure.

20. The method according to claim 13, further comprising: A third alternating stack of a third insulating layer and a third sacrificial material layer is formed on top of the second alternating stack; A third layer of memory opening and a third layer of isolation opening are formed through the third alternating stack; as well as A third sacrificial memory opening filling structure and a third sacrificial isolation opening filling structure are formed in the third layer memory opening and the third layer isolation opening, respectively.

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