Intelligent cache allocation method and control component

Abstract

The invention provides an intelligent cache allocation method and a control component. The control component comprises a medium interface controller, a cache manager and a storage command processing unit; the medium interface controller obtains the first write command from the storage command processing unit and sends the first storage medium write command to the NVM chip; second data are obtained from the cache indicated by the first write command and output to the NVM chip, and the second data are data to be written into the NVM chip indicated by the first write command; in response to the fact that the second data is completely output to the NVM chip, the medium interface controller requests the cache manager to release the cache indicated by the first write command.

Description

Technical Field

[0001] This application relates to storage technology, and in particular, to a method and control components thereof for accessing a smart delay allocation cache in an NVM chip. Background Technology

[0002] Figure 1 A block diagram of a storage device is shown. Storage device 102 is coupled to a host computer to provide storage capabilities. The host computer and storage device 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase-change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), and XPoint memory are common types of NVM. Data stored in NVM is susceptible to corruption to some extent. To overcome this, error correction codes (ECCs) are typically used to protect the data stored in the NVM when accessing it. Commonly used error correction codes include BCH codes, LDPC codes, and RS codes.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] An NVM chip includes one or more Logic Units (LUNs). An NVM chip package may include one or more dies. Typically, a Logic Unit corresponds to a single die. A Logic Unit may include multiple Planes. Multiple Planes within a Logic Unit can be accessed in parallel, while multiple Logic Units within an NVM chip can execute commands and report status independently of each other. The meanings of target, Logic Unit, and Plane are provided in the "Open NAND Flash Interface Specification (Revision 3.0)," available at http: / / www.micron.com / ~ / media / Documents / Products / Other%20Documents / ONFI3_0Gold.ashx, which is part of the prior art.

[0008] NVM chips typically store and retrieve data in pages, while erasing data in blocks. A block (also called a physical block) contains multiple pages (also called physical pages). Physical pages have a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0009] Figure 2 A detailed block diagram of the control components of the storage device is shown.

[0010] The host accesses the storage device using I / O commands that conform to the storage protocol. The control unit generates one or more storage commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that conform to the NVM chip's interface protocol based on the storage commands. The control unit also tracks the completion of all storage commands generated from a single I / O command and indicates the processing results of the I / O commands to the host.

[0011] See Figure 2 The control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface receives I / O commands from the host and generates storage commands, which are then provided to the storage command processing unit. A storage command may access a storage space of the same size, such as 4KB. The data unit recorded in the NVM chip corresponding to the data accessed by a storage command is called a data frame. A physical page records one or more data frames. For example, if the size of a physical page is 17664 bytes and the size of a data frame is 4KB, then one physical page can store four data frames.

[0012] The storage media management unit (SMMU) maintains a logical address to physical address translation for each storage command. For example, the SMMU includes an FTL table. For a read command, the SMMU outputs the physical address corresponding to the logical address accessed by the storage command; for a write command, the SMMU allocates an available physical address and records the mapping between the accessed logical address and the allocated physical address. The SMMU also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0013] The storage command processing unit, based on the physical address provided by the storage media management unit, operates the media interface controller to issue storage media access commands to the NVM chip. For clarity, the commands sent by the storage command processing unit to the media interface controller are called media interface commands, while the commands sent by the media interface controller to the NVM chip are called storage media access commands. Storage media access commands conform to the NVM chip's interface protocol. Taking read commands as an example, the NVM chip supports various types of read commands based on the size of the data being read, such as read commands to read an entire physical page, read commands to read one, two, or more data frames, read commands to read multiple planes, and read commands to read multiple physical pages of a word line, etc.

[0014] The media interface command corresponds to the storage media access command, so the media interface controller determines the type of the generated storage media access command based on the type of the media interface command.

[0015] Figure 3A A schematic diagram of a storage medium access (read) command according to the ONFI protocol is shown.

[0016] The control unit is coupled to the NVM chip through multiple leads. The signals carried on the leads include DQ signals for transmitting address and data, as well as SR (status) signals. Figure 3A In the middle, the direction to the right is the direction in which time flows. Figure 3A The first row is indicated by a legend for "cycle type," which shows the meaning of the signals transmitted on the DQ signal below it.

[0017] See Figure 3A To send a storage medium access (read) command to the NVM chip, the control unit sequentially sends a "00h" signal (cycle type CMD), "C1", "C2", "R1", "R2" and "R3" signals (cycle type ADDR), and a "30H" signal on the DQ pin. Subsequently, the NVM chip indicates that it is processing the read command via the SR signal. After time tR, the NVM chip completes the read command processing via the SR signal. Next, the NVM chip outputs the data read according to the read command, "D0", "D1", "D2"... (cycle type DOUT), on the DQ pin. The control unit collects this data to obtain the processing result of the read command.

[0018] Figure 3B The waveform of the storage medium access (read) command is shown.

[0019] See also Figure 3ADuring transmissions in the "DOUT" phase of the cycle, the control unit provides multiple "read enable" signals to the NVM chip via leads (e.g., the RE signal according to the ONFI protocol). The NVM chip responds to each read enable signal by outputting one or two bytes of data on the DQ signal. Figure 3B In the example, "Output Data 2" indicates that 1 byte of data is output for each read enable signal, while "Output Data 3" indicates that 2 bytes of data are output for each read enable signal. The ONFI protocol defines various operating modes (SDR, NV-DDR, NV-DDR2, etc.) and the number of bytes output for each read enable signal in each operating mode. In some operating modes defined by the ONFI protocol, the control unit also uses, for example, the CLK signal to replace the read enable signal to instruct the NVM chip to output data. Summary of the Invention

[0020] For storage media access read commands, current mainstream NVM chips require 50µs (microseconds) or even longer to prepare output data. In existing technologies, the media interface controller needs to provide a buffer to receive data output from the NVM chip. However, during the waiting time for the NVM chip to output data, the buffer is not used, resulting in low buffer utilization. To achieve high-speed access, buffers typically sacrifice circuit area, leading to increased integrated circuit chip costs due to low buffer utilization. Alternatively, within a specified cost range, the low buffer capacity may limit chip performance. A similar problem exists for storage media access write commands. Current mainstream NVM chips require approximately 10 milliseconds to complete the process of "programming" data into the NVM chip. After the media interface controller transmits the data to the NVM chip, it still retains the transmitted data in the buffer until the NVM chip indicates successful processing of the storage media access write command after approximately 10 milliseconds. Retaining data in the buffer is to handle situations such as storage media access write command failure. If the storage media access write command fails, a new storage media access write command needs to be issued to the NVM chip, and the buffered data needs to be transmitted to the NVM chip again. During the 10 milliseconds of waiting for the storage medium access write command to complete, the corresponding cache is not effectively utilized.

[0021] To address one or more of the aforementioned technical problems, according to a first aspect of this application, a first read command processing method according to the first aspect of this application is provided, comprising: obtaining a first read command; requesting the allocation of a first cache, the first cache being used to hold first data, the first data being data to be read by the first read command; storing the first data read from the NVM chip according to the first read command in the allocated cache, the allocated cache being the first cache or the capacity of the allocated cache being less than the capacity of the first cache.

[0022] According to the first read command processing method of the first aspect of this application, a second read command processing method according to the first aspect of this application is provided, the method further comprising: in response to obtaining the first read command, issuing a first storage medium read command to the NVM chip; and in response to fully sending the first storage medium read command to the NVM chip, initiating an allocation request for the first cache.

[0023] According to the second read command processing method of the first aspect of this application, a third read command processing method according to the first aspect of this application is provided, wherein the step of initiating an allocation request for the first cache in response to completely sending the first storage medium read command to the NVM chip includes: initiating an allocation request for the first cache after a specified time has elapsed since the first storage medium read command has been completely sent to the NVM chip.

[0024] According to the third read command processing method of the first aspect of this application, a fourth read command processing method according to the first aspect of this application is provided, wherein in response to completely sending a first storage medium read command to the NVM chip, a timer is started, the timer having a specified timing duration; and in response to the timer expiring, an allocation request for the first cache is initiated.

[0025] According to the second read command processing method of the first aspect of this application, a fifth read command processing method according to the first aspect of this application is provided, which initiates an allocation request for the first cache in response to fully sending a first storage medium read command to the NVM chip and in response to the NVM chip being ready to output the first data.

[0026] According to one of the second to fifth read command processing methods of the first aspect of this application, a sixth read command processing method according to the first aspect of this application is provided, wherein sending the first storage medium read command completely to the NVM chip is to send a signal carrying the address and the read command to the NVM chip according to the interface protocol of the NVM chip.

[0027] According to the fifth read command processing method of the first aspect of this application, a seventh read command processing method according to the first aspect of this application is provided, the method further comprising: querying the status of the NVM chip according to the interface protocol of the NVM chip; and determining, based on the status, whether the NVM chip is ready to output the first data.

[0028] According to one of the first to seventh read command processing methods of the first aspect of this application, an eighth read command processing method according to the first aspect of this application is provided, wherein the first data read from the NVM chip according to the first read command is stored in an allocated cache, comprising: obtaining the first data from the NVM chip; and storing the obtained first data in the allocated cache.

[0029] According to the eighth read command processing method of the first aspect of this application, a ninth read command processing method according to the first aspect of this application is provided. If the second cache is allocated in response to the request, a portion of the first data is obtained from the NVM chip and the portion of data is stored in the allocated second cache, the capacity of the second cache is less than the capacity of the first cache, and the size of the portion of data is less than or equal to the capacity of the second cache; a request is made to allocate a third cache; the acquisition of another portion of the first data from the NVM chip is paused, and the other portion of data is not output by the NVM chip.

[0030] According to the ninth read command processing method of the first aspect of this application, a tenth read command processing method according to the first aspect of this application is provided, the method further comprising: in response to obtaining the third cache, resuming the acquisition of the other part of data; and storing the other part of data in the third cache.

[0031] According to the eighth read command processing method of the first aspect of this application, an eleventh read command processing method according to the first aspect of this application is provided, wherein if the second cache is allocated in response to the request and the capacity of the second cache is less than the capacity of the first cache, a third cache is requested to be allocated; and the acquisition of the first data output by the NVM chip is postponed.

[0032] According to the eleventh read command processing method of the first aspect of this application, a twelfth read command processing method according to the first aspect of this application is provided, the method further comprising: in response to obtaining a third cache, initiating the acquisition of the first data; storing the first data in a second cache and a third cache.

[0033] According to the first to twelfth read command processing methods of the first aspect of this application, a thirteenth read command processing method according to the first aspect of this application is provided, in response to the fact that all data in the first data is stored in the allocated cache, returning the first read command processing completion information and the index of the allocated cache.

[0034] According to the thirteenth read command processing method of the first aspect of this application, a fourteenth read command processing method according to the first aspect of this application is provided, the method further comprising: retrieving the first data from the allocated cache; and requesting the release of at least one cache allocated during the process of retrieving the first data.

[0035] According to a second aspect of this application, a first write command processing method according to the second aspect of this application is provided, comprising: obtaining a first write command; obtaining second data from a cache indicated by the first write command and outputting the second data to an NVM chip, wherein the second data is data to be written to the NVM chip as indicated by the first write command; and requesting the release of the cache indicated by the first write command.

[0036] According to the first write command processing method of the second aspect of this application, a second write command processing method according to the second aspect of this application is provided, wherein in response to the second data being completely output to the NVM chip, the second data is written to a memory, which is different from a cache; and in response to the second data being completely written to the memory, a request is made to release the cache indicated by the first write command.

[0037] According to the second write command processing method of the second aspect of this application, a third write command processing method according to the second aspect of this application is provided, the method further comprising: responding to obtaining information from the NVM chip indicating that the processing of a first storage medium write command is complete; deleting second data from the memory.

[0038] According to the first or second write command processing method of the second aspect of this application, a fourth write command processing method according to the second aspect of this application is provided, the method further comprising: responding to an indication from the NVM chip that the processing of the first storage medium write command has failed; requesting the allocation of a fourth cache, the fourth cache being used to hold the second data; retrieving the second data from the memory and writing the second data into the fourth cache; and, in response to the second data being completely written into the fourth cache, issuing a second storage medium write command to the NVM chip to transfer the second data from the fourth cache to the NVM chip.

[0039] According to the fourth write command processing method of the second aspect of this application, a fifth write command processing method according to the second aspect of this application is provided, the method further comprising: requesting the release of the fourth cache in response to obtaining information from the NVM chip indicating that the write command processing of the second storage medium was successful; or, requesting the release of the fourth cache in response to the complete transfer of the second data in the fourth cache to the NVM chip.

[0040] According to a third aspect of this application, a first control component according to the third aspect of this application is provided, including a media interface controller, a cache manager, and a storage command processing unit; wherein, the media interface controller obtains a first read command from the storage command processing unit and sends a first storage media read command to the NVM chip; in response to the first read command, the media interface controller requests the cache manager to allocate a first cache, the first cache being used to hold first data, the first data being the data to be read by the first read command; the media interface controller stores the data read from the NVM chip according to the first read command in the allocated cache.

[0041] According to the first control component of the third aspect of this application, a second control component according to the third aspect of this application is provided, wherein in response to obtaining a first read command, the media interface controller generates and sends a first storage medium read command to the NVM chip; and in response to fully sending the first storage medium read command to the NVM chip, the media interface controller initiates an allocation request for the first cache to the cache manager.

[0042] According to the second control component of the third aspect of this application, a third control component according to the third aspect of this application is provided, wherein after a specified time has elapsed since the first storage medium read command has been fully sent to the NVM chip, the media interface controller initiates an allocation request for the first cache to the cache manager.

[0043] According to the third control component of the third aspect of this application, a fourth control component according to the third aspect of this application is provided, wherein the media interface controller includes a timer; in response to fully sending a first storage medium read command to the NVM chip, the media interface controller starts the timer, the timer having a specified timing duration; in response to the timer expiring, the media interface controller initiates an allocation request for the first cache to the cache manager.

[0044] According to the second control component of the third aspect of this application, a fifth control component according to the third aspect of this application is provided, wherein in response to fully sending a first storage medium read command to the NVM chip, and in response to the NVM chip being ready to output the first data, the media interface controller initiates an allocation request for the first cache to the cache manager.

[0045] According to one of the second to fifth control components of the third aspect of this application, a sixth control component according to the third aspect of this application is provided, wherein sending the first storage medium read command completely to the NVM chip is to send a signal carrying the address and the read command to the NVM chip according to the interface protocol of the NVM chip.

[0046] According to the fifth control component of the third aspect of this application, a seventh control component according to the third aspect of this application is provided, wherein the media interface controller queries the status of the NVM chip according to the interface protocol of the NVM chip; and the media interface controller determines, based on the status, whether the NVM chip is ready to output the first data.

[0047] According to one of the first to seventh control components of the third aspect of this application, an eighth control component according to the third aspect of this application is provided, wherein the media interface controller obtains the first data from the NVM chip; and the media interface controller stores the obtained first data in an allocated cache.

[0048] According to the eighth control component of the third aspect of this application, a ninth control component according to the third aspect of this application is provided. If the cache manager allocates a second cache in response to the request, the media interface controller obtains a portion of the first data and stores the portion of data in the allocated second cache, the capacity of the second cache being less than the capacity of the first cache, and the size of the portion of data being less than or equal to the capacity of the second cache; the media interface controller requests the cache manager to allocate a third cache; the media interface controller suspends obtaining another portion of the first data from the NVM chip, the other portion of data not being output by the NVM chip.

[0049] According to the ninth control component of the third aspect of this application, a tenth control component according to the third aspect of this application is provided, wherein in response to acquiring the third cache, the media interface controller resumes acquiring the other part of the data; the media interface controller stores the other part of the data in the third cache.

[0050] According to the eighth control component of the third aspect of this application, an eleventh control component according to the third aspect of this application is provided, wherein if the cache manager allocates a second cache in response to the request, and the capacity of the second cache is less than the capacity of the first cache, the media interface controller further requests the allocation of a third cache, and the media interface controller postpones the acquisition of the first data output by the NVM chip.

[0051] According to the eleventh control component of the third aspect of this application, a twelfth control component according to the third aspect of this application is provided, wherein in response to acquiring the third cache, the media interface controller initiates the acquisition of the first data; the media interface controller stores the first data in the second cache and the third cache.

[0052] According to one of the first to twelfth control components of the third aspect of this application, a thirteenth control component according to the third aspect of this application is provided, wherein in response to all data in the first data being stored in the allocated cache, the media interface controller returns the first read command processing completion information and the index of the allocated cache to the storage command processing unit.

[0053] According to the thirteenth control component of the third aspect of this application, a fourteenth control component according to the third aspect of this application is provided, wherein the storage command processing unit retrieves the first data from the allocated cache; and the storage command processing unit requests the cache manager to release at least one cache allocated during the process of retrieving the first data.

[0054] According to one of the first to fourteenth control components of the third aspect of this application, a fifteenth control component according to the third aspect of this application is provided, wherein the media interface controller obtains a first write command from the storage command processing unit; the media interface controller obtains second data from the cache indicated by the first write command and outputs the second data to the NVM chip, wherein the second data is the data to be written to the NVM chip indicated by the first write command; and the media interface controller requests the cache manager to release the cache indicated by the first write command.

[0055] According to the fifteenth control component of the third aspect of this application, a sixteenth control component according to the third aspect of this application is provided, wherein in response to the second data being completely output to the NVM chip, the media interface controller writes the second data into the memory; and in response to the second data being completely written into the memory, the media interface controller requests the cache manager to release the cache indicated by the first write command.

[0056] According to the fifteenth or sixteenth control component of the third aspect of this application, a seventeenth control component according to the third aspect of this application is provided, wherein the media interface controller deletes the second data from the memory in response to receiving information from the NVM chip indicating that the processing of the first storage medium write command is complete.

[0057] According to the fifteenth or sixteenth control component of the third aspect of this application, an eighteenth control component according to the third aspect of this application is provided, wherein the media interface controller, in response to receiving feedback from the NVM chip indicating that the processing of the first storage medium write command has failed, requests the cache manager to allocate a fourth cache, the fourth cache being used to hold second data; the media interface controller retrieves the second data from the memory and writes the second data into the fourth cache; in response to the second data being completely written into the fourth cache, the media interface controller issues a second storage medium write command to the NVM chip to transfer the second data from the fourth cache to the NVM chip.

[0058] According to the eighteenth control component of the third aspect of this application, a nineteenth control component according to the third aspect of this application is provided, in response to obtaining information from the NVM chip indicating that the second storage medium write command has been successfully processed, the media interface controller requests the cache manager to release the fourth cache; or, in response to obtaining information from the NVM chip indicating that the second storage medium write command has been successfully processed, the media interface controller requests the cache manager to release the fourth cache.

[0059] According to a fourth aspect of this application, a first information processing apparatus according to the fourth aspect of this application is provided, comprising a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method of any one of the first and / or second aspects described above. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0061] Figure 1 A block diagram of a storage device in the prior art; Figure 2 A block diagram of the control components of a storage device in the prior art; Figure 3A This is a schematic diagram of a storage medium access command according to the ONFI protocol in the prior art; Figure 3B This is a waveform diagram of a storage medium access command according to the ONFI protocol in the prior art; Figure 4A A schematic diagram of a control component provided in an embodiment of this application; Figure 4B A schematic diagram of a media interface controller provided in an embodiment of this application; Figure 5A A flowchart illustrating a read command processing method provided in an embodiment of this application; Figure 5B This is a schematic diagram illustrating a media interface controller processing a read command, as provided in an embodiment of this application. Figure 5C A schematic diagram illustrating the processing of a read command by a media interface controller according to an embodiment of this application; Figure 5D A comparative schematic diagram of the prior art and the read command processing method in this application; Figure 6A A flowchart illustrating a write command processing method provided in an embodiment of this application; Figure 6B This is a schematic diagram illustrating a control component processing a write command, as provided in an embodiment of this application. Detailed Implementation

[0062] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0063] Figure 4A A schematic diagram of a control component according to an embodiment of this application is provided.

[0064] like Figure 4A As shown, the control unit 40 includes a media interface controller 41, a storage command processing unit 42, and a cache manager 43. The cache manager 43 is coupled to the storage command processing unit 42, and the media interface controller 41 is also coupled to the NVM chip 50 and the cache manager 43. The media interface controller 41 is coupled to a memory 60 outside the control unit 40, enabling data transfer between the media interface controller 41 and the memory 60. The cache manager 43 manages cache units 44. Cache units 44 include at least one cache, such as... Figure 4A There are four caches: cache module 1, cache module 2, cache module 3, and cache module 4, each with a length of 4KB (16 bytes). In this embodiment, the number of caches in cache unit 44 can be less than or greater than 4, such as 2, 6, 8, 16, or more. The NVM chip 50 includes multiple LUNs (Logic Unit Numbers). As an example, Figure 4A There are 8 logic units, namely logic unit 0 to logic unit 7.

[0065] The media interface controller 41 obtains read or write commands from the storage command processing unit 42, and sends different storage medium commands to the NVM chip 50 depending on the obtained command. For example, if the media interface controller 41 obtains a read command from the storage command processing unit 42, it sends a storage medium read command to the NVM chip 50. Similarly, if the media interface controller 41 obtains a write command from the storage command processing unit 42, it sends a storage medium write command to the NVM chip 50. In this embodiment, the write command can also be called a programming command, and the storage medium write command can also be called a storage medium programming command.

[0066] The storage command processing unit 42 generates a read command or write command that conforms to the processing rules of the media interface controller 41 based on the received command, or the storage command processing unit 42 directly sends the received command to the media interface controller 41. For example, if the storage command processing unit 42 receives a read command sent by the host, it generates a read command that conforms to the processing rules of the media interface controller 41 and sends it to the media interface controller 41. Alternatively, the control unit 40 may also include a host command processing unit, which is coupled to the storage command processing unit 42. In this case, the host command processing unit receives a write command sent by the host, generates a write command that conforms to the processing rules of the media interface controller 41 based on the write command, and sends the generated write command to the media interface controller 41 via the storage command processing unit 42.

[0067] The cache manager 43 allocates or releases cache according to requests from the storage command processing unit 42 and the media interface controller 41. Both the storage command processing unit 42 and the media interface controller 41 can request the cache manager 43 to allocate or release cache. For example, if the storage command processing unit 42 requests the cache manager 43 to release the first cache, the cache manager 43 will release the first cache, making it available for allocation again. As another example, if the media interface controller 41 requests the cache manager 43 to allocate a 16KB cache, and the cache manager 43 currently has 12KB of remaining allocable cache, the cache manager 43 will first allocate the 12KB cache to the media interface controller 41, and then allocate the remaining 4KB cache to the media interface controller 41 after receiving requests to release more than 4KB of cache. In this embodiment, the cache manager 43 can be the cache manager described in Chinese patent application number 201911346536.8, entitled "Cache Manager and Control Component". Optionally, the cache unit 44 is located outside the control component 40.

[0068] Figure 4B A schematic diagram of the media interface controller 41 is shown.

[0069] See Figure 4B The media interface controller 41 includes a timer unit 411 and a microinstruction execution unit 412. The timer unit 411 includes N timers, where N is a positive integer. The microinstruction execution unit 412 is coupled to each logic unit in the NVM chip 50. The microinstruction execution unit 412 is also coupled to the memory command processing unit 42 and the cache manager 43.

[0070] Figure 5A A flowchart of a read command processing method in this embodiment is provided.

[0071] by Figure 4A Taking the control unit 40 as an example, the control unit 40 can perform... Figure 5A The read command processing method is as follows. Specifically, in step S510, the media interface controller 41 obtains a read command from the storage command processing unit 42. In step S520, in response to the read command, the media interface controller 41 requests the allocation of a first cache from the cache manager 43. At this time, the first cache to be allocated is used to hold the data to be read by the read command.

[0072] Optionally, step S511 is included before performing step S520. In response to the read command, the media interface controller 41 issues a storage media read command to the NVM chip 50. The storage media read command is generated by the media interface controller 41.

[0073] In this embodiment, the media interface controller 41 initiates an allocation request for the first cache to the cache manager 43 after the storage medium read command has been completely sent to the NVM chip 50. Optionally, the media interface controller 41 initiates the allocation request for the first cache to the cache manager 43 after a specified time has elapsed since the storage medium read command was completely sent to the NVM chip 50. In this embodiment, the specified time can be adjusted according to the NVM chip 50. For example, the media interface controller 41 initiates the allocation request for the first cache to the cache manager 43 10µs after receiving the information from the NVM chip 50 indicating that the storage medium read command has been received.

[0074] Optionally, the media interface controller 41 includes a timer 411. In response to fully sending a storage media read command to the NVM chip 50, the media interface controller 41 starts the timer 411, the timer having a specified duration. In response to the timer 411 expiring, the media interface controller 41 initiates an allocation request for the first cache to the cache manager 43.

[0075] In one embodiment, in response to fully sending a storage medium read command to the NVM chip 50 and in response to the NVM chip 50 being ready to output the first data, the media interface controller 41 initiates an allocation request for the first cache to the cache manager 43. In this embodiment, the media interface controller 41 requests the allocation of the first cache from the cache manager 43 only after determining that the NVM chip is ready to output the first data, thereby further reducing the cache occupancy time. Optionally, the media interface controller 41 queries the status of the NVM chip 50 according to the interface protocol of the NVM chip 50. Based on the queried status, the media interface controller 41 determines whether the NVM chip 50 is ready to output the first data. In this embodiment, the interface protocol of the NVM chip 50 is the ONFI (Open NAND Flash Interface) protocol or the Toggle protocol.

[0076] In some embodiments, sending a storage medium read command to the NVM chip 50 involves sending a signal carrying the address and the read command to the NVM chip 50 according to the NVM chip 50's interface protocol. That is, the storage medium read command must conform to the NVM chip 50's interface protocol, and the address carried in the storage medium read command is the physical address in the NVM chip 50.

[0077] Continuing with step S530, the first data read from the NVM chip 50 according to the read command is stored in the allocated cache. The allocated cache is either the first cache or its capacity is less than the first cache's capacity. In this embodiment, although the media interface controller 41 requests the allocation of the first cache from the cache manager 43, the cache managed by the cache manager 43 may have a capacity smaller than the first cache. If the cache is sufficient, the cache manager 43 can directly allocate the first cache to the media interface controller 41. However, if the cache is insufficient, the cache manager 43 will first allocate a portion of the cache to the media interface controller 41. For example, if the media interface controller 41 requests the allocation of a first cache with a length of 16K, but the cache manager 43 only has 8K of unallocated cache, then the cache manager 43 will allocate a second cache with a length of 8K to the media interface controller.

[0078] In some embodiments, after the media interface controller 41 obtains the first data from the NVM chip 50, the media interface controller 41 stores the obtained first data in the allocated cache. Optionally, if the cache manager 43 allocates the first cache to the media interface controller 41, the media interface controller 41 stores all the first data in the first cache.

[0079] In another embodiment, if the cache manager 43 allocates a second cache to the media interface controller 41, the media interface controller 41 only retrieves a portion of the first data and stores this portion in the allocated second cache. The size of this portion is less than or equal to the capacity of the second cache. For example, if the second cache is 4K and the length of the first data is 12K, the media interface controller 41 first retrieves a 4K portion of the first data and stores this 4K data in the second cache. Similarly, if the second cache is 6K and the first data is 8K, the media interface controller 41 first stores a 4K portion of the first data in the second cache. If the second cache is allocated, the media interface controller 41 also requests the cache manager 43 to allocate a third cache. The total capacity of the third cache and the second cache is greater than or equal to the length of the first data. For example, if the first data is 14K and the cache manager 43 allocates cache in 4K increments, then to store 14K of data, the cache manager 43 needs to allocate a total of 16K of cache, including an 8K second cache and an 8K third cache. The media interface controller 41 also pauses the acquisition of another portion of the first data from the NVM chip 50, which is not output by the NVM chip 50. Continuing with the previous example, after the media interface controller 41 acquires 8K of the 14K first data, it stores this 8K data in the second buffer and then pauses the acquisition of the remaining 6K data.

[0080] Furthermore, after acquiring the third buffer, the media interface controller 41 resumes acquiring the other portion of data and stores it in the third buffer. Continuing with the previous example, after acquiring the third buffer, the media interface controller 41 resumes receiving the first data and stores the remaining 6K data in the third buffer.

[0081] In another embodiment, if the cache manager 43 allocates a second cache to the media interface controller 41, the capacity of the second cache is less than the length of the first data. The media interface controller 41 also requests the cache manager 43 to allocate a third cache. In this embodiment, the media interface controller 41 waits to acquire a cache large enough to hold the complete first data before receiving the first data transmitted by the NVM chip 50. Therefore, after acquiring the second cache, the media interface controller 41 postpones acquiring the first data output by the NVM chip 50.

[0082] Furthermore, in response to acquiring the third cache, the media interface controller 41 initiates the acquisition of the first data. The media interface controller 41 stores the first data in the second cache and the third cache.

[0083] Continuing with step S540, in response to the fact that all data in the first data is stored in the allocated cache, the media interface controller 41 returns read command processing completion information and the index of the allocated cache to the storage command processing unit 42.

[0084] In step S550, the storage command processing unit 42 retrieves the first data from the allocated cache. The storage command processing unit 42 also requests the cache manager 43 to release at least one cache allocated during the process of retrieving the first data. For example, upon receiving read command processing completion information and the index of the allocated cache, the storage command processing unit 42 knows that the read command has been processed and can retrieve the first data from the cache. The storage command processing unit 42 locates the allocated cache based on the cache index; the allocated cache may be the first cache, or it may be the second or third cache. After the storage command processing unit 42 completes retrieving the first data, it requests the cache manager 43 to release the cache based on the index of the allocated cache.

[0085] Figure 5B The timing diagram of the media interface controller 41 processing two read commands is given.

[0086] Taking the media interface controller 41 receiving read command 1 and read command 2 successively sent by the storage command processing unit 42 as an example: After receiving read command 1, the microinstruction execution unit 412 learns that the read command is to read 4K of data from logic unit 1 in the NVM chip 50. The microinstruction execution unit 412 generates storage media read command 1, sends storage media read command 1 to the NVM chip 50, and starts timer 1 in the timer unit 411 after storage media read command 1 has been completely sent to the NVM chip 50. After receiving read command 2, the microinstruction execution unit 412 learns that the read command is to read 8K of data from logic unit 2 in the NVM chip 50. The microinstruction execution unit 412 generates storage media read command 2, sends storage media read command 2 to the NVM chip 50, and starts timer 2 in the timer unit 411 after storage media read command 2 has been completely sent to the NVM chip 50.

[0087] After timer 1 expires, the microinstruction execution unit 412 requests the cache manager 43 to allocate a cache with a capacity of 4K. After timer 2 expires, the microinstruction execution unit 412 requests the cache manager 43 to allocate a cache with a capacity of 8K. The cache manager 43 returns the indices of cache module 1, cache module 2, and cache module 3 in sequence according to the order of the requests. Upon receiving the cache indices, the microinstruction execution unit 412 begins receiving data transmitted by the NVM chip 50, first receiving 4K of data from logic unit 1 and storing it in cache module 1, then receiving 8K of data from logic unit 2 and storing it in cache modules 2 and 3.

[0088] Figure 5C Another timing diagram for the media interface controller 41 to process read commands is given.

[0089] Taking the reading command 1 sent by the storage command processing unit 42 to the media interface controller 41 as an example, after the microinstruction execution unit 412 receives the reading command 1, it learns that the reading command is to read 16K of data from logic unit 1 in the NVM chip 50. The microinstruction execution unit 412 generates the storage medium read command 1, sends the storage medium read command 1 to the NVM chip 50, and after the storage medium read command 1 has been completely sent to the NVM chip 50, it starts timer 1 in the timer unit 411. After timer 1 expires, the microinstruction execution unit 412 requests the cache manager 43 to allocate a cache with a capacity of 16K. Among the caches managed by the cache manager 43, only the cache modules 1 and 2, totaling 8K, are available for allocation. The cache manager 43 feeds back the indices of cache modules 1 and 2 to the microinstruction execution unit 412. After receiving the cache index, the microinstruction execution unit 412 finds that cache modules 1 and 2 are insufficient to hold 16K of data. At this point, logic unit 1 is ready to output data, so the microinstruction execution unit 412 receives 8K of data and stores it in cache modules 1 and 2. It then pauses receiving data output from logic unit 1 and waits for the cache manager 43 to provide the remaining 8K of cache indexes. After receiving the indices for cache modules 3 and 4 from the cache manager 43, it resumes receiving data output from logic unit 1 and stores the remaining 8K of data in cache modules 3 and 4.

[0090] Figure 5D A schematic diagram illustrating the execution of a read command using existing technologies and methods described in the embodiments of this application is shown. Figure 5D Reading data from logic unit 0, logic unit 1, and logic unit 2 is done using existing technology, while reading data from logic unit 3 and logic unit 4 is done using the method described in the embodiments of this application. Figure 5DThe diagram shows four cache modules: cache module 1, cache module 2, cache module 3, and cache module 4. In existing technology, during time period T1, when the storage command processing unit issues a read command, cache module 1 and cache module 2 are already allocated; that is, cache module 1 and cache module 2 are occupied or allocated from time period T1 onwards. Time period T2 is when the NVM chip outputs data, which has no impact on the cache state and is therefore not shown in the diagram. During time period T3, the storage command processing unit completes the data reading, the cache usage is finished, and it requests the release of cache module 1 and cache module 2. Therefore, time period T3 can be considered the end of cache module 1 and cache module 2's occupancy, after which cache module 1 and cache module 2 can be re-allocated. When reading data from logic unit 2, the storage command processing unit can only request the allocation of cache module 1 during time period T4, because the storage command processing unit occupies cache module 1 from time period T4 to time period T6. It can be seen that in existing technology, each cache is occupied for three time periods, from T1 to T3.

[0091] In this embodiment, the storage command processing unit does not require an allocated cache when issuing a read command. For example, when reading data from logic unit 3, the storage command processing unit issues a read command during time period T3, requests the allocation of cache module 2 during time period T4, and ends its occupation of cache module 2 during time period T5. Similarly, when reading data from logic unit 4, it begins occupying cache module 2 during time period T6 and ends its occupation of cache module 2 during time period T7. Although this embodiment still requires three time periods from issuing a read command to the cache being fully used, the occupation of each cache is only two time periods, significantly reducing the cache occupation time, thereby improving cache utilization and reducing the required cache capacity. It should be noted that... Figure 5D The time intervals in the diagram are not necessarily of equal length. The proportion of time intervals is for illustrative purposes only and does not represent the actual time proportions. For example, T1 and T2 are not equal.

[0092] Figure 6A This is a flowchart illustrating the write command processing method in an embodiment of this application.

[0093] The following describes the functions that control component 40 can perform. Figure 6A The write command processing method is described using an example. In step S610, the media interface controller 41 obtains a first write command from the storage command processing unit 42. The first write command carries a cache index, which points to a cache containing data to be written to the NVM chip 50. In step S620, the media interface controller 41 obtains second data from the cache indicated by the first write command and outputs the second data to the NVM chip 50. The second data is the data to be written to the NVM chip 50 as indicated by the first write command.

[0094] In step S630, the media interface controller 41 requests the cache manager 43 to release the cache indicated by the first write command. Optionally, in response to the second data being completely output to the NVM chip 50, the media interface controller 41 writes the second data to the memory 60. In response to the second data being completely written to the memory 60, the media interface controller 41 requests the cache manager 43 to release the cache indicated by the first write command.

[0095] Further, if the media interface controller 41 receives information from the NVM chip 50 indicating that the processing of the first storage medium write command is complete, then step S660 is executed, and the media interface controller 41 deletes the second data from the memory 60. If the media interface controller 41 receives information from the NVM chip 50 indicating that the processing of the first storage medium write command has failed, then step S640 is executed. The media interface controller 41 requests the cache manager 43 to allocate a fourth cache, which is used to hold the second data. The media interface controller 41 retrieves the second data from the memory 60 and writes the second data into the fourth cache. In response to the second data being completely written into the fourth cache, the media interface controller 41 issues a second storage medium write command to the NVM chip 50 to transfer the second data from the fourth cache to the NVM chip 50.

[0096] Continuing with step S650, in response to receiving feedback from the NVM chip 50 indicating successful processing of the second storage medium write command, the media interface controller 41 requests the cache manager 43 to release the fourth cache; or, in response to receiving feedback from the NVM chip 50 indicating successful processing of the second storage medium write command, the media interface controller 41 requests the cache manager 43 to release the fourth cache. In this embodiment, the media interface controller 41 can choose to request the release of the fourth cache after the second data has been completely transferred to the NVM chip 50, or, to prevent the write command processing from failing again, wait until receiving the successful write command processing information before requesting the release of the fourth cache. After executing S650, step S660 is executed, and the execution method is as described above, and will not be repeated here.

[0097] Figure 6B A schematic diagram of the control unit 40 processing write commands is provided.

[0098] Taking a command issued by the host to write 4K of data to the NVM chip 50 as an example: After receiving the command from the host, the storage command processing unit 42 requests the allocation of 4K of cache from the cache manager 43. The cache manager 43 confirms that the 4K cache module 1 is allocable and sends the index of cache module 1 back to the storage command processing unit 42. After receiving the cache index, the storage command processing unit 42 sends a first write command to the media interface controller 41. The media interface controller 41 generates a first storage medium write command and sends the first storage medium write command and the data in cache module 1 to the NVM chip 50 in sequence. Then, the media interface controller 41 writes the second data in cache module 1 to the memory 60. After receiving the information that the write data was successfully sent back from the memory 60, the media interface controller 41 requests the cache manager to release cache module 1. Afterwards, the media interface controller 41 receives the information that the first storage write command processing failed from the NVM chip 50, and the media interface controller 41 requests the allocation of 4K of cache from the cache manager 43. The cache manager 43 allocates the currently free cache module 2 to the media interface controller 41 and sends back the index of cache module 2. The media interface controller 41 reads the second data from the memory 60 and stores it in the cache module 2. Subsequently, the media interface controller 41 generates a second storage medium write command and sends the second storage medium write command and the second data in the cache module 2 sequentially to the NVM chip 50. After receiving feedback from the NVM chip 50 indicating that the second storage medium write command has been successfully processed, the media interface controller 41 requests the cache manager 43 to release the cache module 2 and delete the second data from the memory 60. The media interface controller 41 then also sends feedback to the storage command processing unit 42 indicating that the first write command has been processed.

[0099] Although the examples referred to in the present application are described for illustrative purposes only and not for limiting the scope of the application, changes, additions and / or deletions to the implementation may be made without departing from the scope of the application.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A write command processing method, characterized in that, include: In response to obtaining a first write command from the storage command processing unit, a first storage medium write command is generated and sent to the NVM chip; The second data is retrieved from the cache indicated by the first write command and output to the NVM chip. The second data is the data to be written to the NVM chip as indicated by the first write command. In response to the complete output of the second data to the NVM chip, a request is made to release the cache indicated by the first write command.

2. The method as described in claim 1, characterized in that, Also includes: In response to the complete output of the second data to the NVM chip, the second data is written into a memory, which is different from a cache. In response to the complete writing of the second data into the memory, a request is made to release the cache indicated by the first write command.

3. The method as described in claim 2, characterized in that, In response to the information received from the NVM chip indicating that the processing of the first storage medium write command failed, a request is made to allocate a fourth cache, and the second data is read from the memory and stored in the fourth cache; Generate and send a second storage medium write command to the NVM chip, and output the second data to the NVM chip; In response to receiving feedback from the NVM chip indicating that the processing of the write command to the second storage medium is complete, a request is made to release the fourth cache and delete the second data in the memory.

4. A method for processing read commands, characterized in that, include: In response to obtaining a first read command from the storage command processing unit, a first storage medium read command is generated and sent to the NVM chip; After the first storage medium read command is completely sent to the NVM chip, an allocation request is initiated to request the allocation of the first cache. The first cache is used to hold the first data, which is the data to be read by the first read command. The first data read from the NVM chip according to the first storage medium read command is stored in the cache allocated based on the allocation request, wherein the allocated cache is the first cache or the capacity of the allocated cache is less than the capacity of the first cache.

5. The method as described in claim 4, characterized in that, in, After a specified time has elapsed since the first storage medium read command was fully sent to the NVM chip, an allocation request for the first cache is initiated.

6. The method as described in claim 4, characterized in that, In response to sending a first storage medium read command completely to the NVM chip, and in response to the NVM chip being ready to output the first data, an allocation request for the first cache is initiated.

7. The method according to any one of claims 4-6, characterized in that, If the allocation request is in response to the allocation request and the second cache is allocated, a portion of the first data is obtained from the NVM chip and the portion of the data is stored in the allocated second cache. The capacity of the second cache is less than the capacity of the first cache, and the size of the portion of the data is less than or equal to the capacity of the second cache. The acquisition of another portion of the first data from the NVM chip is paused, and the other portion of data is not output by the NVM chip; Request the allocation of a third cache; wherein the total capacity of the third cache and the second cache is greater than or equal to the length of the first data; In response to the allocation of a third cache to obtain another portion of the first data from the NVM chip, the other portion of the data is stored in the third cache.

8. A control component, characterized in that, It includes a media interface controller, a cache manager, and a storage command processing unit; among which, The media interface controller obtains a first write command from the storage command processing unit and sends a first storage medium write command to the NVM chip; and obtains second data from the cache indicated by the first write command and outputs the second data to the NVM chip, wherein the second data is the data to be written to the NVM chip as indicated by the first write command. In response to the complete output of the second data to the NVM chip, the media interface controller requests the cache manager to release the cache indicated by the first write command.

9. The control component as claimed in claim 8, characterized in that, Also includes: The media interface controller obtains the first read command from the storage command processing unit and sends the first storage medium read command to the NVM chip. In response to sending the first storage medium read command completely to the NVM chip, the media interface controller initiates an allocation request to the cache manager to request the allocation of the first cache, which is used to hold the first data, which is the data to be read by the first read command. The media interface controller stores the data read from the NVM chip according to the first storage media read command in the cache allocated based on the allocation request.

10. The control component as claimed in claim 9, characterized in that, The media interface control responds to sending a first storage medium read command completely to the NVM chip by starting a timer with a specified timing duration. When the timer expires, the media interface control sends an allocation request to the cache manager to request the allocation of the first cache. or The media interface control queries the status of the NVM chip according to the NVM chip's interface protocol; In response to determining, based on the state, that the NVM chip is ready to output the first data; The media interface control sends an allocation request to the cache manager to request the allocation of the first cache.

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