System and method for accelerating power supply safety management start-up sequence

Abstract

To help shorten the amount of time before a secure power management integrated circuit (PMIC) releases a processing system from a secure state, the secure PMIC includes first digital circuitry that first configures a voltage threshold comparator and then enables a voltage regulator to power the remainder of the PMIC. Further, while the remainder of the PMIC is powered on, the secure PMIC includes second digital circuitry that is different from the first digital circuitry and performs logic built-in self-test (LBIST) on secure logic circuitry configured to monitor the voltage threshold comparator.

Description

Technical Field

[0001] It involves a power management system. Background Technology

[0002] Some systems (such as those implemented in automobiles) include processors configured to provide various functions, such as navigation, audio, and safety features. To power these processors, such systems include voltage regulators, each supplying a corresponding voltage to one or more corresponding processors. Furthermore, the system implements a power management integrated circuit (PMIC) that monitors the voltage output by the corresponding voltage regulator to help prevent or mitigate overvoltage events caused by the voltage regulator. Additionally, to help ensure proper configuration and operation of the PMIC, it is configured to perform one or more self-tests before the voltage regulator is enabled to supply voltage to the corresponding processor. Only after these self-tests are performed is each PMIC configured to enable its respective voltage regulator to supply voltage to the corresponding processor. Summary of the Invention

[0003] According to a first aspect of this disclosure, an integrated circuit (IC) is provided, the IC comprising: a first digital circuit system configured to: configure a voltage threshold comparator based on configuration data; and, based on the configuration of the voltage threshold comparator, enable a voltage regulator such that the voltage regulator outputs a voltage and at least a portion of the IC begins to power on; and a second digital circuit system, separate from the first digital circuit system, and configured to: perform a Logic Built-in Self-Test (LBIST) on a third digital circuit system configured to monitor the voltage threshold comparator while the at least a portion of the IC is powered on.

[0004] In one or more embodiments, the third digital circuit system is configured to verify configuration data based on one or more data error protection operations after LBIST is completed.

[0005] In one or more embodiments, the first digital circuit system is configured to verify the configuration data based on a data error protection operation different from the one or more data error protection operations before configuring the voltage threshold comparator based on the configuration data.

[0006] In one or more embodiments, the third digital circuit system is configured to perform an analog built-in self-test (ABIST) to determine whether the voltage threshold comparator includes one or more potential faults.

[0007] In one or more embodiments, the third digital circuit system is configured to release at least a portion of the system, including the IC, from a secure state based on the completion of ABIST.

[0008] In one or more embodiments, the IC further includes: a multiplexer configured to: provide the output of a voltage threshold comparator to a voltage regulator based on a first digital circuit system configuration; and provide a safety signal from a third digital circuit system to the voltage regulator based on ABIST.

[0009] In one or more embodiments, the third digital circuit system is configured to disable the voltage regulator via a safety signal in response to a voltage threshold comparator detecting an overvoltage event, so that the voltage regulator does not provide voltage.

[0010] In one or more embodiments, the third digital circuit system is configured to load configuration data from the first digital circuit system based on LBIST.

[0011] According to a second aspect of this disclosure, a method is conceived comprising: configuring a voltage threshold comparator by a first digital circuit system of an integrated circuit (IC) based on configuration data; enabling a voltage regulator based on the configuration of the voltage threshold comparator, such that the voltage regulator outputs a voltage and at least a portion of the IC begins to power on; and performing a logic built-in self-test (LBIST) on a second digital circuit system configured to monitor the voltage threshold comparator while the at least a portion of the IC is powered on.

[0012] In one or more embodiments, the method further includes: after LBIST, a second digital circuit system verifying configuration data based on one or more data error protection operations.

[0013] In one or more embodiments, the method further includes: verifying the configuration data by a first digital circuitry system based on a data error protection operation different from the one or more data error protection operations before configuring the voltage threshold comparator based on the configuration data.

[0014] In one or more embodiments, the method further includes performing an analog built-in self-test (ABIST) by a second digital circuit system to determine whether the voltage threshold comparator includes one or more potential faults.

[0015] In one or more embodiments, the method further includes: based on the completion of ABIST, a second digital circuit system releasing at least a portion of the system including the IC from a secure state.

[0016] In one or more embodiments, the method further includes: providing the output of a voltage threshold comparator to a voltage regulator based on a voltage threshold comparator configured by a first digital circuit system; and providing a safety signal from a second digital circuit system to the voltage regulator based on ABIST.

[0017] In one or more embodiments, the method further includes: in response to a voltage threshold comparator detecting an overvoltage event, disabling a voltage regulator via a safety signal such that the voltage regulator does not provide voltage.

[0018] In one or more embodiments, the method further includes: loading configuration data from a first digital circuit system based on LBIST.

[0019] According to a third aspect of this disclosure, an integrated circuit (IC) is provided, the IC comprising: a voltage threshold comparator configured to monitor a voltage output by a voltage regulator; a first digital circuit system configured to: load configuration data from a memory; and, based on verifying the configuration data, enable the voltage regulator such that the voltage regulator outputs the voltage and the IC begins to power on; and a second digital circuit system, separate from the first digital circuit system and configured to, while the IC is powered on, perform a Logic Built-in Self-Test (LBIST) on a third digital circuit system configured to monitor the voltage threshold comparator.

[0020] In one or more embodiments, the first digital circuit system is configured to configure a voltage threshold comparator based on configuration data before enabling the voltage regulator.

[0021] In one or more embodiments, the third digital circuit system is configured to perform an analog built-in self-test (ABIST) based on LBIST to determine one or more potential faults in the voltage threshold comparator.

[0022] In one or more embodiments, a third digital circuit system is configured to release at least a portion of a system including an IC from a secure state, based on ABIST. Attached Figure Description

[0023] This disclosure will be better understood by referring to the accompanying drawings, which will make its many features and advantages clear to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0024] Figure 1 This is a block diagram of a safety power management integrated circuit (PMIC) configured to provide voltage monitoring functionality according to some embodiments.

[0025] Figure 2 This is a block diagram of a secure PMIC architecture according to some embodiments, the secure PMIC architecture being configured to perform at least a portion of a built-in logic self-test (LBIST) while powering on at least a portion of the secure PMIC.

[0026] Figure 3This is a timing diagram of example secure boot sequences according to some embodiments, each secure boot sequence including LBIST and ABIST.

[0027] Figure 4 This is a flowchart of an example method according to some embodiments, the example method including performing at least a portion of LBIST while powering on at least a portion of a safety PMIC. Detailed Implementation

[0028] The systems and techniques disclosed herein include safe power management integrated circuits (PMICs) configured to test the safety and robustness of power supplies implemented, for example, in automotive systems, electric vehicle systems, aerospace systems, etc. For example, within such systems, a safe PMIC includes one or more voltage regulators configured to provide a predetermined voltage (e.g., a voltage range) to one or more processors based on the power supply. These processors are configured to perform one or more functions of the system, such as infotainment functions (e.g., navigation, calling, music streaming), climate functions (e.g., electric pump, HVAC), vehicle functions (e.g., safety functions, transmission functions, power steering), power functions (e.g., battery management, power inverter), radar systems, vision systems, etc. To help prevent overvoltage events caused by the voltage regulators, the safe PMIC further includes a voltage threshold comparator connected to the voltage regulator, such that the voltage threshold comparator provides an output based on a comparison of the voltage output by the voltage regulator with a voltage threshold (e.g., a reference voltage). As an example, based on the voltage output by the voltage regulator exceeding a voltage threshold (e.g., an overvoltage event), the voltage threshold comparator outputs a signal at a first value, defined by one or more supply voltages indicating that an overvoltage event has occurred. In response to this signal, the safety PMIC then disables the voltage regulator, preventing it from supplying voltage to the processor. To configure the voltage threshold comparator, the PMIC includes or is otherwise connected to memory, such as a non-volatile memory device, storing safety configuration data indicating one or more parameters of the voltage threshold comparator, such as a reference voltage to be supplied, a first supply voltage to be supplied, a second supply voltage to be supplied, an impedance value, or any combination thereof. Based on system power-on, the PMIC configures the voltage threshold comparator based on the safety configuration data stored in memory. For example, the PMIC supplies one or more voltages to the voltage threshold comparator, adjusts one or more impedances of the voltage threshold comparator, or both, as indicated by the safety configuration data.

[0029] Additionally, to help prevent potential faults in the secure PMIC and to help ensure that the secure PMIC is operating reliably, the secure PMIC is configured to perform one or more built-in self-tests before the corresponding voltage regulator is enabled to supply voltage to one or more processors. For example, in response to system power-on, the secure PMIC first places at least a portion of the system (e.g., the processor) into a secure state. Then, the digital circuitry of the secure PMIC performs a Logic Built-in Self-Test (LBIST) to test the secure circuitry (e.g., the secure logic circuitry) of the secure PMIC under certain conditions. That is, the digital circuitry performs LBIST to detect potential faults in the secure circuitry that may occur under certain conditions. For example, during LBIST, the digital circuitry tests whether one or more potential faults exist under certain conditions for one or more operations associated with the secure circuitry (e.g., data error protection operations), components of the secure circuitry (e.g., memory devices, logic gates), or both. After the digital circuit system determines, based on LBIST, that there are no potential faults in the safety circuit system, the safety circuit system loads safety configuration data from memory (e.g., is configured to load configuration data) and performs one or more error correction codes (ECC), cyclic redundancy checks (CRC), or both to determine if the safety configuration data is valid. Based on the validity of the safety configuration data, the safety circuit system begins to signal the voltage threshold comparator based on the verified safety configuration data. Furthermore, based on the validity of the safety configuration data, the safety circuit system enables a voltage regulator to output a voltage that powers on at least a portion of the safety PMIC. For example, the voltage regulator outputs a voltage that powers on one or more microcontrollers, capacitors, memories, or any combination thereof within the safety PMIC.

[0030] After the safety PMIC is powered on, the safety circuitry system tests the robustness of the voltage threshold comparator. For example, the safety circuitry system performs an Analog Built-in Self-Test (ABIST), which includes testing the output of the voltage threshold comparator under certain conditions. That is, the safety circuitry system performs ABIST to detect potential faults in the voltage threshold comparator under certain conditions. For example, during ABIST, the safety circuitry system places the voltage regulator, the voltage threshold comparator, or both under conditions that would trigger certain events (e.g., an overvoltage event) and monitors the output of the voltage threshold comparator to determine if such an event has been detected. After determining that there are no potential faults in the voltage threshold comparator, the safety circuitry system indicates that the voltage regulator is available for normal operation by, for example, generating a signal indicating that the safety state of said part of the system will be released.

[0031] However, waiting for the digital circuitry system to complete the LBIST before powering on the security PMIC and executing ABIST increases the amount of time at least a portion of the system remains in a secure state. In other words, waiting for the digital circuitry system to complete the LBIST before powering on the PMIC and executing ABIST increases the amount of time before said portion of the system can begin normal operation. Thus, the systems and techniques disclosed herein are directed to a security PMIC configured to concurrently execute at least a portion of the LBIST while at least a portion of the security PMIC is powered on. For example, the security PMIC includes a first digital circuitry system (e.g., a security configuration circuitry system) that first verifies security configuration data and a second digital circuitry system (e.g., an LBIST circuitry system) that executes the LBIST separately from the first digital circuitry system. Based on the system power-on, the security PMIC places at least a portion of the system into a secure state. Furthermore, based on the system power-on, the first digital circuitry system retrieves security configuration data from memory and executes one or more CRC, ECC, or both to verify the security configuration data. The first digital circuitry system then signals a voltage threshold comparator based on the verified security configuration data. Additionally, the safety circuitry system activates a voltage regulator to provide voltage, causing at least a portion of the safety PMIC to power on. Simultaneously with the power-on of said portion of the safety PMIC, the second digital circuitry system performs an LBIST to determine whether the safety circuitry system includes one or more potential faults. After the second digital circuitry system determines that the safety circuitry system does not include any potential faults, the safety circuitry system loads safety configuration data from the first digital circuitry system, verifies the safety configuration data, and begins normal operation.

[0032] Furthermore, after the safety PMIC has been powered on and the safety circuitry has begun normal operation (e.g., after the safety circuitry has verified the safety configuration data), the safety circuitry performs an ABIST. Based on the ABIST indicating that the voltage threshold comparator has no potential fault, the safety circuitry releases the portion of the system from the safe state, and that portion of the system begins normal operation. Because the first digital circuitry enables the voltage regulator before the second digital circuitry performs an LBIST, the second digital circuitry is enabled to perform an LBIST simultaneously with the power-on of at least a portion of the safety PMIC. Performing an LBIST in this manner simultaneously with the power-on of at least a portion of the safety PMIC helps to shorten the amount of time before the safety circuitry can release the portion of the system from the safe state, thereby allowing the system to begin normal operation more quickly.

[0033] Now for reference Figure 1According to some embodiments, a safety PMIC 100 configured to provide voltage monitoring functionality is presented. In embodiments, the safety PMIC 100 is implemented within one or more automotive systems, electric vehicle systems, aviation systems, etc., and includes a voltage regulator 102. This voltage regulator 102 includes, for example, an analog voltage regulator configured to provide voltage to at least a portion of the system (e.g., one or more processors) that performs one or more functions of the system, such as infotainment functions (e.g., navigation, calling, music streaming), climate functions (e.g., electric pump, HVAC), vehicle functions (e.g., safety, transmission, power steering), power functions (e.g., battery management, power inverter), radar systems, vision systems, or any combination thereof. To help prevent or mitigate overvoltage events caused by the voltage regulator 102, the safety PMIC 100 includes a voltage threshold comparator 104, which includes, for example, an analog voltage threshold comparator configured to perform range monitoring 122. That is, the voltage threshold comparator 104 is configured to monitor the voltage output by the voltage regulator 102. For example, this range monitoring 122 includes the voltage threshold comparator 104, which compares the voltage output by the voltage regulator 102 with a predetermined threshold voltage to detect one or more overvoltage events. As an example, based on the voltage output by the voltage regulator 102 exceeding a reference voltage supplied to the voltage threshold comparator 104, the voltage threshold comparator 104 is configured to generate an output indicating that an overvoltage event has occurred. In response to the voltage threshold comparator 104 generating an output indicating an overvoltage event, the safety PMIC 100 is configured to disable the voltage regulator 102 so that the voltage regulator 102 no longer supplies voltage, output a signal indicating an overvoltage event for diagnostic purposes, or both.

[0034] To help ensure reliable operation of the voltage threshold comparator 104, the secure PMIC 100 includes a secure logic circuitry system 108 configured to detect one or more potential faults in the configuration or operation of the voltage threshold comparator 104. This secure logic circuitry system 108 includes, for example, a digital circuitry system having one or more microcontrollers, programmable logic devices, storage devices (e.g., programmable read-only memory (PROM), electrically erasable read-only memory (EEPROM), flash memory, solid-state memory), or any combination thereof. In an embodiment, based on power-on of at least a portion of the system (e.g., one or more processors), the secure logic circuitry system 108 is configured to output a secure state control signal 118, which places said portion of the system in a secure state, disabling normal operation of said portion of the system. When said portion of the system is in a secure state, an LBIST circuitry system 124, included with or otherwise connected to the secure logic circuitry system 108, performs an LBIST against the secure logic circuitry system 108. The LBIST circuit system 124 includes, for example, a digital circuit system having one or more microcontrollers, programmable logic devices, storage devices 116 (e.g., PROM, EEPROM, flash memory, solid-state memory), or any combination thereof. During LBIST, the LBIST circuit system 124 is configured to check the security logic circuit system 108 for one or more potential faults. For example, the LBIST circuit system 124 is configured to test the data error protection operation 114, storage devices 116, one or more components of the security logic circuit system 108 (e.g., logic gates, microprocessors), or any combination thereof under one or more conditions to determine whether the security logic circuit system 108 includes one or more potential faults.

[0035] After the LBIST circuitry system 124 determines, based on the LBIST, that the security logic circuitry system 108 does not contain one or more potential faults (e.g., based on LBIST completion), the security logic circuitry system 108 is configured to load security configuration data 112 from memory 106 into storage device 116. Memory 106 includes non-volatile memory, hard disk drives, solid-state drives, flash memory, random access memory, etc., included in or otherwise connected to the security PMIC 100. Security configuration data 112 indicates, for example, one or more parameters of the voltage threshold comparator 104, such as the value of a reference voltage to be supplied to the voltage threshold comparator 104, a first supply voltage to be applied to a first terminal of the voltage threshold comparator 104, a second supply voltage to be applied to a second terminal of the voltage threshold comparator 104, the impedance of the voltage threshold comparator 104, or any combination thereof. After security configuration data 112 is loaded into storage device 116, security logic circuitry system 108 implements one or more data error protection operations 114 (e.g., one or more EEC, CRC, or both) to verify, correct, or both of the security configuration data 112. As an example, security logic circuitry system 108 implements data error protection operation 114, which includes a 16-bit CRC to verify security configuration data 112. Based on data error protection operation 114 determining that security configuration data 112 is invalid, cannot be corrected, or both, security logic circuitry system 108 outputs a signal (not shown for clarity) indicating that security configuration data 112 is invalid for diagnostic purposes. Based on data error protection operation 114 determining that security configuration data 112 is valid, can be corrected, or both, security logic circuitry system 108 is configured to provide a signal to voltage threshold comparator 104 based on the verified security configuration data 112 (e.g., based on configuration data). For example, the security logic circuit system 108 provides a reference voltage to voltage threshold comparator 104, a first supply voltage to voltage threshold comparator 104, a second supply voltage to voltage threshold comparator 104, adjusts one or more impedances of the voltage threshold comparator 104, or any combination thereof, based on values ​​indicated in the verified security configuration data 112.

[0036] After the security logic system 108 provides a signal to the voltage threshold comparator 104 based on verified security configuration data 112, the security logic system 108 is configured to begin powering on at least a portion of the security PMIC 100 (e.g., one or more microcontrollers, storage devices 116, capacitors, etc.). As an example, the security logic system 108 is configured to provide a regulator control signal 120 to the voltage regulator 102, which is configured to enable the voltage regulator 102 to output a voltage (e.g., a non-zero voltage) or disable the voltage regulator 102 to not output a voltage. For example, based on a first value included in the regulator control signal 120, the voltage regulator 102 is configured to be enabled and provide a voltage. Furthermore, based on a second value different from the first value included in the regulator control signal 120, the voltage regulator 102 is configured to be disabled and not provide a voltage. To power up at least a portion of the safety PMIC 100, the safety logic circuitry system 108 is configured to provide a regulator control signal 120 (e.g., a regulator control signal 120 with a first value) to the voltage regulator 102. After at least a portion of the safety PMIC 100 has been powered up, the safety logic circuitry system 108 is configured to perform ABIST 110 to detect one or more potential faults in the voltage threshold comparator 104. The safety logic circuitry system 108 is configured to perform ABIST 110 by placing the voltage regulator 102, the voltage threshold comparator 104, or both under certain conditions to trigger a corresponding event (e.g., an overvoltage event). Based on the range monitoring 122 performed by the voltage threshold comparator 104 during these triggered events, the safety logic circuitry system 108 determines whether the voltage threshold comparator 104 includes one or more potential faults. For example, the safety logic circuitry system 108 determines whether the voltage threshold comparator 104 outputs a signal indicating whether a triggered event has been detected. Based on whether the triggered event is detected, the security logic circuitry system 108 determines whether the voltage threshold comparator 104 includes one or more potential faults. Based on the determination that the voltage threshold comparator 104 does not include any potential faults, the security logic circuitry system 108 updates the security state control signal 118, causing the portion of the system (e.g., the processor) to be released from a secure state and to begin normal operation. For example, the security logic circuitry system 108 updates the security state control signal 118 to include a value that releases the portion of the system from a secure state.

[0037] According to an embodiment, the safety PMIC 100 is configured to help reduce the time required to release said portion of the system from a safe state by performing LBIST simultaneously with powering on at least a portion of the safety PMIC 100. For example, in one embodiment, the safety PMIC 100 includes a safety configuration circuitry separate from and distinct from the LBIST circuitry 124, which loads safety configuration data 112 from memory 106, signals a voltage threshold comparator 104 based on the loaded safety configuration data 112, and enables a voltage regulator 102, causing at least a portion of the safety PMIC 100 to begin powering on. Simultaneously with the power-on of said portion of the safety PMIC 100, the LBIST circuitry 124 is configured to perform LBIST to help ensure that the safety logic circuitry 108 does not contain potential faults, allowing the safety logic circuitry 108 to verify the safety configuration data 112. As an example, simultaneously with the power-on of at least a portion of the safety PMIC 100, the LBIST circuitry 124 performs LBIST to test for the presence of one or more potential faults in the safety logic circuitry 108. Based on the absence of detected potential faults, the safety logic circuitry system 108 then verifies the safety configuration data 112 and executes ABIST 110. Because at least a portion of ABIST is executed simultaneously with powering on the portion of the safety PMIC 100, the amount of time required before executing ABIST 110 can be reduced, which shortens the total time required to release the portion of the system from the safe state. Since the safe state is released earlier, the portion of the system can begin normal operation more quickly (e.g., faster startup), thereby improving the user experience.

[0038] See now Figure 2According to some embodiments, a secure PMIC architecture 200 is presented for performing at least a portion of LBIST while powering on at least a portion of a secure PMIC. In embodiments, the secure PMIC architecture 200 is implemented within a secure PMIC 100. The secure PMIC architecture 200 includes a voltage threshold comparator 104, a secure configuration circuitry system 226, a secure logic circuitry system 108, an LBIST circuitry system 124, and a selector 228. According to embodiments, based on powering on at least a portion of the system (e.g., a system including the secure PMIC 100), the secure configuration circuitry system 226 is configured to load secure configuration data 112 from a memory 106 included in or otherwise connected to the secure PMIC architecture 200. The secure configuration circuitry system 226 includes, for example, one or more microcontrollers, programmable logic devices, storage devices (e.g., PROM, EEPROM, flash memory, solid-state memory), or any combination thereof. As an example, the security configuration circuitry 226 loads security configuration data 112 from memory 106 into a storage device 227 that is similar to or the same as the storage device 116 of the security configuration circuitry 226. After loading the security configuration data 112, the security configuration circuitry 226 then implements one or more data error protection operations 234 to verify the loaded security configuration data 112. These data error protection operations 234 include, for example, one or more ECC, CRC, or both. In some embodiments, the one or more data error protection operations 234 implemented by the security configuration circuitry 226 are different from each of the data error protection operations 114 implemented by the security logic circuitry 108. As an example, according to an embodiment, the data error protection operation 234 includes an 8-bit CRC, and the data error protection operation 114 includes a 16-bit CRC. As another example, the data error protection operation 234 includes one or more ECC, CRC, or both configured to execute faster than the ECC, CRC, or both included in the data error protection operation 114.

[0039] Based on the determination that the loaded security configuration data 112 is valid, the security configuration circuitry 226 configures the voltage threshold comparator 104 by providing a signal to the voltage threshold comparator 104 based on the verified security configuration data 112. For example, the security configuration circuitry 226 provides a reference voltage to the voltage threshold comparator 104, provides a first supply voltage to the voltage threshold comparator 104, provides a second supply voltage to the voltage threshold comparator 104, adjusts one or more impedances of the voltage threshold comparator 104, or any combination thereof, based on the corresponding value indicated in the verified security configuration data 112. Furthermore, after determining that the loaded security configuration data 112 is valid, the security configuration circuitry 226 is configured to begin powering on at least a portion of the security PMIC 100 (e.g., one or more microcontrollers, storage devices, clocks, capacitors) by, for example, enabling the voltage regulator 102 to start outputting a voltage. For example, within the security PMIC architecture 200, selector 228 includes a multiplexer configured to provide either the output of voltage threshold comparator 104 or a security signal 230 from security logic circuitry system 108 as regulator control signal 120 (e.g., a signal to enable or disable voltage regulator 102). Furthermore, selector 228 is configured to output either the output of voltage threshold comparator 104 or the security signal 230 from security logic circuitry system 108 based on a security selection signal 232 provided from security configuration circuitry system 226 (e.g., selecting between the two). As an example, based on a first value for security selection signal 232, selector 228 outputs the output from voltage threshold comparator 104 as regulator control signal 120. Alternatively, based on a second value for security selection signal 232 different from the first value, selector 228 outputs the security signal 230 from security logic circuitry system 108 as regulator control signal 120. According to an embodiment, in order to start powering on the safety PMIC 100, the safety configuration circuit system 226 provides a safety selection signal 232 to the selector 228, the safety selection signal 232 causing the selector 228 (for example, the safety selection signal 232 has a value that causes the selector 228) to output the output of the voltage threshold comparator 104 as the regulator control signal 120.

[0040] In response to receiving the output of voltage threshold comparator 104 as a regulator control signal 120, voltage regulator 102 is configured to begin supplying a voltage to voltage threshold comparator 104, which initiates power-on of at least a portion of safety PMIC 100. Simultaneously with the power-on of said portion of safety PMIC 100, LBIST circuitry 124 performs LBIST to determine whether safety logic circuitry 108 includes one or more potential faults. For example, LBIST circuitry 124 is configured to test data error protection operation 114 under one or more conditions, one or more components of safety logic circuitry 108 (e.g., logic gates, microprocessors), or both, to determine whether safety logic circuitry 108 includes one or more potential faults. Based on the LBIST indication that safety logic circuitry 108 does not include potential faults, safety logic circuitry 108 begins operation and loads safety configuration data 112 from the storage device of safety configuration circuitry 226. Then, the safety logic circuitry system 108 implements one or more data error protection operations 114, including one or more ECC, CRC, or both, different from the data error protection operation 234, to verify the safety configuration data 112, correct errors in the safety configuration data 112, or both. Based on the safety logic circuitry system 108 determining that the safety configuration data 112 is valid, correcting the safety configuration data 112, or both, the safety logic circuitry system 108 performs ABIST 110 to determine whether the voltage threshold comparator 104 includes any potential faults. In this embodiment, because the safety configuration data 112 is configured to perform ABIST simultaneously with the power-on of the safety PMIC 100, the time required to power on said portion of the safety PMIC 100 is reduced, thereby allowing the safety logic circuitry system 108 to perform ABIST 110 earlier. By performing ABIST 110 earlier, the amount of time required before said portion of the system can begin normal operation is reduced.

[0041] After performing ABIST 110 and determining that the voltage threshold comparator 104 does not contain one or more potential faults, the safety logic circuitry system 108 is configured to provide a safety signal 230 to the voltage regulator 102 as a regulator control signal 120. The safety signal 230 is configured, for example, to enable the voltage regulator 102 to output a voltage based on the voltage threshold comparator 104 not detecting an overvoltage event, and to disable the voltage regulator 102 to not output a voltage based on the voltage threshold comparator 104 detecting an overvoltage event. For example, based on the voltage threshold comparator 104 detecting an overvoltage event, the safety logic circuitry system 108 outputs a safety signal 230 with a first value that disables the voltage regulator 102. Furthermore, based on the voltage threshold comparator 104 not detecting an overvoltage event, the safety logic circuitry system 108 outputs a safety signal 230 with a second value different from the first value that enables the voltage regulator 102. To provide a safety signal 230 to the voltage regulator 102 as a regulator control signal 120, a safety configuration circuit system 226 is configured to output a safety selection signal 232, which has a value that causes selector 228 to select the safety signal 230 for output. After providing the safety signal 230 to the voltage regulator 102 as the regulator control signal 120, a safety logic circuit system 108 is configured to release said portion of the system from a safe state by updating a safety state control signal 118. For example, the safety logic circuit system 108 updates the safety state control signal 118 to include a value that causes said portion of the system to begin normal operation.

[0042] See now Figure 3According to some embodiments, a timing diagram 300 is presented, for example, of secure boot sequences 340, 345. Timing diagram 300 includes an axis 350 representing time in microseconds, milliseconds, seconds, etc., and includes a scale representing example times (T1 to T14). In embodiments, secure boot sequences 340, 345 are implemented at least partially by a secure PMIC 100. During the first secure boot sequence 340, at least a portion of the secure PMIC 100 is configured to power on after LBIST completion (e.g., configured to power on based on LBIST completion). For example, between T1 and T3, block 305 of secure boot sequence 340 includes LBIST circuitry 124 performing LBIST to determine whether secure logic circuitry 108 includes one or more potential faults. At T4, LBIST circuitry 124 determines that secure logic circuitry 108 does not include potential faults and begins block 310. Block 310 includes, for example, a security logic circuitry 108 that verifies security configuration data 112 and provides a signal to voltage threshold comparator 104 based on the verified security configuration data 112 (e.g., configuration based on verified security configuration data 112). After configuring the security logic circuitry 108 at T6, at block 315, the security logic circuitry 108 enables voltage regulator 102, causing voltage regulator 102 to begin providing voltage to voltage threshold comparator 104. At T7, at least a portion of the security PMIC 100 begins to power on. Figure 3 This is represented by block 320. At T10, after the PMIC 100 has completed power-on, block 325 includes a safety logic circuitry system 108 performing ABIST 110 to determine whether the voltage threshold comparator 104 contains a potential fault. At T12, after determining that the voltage threshold comparator 104 does not contain one or more potential faults, block 330 includes the safety logic circuitry system 108 providing a safety signal (e.g., safety signal 230) to the voltage regulator 102, which enables the voltage regulator 102 if no overvoltage event is detected and deactivates the voltage regulator 102 if an overvoltage event is detected. After providing the safety signal to the voltage regulator 102, at T13, block 335 includes the safety logic circuitry system 108 releasing at least a portion of the system from a safe state.

[0043] During the second secure boot sequence 345, between T1 and T3, block 310 includes a secure configuration circuitry 226 loading secure configuration data 112 from memory 106 and verifying the secure configuration data 112 (e.g., via data error protection operation 234). Still referring to block 310, after verifying the secure configuration data 112, the secure configuration circuitry 226 configures a voltage threshold comparator 104 based on the verified secure configuration data 112. At T3, block 305 includes an LBIST circuitry 124 performing an LBIST to determine whether the secure logic circuitry 108 includes one or more potential faults. After the LBIST circuitry 124 has determined that the secure logic circuitry 108 does not include one or more potential faults, the secure configuration circuitry 108 verifies the secure configuration data 112 loaded into the secure configuration circuitry 226. For example, the secure configuration circuitry 108 first loads the secure configuration data 112 and implements data error protection operation 114 to verify the secure configuration data 112. Furthermore, at T3, concurrently with block 305, block 315 includes a safety configuration circuitry 226 that enables voltage regulator 102 to output a voltage (e.g., a non-zero predetermined voltage range), and at least a portion of safety PMIC 100 is powered on. For example, safety configuration circuitry 226 provides a safety selection signal 232 that causes selector 228 to provide the output of voltage threshold comparator 104 to voltage regulator 102, thereby enabling voltage regulator 102 to output a voltage that powers at least a portion of safety PMIC 100.

[0044] At T4, simultaneously with at least a portion of block 305, block 320 includes powering on at least a portion of the safety PMIC 100. After the safety PMIC 100 has been powered on, at T7, block 325 includes a safety logic circuitry system 108 performing ABIST 110 to determine whether the voltage threshold comparator 104 contains a potential fault. At T9, after determining that the voltage threshold comparator 104 does not contain one or more potential faults, block 330 includes the safety logic circuitry system 108 providing a safety signal (e.g., safety signal 230) to the voltage regulator 102, which enables the voltage regulator 102 if no overvoltage event is detected and deactivates the voltage regulator 102 if an overvoltage event is detected. After providing the safety signal to the voltage regulator 102, at T10, block 335 includes the safety logic circuitry system 108 releasing at least a portion of the system from a safe state. As shown in timing diagram 300, because the safety logic circuitry system 108 performs LBIST at block 305 simultaneously with at least a portion of the safety PMIC 100 (at block 320) during the safety startup sequence 345, the time required to release said portion of the system from the safe state is earlier (e.g., at T11) compared to the safety startup sequence 340, in which said portion of the safety PMIC 100 is powered on only after the execution of LBIST (e.g., at T14).

[0045] See now Figure 4 According to an embodiment, an example method 400 is presented, which includes performing at least a portion of LBIST while powering on at least a portion of a security PMIC. In the embodiment, example method 400 is performed at least in part by security logic circuitry system 108, security configuration circuitry system 226, or both. Based on system power-on, at block 405, security configuration circuitry system 226 is configured to load security configuration data 112 from memory 106 into the storage device of security configuration circuitry system 226. After loading security configuration data 112, security configuration circuitry system 226 verifies security configuration data 112 by implementing one or more data error protection operations 114. For example, security configuration circuitry system 226 implements one or more ECC, CRC, or both to verify security configuration data 112, correct security configuration data 112, or both. Still referring to block 305, after verifying security configuration data 112, security configuration circuitry system 226 configures voltage threshold comparator 104 based on the verified security configuration data 112. For example, the safety configuration circuit system 226 provides a reference voltage to voltage threshold comparator 104, a first supply voltage to voltage threshold comparator 104, a second supply voltage to voltage threshold comparator 104, adjusts one or more impedances of the voltage threshold comparator 104, or any combination thereof, based on the corresponding value indicated in the verified safety configuration data 112.

[0046] At block 415, after configuring voltage threshold comparator 104, safety configuration circuitry 226 is configured to enable voltage regulator 102, causing voltage regulator 102 to output a non-zero voltage (e.g., a predetermined voltage range). For example, safety configuration circuitry 226 provides a safety selection signal 232 to selector 228, which causes selector 228 to provide the output of voltage threshold comparator 104 to voltage regulator 102. Based on the received output of voltage threshold comparator 104, voltage regulator 102 begins to output a non-zero voltage. After voltage regulator 102 begins to output a non-zero voltage, at block 420, safety PMIC 100 begins to power on. For example, the voltage provided by voltage regulator 102 begins to power on one or more components of safety PMIC 100 (e.g., one or more microcontrollers, storage devices, capacitors, clocks, or any combination thereof). Additionally, concurrently with at least a portion of blocks 415, 420, or both, the LBIST circuitry system 124 is configured to perform an LBIST to determine whether the security logic circuitry system 108 includes one or more potential faults. As an example, during LBIST, the LBIST circuitry system 124 tests one or more conditions of data error protection operation 114, one or more components of the security logic circuitry system 108 (e.g., logic gates, microprocessors), or both, to determine whether the security logic circuitry system 108 includes one or more potential faults. Still referring to block 410, after the LBIST circuitry system 124 determines, based on the LBIST, that the security logic 108 does not include one or more potential faults, the security logic circuitry system 108 loads security configuration data 112 and verifies the security configuration data 112 by implementing one or more data error protection operations 114 (e.g., one or more ECC, CRC, or both). Based on the verified security configuration data 112, the security logic circuitry system 108 then initiates one or more operations (e.g., ABIST 110) based on the verified security configuration data 112.

[0047] For example, now referring to block 425, after the safety logic system 108 has verified that the safety configuration data 112, at least a portion of the safety PMIC 100 has been powered on, or both, the safety logic system 108 performs ABIST 110 to detect one or more potential faults in the voltage threshold comparator 104. As an example, during ABIST 110, the safety logic system 108 places the voltage regulator 102, the voltage threshold comparator 104, or both, under certain conditions to trigger a corresponding event, such as an overvoltage event. Based on the range monitoring 122 performed by the voltage threshold comparator 104 during these triggered events, the safety logic system 108 determines whether the voltage threshold comparator 104 includes one or more potential faults. After completing ABIST 110 (e.g., based on the completion of ABIST 110) and determining that the voltage threshold comparator 104 does not include one or more potential faults, at block 430, the safety logic system 108 is configured to enable overvoltage safety. That is, based on the completion of ABIST 110 and based on the determination that voltage threshold comparator 104 does not contain one or more potential faults, safety logic circuitry system 108 is configured to enable overvoltage protection. For example, safety logic circuitry system 108 is configured to provide a safety signal (e.g., safety signal 230) to voltage regulator 102, which enables voltage regulator 102 when no overvoltage event is detected and deactivates voltage regulator 102 when an overvoltage event is detected. In an embodiment, this safety signal is provided to voltage regulator 102 based on safety selection signal 232 output by safety configuration circuitry system 226. At block 435, after overvoltage protection has been enabled by safety logic circuitry system 108, safety logic circuitry system 108 releases at least a portion of the system from a safe state by, for example, updating safety state control signal 118.

[0048] In some embodiments, certain aspects of the above-described technology may be implemented by executing software through one or more processors of a processing system. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the technology described above. The non-transitory computer-readable storage medium may include, for example, disk or optical disk storage devices, solid-state storage devices (e.g., flash memory), caches, random access memory (RAM), or one or more other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats that can be interpreted or otherwise executed by one or more processors.

[0049] Computer-readable storage media can include any storage medium or combination of storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media can include, but are not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-ray disc), magnetic media (e.g., floppy disk, magnetic tape, or magnetic hard disk), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable storage media can be embedded in a computing system (e.g., system RAM or ROM), permanently attached to a computing system (e.g., magnetic hard disk), removably attached to a computing system (e.g., optical disc or USB-based flash memory), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage device (NAS)).

[0050] It should be noted that not all activities or elements described in the general description above are necessary. A particular activity or part of the apparatus may be unnecessary and may perform one or more additional activities besides those described, or may include one or more additional elements besides those described. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. These concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than restrictive sense, and all such modifications are contemplated to be included within the scope of this disclosure.

[0051] The benefits, other advantages, and solutions to the problem have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to the problem, and any features that may cause any benefit, advantage, or solution to appear or become more apparent should not be construed as essential, necessary, or fundamental features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be apparent to those skilled in the art who benefit from the teachings herein. No limitation is intended beyond the limitations set forth in the appended claims. Therefore, it will be apparent that the specific embodiments disclosed above can be altered or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Thus, the protection sought herein is as set forth in the appended claims.

Claims

1. An integrated circuit (IC), characterized in that, include: The first digital circuit system is configured as follows: Configure the voltage threshold comparator based on the configuration data; as well as Based on the configuration of the voltage threshold comparator, the voltage regulator is enabled, causing the voltage regulator to output a voltage and at least a portion of the IC to begin power-on; and A second digital circuit system, which is separate from the first digital circuit system and configured as follows: While at least a portion of the IC is powered on, a Logic Built-in Self-Test (LBIST) is performed on a third digital circuit system configured to monitor the voltage threshold comparator.

2. The IC according to claim 1, characterized in that, The third digital circuit system is configured to: After the LBIST is completed, the configuration data is verified based on one or more data error protection operations.

3. The IC according to claim 2, characterized in that, The first digital circuit system is configured to: Before configuring the voltage threshold comparator based on the configuration data, the configuration data is verified based on a data error protection operation that is different from the one or more data error protection operations.

4. The IC according to any one of the preceding claims, characterized in that, The third digital circuit system is configured to: Perform a simulated built-in self-test (ABIST) to determine whether the voltage threshold comparator includes one or more potential faults.

5. The IC according to claim 4, characterized in that, The third digital circuit system is configured to: Based on the completion of the ABIST, at least a portion of the system including the IC will be released from a secure state.

6. The IC according to claim 4 or 5, characterized in that, In addition, including: The multiplexer is configured to: Based on the voltage threshold comparator being configured by the first digital circuit system, the output of the voltage threshold comparator is provided to the voltage regulator; and Based on the ABIST, a safety signal is provided from the third digital circuit system to the voltage regulator.

7. The IC according to claim 6, characterized in that, The third digital circuit system is configured to: In response to the voltage threshold comparator detecting an overvoltage event, the voltage regulator is disabled via the safety signal, so that the voltage regulator does not provide the voltage.

8. The IC according to any one of the preceding claims, characterized in that, The third digital circuit system is configured to: Based on the LBIST, the configuration data is loaded from the first digital circuit system.

9. A method, characterized in that, include: The voltage threshold comparator is configured by the first digital circuit system of integrated circuits (ICs) based on configuration data; Based on the configuration of the voltage threshold comparator, the voltage regulator is enabled, causing the voltage regulator to output a voltage and at least a portion of the IC to begin power-on; and While at least a portion of the IC is powered on, a Logic Built-in Self-Test (LBIST) is performed on a second digital circuit system configured to monitor the voltage threshold comparator.

10. The method according to claim 9, characterized in that, In addition, including: Following the LBIST, the second digital circuit system verifies the configuration data based on one or more data error protection operations.

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