Register initialization method and device for chip and chip
By using a programmable flash memory module to store and read the loop structure of the module to configure the address and data, the problem of poor flexibility in hardware circuit initialization is solved, and flexible and reliable register initialization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TSINGTENG MICROSYSTEM CO LTD
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-17
AI Technical Summary
In the existing technology, the register initialization method of the analog IP after the chip is powered on is not flexible enough. The register configuration data and address of the hardware circuit cannot be changed, which makes the initialization process inflexible.
A programmable flash memory module is used to store the cyclic data structure of the module's address and data. Register initialization is achieved by reading and writing this data through the chip, which supports flexible configuration, including modification of address and data.
It improves the flexibility of register initialization configuration, enables flexible modification of chip behavior, and enhances the reliability and flexibility of the initialization process.
Smart Images
Figure CN121879855A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of register configuration technology, such as a register initialization method and apparatus for a chip, and a chip. Background Technology
[0002] Currently, after a chip powers on, it typically requires initialization of analog IPs to bring its clock frequency and voltage to target values. Analog IPs include OSCs (Oscillators) and LDOs (Low Dropout Regulators). This initialization (configuration registers) can be implemented in hardware, such as through an INIT (Initialization) module, or it can be configured by the CPU (Central Processing Unit) in software.
[0003] While the aforementioned hardware circuit method offers advantages in stability and reliability, the register configuration data and addresses cannot be changed. Therefore, the register initialization method of this hardware circuit suffers from a lack of flexibility.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0006] This disclosure provides a register initialization method and apparatus for a chip, as well as a chip, to improve the flexibility of register initialization configuration.
[0007] In some embodiments, the chip includes a programmable flash memory module, and the programmable flash memory module write-to-module data is a circular data structure containing at least a module configuration address and module configuration data; the register initialization method includes: when the chip enters register initialization configuration, reading the module configuration address in the write-to-module data; reading the module configuration data from the write-to-module data based on the module configuration address; and writing the module configuration data into the register to be written.
[0008] In some embodiments, reading module configuration data from the written module data based on the module configuration address includes: reading module configuration data from the written module data in the same circular data structure as the module configuration address.
[0009] In some embodiments, the cyclic data structure further includes a module configuration interval; the register initialization method further includes: after reading the module configuration address in the written module data, reading the module configuration interval from the written module data in the same cyclic data structure as the module configuration address; after waiting for the module configuration interval, reading the module configuration address of the next cyclic data structure in the programmable flash memory module again; reading the module configuration data again, and writing the read module configuration data into the register to be written according to the module configuration address of the next cyclic data structure.
[0010] In some embodiments, the loop data structure further includes a terminator; the register initialization method further includes: after reading the module configuration address in the written module data, reading the loop data structure in the programmable flash memory module again; and if the terminator is read, completing the chip's register initialization operation.
[0011] In some embodiments, the chip further includes an initialization INIT module, the register to be written includes at least one register module; reading the module configuration address in the module data to be written includes: reading the module configuration address in the module data to be written through the INIT module; writing the module configuration data into the register to be written includes: writing the module configuration data into the target register module corresponding to the module configuration address through the INIT module to perform register hardware initialization.
[0012] In some embodiments, the chip further includes a central processing unit (CPU), and the register to be written includes at least one register module; reading the module configuration address in the module data to be written includes: reading the module configuration address in the module data to be written by the CPU; writing the module configuration data into the register to be written includes: writing the module configuration data into the target register module corresponding to the module configuration address by the CPU to perform register software initialization.
[0013] In some embodiments, the method further includes: writing module configuration data into the register to be written, and responding to an initialization configuration adjustment instruction; updating the write-to-module data of the programmable flash memory module based on the initialization configuration adjustment instruction; reading the updated write-to-module data from the programmable flash memory module, and writing the module configuration data of the updated write-to-module data into the register to be written, so as to complete the register initialization configuration adjustment.
[0014] In some embodiments, the register initialization apparatus for a chip includes a processor and a memory storing program instructions, the processor being configured to execute the aforementioned register initialization method for a chip when the program instructions are executed.
[0015] In some embodiments, the chip includes: a chip body; a programmable flash memory module storing write-to-module data, wherein the write-to-module data is a circular data structure containing at least a module configuration address and module configuration data; and a register initialization device for the chip as described above, disposed on the chip body.
[0016] In some embodiments, the chip body includes: an INIT module configured to perform register hardware initialization configuration; or a CPU configured to perform register software initialization configuration.
[0017] The register initialization method, apparatus, and chip for chips provided in this disclosure can achieve the following technical effects: After the chip enters the register initialization configuration, it reads the module configuration address from the written module data, reads the module configuration data from the written module data based on the module configuration address, and then writes the module configuration data into the register to be written. Since the chip obtains the module configuration address and module configuration data from the programmable flash memory module, this application can modify the chip's behavior by writing module data into the programmable flash memory module, thereby realizing the register initialization process. This also improves the flexibility of register initialization configuration while implementing register initialization.
[0018] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description
[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of the hardware structure of the chip provided in the embodiments of this disclosure; Figure 2 This is a schematic diagram of a register initialization method for a chip provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another register initialization method for a chip provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another register initialization method for a chip provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of another register initialization method for a chip provided in an embodiment of this disclosure; Figure 6(a) is a schematic diagram of module data being written into a programmable flash memory module provided in an embodiment of this disclosure; Figure 6(b) is a schematic diagram of module data being written into another programmable flash memory module provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of a register initialization method for a chip in a register initialization configuration scenario provided in this disclosure embodiment; Figure 8 This is a schematic diagram of the register hardware initialization logic used in existing technology; Figure 9 This is a schematic diagram of a register initialization device for a chip provided in an embodiment of this disclosure. Detailed Implementation
[0020] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0021] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0022] Unless otherwise stated, the term "multiple" means two or more.
[0023] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0024] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0025] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0026] Combination Figure 1As shown, this embodiment of the disclosure provides a chip 10, including a programmable flash memory module 101 and a register to be written 104. The module data to be written to the programmable flash memory module 101 is a circular data structure that includes at least a module configuration address and module configuration data. As shown in FIG6(a), the programmable flash memory module 101 is a Flash module, and the module data to be written to the Flash module is a circular data structure that includes at least a module configuration address 1# and a module configuration data 1#, and a module configuration address 2# and a module configuration data 2#.
[0027] Optionally, the module configuration address and / or module configuration data are first written to the programmable flash memory module during chip probing (Chip Probing). After the module configuration address and / or module configuration data are first written, flexible configuration can be performed according to register initialization requirements. Flexible configuration here includes modifying the module configuration address or modifying the module configuration data. Modifying the module configuration address includes, for example, adding / removing a module configuration address.
[0028] Based on the hardware configuration of the aforementioned chip, combined with Figure 2 As shown, this disclosure provides a register initialization method for a chip, including: S01, when the chip enters register initialization configuration, the chip reads the module configuration address from the module data written to the module.
[0029] S02, the chip reads module configuration data from the written module data based on the module configuration address.
[0030] S03, the chip writes the module configuration data into the register to be written.
[0031] The register initialization method for a chip provided in this disclosure involves the chip entering register initialization configuration, reading the module configuration address from the written module data, reading module configuration data from the written module data based on the module configuration address, and then writing the module configuration data into the register to be written. Since the chip obtains the module configuration address and module configuration data from the programmable flash memory module, this application can modify the chip's behavior by writing module data (i.e., the written module data) into the programmable flash memory module, thereby realizing the register initialization process. This also improves the flexibility of register initialization configuration while implementing register initialization.
[0032] Optionally, the chip reads module configuration data from the written module data based on the module configuration address, including: the chip reads module configuration data from the written module data in the same circular data structure as the module configuration address.
[0033] In this way, the module configuration data and module configuration address read by the chip come from the same circular data structure, ensuring the reliability of register initialization configuration.
[0034] Optionally, the cyclic data structure also includes a module configuration interval. The module configuration interval is used to construct the register initialization configuration timing, and is initially written to the programmable flash module by the chip CP. After the module configuration interval is initially written, it can be flexibly configured according to register initialization requirements. Here, flexible configuration includes, but is not limited to, modifying the module configuration interval. In some optional embodiments, referring to Figure 6(b), the programmable flash module 101 is a Flash module, and the module data written to the Flash module is a cyclic data structure that includes at least module configuration address 1# and module configuration data 1#, module configuration interval 1#, and module configuration address 2# and module configuration data 2#, module configuration interval 2#.
[0035] Combination Figure 3 As shown in the embodiments of this disclosure, a register initialization method for a chip is also provided, including: S11, when the chip enters register initialization configuration, the chip reads the module configuration address from the module data written to the module.
[0036] S12, the chip reads module configuration data from the written module data in the same circular data structure as the module configuration address, based on the module configuration address.
[0037] S13, the chip writes the module configuration data to the register to be written.
[0038] S14, after the chip reads the module configuration address from the written module data, it reads the module configuration interval from the written module data which is in the same circular data structure as the module configuration address.
[0039] S15, after the chip waits for the module configuration interval, it reads the module configuration address of the next cycle data structure in the programmable flash memory module again.
[0040] S16, the chip reads the module configuration data again and writes the read module configuration data into the register to be written according to the module configuration address of the next cycle data structure.
[0041] Using the register initialization method for a chip provided in this disclosure, after the chip enters the register initialization configuration, it reads the module configuration address from the write-to-module data, and reads module configuration data from the write-to-module data in the same cyclic data structure as the module configuration address, and then writes the module configuration data into the register to be written. After reading the module configuration address from the write-to-module data, the chip also reads the module configuration interval from the write-to-module data in the same cyclic data structure as the module configuration address, waits for the module configuration interval, reads the module configuration address of the next cyclic data structure in the programmable flash memory module again, and reads the module configuration data again, and writes the read module configuration data into the register to be written according to the module configuration address of the next cyclic data structure.
[0042] Since the chip obtains the module configuration address, module configuration data, and module configuration interval from the programmable flash memory module, the behavior of the chip can be modified by writing the module data (module configuration address and / or module configuration data and / or module configuration interval) into the programmable flash memory module, thereby realizing the initialization configuration of multiple registers and improving the flexibility and reliability of register initialization configuration.
[0043] Optionally, the circular data structure also includes a terminator. The terminator indicates that the written module data is the last data, and the terminator is data in a custom format. The custom format can be flexibly set according to register initialization requirements. As an example, the terminator is 0x5a5a5a5a. Furthermore, the terminator is first written to the programmable flash module by the chip CP. After the terminator is first written, it can be flexibly configured according to register initialization requirements. Here, flexible configuration includes, but is not limited to, modifying the terminator format, or deleting the terminator. In some optional embodiments, referring to Figure 6(b), the programmable flash module 101 is a Flash module, and the module data written to the Flash module is a circular data structure that includes at least module configuration address 1# and module configuration data 1#, module configuration interval 1#, module configuration address 2# and module configuration data 2#, module configuration interval 2#, module configuration address 3# and module configuration data 3#, and a terminator.
[0044] Combination Figure 4 As shown in the embodiments of this disclosure, a register initialization method for a chip is also provided, including: S21, when the chip enters register initialization configuration, the chip reads the module configuration address from the module data written to the module.
[0045] S22, the chip reads module configuration data from the written module data in the same circular data structure as the module configuration address, based on the module configuration address.
[0046] S23, the chip writes the module configuration data into the register to be written.
[0047] S24, after the chip reads the module configuration address from the data written to the module, it reads the loop data structure in the programmable flash memory module again.
[0048] S25, upon reading the end-of-line character, the chip completes the register initialization operation.
[0049] Using the register initialization method for a chip provided in this disclosure, after the chip enters register initialization configuration, it reads the module configuration address from the module data to be written, and reads module configuration data from the module data to be written based on the module configuration address, and then writes the module configuration data into the register to be written. After reading the module configuration address from the module data to be written, the chip reads the circular data structure in the programmable flash memory module again. If the end-of-line character is read, it indicates that the last data has been read, and the register initialization ends. Since the chip obtains the module configuration address, module configuration data, and end-of-line character from the programmable flash memory module, this application can modify the chip's behavior by writing module data (module configuration address and / or module configuration data and / or end-of-line character) into the programmable flash memory module, thereby realizing the initialization configuration of multiple registers and improving the flexibility and reliability of register initialization configuration.
[0050] In the disclosed embodiments, the chip can implement register initialization configuration through hardware.
[0051] In some alternative embodiments, combined with Figure 1 As shown, chip 10 also includes an INIT module 102, and the register to be written 104 includes at least one register module. The INIT module 102 is a hardware circuit used to implement full chip initialization.
[0052] The chip reads the module configuration address from the data written to the module, including: the chip reads the module configuration address from the data written to the module through the INIT module.
[0053] The chip writes module configuration data to the register to be written, including: the chip writes the module configuration data to the target register module corresponding to the module configuration address through the INIT module to perform register hardware initialization.
[0054] In this way, after the chip enters the register initialization configuration, it first reads the module configuration address from the written module data through the INIT module, then reads the module configuration data from the written module data through the INIT module, and finally writes the module configuration data into the target register module corresponding to the module configuration address through the INIT module. Since the chip obtains the module configuration address and module configuration data from the programmable flash memory module, the hardware behavior of the INIT module can be modified by writing the module data (module configuration address and / or module configuration data) into the programmable flash memory module, thereby realizing the hardware initialization process of the register and improving the flexibility of the register hardware initialization configuration.
[0055] In the disclosed embodiments, the chip can be configured to initialize registers via software.
[0056] In some alternative embodiments, combined with Figure 1 As shown, chip 10 also includes CPU 103, and register 104 to be written includes at least one register module. The logic executed by CPU 103 is stored in ROM (Read-Only Memory) through program code.
[0057] The chip reads the module configuration address from the data written to the module, including: the chip reads the module configuration address from the data written to the module via the CPU.
[0058] The chip writes module configuration data to the register to be written, including: the chip writes the module configuration data to the target register module corresponding to the module configuration address through the CPU.
[0059] In this way, after the chip enters the register initialization configuration, it first reads the module configuration address from the written module data through the CPU, then reads the module configuration data from the written module data through the CPU, and finally writes the module configuration data into the target register module corresponding to the module configuration address through the CPU. Since the chip obtains the module configuration address and module configuration data from the programmable flash memory module, the embodiments of this disclosure can modify the CPU's software behavior by writing the module data (module configuration address and / or module configuration data) into the programmable flash memory module, thereby realizing the software initialization process of the register and improving the flexibility of the register software initialization configuration.
[0060] It should be noted that the chip can perform register hardware initialization configuration through the INIT module, or it can perform register software initialization configuration through the CPU. The chip's use of the INIT module's hardware behavior for register hardware initialization configuration offers better stability and reliability.
[0061] Combination Figure 5As shown in the embodiments of this disclosure, a register initialization method for a chip is also provided, including: S31, when the chip enters register initialization configuration, the chip reads the module configuration address from the module data written to the module.
[0062] S32, the chip reads module configuration data from the written module data based on the module configuration address.
[0063] S33, the chip writes the module configuration data into the register to be written.
[0064] S34: After the chip writes the module configuration data to the register to be written, it responds to the initialization configuration adjustment instruction.
[0065] S35, the chip updates the written module data of the programmable flash memory module based on the initialization configuration adjustment instruction.
[0066] S36, the chip reads the updated write module data from the programmable flash memory module and writes the updated write module configuration data into the register to be written, so as to complete the register initialization configuration adjustment.
[0067] The register initialization method for a chip provided in this disclosure involves the chip entering register initialization configuration, reading the module configuration address from the written module data, reading module configuration data from the written module data based on the module configuration address, and then writing the module configuration data into the register to be written. After writing the module configuration data into the register to be written, the chip also responds to an initialization configuration adjustment instruction and updates the written module data of the programmable flash memory module based on the initialization configuration adjustment instruction. The chip then reads the updated written module data of the programmable flash memory module and writes the updated module configuration data into the register to be written, thereby completing the register initialization configuration adjustment. This disclosure modifies the chip's behavior by updating the written module data in the programmable flash memory module, thereby achieving register initialization configuration adjustment and enabling flexible adjustment of the register initialization configuration.
[0068] In a practical application, the following process is executed after the chip is powered on: the chip powers on; the chip waits for the power supply to be established; after the power supply is established, the POR (Power-On Reset) reset is released; the OSC clock is established and after the OSC clock is established, the register initialization configuration is started.
[0069] Figure 8 This is a schematic diagram of the register hardware initialization logic used in existing technology. For example... Figure 8 As shown, the programmable flash memory module is a Flash module, and the registers to be written include register module A, register module B and register module C.
[0070] The existing register hardware initialization configuration process is as follows: In step S001, the INIT module occupies the bus, and the chip reads the address 0x14000000 from the Flash module through the INIT module. This address is set by the INIT module and cannot be changed.
[0071] In step S002, the chip reads data 0xA from address 0x14000000 via the INIT module. Data 0xA is written to the Flash module during chip CP.
[0072] Step S003: The chip writes data 0xA to register module A corresponding to address 0x40001000. Address 0x40001000 is set by the INIT module and cannot be changed.
[0073] The chip completes the initialization configuration of all register modules according to the above logic, and releases the bus through the INIT module after the initialization configuration is completed.
[0074] In another practical application, Figure 7 This is a schematic diagram of a register initialization method for a chip in a register initialization configuration scenario provided by an embodiment of this disclosure. For example... Figure 7 As shown, the programmable flash memory module is a Flash module that stores the data to be written to the module. The registers to be written include register module A, register module B, and register module C. The module configuration addresses, module configuration data, and module configuration intervals of each loop data structure in the data to be written to the module are all written to the Flash module during chip CP.
[0075] The register initialization method for the chip specifically performs the following steps: In step S101, the chip reads the module configuration address 0x40001000 of the module data being written through the INIT module.
[0076] In step S102, the chip reads the module configuration data 0xA from the written module data in the same circular data structure as the module configuration address 0x40001000 through the INIT module.
[0077] In step S103, the chip reads the written module data reading module configuration interval through the INIT module, which is in the same circular data structure as the module configuration address 0x40001000.
[0078] In step S104, the chip writes the module configuration data 0xA to the register module A corresponding to the module configuration address 0x40001000 through the INIT module.
[0079] In step S105, after the chip waits for the module configuration interval, it reads the module configuration address 0x40002000 of the next cycle data structure written to the module data again through the INIT module.
[0080] In step S106, the chip reads module configuration data 0xB from the written module data in the same loop data structure as module configuration address 0x40002000 through the INIT module, and writes module configuration data 0xB into register module B corresponding to module configuration address 0x40002000 in the next loop data structure.
[0081] In step S107, the chip continues to read the module configuration address and module configuration data of the next loop data structure according to the above logic, and completes the register initialization hardware configuration of all registers to be written when the INIT module reads the end symbol.
[0082] Combination Figure 9 As shown, this disclosure provides a register initialization device 70 for a chip, including a processor 700 and a memory 701. Optionally, the device 70 may further include a communication interface 702 and a bus 703. The processor 700, communication interface 702, and memory 701 can communicate with each other via the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call logical instructions in the memory 701 to execute the register initialization method for the chip described in the above embodiment.
[0083] Furthermore, the logic instructions in the aforementioned memory 701 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.
[0084] The memory 701, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 700 executes functional applications and data processing by running the program instructions / modules stored in the memory 701, that is, it implements the register initialization method for the chip in the above embodiments.
[0085] The memory 701 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 701 may include high-speed random access memory and may also include non-volatile memory.
[0086] This disclosure provides a chip, including: a chip body, a programmable flash memory module, and the aforementioned register initialization device 70 for the chip. The programmable flash memory module stores write-in module data, which is a circular data structure containing at least a module configuration address and module configuration data. The register initialization device 70 for the chip is mounted on the chip body. The mounting relationship described herein is not limited to placement within the chip body, but also includes mounting connections with other components of the chip, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the register initialization device 70 for the chip can be adapted to any feasible chip body to implement other feasible embodiments.
[0087] Optionally, the chip also includes an INIT module and a CPU. The INIT module is configured to perform register hardware initialization configuration. Alternatively, the CPU is configured to perform register software initialization configuration.
[0088] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the above-described register initialization method for a chip.
[0089] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.
[0090] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.
[0091] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0092] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0093] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
Claims
1. A register initialization method for a chip, characterized in that, The chip includes a programmable flash memory module. The data written to the programmable flash memory module is a circular data structure containing at least the module configuration address and module configuration data. The register initialization method includes: When the chip enters register initialization configuration, read the module configuration address from the data written to the module. Based on the module configuration address, read the module configuration data from the data written to the module. Write the module configuration data to the register to be written.
2. The register initialization method according to claim 1, characterized in that, Based on the module configuration address, read module configuration data from the data written to the module, including: Read module configuration data from the written module data in the same circular data structure as the module configuration address.
3. The register initialization method according to claim 2, characterized in that, The circular data structure also includes module configuration intervals; the register initialization method also includes: After reading the module configuration address from the written module data, read the module configuration interval from the written module data that is in the same circular data structure as the module configuration address. After waiting for the module configuration interval, read the module configuration address of the next loop data structure in the programmable flash memory module again; Read the module configuration data again, and write the read module configuration data into the register to be written according to the module configuration address of the next loop data structure.
4. The register initialization method according to claim 2, characterized in that, Loop data structures also include a terminator; register initialization methods also include: After reading the module configuration address from the data written to the module, the circular data structure in the programmable flash memory module is read again. If the end-of-line character is read, complete the chip's register initialization operation.
5. The register initialization method according to any one of claims 1 to 4, characterized in that, The chip also includes an initialization INIT module, and the registers to be written include at least one register module; Reading the module configuration address from the written module data includes: reading the module configuration address from the written module data through the INIT module; Writing module configuration data to the register to be written includes: writing the module configuration data to the target register module corresponding to the module configuration address through the INIT module to perform register hardware initialization.
6. The register initialization method according to any one of claims 1 to 4, characterized in that, The chip also includes a central processing unit (CPU), and the registers to be written include at least one register module; Reading the module configuration address from the data written to the module includes: reading the module configuration address from the data written to the module via the CPU; Writing module configuration data to the register to be written includes: writing the module configuration data to the target register module corresponding to the module configuration address through the CPU to perform register software initialization.
7. The register initialization method according to any one of claims 1 to 4, characterized in that, Also includes: After writing the module configuration data to the register to be written, respond to the initialization configuration adjustment command; Based on the initialization configuration adjustment command, update the written module data of the programmable flash memory module; Read the updated write-to-module data from the programmable flash memory module, and write the updated write-to-module configuration data into the register to be written, thereby completing the register initialization configuration adjustment.
8. A register initialization device for a chip, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute, when running the program instructions, the register initialization method for the chip as described in any one of claims 1 to 7.
9. A chip, characterized in that, include: Chip body; A programmable flash memory module stores data to be written to the module, wherein the data to be written to the module is a circular data structure containing at least the module configuration address and the module configuration data. The register initialization device for a chip as described in claim 8 is disposed on the chip body.
10. The chip according to claim 9, characterized in that, The chip itself includes: The INIT module is configured to perform register hardware initialization configuration; or, The CPU is configured to perform register software initialization configuration.