Resource memory access device and method, chip and computer equipment

Abstract

The invention discloses a resource access device and method, a chip and computer equipment, and belongs to the technical field of resource management. The device comprises a shader core, an address generation unit and a memory management unit, the shader core is used for sending a resource access request to the address generation unit, and the resource access request comprises resource address information corresponding to a to-be-accessed resource; the address generation unit is used for determining a block mapping table address and an in-block offset corresponding to the to-be-accessed resource based on the resource address information under the condition that the to-be-accessed resource is a sparse resource, and determining a virtual address corresponding to the to-be-accessed resource based on the block mapping table address and the in-block offset, transmitting the virtual address to the memory management unit; and the memory management unit is used for converting the received virtual address into a physical address and executing a resource access operation based on the physical address. According to the scheme provided by the invention, the resource access process can be optimized, and the flexibility of block mapping management of sparse resources is improved.

Description

Technical Field

[0001] This application relates to the field of resource management technology, and in particular to a resource memory access device, method, chip, and computer equipment. Background Technology

[0002] Sparse resource is a technique that supports a resource whose storage space requirements exceed the actual storage space occupied. By dividing the resource into small regions (tiles) and mapping them to storage space one by one, the resource, texture coordinates and their virtual addresses are decoupled from the physical memory space.

[0003] In related technologies, for sparse resources, resource blocks are directly mapped and baked into the system GPU (Graphics Processing Unit) page table through virtual memory mapping that relies on the operating system. Its updates depend on the virtual memory management DDI (Device Driver Interface) of the relevant operating system GPU.

[0004] Since the current hardware implementation of block mapping is based on the virtual memory mapping of the system GPU, its updates also require updating the system GPU page table. However, the block size is limited by the system page size, which will cause small, difficult-to-batch CPU (Central Processing Unit) and GPU loads when performing updates. Summary of the Invention

[0005] This application provides a resource memory access device, method, chip, and computer equipment, the technical solution of which includes the following aspects.

[0006] On the one hand, embodiments of this application provide a resource memory access device, the device including a shader core, an address generation unit, and a memory management unit; The shader core is used to send a resource memory access request to the address generation unit, and the resource memory access request includes the resource address information corresponding to the resource to be accessed. The address generation unit is configured to, when the memory resource to be accessed is a sparse resource, determine the block mapping table address and the offset within the block corresponding to the memory resource to be accessed based on the resource address information, and determine the virtual address corresponding to the memory resource to be accessed based on the block mapping table address and the offset within the block, and transmit the virtual address to the memory management unit. The memory management unit is used to convert the received virtual address into a physical address and perform resource memory access operations based on the physical address; Wherein, the block mapping table corresponding to the block mapping table address is a data structure used to manage the virtual storage space where the sparse resource is located, and the offset within the block is used to indicate the offset of the virtual address of the memory resource to be accessed in the virtual storage space relative to the block virtual address of the block to which the memory resource to be accessed belongs.

[0007] On the other hand, embodiments of this application provide a resource memory access method, the method being used in a resource memory access device, the device including a shader core, an address generation unit, and a memory management unit; The method includes: The shader core sends a resource memory access request to the address generation unit, and the resource memory access request includes the resource address information corresponding to the resource to be accessed. When the memory resource to be accessed is a sparse resource, the address generation unit determines the block mapping table address and the offset within the block corresponding to the memory resource to be accessed based on the resource address information, and determines the virtual address corresponding to the memory resource to be accessed based on the block mapping table address and the offset within the block, and transmits the virtual address to the memory management unit. The memory management unit converts the received virtual address into a physical address and performs resource memory access operations based on the physical address; Wherein, the block mapping table corresponding to the block mapping table address is a data structure used to manage the virtual storage space where the sparse resource is located, and the offset within the block is used to indicate the offset of the virtual address of the memory resource to be accessed in the virtual storage space relative to the block virtual address of the block to which the memory resource to be accessed belongs.

[0008] On the other hand, this application provides a chip that integrates any of the resource access devices described in the above embodiments.

[0009] This application provides a computer device, which includes any of the resource access devices or chips described in the above embodiments.

[0010] On the other hand, embodiments of this application provide a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the above-described resource access method.

[0011] On the other hand, embodiments of this application provide a computer program product, which includes a computer program stored in a computer-readable storage medium. A processor reads from the computer-readable storage medium and executes the computer program to implement the above-described resource access method.

[0012] The technical solution provided in this application can bring the following beneficial effects: The resource memory access device proposed in this application establishes a block mapping table for sparse resources, which manages the virtual memory space where sparse resources reside. Based on this, when the address generation unit receives a resource memory access request from the shader core and determines that the resource to be accessed is a sparse resource, it first determines the block mapping table address and the offset within the block based on the resource address information. Then, based on the block mapping table address and the offset within the block, it determines the virtual address corresponding to the resource to be accessed, and transmits the virtual address to the memory management unit. The memory management unit then converts the virtual address into a physical address, enabling resource memory access operations to be performed based on the physical address. By using a general buffer resource as the block mapping table, the accelerated characteristics of hardware sparse resource access can be preserved while gaining the flexibility of software implementation in block mapping management, thereby optimizing the resource memory access process. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This invention provides a schematic diagram of the structure of a resource access device according to an exemplary embodiment of the present application. Figure 2 A schematic diagram of a block mapping table provided in an exemplary embodiment of this application is shown; Figure 3 A schematic diagram of the structure of a resource access device provided in another exemplary embodiment of this application is shown; Figure 4 A flowchart illustrating a resource access method provided in an exemplary embodiment of this application is shown; Figure 5 A schematic diagram of the structure of a computer device provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0016] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0017] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0018] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0019] First, a brief introduction to the terms used in the embodiments of this application will be given.

[0020] Sparse resources, also known as tiled resources, and specifically texture resources (including partially resident textures, PRTs, and virtual textures), are a technology that supports resources whose total storage space requirements exceed their actual storage usage. Early implementations of sparse resources primarily used texture resources, while most current implementations support both texture and buffer resources. The resource access mechanism proposed in this application mainly targets these two categories of general resources, hence the term "sparse resources."

[0021] A block mapping table is a data structure used to manage the virtual storage space where sparse resources reside. In this embodiment, the block mapping table is an application-visible index table. Optionally, the block mapping table stores the block sequence number corresponding to each block and the block mapping element, which can be a 32-bit or 64-bit binary number. That is, each block in the sparse resource space corresponds to a block mapping element in the block mapping table, and this block mapping element is used to indicate the block address information of the block in the virtual storage space.

[0022] Resource descriptors are the entry points for GPU shaders to access resources. Generally, a resource descriptor includes basic information such as resource format and layout, as well as the base address of the resource's storage space. In this embodiment, the block address information of the block to which the sparse resource belongs comes from the block mapping table; therefore, a fixed virtual base address is not required, and the base address in its resource descriptor can directly use the block mapping table address. Other information in the resource descriptor is not significantly different for sparse resources from that for ordinary resources.

[0023] In related technologies, memory access implementations for sparse resources are divided into hardware sparse resources and software sparse resources. For hardware sparse resources, a common approach relies on the operating system's virtual memory mapping, directly mapping and baking resource blocks into the system GPU page table. Updates depend on the GPU's Virtual Memory Management (DDI) of the relevant operating system. Other implementations include using special virtual block page table designs. For software sparse resources, implementation is mainly done by parts of the application. The application uses its own managed general resources as page tables and block pools. The shader program first accesses the page table resources to find the actual block storage location. For texture resources, special processing is usually required during the sampling process, such as adding padding or performing software sampling filtering.

[0024] Despite its long history, sparse resources have not been widely adopted in practical applications, mainly due to some usability and performance issues in their application.

[0025] 1. Impact on GPU memory access performance.

[0026] a. Limitations of compression techniques. Early implementations of sparse resources were often incompatible with real-time compression techniques because sparse resources are strongly bound to their coordinate space, while real-time compression techniques often rely on additional compression metadata (headers) independent of the resource coordinate space, increasing implementation complexity. Therefore, real-time compression often needs to be disabled for GPU reading and writing of sparse resources, impacting bandwidth and performance.

[0027] b. Additional page fault handling overhead. For sparse resources, unmapped blocks differ from regular page faults. They are generally not treated as errors directly, but rather as recoverable exceptions or their status needs to be fed back to the shader program, increasing the implementation complexity of memory access hardware and software. Subsequent accesses still require performing step-by-step page table lookups until it is confirmed whether the memory is mapped.

[0028] 2. The performance overhead of updating the block mapping itself.

[0029] Because the current hardware implementation of block mapping is based on the system GPU's virtual memory mapping, its updates also require system GPU page table updates, including associated synchronization and page table mapping cache invalidation (TLB Invalidate). Furthermore, update commands must be submitted by the CPU through a specific API (Application Programming Interface), and direct updates via GPU shaders are not supported. Additionally, the block size is limited by the system page size, resulting in small, difficult-to-batch CPU and GPU loads during update execution.

[0030] To address the aforementioned issues, this application adds a block mapping table between the resource address information and the virtual address for sparse resources. This block mapping table manages the virtual storage space where the sparse resources reside. During resource access, the address generation unit can first determine the block mapping table address and intra-block offset corresponding to the resource to be accessed based on the resource address information. Then, based on the block mapping table address and intra-block offset, it determines the virtual address corresponding to the resource to be accessed. This enables read / write operations in the GPU shader, with the GPU managing the block mapping. While retaining the acceleration characteristics of hardware sparse resource access, it also gains the flexibility of software implementation in block mapping management, thereby optimizing the resource access process.

[0031] The resource access device proposed in this application will be described below through specific embodiments.

[0032] Please refer to Figure 1 This illustrates a schematic diagram of the structure of a resource access device provided in an exemplary embodiment of this application. Figure 1 As shown, the resource memory access device 100 includes a shader core 110, an address generation unit 120, and a memory management unit 130.

[0033] The shader core 110 is used to send a resource memory access request to the address generation unit 120. The resource memory access request includes the resource address information corresponding to the resource to be accessed.

[0034] Optionally, the shader core 110 is a basic processing unit within the GPU specifically designed to execute graphics rendering and parallel computing instructions. Optionally, the shader core 110 can respond to resource memory access instructions in the shader program and generate a resource memory access request corresponding to the resource to be accessed, so that other hardware units can access the resource based on this request. It can be understood that the shader program drives the shader core, and the shader core executes the shader program. The shader program, as a piece of code executed on the GPU, provides the shader core with a continuous sequence of instructions, and the shader core is responsible for executing this sequence of instructions.

[0035] In some embodiments, in response to a resource memory access instruction in the shader program, the shader core 110 determines the resource address information of the resource to be accessed and generates a resource memory access request corresponding to the resource to be accessed. This resource memory access request includes the resource address information corresponding to the resource to be accessed, and then sends the resource memory access request to the address generation unit 120. Optionally, if the resource memory access request is a resource write request, the shader core 110 also needs to transmit the resource data to be written to the resource at the same time.

[0036] Optionally, the resource address information corresponding to the memory resource to be accessed is used to indicate the relevant address information of the memory resource to be accessed, such as the address information of the memory resource to be accessed in the UV coordinate system, the address information of the memory resource to be accessed in the virtual memory space, etc. Among them, the UV coordinate system is the core coordinate system in computer graphics used to map 2D texture images onto the surface of 3D models.

[0037] The resource address information may include the resource coordinates and resource descriptor corresponding to the memory resource to be accessed. Optionally, the resource coordinates are used to uniquely identify the memory resource to be accessed within the sparse resource space. For example, for a texture resource, its resource coordinates within the texture resource space can be represented as a... A tuple. Among them, The horizontal component (x-axis) of the texture coordinates; Represents the vertical component (ordinate) of the texture coordinates; This indicates the Mipmap (multi-level asymptotic texture) level number to be accessed. Mipmap is a multi-resolution texture pyramid technique that solves the texture sampling aliasing problem and optimizes rendering performance in real-time rendering by pre-generating a series of image levels that are progressively reduced by half for the original texture. The Mipmap level number is used to indicate which resolution to select. This represents the array slice index, which is an integer index within the texture array or multidimensional GPU resource used to select a specific sub-resource. The array slice index indicates which texture to select. Optionally, the resource descriptor indicates the block mapping table information corresponding to the memory resource to be accessed, such as the virtual address of the block mapping table in the virtual memory space.

[0038] Address generation unit 120 is used to determine the block mapping table address and intra-block offset corresponding to the memory resource to be accessed based on the resource address information when the memory resource to be accessed is a sparse resource, and to determine the virtual address corresponding to the memory resource to be accessed based on the block mapping table address and intra-block offset, and to transmit the virtual address to memory management unit 130.

[0039] Optionally, the Address Generation Unit (AGU) 120 is a hardware unit used to convert resource address information in a resource memory access request into a virtual address. In this embodiment, a block mapping table is added between the resource address information and the virtual address for sparse resources. Based on this, when the memory resource to be accessed is a sparse resource, the address generation unit 120 needs to first convert the resource address information into the block mapping table address and the offset within the block corresponding to the memory resource to be accessed, and then determine the virtual address corresponding to the memory resource to be accessed.

[0040] The block mapping table address is used to indicate the location information of the block mapping table corresponding to the memory resource to be accessed within the virtual storage space. The block mapping table corresponding to the block mapping table address is a data structure used to manage the virtual storage space where sparse resources reside.

[0041] In this embodiment, the block mapping table is an application-visible index table. That is, the block mapping table can be implemented using a shader-accessible general buffer resource or a generic buffer resource. Optionally, the generic or general buffer resource can be designed to be used by various different programs, modules, or system calls to meet various temporary and unspecified data storage needs.

[0042] Optionally, the block mapping table stores the block sequence number corresponding to each block and the block mapping element, which can be a 32-bit or 64-bit binary number. That is, each block in the sparse resource space has a corresponding block mapping element in the block mapping table, which is used to indicate the block address information of the block in the virtual storage space.

[0043] Therefore, given the known block mapping table address, in order to determine the virtual address corresponding to the memory resource to be accessed, it is also necessary to first determine the relative position of the memory resource to be accessed within the block mapping table. That is, the address generation unit 120 needs to determine the intra-block offset corresponding to the memory resource to be accessed. This intra-block offset is used to indicate the offset of the virtual address of the memory resource to be accessed in the virtual storage space relative to the block virtual address of the block to which the memory resource to be accessed belongs.

[0044] In some embodiments, upon receiving a resource memory access request sent by the shader core 110 and determining that the memory resource to be accessed is a sparse resource, the address generation unit 120 may first determine the block mapping table address and the offset within the block corresponding to the memory resource to be accessed based on the resource address information in the resource memory access request, thereby determining the virtual address of the memory resource to be accessed in the virtual memory space according to the block mapping table address and the offset within the block, and transmitting the virtual address to the memory management unit 130.

[0045] Optionally, to support dynamic, larger blocks, the address width of the block mapping table address can be set to 44-48 bits, and the offset width of the offset within the block can be set to 16-20 bits.

[0046] The memory management unit 130 is used to convert the received virtual address into a physical address and perform resource memory access operations based on the physical address.

[0047] Optionally, the Memory Management Unit (MMU) 130 is a hardware unit responsible for translating virtual addresses into physical addresses and performing memory access permission control.

[0048] In some embodiments, after receiving the virtual address transmitted by the address generation unit 120, the memory management unit 130 needs to first convert the virtual address into a physical address before performing resource memory access operations based on the physical address. Optionally, the mapping relationship between the virtual address and the physical address can be pre-established by the operating system and stored in the memory management unit 130 using a TLB (Translation Lookaside Buffer) structure. This allows the memory management unit 130 to determine the physical address corresponding to the virtual address based on a fast lookup mechanism and perform resource memory access operations based on the physical address.

[0049] Optionally, a resource memory access request may include at least one of a resource read request and a resource write request. Optionally, if the resource memory access request is a resource read request, the memory management unit 130 needs to read the sparse resource from the physical storage space indicated by the physical address and return the sparse resource to the shader core 110 so that the shader core 110 can use the sparse resource. Optionally, if the resource memory access request is a resource write request, the memory management unit 130 needs to write the sparse resource to the physical storage space indicated by the physical address.

[0050] In summary, in this embodiment, a block mapping table is set up for sparse resources, and the virtual memory space where the sparse resources reside is managed through this block mapping table. Based on this, when the address generation unit receives a resource memory access request from the shader core and determines that the resource to be accessed is a sparse resource, it first determines the block mapping table address and the offset within the block based on the resource address information. Then, based on the block mapping table address and the offset within the block, it determines the virtual address corresponding to the resource to be accessed, and transmits the virtual address to the memory management unit. The memory management unit then converts the virtual address into a physical address to perform the resource memory access operation based on the physical address. By using a general buffer resource as the block mapping table, it is possible to retain the accelerated characteristics of hardware sparse resource access while gaining the flexibility of software implementation in block mapping management, thereby optimizing the resource memory access process.

[0051] In some embodiments, considering that the offset within a block indicates the offset of the virtual address of the memory resource to be accessed relative to the block virtual address of the block to which the memory resource belongs, it is necessary to first determine the block to which the memory resource belongs in order to determine the virtual address corresponding to the memory resource to be accessed.

[0052] Optionally, the resource memory access request sent by the shader core 110 to the address generation unit 120 includes resource address information corresponding to the memory resource to be accessed. This resource address information includes the resource coordinates and resource descriptor corresponding to the memory resource to be accessed.

[0053] Address generation unit 120 is used to determine the block sequence number and offset within the block corresponding to the memory resource to be accessed based on the resource coordinates; determine the block virtual address of the block indicated by the block sequence number based on the block mapping table corresponding to the block mapping table address; and determine the virtual address corresponding to the memory resource to be accessed based on the block virtual address and the offset within the block.

[0054] Optionally, the sparse resource space comprises several blocks, each corresponding to a block sequence number. In the block mapping table corresponding to the sparse resource space, this block sequence number corresponds one-to-one with the block mapping element, and indicates the order of the block mapping elements in the block mapping table. Optionally, the block mapping table stores the block sequence number corresponding to the block and the block mapping element, whereby the block mapping element indicates the block's virtual address, and the virtual address indicates the block's location in the virtual storage space.

[0055] Based on this, after determining the block sequence number, the address generation unit 120 can determine the block mapping element corresponding to the block according to the correspondence between the block sequence number and the block mapping element in the block mapping table, and obtain the block virtual address from the block mapping element.

[0056] Optionally, after determining the block virtual address, the address generation unit 120 can add the block virtual address and the intra-block offset to obtain the virtual address corresponding to the memory resource to be accessed. This is achieved by combining the offset of the virtual address of the memory resource to be accessed relative to the block virtual address of the block to which the memory resource belongs, as indicated by the intra-block offset. That is, the virtual address corresponding to the memory resource to be accessed = block virtual address + intra-block offset.

[0057] By determining the block sequence number of the block to which the memory resource to be accessed belongs, the block virtual address of that block can be obtained. By adding the block virtual address and the offset within the block, the virtual address corresponding to the memory resource to be accessed can be obtained. This enables block mapping management of sparse resources and ensures the accuracy of the virtual address.

[0058] Regarding the process of determining the block sequence number and the offset within the block, in one possible implementation, the address generation unit 120 is used to determine the starting address of the block corresponding to the memory resource to be accessed based on the resource coordinates. The starting address of the block is used to indicate the location information of the block to which the memory resource to be accessed belongs in the sparse resource space. Based on the starting address of the block and the block information of each block in the sparse resource space, the block sequence number and the offset within the block corresponding to the memory resource to be accessed are determined.

[0059] Optionally, taking sparse resources as 2D single-sampled texture resources as an example, their corresponding resource coordinates can be represented as a... Tuples. Based on this, the address generation unit 120 can generate addresses according to the memory resources to be accessed. Texture coordinates, mipmap levels, and array slice indices are used to obtain the starting address of the block corresponding to the memory resource to be accessed through address translation. In one possible implementation, the address generation unit 120 can take the resource coordinates as input and output the starting address of the block based on the address translation function. The design of this address translation function is related to the sparse resource settings and hardware design.

[0060] Optionally, the block start address is used to indicate the location information of the block to which the memory resource to be accessed belongs within the sparse resource space. Optionally, the block start address is equal to the resource address of the memory resource to be accessed within the sparse resource space minus the start address of the sparse resource space. Assuming the start address of the sparse resource space is 0, then the block start address is equal to the resource address of the memory resource to be accessed within the sparse resource space.

[0061] Furthermore, in order to determine which block the memory resource to be accessed belongs to, and the offset of the memory resource to be accessed within the block, the address generation unit 120 also needs to combine the block information of each block in the sparse resource space to determine the block sequence number and the offset within the block corresponding to the memory resource to be accessed.

[0062] Optionally, the block information may include the block size, which refers to the amount of space occupied by the block within the sparse resource space. That is, the starting address of the block corresponding to the memory resource to be accessed is equal to the total block size of all blocks in the sparse resource space preceding the block to which the memory resource to be accessed belongs, plus the offset of the memory resource to be accessed within the block.

[0063] Based on this, the address generation unit 120 can determine the number of blocks preceding the block to which the memory resource to be visited belongs, based on the block start address and the block information of each block in the sparse resource space, thereby obtaining the block sequence number and the offset within the block corresponding to the memory resource to be visited.

[0064] Optionally, the block sequence number corresponding to the memory resource to be accessed is also related to the block sequence number of the first block in the block mapping table. Optionally, if the block sequence number of the first block in the block mapping table is 1, the block sequence number corresponding to the memory resource to be accessed = the number of blocks preceding the block to which the memory resource to be accessed belongs + 1. Optionally, if the block sequence number of the first block in the block mapping table is 0, the block sequence number corresponding to the memory resource to be accessed = the number of blocks preceding the block to which the memory resource to be accessed belongs.

[0065] For example, if the first block in the block mapping table has a block sequence number of 1, and there are 4 blocks preceding the block containing the memory resource to be accessed, then the block sequence number corresponding to the memory resource to be accessed is 5. As another example, if the first block in the block mapping table has a block sequence number of 0, and there are 4 blocks preceding the block containing the memory resource to be accessed, then the block sequence number corresponding to the memory resource to be accessed is 4.

[0066] By first determining the starting address of the block corresponding to the memory resource to be accessed, and then combining the block information of each block in the sparse resource space corresponding to the block mapping table, the block sequence number of the block to which the memory resource to be accessed belongs can be determined, thus ensuring the accuracy of the block sequence number and improving the accuracy of the virtual address.

[0067] Optionally, the block sizes of each block can be the same or different, and this application embodiment does not limit this. Optionally, the block size is not limited to the implementation of the operating system and video memory management unit; the shader program can choose to use larger blocks to reduce the lookup frequency. Optionally, the block size is usually a power of 2, and the actual stored value can be the result of an offset based on the block size. For example, for a 64KiB block, a 32-bit element can represent a maximum of 48 bits of address space.

[0068] Indicative, such as Figure 2 As shown, Figure 2 (1) in the text represents the sparse resource space, which contains several blocks; Figure 2(2) in the table represents the block mapping table, which stores the block sequence number corresponding to the block and the block mapping element; Figure 2 (3) in the text represents the block mapping table resource (including the corresponding video memory allocation), and the block mapping table resource adopts the general buffer resource; Figure 2 (4) in the figure represents the physical storage space corresponding to sparse resources in video memory.

[0069] In one possible implementation, to improve the management efficiency of the block mapping table, the block size of each block can be configured to be the same. Optionally, when the block sizes of each block in the sparse resource space are the same, the address generation unit 120 is used to determine the block sequence number and the offset within the block corresponding to the memory resource to be accessed based on the result of the division operation between the block start address and the block size.

[0070] Optionally, the result of the division operation between the block start address and the block size refers to the result of the division operation with the block start address as the dividend and the block size as the divisor. Optionally, the division result includes the quotient and the remainder, and the address generation unit 120 can determine the remainder of the division result as the offset within the block.

[0071] Optionally, if the block sequence number of the first block in the block mapping table is 0, the block sequence number can be a value rounded down based on the result of a division operation. Optionally, if the block sequence number of the first block in the block mapping table is 1, the block sequence number can be a value rounded up based on the result of a division operation.

[0072] In another possible implementation, to improve the flexibility of block design, each block in the sparse resource space can be configured with its own block size. Optionally, when the block sizes of each block in the sparse resource space are different, the address generation unit 120 is used to determine the block sequence number and the offset within the block corresponding to the memory resource to be accessed based on the block start address and the block size of each block.

[0073] Optionally, the address generation unit 120 can use the block starting address to successively subtract the block size of the first block, the block size of the second block, the block size of the third block, and so on, compare the remainder with the block size of the next block, and thus determine the block to which the memory resource to be accessed belongs if the remainder is less than the block size of the next block, and determine the remainder as the offset within the block.

[0074] For example, if the block size of the first block is 5, the block size of the second block is 10, the block size of the third block is 7, and the starting address of the block is 18, then after subtracting the block sizes of the first and second blocks from the starting address of the block, the remainder is 3, which is less than the block size of the third block. Therefore, it can be determined that the block to which the memory resource to be accessed belongs is the third block, and the offset within the block is 3.

[0075] By combining the block size of each block with the starting address of the block corresponding to the memory resource to be accessed, the block sequence number corresponding to the memory resource to be accessed can be determined, which can further ensure the accuracy of the block sequence number.

[0076] like Figure 2 As shown, for the memory resource to be accessed, the address generation unit first determines the starting address of the block corresponding to the block to which the memory resource belongs through address translation based on the resource coordinates. Then, based on the starting address and the block size of each block in the sparse resource space, it determines the block sequence number and the offset within the block. Further, based on the correspondence between the block sequence number and the block mapping element in the block mapping table, it determines the block mapping element corresponding to the block and obtains the block virtual address from the block mapping element. Thus, by using the block virtual address plus the offset within the block, the virtual address corresponding to the memory resource to be accessed can be obtained. Finally, by converting the virtual address to a physical address, the resource access operation can be performed in the physical storage space based on the physical address.

[0077] Optionally, without distinguishing between sparse resources, that is, after receiving a resource access request, the address generation unit 120 directly performs block mapping based on the resource address information of the resource to be accessed. In this case, the resource descriptor can directly store the block mapping table address corresponding to the resource to be accessed, and the address generation unit 120 can directly obtain the block mapping table address from the resource descriptor.

[0078] Optionally, when distinguishing between sparse resources and other resources (such as ordinary resources), in order to facilitate the block mapping process performed by the address generation unit 120, it is necessary to indicate to the address generation unit that the memory resource to be accessed is a sparse resource through a resource descriptor. Therefore, the address generation unit 120 is used to obtain the block mapping table address corresponding to the memory resource to be accessed from the resource descriptor when the resource descriptor indicates that the memory resource to be accessed is a sparse resource.

[0079] Optionally, the resource type of the memory resource to be accessed can be indicated by adding a resource bit to the resource descriptor. In one possible implementation, after receiving a memory access request, the address generation unit 120 parses the resource descriptor and determines the resource type indicated by the resource bit. If the resource type indicated by the resource bit is a sparse resource, the address generation unit 120 further determines the block mapping table address and the offset within the block corresponding to the memory resource to be accessed.

[0080] By using resource descriptors to indicate the resource type of the memory resource to be accessed, the address generation unit can more easily determine whether to perform block mapping for the memory resource to be accessed, thereby improving the accuracy of resource access.

[0081] In some embodiments, in order to implement sparse resource access based on block mapping, it is also necessary to create a corresponding resource descriptor for each sparse resource before resource access, so that during the resource access process, the virtual address corresponding to the sparse resource can be determined by combining the block mapping table address corresponding to the sparse resource in the resource descriptor.

[0082] Optionally, shader core 110 is used to create resource descriptors corresponding to sparse resources based on the association between sparse resources and block mapping tables.

[0083] Optionally, the association between sparse resources and the block mapping table can be specified by the shader core 110, or it can be input to the shader core 110 by the shader program. Optionally, the association between sparse resources and the block mapping table can be established based on the first resource information of the sparse resources and the second resource information of the block mapping table.

[0084] Optionally, a sparse resource corresponds to at least one resource descriptor, and different resource descriptors in the at least one resource descriptor are used to indicate the association between the sparse resource and different block mapping tables. That is, a sparse resource can correspond to one or more block mapping tables.

[0085] In one possible implementation, shader core 110 is configured to respond to first resource binding information in the shader program when creating a resource descriptor corresponding to a sparse resource. The first resource binding information is used to indicate the association between the sparse resource and the block mapping table.

[0086] That is, after the sparse resource is created, the first resource binding information is input to the shader core 110 when the resource descriptor is created. The shader core 110 responds to the first resource binding information and creates a resource descriptor for the sparse resource based on the association between the sparse resource indicated by the first resource binding information and the block mapping table.

[0087] In the above implementation of resource descriptors, the first resource binding information may include the association between sparse resources and at least two block mapping tables, thereby enabling the creation of at least two resource descriptors for sparse resources at one time and improving the creation efficiency of resource descriptors.

[0088] In another possible implementation, shader core 110 is configured to respond to first resource binding information in the shader program when creating sparse resources, the first resource binding information indicating the association between sparse resources and block mapping tables.

[0089] That is, when creating a sparse resource, the first resource binding information is directly input into the shader core 110, and the shader core 110 responds to the first resource binding information and creates a resource descriptor for the sparse resource based on the association between the sparse resource indicated by the first resource binding information and the block mapping table.

[0090] In the above implementation of resource descriptors, block mapping table resources are allocated or associated when sparse resources are created, which can achieve strong binding between the block mapping table and the corresponding sparse resources.

[0091] In another possible implementation, shader core 110 is configured to respond to second resource binding information in the shader program after creating at least two sparse resources, the second resource binding information indicating the association between the at least two sparse resources and the block mapping table.

[0092] That is, after multiple sparse resources are created, the second resource binding information will be input to the shader core 110. In this way, the shader core 110 responds to the second resource binding information and can create resource descriptors for multiple sparse resources at once, thereby improving the efficiency of resource descriptor creation.

[0093] Regardless of the resource descriptor implementation method used, it is guaranteed that the resource descriptor corresponding to the sparse resource contains the block mapping table address for address calculation during sampling. Furthermore, by including the block mapping in the resource descriptor of the sparse resource, it is possible to avoid introducing additional resource descriptors during resource memory access.

[0094] In some embodiments, the shader core 110 is also configured to create a block mapping table based on mapping table creation instructions in the shader program; and update the block mapping table based on mapping table update instructions in the shader program.

[0095] In other words, the block map is visible to the application, and the shader program can create and update the block map through the shader core 110, thereby improving the flexibility of block map management. Optionally, the block map can adopt a buffer resource design, allowing the block map to be directly managed by the shader program and accessed for reading and writing in the GPU shader.

[0096] Optionally, the block mapping table includes block mapping elements, each corresponding one-to-one with a block in the sparse resource space. The block mapping elements indicate the block address information corresponding to the block. The block address information includes at least one of the following: the virtual address of the GPU heap range (GPUVA), the virtual address bit range, and the block offset. The block offset can be the offset of the block relative to the starting virtual address of the block in the block mapping table, and can be a negative number.

[0097] Optionally, creating a block mapping table may include determining the block mapping element corresponding to the block to which the sparse resource belongs, and saving the correspondence between the block sequence number and the block mapping element. Optionally, updating the block mapping table may include updating the block mapping element corresponding to the block to which the sparse resource belongs, and re-saving the correspondence between the block sequence number and the block mapping element.

[0098] Optionally, the block map table can be accessed and read / written directly by the shader as a separate resource. Furthermore, to maintain data consistency, it is generally not allowed to be read (accessing the sparse resource associated with the block map table) and written / modified simultaneously within the same shader program.

[0099] In some embodiments, to further optimize the resource access process, the resource access device may also include a caching and texture filtering unit.

[0100] Please refer to Figure 3 This illustrates a schematic diagram of the structure of a resource access device provided in another exemplary embodiment of this application. Figure 3 As shown, the resource memory access device 300 includes a shader core 310, an address generation unit 320, a memory management unit 330, a cache 340, and a texture filtering unit 350.

[0101] Optionally, the resource memory access request includes at least one of a resource read request and a resource write request. Optionally, the shader core 310 transmits a resource read request to the address generation unit 320, the resource read request including the resource coordinates and resource descriptor corresponding to the resource to be read. Optionally, the shader core 310 transmits a resource write request to the address generation unit 320, the resource write request including the resource coordinates, resource descriptor, and resource data corresponding to the resource to be written.

[0102] Optionally, the address generation unit 320 determines whether the memory resource to be accessed is a sparse resource. If the memory resource to be accessed is a sparse resource, the resource coordinates and resource descriptor are converted into block mapping table addresses and offsets within blocks, and the virtual address corresponding to the memory resource to be accessed is further determined through block mapping.

[0103] Optionally, cache 340 is used to store virtual addresses and sparse resources accessed within a first time threshold. In one possible implementation, address generation unit 320 does not directly transmit the virtual address to memory management unit 330, but first transmits the virtual address of the memory resource to be accessed to cache 340, so that cache 340 can determine whether a hit occurs, and determine whether to transmit the virtual address to memory management unit 330 based on the hit status.

[0104] Optionally, the address generation unit 320 is used to transmit the virtual address of the memory resource to be accessed to the cache 340. Optionally, the cache 340 is used to transmit the virtual address of the memory resource to be accessed to the memory management unit 330 when it receives the virtual address of the memory resource to be accessed and misses the memory access.

[0105] In one possible implementation, when the resource access request is a resource read request, if cache 340 receives the virtual address of the resource to be accessed and a hit occurs, it means that cache 340 stores the sparse resource corresponding to the virtual address, and the sparse resource can be directly read from cache 340 and returned. In another possible implementation, if cache 340 receives the virtual address of the resource to be accessed and a miss occurs, it means that cache 340 does not store the sparse resource corresponding to the virtual address. In this case, it is necessary to further convert the virtual address to a physical address through memory management unit 330 and read the sparse resource from the physical storage space.

[0106] In another possible implementation, when the resource access request is a resource write request, the cache 340 can directly transmit the virtual address to the memory management unit 330, which will then convert the virtual address into a physical address and write sparse resources into the storage space indicated by the physical address. After the data writing is completed, the cache 340 will return a data write completion signal to the shader core 310.

[0107] By first transmitting the virtual address to the cache and determining whether a cache hit occurs, and then considering whether to further transmit the virtual address to the memory management unit, it is possible to directly read sparse resources when the cache contains sparse resources corresponding to the virtual addresses, which can effectively improve the efficiency of resource access.

[0108] Optionally, to improve the quality of resource access, the resource access device may also include a texture filtering unit 350, so that after reading sparse resources, the sparse resources are first processed by the texture filtering unit 350, and then the processed sparse resources are returned to the shader core 310.

[0109] In one possible implementation, the texture filtering unit 350 is configured to perform texture filtering processing on the memory to be accessed when the memory access request is a resource read request and the returned memory to be accessed is received, and then transmit the processed memory to be accessed to the shader core 310.

[0110] Optionally, texture filtering can be texel interpolation calculation, which generates a smooth and continuous texture output by weighted averaging of the color values ​​of multiple neighboring texels. Optionally, texture filtering may also include other processing methods, which are not limited in this embodiment.

[0111] When a resource access request is a resource read request and the resource to be accessed has already been read, the resource quality can be improved by first performing texture filtering processing on the resource to be accessed through the texture filtering unit, and then returning the processed resource to be accessed to the shader core. This helps to improve the resource processing efficiency of the shader core.

[0112] Optionally, in the resource access device proposed in this application, block mapping table access is a general access behavior. In order to improve the efficiency of resource access, the following methods can also be used to reduce block mapping latency.

[0113] Method 1: Relying on Memory Access Coalescing and Cache Hierarchy. Since a single block mapping element in the block map table corresponds to a spatially contiguous block in sparse resources, the spatiotemporal locality of texture and buffer data accesses is amplified when accessing the block map table for typical graphics applications. It can be expected that requests for block map elements are highly likely to be repeated within the same batch of resource access requests from a single thread. Therefore, the memory access merging strategy can effectively reduce actual memory accesses to the block map table. Storing the block map table can improve cache priority and prevent premature evicting. Furthermore, the cache line size of the block map table can be adjusted based on actual access statistics.

[0114] In one possible implementation, when all resource access requests submitted in the same batch are for a single block within the sparse resource space, i.e., a block mapping element in the corresponding block mapping table, the address generation unit can merge the resource access requests, determine the block sequence number only once, and access the block mapping table once to determine the block virtual address of the block indicated by the block sequence number.

[0115] Method 2: Implement a dedicated block mapping cache or dynamically reserve some cache lines for use in the block mapping table. Similar to dedicated block mapping hardware, block mapping data is specially processed and allocated a separate low-latency cache space.

[0116] Furthermore, when real-time compression techniques using metadata exist, the compressed metadata may exist independently of the actual resource data. In this embodiment, the block mapping table is based on storage space mapping, meaning the block address mapping is independent of compression operations, thus ensuring compatibility with such compression techniques.

[0117] Based on the above embodiments, the beneficial effects of the resource access device proposed in this application are summarized as follows.

[0118] 1. Improved programmability and flexibility of sparse resource block mapping management. Since the block mapping table is implemented using general resources, it can be read and written in the GPU shader without relying on the CPU to submit specific block mapping update commands, thus allowing for fully GPU-implemented block mapping management. Furthermore, because block mapping no longer depends on system page tables or special block mapping hardware implementations, and the block size is not limited by the operating system and memory management unit implementation, applications can choose to use larger blocks to reduce lookup frequency.

[0119] 2. Reduce block update overhead. As mentioned earlier, since the block mapping table can be updated directly by the GPU shader, and read-write synchronization is performed through a lightweight resource barrier, and partial cache flush is performed after the block update, there is no need to perform more expensive operations such as clearing the GPU command queue and clearing the TLB.

[0120] 3. Simplify the implementation of the video memory management unit and system page table. Sparse resource implementations based on system page tables often introduce additional complexity into the video memory management unit to handle the differences between ordinary page misses and virtual block page misses. Separating the sparse resource block mapping from the system virtual memory mapping eliminates the need for special handling of page misses during system page table lookups, thus simplifying its design.

[0121] 4. Compatibility with programming interfaces. The block mapping implementation in programming interfaces (such as Tiled Resource in DirectX® and Sparse Resident Resource in Vulkan®) is transparent to the application; therefore, the general block mapping resource proposed in this application can be fully used to implement its functionality.

[0122] Please refer to Figure 4This document illustrates a flowchart of a resource memory access method provided in an exemplary embodiment of this application. This embodiment uses the method in a resource memory access device as an example. The device includes a shader core, an address generation unit, and a memory management unit. Optionally, the method includes the following steps.

[0123] Step 410: The shader core sends a resource memory access request to the address generation unit. The resource memory access request includes the resource address information corresponding to the resource to be accessed.

[0124] Optionally, a shader core is a basic processing unit within the GPU specifically designed to execute graphics rendering and parallel computing instructions. Optionally, a shader core can respond to resource memory access instructions in the shader program and generate a resource memory access request corresponding to the resource to be accessed, so that other hardware units can access the resource based on this request. It can be understood that the shader program drives the shader core, and the shader core executes the shader program. The shader program, as a piece of code executed on the GPU, provides the shader core with a continuous sequence of instructions, and the shader core is responsible for executing this sequence of instructions.

[0125] In some embodiments, in response to a resource memory access instruction in the shader program, the shader core determines the resource address information of the resource to be accessed and generates a resource memory access request corresponding to the resource to be accessed. This resource memory access request includes the resource address information corresponding to the resource to be accessed, and then sends the resource memory access request to the address generation unit. Optionally, if the resource memory access request is a resource write request, the shader core also needs to transmit the resource data to be written to the resource at the same time.

[0126] Optionally, the resource address information corresponding to the memory resource to be accessed is used to indicate the relevant address information of the memory resource to be accessed, such as the address information of the memory resource to be accessed in the UV coordinate system, the address information of the memory resource to be accessed in the virtual memory space, etc. Among them, the UV coordinate system is the core coordinate system in computer graphics used to map 2D texture images onto the surface of 3D models.

[0127] The resource address information may include the resource coordinates and resource descriptor corresponding to the memory resource to be accessed. Optionally, the resource coordinates are used to uniquely identify the memory resource to be accessed within the sparse resource space. For example, for a texture resource, its resource coordinates within the texture resource space can be represented as a... A tuple. Among them, The horizontal component (x-axis) of the texture coordinates; Represents the vertical component (ordinate) of the texture coordinates; This indicates the Mipmap (multi-level asymptotic texture) level number to be accessed. Mipmap is a multi-resolution texture pyramid technique that solves the texture sampling aliasing problem and optimizes rendering performance in real-time rendering by pre-generating a series of image levels that are progressively reduced by half for the original texture. The Mipmap level number is used to indicate which resolution to select. This represents the array slice index, which is an integer index within the texture array or multidimensional GPU resource used to select a specific sub-resource. The array slice index indicates which texture to select. Optionally, the resource descriptor indicates the block mapping table information corresponding to the memory resource to be accessed, such as the virtual address of the block mapping table in the virtual memory space.

[0128] Step 420: When the memory resource to be accessed is a sparse resource, the address generation unit determines the block mapping table address and the offset within the block corresponding to the memory resource to be accessed based on the resource address information, and determines the virtual address corresponding to the memory resource to be accessed based on the block mapping table address and the offset within the block, and transmits the virtual address to the memory management unit.

[0129] Optionally, the address generation unit is a hardware unit used to convert resource address information in a resource memory access request into a virtual address. In this embodiment, a block mapping table is added between the resource address information and the virtual address for sparse resources. Based on this, when the memory resource to be accessed is a sparse resource, the address generation unit needs to first convert the resource address information into the block mapping table address and the offset within the block corresponding to the memory resource to be accessed, and then determine the virtual address corresponding to the memory resource to be accessed.

[0130] The block mapping table address is used to indicate the location information of the block mapping table corresponding to the memory resource to be accessed within the virtual storage space. The block mapping table corresponding to the block mapping table address is a data structure used to manage the virtual storage space where sparse resources reside.

[0131] In this embodiment, the block mapping table is an application-visible index table. That is, the block mapping table can be implemented using a shader-accessible general buffer resource or a generic buffer resource. Optionally, the generic or general buffer resource can be designed to be used by various different programs, modules, or system calls to meet various temporary and unspecified data storage needs.

[0132] Optionally, the block mapping table stores the block sequence number corresponding to each block and the block mapping element, which can be a 32-bit or 64-bit binary number. That is, each block in the sparse resource space has a corresponding block mapping element in the block mapping table, which is used to indicate the block address information of the block in the virtual storage space.

[0133] Therefore, given the known block mapping table address, in order to determine the virtual address corresponding to the memory resource to be accessed, it is also necessary to first determine the relative position of the memory resource to be accessed within the block mapping table. That is, the address generation unit needs to determine the intra-block offset corresponding to the memory resource to be accessed. This intra-block offset is used to indicate the offset of the virtual address of the memory resource to be accessed in the virtual storage space relative to the block virtual address of the block to which the memory resource to be accessed belongs.

[0134] In some embodiments, when a resource memory access request is received from the shader core and it is determined that the memory access resource is a sparse resource, the address generation unit can first determine the block mapping table address and the offset within the block corresponding to the memory access resource based on the resource address information in the resource memory access request. Then, based on the block mapping table address and the offset within the block, the virtual address of the memory access resource in the virtual memory space is determined, and the virtual address is transmitted to the memory management unit.

[0135] Optionally, to support dynamic, larger blocks, the address width of the block mapping table address can be set to 44-48 bits, and the offset width of the offset within the block can be set to 16-20 bits.

[0136] In step 430, the memory management unit converts the received virtual address into a physical address and performs resource memory access operations based on the physical address.

[0137] Optionally, the memory management unit is a hardware unit responsible for translating virtual addresses into physical addresses and executing memory access permission control.

[0138] In some embodiments, after receiving the virtual address transmitted by the address generation unit, the memory management unit needs to first convert the virtual address into a physical address before it can perform resource memory access operations based on the physical address. Optionally, the mapping relationship between the virtual address and the physical address can be pre-established by the operating system and stored in the memory management unit using a TLB structure. This allows the memory management unit to determine the physical address corresponding to the virtual address based on a fast lookup mechanism and perform resource memory access operations based on the physical address.

[0139] Optionally, a resource memory access request may include at least one of a resource read request and a resource write request. Optionally, if the resource memory access request is a resource read request, the memory management unit needs to read the sparse resource from the physical storage space indicated by the physical address and return the sparse resource to the shader core so that the shader core can use the sparse resource. Optionally, if the resource memory access request is a resource write request, the memory management unit needs to write the sparse resource to the physical storage space indicated by the physical address.

[0140] In summary, in this embodiment, a block mapping table is set up for sparse resources, and the virtual memory space where the sparse resources reside is managed through this block mapping table. Based on this, when the address generation unit receives a resource memory access request from the shader core and determines that the resource to be accessed is a sparse resource, it first determines the block mapping table address and the offset within the block based on the resource address information. Then, based on the block mapping table address and the offset within the block, it determines the virtual address corresponding to the resource to be accessed, and transmits the virtual address to the memory management unit. The memory management unit then converts the virtual address into a physical address to perform the resource memory access operation based on the physical address. By using a general buffer resource as the block mapping table, it is possible to retain the accelerated characteristics of hardware sparse resource access while gaining the flexibility of software implementation in block mapping management, thereby optimizing the resource memory access process.

[0141] In some embodiments, considering that the offset within a block indicates the offset of the virtual address of the memory resource to be accessed relative to the block virtual address of the block to which the memory resource belongs, it is necessary to first determine the block to which the memory resource belongs in order to determine the virtual address corresponding to the memory resource to be accessed.

[0142] Optionally, the resource memory access request sent by the shader core to the address generation unit includes the resource address information corresponding to the memory resource to be accessed. This resource address information includes the resource coordinates and resource descriptor corresponding to the memory resource to be accessed.

[0143] The address generation unit determines the block sequence number and intra-block offset corresponding to the memory resource to be accessed based on the resource coordinates; it determines the block virtual address of the block indicated by the block sequence number based on the block mapping table corresponding to the block mapping table address; and it determines the virtual address corresponding to the memory resource to be accessed based on the block virtual address and intra-block offset.

[0144] Optionally, the sparse resource space comprises several blocks, each corresponding to a block sequence number. In the block mapping table corresponding to the sparse resource space, this block sequence number corresponds one-to-one with the block mapping element, and indicates the order of the block mapping elements in the block mapping table. Optionally, the block mapping table stores the block sequence number corresponding to the block and the block mapping element, whereby the block mapping element indicates the block's virtual address, and the virtual address indicates the block's location in the virtual storage space.

[0145] Based on this, after determining the block sequence number, the address generation unit can determine the block mapping element corresponding to the block according to the correspondence between the block sequence number and the block mapping element in the block mapping table, and obtain the block virtual address from the block mapping element.

[0146] Optionally, after determining the block virtual address, the address generation unit can add the block virtual address and the intra-block offset to obtain the virtual address corresponding to the memory resource to be accessed. This is achieved by combining the offset of the virtual address of the memory resource to be accessed relative to the block virtual address of the block to which the memory resource belongs, as indicated by the intra-block offset. That is, the virtual address corresponding to the memory resource to be accessed = block virtual address + intra-block offset.

[0147] By determining the block sequence number of the block to which the memory resource to be accessed belongs, the block virtual address of that block can be obtained. By adding the block virtual address and the offset within the block, the virtual address corresponding to the memory resource to be accessed can be obtained. This enables block mapping management of sparse resources and ensures the accuracy of the virtual address.

[0148] Regarding the process of determining the block sequence number and the offset within the block, in one possible implementation, the address generation unit determines the starting address of the block corresponding to the memory resource to be accessed based on the resource coordinates. The starting address of the block is used to indicate the location information of the block to which the memory resource to be accessed belongs in the sparse resource space. Based on the starting address of the block and the block information of each block in the sparse resource space, the block sequence number and the offset within the block corresponding to the memory resource to be accessed are determined.

[0149] Optionally, taking sparse resources as 2D single-sampled texture resources as an example, their corresponding resource coordinates can be represented as a... Tuples. Based on this, the address generation unit can determine the address based on the memory resource to be accessed. Texture coordinates, mipmap levels, and array slice indices are used to obtain the starting address of the block corresponding to the memory resource to be accessed through address translation. In one possible implementation, the address generation unit can take the resource coordinates as input and output the starting address of the block based on the address translation function. The design of this address translation function is related to the sparse resource settings and hardware design.

[0150] Optionally, the block start address is used to indicate the location information of the block to which the memory resource to be accessed belongs within the sparse resource space. Optionally, the block start address is equal to the resource address of the memory resource to be accessed within the sparse resource space minus the start address of the sparse resource space. Assuming the start address of the sparse resource space is 0, then the block start address is equal to the resource address of the memory resource to be accessed within the sparse resource space.

[0151] Furthermore, in order to determine which block the memory resource to be accessed belongs to, and the offset of the memory resource to be accessed within its block, the address generation unit also needs to combine the block information of each block in the sparse resource space to determine the block sequence number and the offset within the block corresponding to the memory resource to be accessed.

[0152] Optionally, the block information may include the block size, which refers to the amount of space occupied by the block within the sparse resource space. That is, the starting address of the block corresponding to the memory resource to be accessed is equal to the total block size of all blocks in the sparse resource space preceding the block to which the memory resource to be accessed belongs, plus the offset of the memory resource to be accessed within the block.

[0153] Based on this, the address generation unit can determine the number of blocks preceding the block to which the memory resource to be visited belongs, based on the block start address and the block information of each block in the sparse resource space, thereby obtaining the block sequence number and the offset within the block corresponding to the memory resource to be visited.

[0154] Optionally, the block sequence number corresponding to the memory resource to be accessed is also related to the block sequence number of the first block in the block mapping table. Optionally, if the block sequence number of the first block in the block mapping table is 1, the block sequence number corresponding to the memory resource to be accessed = the number of blocks preceding the block to which the memory resource to be accessed belongs + 1. Optionally, if the block sequence number of the first block in the block mapping table is 0, the block sequence number corresponding to the memory resource to be accessed = the number of blocks preceding the block to which the memory resource to be accessed belongs.

[0155] For example, if the first block in the block mapping table has a block sequence number of 1, and there are 4 blocks preceding the block containing the memory resource to be accessed, then the block sequence number corresponding to the memory resource to be accessed is 5. As another example, if the first block in the block mapping table has a block sequence number of 0, and there are 4 blocks preceding the block containing the memory resource to be accessed, then the block sequence number corresponding to the memory resource to be accessed is 4.

[0156] By first determining the starting address of the block corresponding to the memory resource to be accessed, and then combining the block information of each block in the sparse resource space corresponding to the block mapping table, the block sequence number of the block to which the memory resource to be accessed belongs can be determined, thus ensuring the accuracy of the block sequence number and improving the accuracy of the virtual address.

[0157] Optionally, the block sizes of each block can be the same or different, and this application embodiment does not limit this. Optionally, the block size is not limited to the implementation of the operating system and video memory management unit; the shader program can choose to use larger blocks to reduce the lookup frequency. Optionally, the block size is usually a power of 2, and the actual stored value can be the result of an offset based on the block size. For example, for a 64KiB block, a 32-bit element can represent a maximum of 48 bits of address space.

[0158] In one possible implementation, to improve the management efficiency of the block mapping table, the block size of each block can be configured to be the same. Optionally, when the block size of each block in the sparse resource space is the same, the address generation unit determines the block sequence number and the offset within the block corresponding to the memory resource to be accessed based on the result of the division operation between the block start address and the block size.

[0159] Optionally, the result of the division operation between the block start address and the block size refers to the result of the division operation with the block start address as the dividend and the block size as the divisor. Optionally, the division result includes the quotient and the remainder, and the address generation unit can determine the remainder of the division result as the offset within the block.

[0160] Optionally, if the block sequence number of the first block in the block mapping table is 0, the block sequence number can be a value rounded down based on the result of a division operation. Optionally, if the block sequence number of the first block in the block mapping table is 1, the block sequence number can be a value rounded up based on the result of a division operation.

[0161] In another possible implementation, to improve the flexibility of block design, each block within the sparse resource space can be configured with its own block size. Optionally, when the block sizes of each block within the sparse resource space are different, the address generation unit determines the block sequence number and the offset within the block corresponding to the memory resource to be accessed based on the block start address and the block size of each block.

[0162] Optionally, the address generation unit can use the block starting address to successively subtract the block size of the first block, the block size of the second block, the block size of the third block, and so on, compare the remainder with the block size of the next block, and thus determine the block to which the memory resource to be accessed belongs if the remainder is less than the block size of the next block, and determine the remainder as the offset within the block.

[0163] For example, if the block size of the first block is 5, the block size of the second block is 10, the block size of the third block is 7, and the starting address of the block is 18, then after subtracting the block sizes of the first and second blocks from the starting address of the block, the remainder is 3, which is less than the block size of the third block. Therefore, it can be determined that the block to which the memory resource to be accessed belongs is the third block, and the offset within the block is 3.

[0164] By combining the block size of each block with the starting address of the block corresponding to the memory resource to be accessed, the block sequence number corresponding to the memory resource to be accessed can be determined, which can further ensure the accuracy of the block sequence number.

[0165] Optionally, without distinguishing between sparse resources and non-sparse resources, that is, after receiving a resource access request, the address generation unit directly performs block mapping based on the resource address information of the resource to be accessed. In this case, the resource descriptor can directly store the block mapping table address corresponding to the resource to be accessed, and the address generation unit can directly obtain the block mapping table address from the resource descriptor.

[0166] Optionally, when distinguishing between sparse resources and other resources (such as ordinary resources), in order to facilitate the address generation unit's block mapping processing, it is necessary to indicate to the address generation unit that the memory resource to be accessed is a sparse resource through a resource descriptor. Then, when the resource descriptor indicates that the memory resource to be accessed is a sparse resource, the address generation unit obtains the block mapping table address corresponding to the memory resource to be accessed from the resource descriptor.

[0167] Optionally, a resource bit can be added to the resource descriptor to indicate the resource type of the memory resource to be accessed. In one possible implementation, after receiving a memory access request, the address generation unit parses the resource descriptor and determines the resource type indicated by the resource bit. If the resource type indicated by the resource bit is a sparse resource, the address generation unit further determines the block mapping table address and the offset within the block corresponding to the memory resource to be accessed.

[0168] By using resource descriptors to indicate the resource type of the memory resource to be accessed, the address generation unit can more easily determine whether to perform block mapping for the memory resource to be accessed, thereby improving the accuracy of resource access.

[0169] In some embodiments, in order to implement sparse resource access based on block mapping, it is also necessary to create a corresponding resource descriptor for each sparse resource before resource access, so that during the resource access process, the virtual address corresponding to the sparse resource can be determined by combining the block mapping table address corresponding to the sparse resource in the resource descriptor.

[0170] Optionally, the shader core creates resource descriptors corresponding to sparse resources based on the association between sparse resources and block mapping tables.

[0171] Optionally, the association between sparse resources and the block map table can be specified by the shader core or input by the shader program to the shader core. Optionally, the association between sparse resources and the block map table can be established based on the first resource information of the sparse resources and the second resource information of the block map table.

[0172] Optionally, a sparse resource corresponds to at least one resource descriptor, and different resource descriptors in the at least one resource descriptor are used to indicate the association between the sparse resource and different block mapping tables. That is, a sparse resource can correspond to one or more block mapping tables.

[0173] In one possible implementation, when the shader core creates a resource descriptor corresponding to a sparse resource, it responds to first resource binding information in the shader program, which is used to indicate the association between the sparse resource and the block mapping table.

[0174] That is, after the sparse resource is created, the first resource binding information is input into the shader core when the resource descriptor is created. The shader core then responds to the first resource binding information and creates a resource descriptor for the sparse resource based on the association between the sparse resource indicated by the first resource binding information and the block mapping table.

[0175] In the above implementation of resource descriptors, the first resource binding information may include the association between sparse resources and at least two block mapping tables, thereby enabling the creation of at least two resource descriptors for sparse resources at one time and improving the creation efficiency of resource descriptors.

[0176] In another possible implementation, when the shader core creates a sparse resource, it responds to first resource binding information in the shader program, which indicates the association between the sparse resource and the block mapping table.

[0177] That is, when creating a sparse resource, the first resource binding information is directly input into the shader core, and the shader core responds to the first resource binding information and creates a resource descriptor for the sparse resource based on the association between the sparse resource indicated by the first resource binding information and the block mapping table.

[0178] In the above implementation of resource descriptors, block mapping table resources are allocated or associated when sparse resources are created, which can achieve strong binding between the block mapping table and the corresponding sparse resources.

[0179] In another possible implementation, after creating at least two sparse resources, the shader core responds to second resource binding information in the shader program, which indicates the association between the at least two sparse resources and the block mapping table.

[0180] That is, after multiple sparse resources are created, the second resource binding information is input into the shader core. The shader core responds to the second resource binding information and can create resource descriptors for multiple sparse resources at once, thus improving the efficiency of resource descriptor creation.

[0181] Regardless of the resource descriptor implementation method used, it is guaranteed that the resource descriptor corresponding to the sparse resource contains the block mapping table address for address calculation during sampling. Furthermore, by including the block mapping in the resource descriptor of the sparse resource, it is possible to avoid introducing additional resource descriptors during resource memory access.

[0182] In some embodiments, the shader core creates a block map based on the map creation instructions in the shader program; and updates the block map based on the map update instructions in the shader program.

[0183] In other words, the block map is visible to the application, and shader programs can create and update the block map through the shader kernel, thereby improving the flexibility of block map management. Optionally, the block map can adopt a buffer resource design, allowing the block map to be directly managed by the shader program and accessed for reading and writing within the GPU shader.

[0184] Optionally, the block mapping table includes block mapping elements, each corresponding one-to-one with a block in the sparse resource space. The block mapping elements indicate the block address information corresponding to the block, which includes at least one of the following: a virtual address within the GPU heap, a virtual address bit range, and a block offset. The block offset can be the offset of the block relative to the starting virtual address of the block in the block mapping table, and can be a negative number.

[0185] Optionally, creating a block mapping table may include determining the block mapping element corresponding to the block to which the sparse resource belongs, and saving the correspondence between the block sequence number and the block mapping element. Optionally, updating the block mapping table may include updating the block mapping element corresponding to the block to which the sparse resource belongs, and re-saving the correspondence between the block sequence number and the block mapping element.

[0186] Optionally, the block map table can be accessed and read / written directly by the shader as a separate resource. Furthermore, to maintain data consistency, it is generally not allowed to be read (accessing the sparse resource associated with the block map table) and written / modified simultaneously within the same shader program.

[0187] In some embodiments, to further optimize the resource access process, the resource access device may also include a caching and texture filtering unit.

[0188] Optionally, a resource memory access request includes at least one of a resource read request and a resource write request. Optionally, the shader core transmits a resource read request to the address generation unit, the resource read request including the resource coordinates and resource descriptor corresponding to the resource to be read. Optionally, the shader core transmits a resource write request to the address generation unit, the resource write request including the resource coordinates, resource descriptor, and resource data corresponding to the resource to be written.

[0189] Optionally, the address generation unit determines whether the memory resource to be accessed is a sparse resource. If the memory resource to be accessed is a sparse resource, the resource coordinates and resource descriptor are converted into block mapping table addresses and offsets within blocks, and the virtual address corresponding to the memory resource to be accessed is further determined through block mapping.

[0190] Optionally, the cache stores virtual addresses and sparse resources accessed within a first-time threshold. In one possible implementation, the address generation unit does not directly transmit the virtual address to the memory management unit, but first transmits the virtual address of the memory resource to be accessed to the cache, so that the cache can determine whether a hit occurs, and determine whether to transmit the virtual address to the memory management unit based on the hit status.

[0191] Optionally, the address generation unit transmits the virtual address of the memory resource to be accessed to the cache. Optionally, if the cache receives the virtual address of the memory resource to be accessed but misses a memory cache hit, it transmits the virtual address of the memory resource to the memory management unit.

[0192] In one possible implementation, when the memory access request is a read request, if the cache receives the virtual address of the resource to be accessed and a cache hit occurs, it means that the cache stores the sparse resource corresponding to the virtual address, and the sparse resource can be directly read from the cache and returned. In another possible implementation, if the cache receives the virtual address of the resource to be accessed and a cache miss occurs, it means that the cache does not store the sparse resource corresponding to the virtual address. In this case, it is necessary to further convert the virtual address to a physical address through the memory management unit and read the sparse resource from the physical storage space.

[0193] In another possible implementation, when the resource access request is a resource write request, the cache can directly transmit the virtual address to the memory management unit, which will then convert the virtual address into a physical address and write sparse resources into the storage space indicated by the physical address. After the data write is completed, the cache will return a data write completion signal to the shader core.

[0194] By first transmitting the virtual address to the cache and determining whether a cache hit occurs, and then considering whether to further transmit the virtual address to the memory management unit, it is possible to directly read sparse resources when the cache contains sparse resources corresponding to the virtual addresses, which can effectively improve the efficiency of resource access.

[0195] Optionally, to improve the quality of resource access, the resource access device may also include a texture filtering unit, so that after reading sparse resources, the sparse resources are first processed by the texture filtering unit, and then the processed sparse resources are returned to the shader core.

[0196] In one possible implementation, when the resource access request is a resource read request and the returned resource to be accessed is received, the texture filtering unit performs texture filtering processing on the resource to be accessed and transmits the processed resource to be accessed to the shader core.

[0197] Optionally, texture filtering can be texel interpolation calculation, which generates a smooth and continuous texture output by weighted averaging of the color values ​​of multiple neighboring texels. Optionally, texture filtering may also include other processing methods, which are not limited in this embodiment.

[0198] When a resource access request is a resource read request and the resource to be accessed has already been read, the resource quality can be improved by first performing texture filtering processing on the resource to be accessed through the texture filtering unit, and then returning the processed resource to be accessed to the shader core. This helps to improve the resource processing efficiency of the shader core.

[0199] In some embodiments, the resource memory access device in this application can be integrated into a chip. This application provides a chip that includes the resource memory access device as provided in any of the above embodiments.

[0200] Optionally, the chip can be a processor, such as an AI processor, a CPU processor, or other processors with vector operation requirements (especially multi-issue and vector branch operation requirements), which is not limited in this application embodiment.

[0201] Optionally, embodiments of this application also provide a graphics card, which includes the chip provided in the above embodiments.

[0202] Please refer to Figure 5 This diagram illustrates a structural block diagram of a computer device 500 provided in an exemplary embodiment of this application. The computer device 500 may be a terminal or a server.

[0203] Typically, computer device 500 includes a processor 501 and a memory 502.

[0204] Processor 501 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 501 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). Processor 501 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 501 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 501 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0205] In some embodiments, the processor 501 may integrate the resource memory access device provided in the above embodiments. When there is a resource memory access requirement, the resource memory access device can be used to perform the resource memory access task.

[0206] Memory 502 may include one or more computer-readable storage media, which may be tangible and non-transitory. Memory 502 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices.

[0207] In some embodiments, the computer device 500 may also optionally include a peripheral device interface 503 and at least one peripheral device.

[0208] Those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on the computer device 500, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0209] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0210] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A resource access device, characterized in that, The device includes a shader core, an address generation unit, and a memory management unit; The shader core is used to send a resource memory access request to the address generation unit, and the resource memory access request includes the resource address information corresponding to the resource to be accessed. The address generation unit is configured to, when the memory resource to be accessed is a sparse resource, determine the block mapping table address and the offset within the block corresponding to the memory resource to be accessed based on the resource address information, and determine the virtual address corresponding to the memory resource to be accessed based on the block mapping table address and the offset within the block, and transmit the virtual address to the memory management unit. The memory management unit is used to convert the received virtual address into a physical address and perform resource memory access operations based on the physical address; Wherein, the block mapping table corresponding to the block mapping table address is a data structure used to manage the virtual storage space where the sparse resource is located, and the offset within the block is used to indicate the offset of the virtual address of the memory resource to be accessed in the virtual storage space relative to the block virtual address of the block to which the memory resource to be accessed belongs.

2. The apparatus according to claim 1, characterized in that, The resource address information includes the resource coordinates and resource descriptor corresponding to the memory resource to be accessed. The resource coordinates are used to uniquely identify the memory resource to be accessed, and the resource descriptor is used to indicate the block mapping table information corresponding to the memory resource to be accessed. The address generation unit is used for: The block sequence number and intra-block offset corresponding to the memory resource to be accessed are determined based on the resource coordinates. Based on the block mapping table corresponding to the block mapping table address, determine the block virtual address of the block indicated by the block sequence number; Based on the block virtual address and the offset within the block, the virtual address corresponding to the memory resource to be accessed is determined.

3. The apparatus according to claim 2, characterized in that, The address generation unit is used for: The starting address of the block corresponding to the memory resource to be accessed is determined based on the resource coordinates. The starting address of the block is used to indicate the location information of the block to which the memory resource to be accessed belongs in the sparse resource space. Based on the starting address of the block and the block information of each block in the sparse resource space, the block sequence number and the offset within the block corresponding to the memory resource to be accessed are determined.

4. The apparatus according to claim 3, characterized in that, The address generation unit is used for: When all blocks in the sparse resource space have the same block size, the block sequence number and the offset within the block corresponding to the memory resource to be accessed are determined based on the result of the division operation between the block start address and the block size.

5. The apparatus according to claim 2, characterized in that, The address generation unit is used for: If the resource descriptor indicates that the memory resource to be accessed is a sparse resource, the block mapping table address corresponding to the memory resource to be accessed is obtained from the resource descriptor; The resource descriptor includes resource bits, which are used to indicate the resource type of the memory resource to be accessed.

6. The apparatus according to claim 2, characterized in that, The shader core is used for: Based on the association between sparse resources and block mapping tables, resource descriptors corresponding to the sparse resources are created; The sparse resource corresponds to at least one resource descriptor, and different resource descriptors in the at least one resource descriptor are used to indicate the association between the sparse resource and different block mapping tables.

7. The apparatus according to claim 6, characterized in that, The shader core is used for: When creating the resource descriptor corresponding to the sparse resource, the first resource binding information in the response shader program is used to indicate the association between the sparse resource and the block mapping table; or, When creating the sparse resource, respond to the first resource binding information in the shader procedure; or, After creating at least two sparse resources, a second resource binding information is provided in the shader procedure, which indicates the association between the at least two sparse resources and the block mapping table.

8. The apparatus according to claim 2, characterized in that, The shader core is used for: Based on the mapping table creation instructions in the shader program, a block mapping table is created. The block mapping table includes block mapping elements, and each block mapping element corresponds one-to-one with a block. The block mapping elements are used to indicate the block address information corresponding to the block. The block address information includes at least one of the following: virtual address within the GPU heap range, virtual address bit range, and block offset. The block mapping table is updated based on the mapping table update instructions in the shader program.

9. The apparatus according to any one of claims 1 to 8, characterized in that, The block mapping table is a general buffer resource, or a general buffer resource.

10. The apparatus according to any one of claims 1 to 9, characterized in that, The device further includes a cache for storing virtual addresses and sparse resources accessed within a first time threshold. The address generation unit is also used to transmit the virtual address of the memory resource to be accessed to the cache; The cache is used to transmit the virtual address of the memory resource to the memory management unit when a virtual address of the memory resource to be accessed is received but not accessed.

11. The apparatus according to any one of claims 1 to 10, characterized in that, The resource access request includes at least one of a resource read request and a resource write request; the apparatus further includes a texture filtering unit. The texture filtering unit is used for: If the resource access request is the resource read request and the returned resource to be accessed is received, texture filtering processing is performed on the resource to be accessed, and the processed resource to be accessed is transmitted to the shader core.

12. A resource access method, characterized in that, The method is used in a resource memory access device, which includes a shader core, an address generation unit, and a memory management unit. The method includes: The shader core sends a resource memory access request to the address generation unit, and the resource memory access request includes the resource address information corresponding to the resource to be accessed. When the memory resource to be accessed is a sparse resource, the address generation unit determines the block mapping table address and the offset within the block corresponding to the memory resource to be accessed based on the resource address information, and determines the virtual address corresponding to the memory resource to be accessed based on the block mapping table address and the offset within the block, and transmits the virtual address to the memory management unit. The memory management unit converts the received virtual address into a physical address and performs resource memory access operations based on the physical address; Wherein, the block mapping table corresponding to the block mapping table address is a data structure used to manage the virtual storage space where the sparse resource is located, and the offset within the block is used to indicate the offset of the virtual address of the memory resource to be accessed in the virtual storage space relative to the block virtual address of the block to which the memory resource to be accessed belongs.

13. A chip, characterized in that, The chip integrates a resource memory access device as described in any one of claims 1 to 11.

14. A computer device, characterized in that, The device includes a resource access device as described in any one of claims 1 to 11 or a chip as described in claim 13.

Images