Multi-protocol bus interface card of modularized transceiver interface

Abstract

The invention relates to a multi-protocol bus interface card of a modularized transceiver interface, and belongs to the technical field of vehicle-mounted electronics and communication equipment. Through the modular transceiver interface design, an efficient and flexible hardware architecture solution is provided for the multi-protocol bus interface card, and the market adaptability and cost effectiveness of products are remarkably improved.

Description

Technical Field

[0001] This invention belongs to the field of vehicle electronics and communication equipment technology, and specifically relates to a multi-protocol bus interface card with a modular transceiver interface. Background Technology

[0002] With the increasing demand for multi-protocol coexistence and rapid deployment in industrial automation and vehicle-mounted electronic and communication equipment, general-purpose multi-protocol interface cards have become a common requirement. However, existing interface cards often harden protocols into dedicated circuits or integrate them into multiple chips at the hardware level, resulting in the following main shortcomings: Fixed hardware configuration and poor adaptability: The protocol configuration of traditional interface cards is determined in the hardware design stage, and cannot be flexibly adjusted according to actual application needs, resulting in poor product adaptability.

[0003] Product line management is complex: different protocol combinations require the design of dedicated hardware, and the large number of product SKUs leads to high design costs, inventory management and maintenance costs.

[0004] Lack of standardized plug-in interfaces: There is a lack of unified electrical / mechanical standards between physical layer modules of different protocols, which makes it impossible to achieve interchangeability and modular reuse.

[0005] Insufficient on-site rapid response capability: When customer needs change, it is impossible to respond quickly, and it usually requires redesigning the entire hardware system. Summary of the Invention

[0006] (a) Technical problems to be solved The technical problems to be solved by this invention are: 1. How to support multiple different physical layer protocols and enable rapid on-site system reconfiguration without modifying the carrier board (solving the problems of modular plug-in and intelligent identification); 2. How to standardize the transceiver module interface to achieve interchangeability between different protocol modules (solving the problems of defining a unified electrical / mechanical interface and supplementing necessary error prevention / protection design); 3. How to ensure the automatic identification, driver loading and configuration are safe and reliable after module plugging and unplugging (solving the problems of EEPROM description specification and FPGA / I²C / MFD driver chain).

[0007] (II) Technical Solution To address the aforementioned technical problems, this invention provides a modular transceiver interface card for a multi-protocol bus interface, comprising a general-purpose carrier board module, a pluggable transceiver module, an intelligent identification and configuration module, and a protocol adaptation and control module. The general-purpose carrier board module is used to provide the infrastructure for interface cards, including pluggable transceiver modules, PCIe interfaces, FPGA chips and I²C buses. It provides a unified physical and electrical interface for pluggable transceiver modules and implements hardware functions such as domain clock management, domain power management and signal integrity protection through FPGA chips. Pluggable transceiver modules are used to provide independent physical layer modules designed for different protocols. They are plugged into a general-purpose carrier board module through a standard interface to realize the physical layer functions of specific protocols, as well as level conversion, isolation, and termination resistor functions. The intelligent identification and configuration module is used to read information from the EEPROM in the pluggable transceiver module through the I²C controller inside the FPGA chip provided by the general carrier board module, identify the module type and configuration parameters, and complete device instantiation and resource configuration through the MFD driver of the Linux host. The protocol adaptation and control module is used to implement protocol-specific software control functions for pluggable transceiver modules through the register mapping and sysfs interface of the FPGA chip provided by the general carrier board module. These functions include UART mode switching, CAN terminating resistor control, and FlexRay configuration, providing a unified control interface for different protocols.

[0008] (III) Beneficial Effects This invention proposes a multi-protocol bus interface card architecture for modular transceiver interfaces, consisting of a carrier board, a pluggable transceiver module, and intelligent identification and configuration. This architecture improves reusability and response speed while reducing cost and complexity, offering the following advantages: 1. Strict separation of carrier board and transceiver module + unified physical / electrical interface specifications A standardized pluggable interface (20-pin) is proposed to support power, differential data, clock, I²C identification and several GPIO signals, enabling hot-swappable interchangeability of physical layer modules of different protocols; Technical benefits: Enables hardware reuse, reduces the time and cost of supporting new protocols, and reduces the number of SKUs.

[0009] 2. Automatic identification and managed configuration link for module-level EEPROM + FPGA drivers Each module carries an EEPROM. The carrier board reads the identification information through the I²C controller on the FPGA, and the Linux MFD driver automatically creates the I²C adapter and instantiates the device, thereby automatically loading the corresponding driver and FPGA bit file (or firmware).

[0010] Technical benefits: It can be recognized and configured simply by inserting, supports rapid on-site reconfiguration, and reduces manual configuration errors.

[0011] 3. FPGA-based central control and register mapping (PCIe host access compatible) The FPGA provides centralized management of slot GPIOs, clock, power control, I²C bridging, and transceiver data paths, and maps necessary registers to the host via PCIe. Partial FPGA reconfiguration is supported to load different protocol logic (optional).

[0012] Technical benefits: Reduces host driver complexity and improves system scalability and performance isolation.

[0013] Domain clock and power supply and software-controllable terminal / level management 4. Provide each transceiver module with an independent programmable clock domain and power enable control, and control the on / off of CAN bus terminating resistors, RS485 bias, etc. via software.

[0014] Technical benefits: Improves signal integrity management and system compatibility, facilitating correct operation in different topologies / expansion scenarios.

[0015] 5. Modular hardware and software co-working interface abstraction (sysfs / MFD driver interface) Under Linux, register I²C adapters, character / network / network devices via MFD drivers, and provide a sysfs interface for users to query and switch modes (such as UART mode, CAN terminal).

[0016] Technical benefits: User-friendly operation and easy integration with existing software stacks. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall architecture of the modular transceiver interface card of the present invention; Figure 2 Diagram of the intelligent recognition system's connection architecture; Figure 3 To automatically identify flowcharts; Figure 4 This is a GPIO-based system architecture diagram; Figure 5 This is a diagram showing the composition and association of the interface card module. Detailed Implementation

[0018] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0019] (I) Overall Architecture This invention provides a modular transceiver interface card for a multi-protocol bus, which consists of four core functional modules: a general-purpose carrier board module, a pluggable transceiver module, an intelligent identification and configuration module, and a protocol adaptation and control module.

[0020] The general-purpose carrier board module is used to provide the infrastructure for interface cards, including pluggable transceiver modules, PCIe interfaces, FPGA chips, clock distribution, power management and I²C bus infrastructure, etc. It provides a unified physical and electrical interface for pluggable transceiver modules and implements hardware functions such as domain clock management, domain power management and signal integrity protection through FPGA chips. Pluggable transceiver modules are used to provide independent physical layer modules designed for different protocols. They are plugged into a general-purpose carrier board module through a standard interface to realize the physical layer functions of specific protocols and necessary functions such as level conversion, isolation and termination resistors. The intelligent identification and configuration module is used to read information from the EEPROM in the pluggable transceiver module through the I²C controller inside the FPGA chip provided by the general carrier board module, identify the module type and configuration parameters, and complete device instantiation and resource configuration through the MFD driver of the Linux host. The protocol adaptation and control module is used to implement protocol-specific software control functions for the pluggable transceiver module through the register mapping and sysfs interface of the FPGA chip provided by the general carrier board module. These functions include UART mode switching, CAN terminating resistor control, FlexRay configuration, etc., providing a unified control interface for different protocols. These four modules work together to achieve strict separation between the general-purpose carrier board module and the transceiver module. They also achieve interchangeability between different protocol modules through a unified interface standard, supporting rapid on-site system reconfiguration without modifying the carrier board.

[0021] (II) Key Technical Details 1. Universal Carrier Board Module The universal carrier board module provides the infrastructure for multi-protocol bus interface cards, including components such as PCIe interfaces, FPGA chips, power management, clock distribution, transceiver module slots, and I²C buses, providing a unified physical and electrical interface for pluggable transceiver modules. This universal carrier board module includes a standardized interface submodule, an FPGA central control submodule, and a signal integrity protection submodule.

[0022] The standardized interface submodule defines a unified 20-pin standard interface, ensuring physical interchangeability between pluggable transceiver modules of different protocols. The electrical interface specifications of this standardized interface submodule include: • Pins 1-2 provide a 3.3V power supply with a maximum current of 1A and overcurrent protection; •Pin 3-4 provides a 5V power supply with a maximum current of 1A, used to drive special transceiver chips; • Pins 5-6 provide both digital and analog grounds; • Pins 7-8 provide LVDS differential data signals (DATA_P / DATA_N), supporting a transmission rate of up to 500Mbps; • Pins 9-10 provide LVDS differential clock signals (CLK_P / CLK_N) with a frequency range of 25-200MHz; • Pins 11-12 provide an I²C bus interface (SDA / SCL) for module identification and configuration, supporting standard 100kHz and fast 400kHz modes; • Pins 13-20 provide 8 custom GPIO signals at a 3.3V level for protocol-specific control functions.

[0023] This standardized interface submodule adopts an LVDS differential signal design to meet the data transmission rate requirements of extended multi-channel low-speed buses. It also provides dual power supplies of 3.3V and 5V to meet the power requirements of different pluggable transceiver modules. Eight GPIOs are reserved for protocol-specific control functions, such as UART mode switching and CAN terminating resistor control.

[0024] The FPGA central control submodule centrally manages the slot GPIO, clock, power control, I²C bridging, and transceiver data paths through the FPGA chip, and maps necessary registers to the Linux host via the PCIe interface. This FPGA central control submodule implements the I²C master controller logic internally within the FPGA chip, responsible for generating I²C clock and data signals, supporting standard and fast modes. It maps the I²C controller registers to the PCIe configuration space, enabling Linux host access. BAR0 is used for control registers, and BAR1 is used for the DMA data channel, supporting MSI interrupt reporting for faults. This FPGA central control submodule also implements domain-specific clock management, generating independent clock signals for each slot through the FPGA chip's internal clock management unit, supporting programmable frequency output from 25MHz to 200MHz. These signals are provided to pluggable transceiver modules via Pins 9-10 (CLK_P / CLK_N) of the standard interface, allowing different pluggable transceiver modules to operate at different clock frequencies, avoiding clock domain conflicts. This FPGA central control submodule also implements domain-specific power management, independently controlling the power enable of each slot through the FPGA chip's internal power management logic. It provides dual 3.3V and 5V power outputs, each with a maximum output of 1A. It supports software-controlled power switching and software reset of pluggable transceiver modules, allowing for safe power shutdown when a pluggable transceiver module needs to be removed. The FPGA central control submodule also implements GPIO-to-internal register mapping logic, enabling the Linux host to access the FPGA chip's internal register space via the PCIe MFD driver. It also supports partial FPGA chip reconfiguration to load different protocol logic (optional). This centralized management approach reduces host driver complexity and improves system scalability and performance isolation.

[0025] The signal integrity protection submodule ensures reliable signal transmission through differential signal design, signal isolation, and EMI suppression. All high-speed signals in this submodule utilize LVDS differential transmission, transmitting data via Pins 7-8 (DATA_P / DATA_N) of the standard interface to meet the data transmission rate requirements of extended multiple low-speed buses. Electrical isolation is provided between the pluggable transceiver modules to prevent mutual interference. The PCB design employs a four-layer structure with complete ground and power planes, effectively suppressing EMI interference. This signal integrity protection mechanism ensures the stability and reliability of the system under various operating environments.

[0026] 2. Pluggable transceiver module Pluggable transceiver modules are used to implement the physical layer functions of specific protocols. Independent physical layer modules are designed for different protocols and are plugged into a general-purpose carrier board module through a standard interface to perform protocol-specific functions such as level conversion, isolation, and terminating resistors. This pluggable transceiver module includes various types of transceiver modules such as high-speed serial transceiver submodules, CAN FD transceiver submodules, FlexRay transceiver submodules, and SPI / I2C bus driver circuit submodules.

[0027] The high-speed serial transceiver submodule supports multiple serial communication standards, including RS232, RS422, and RS485. It can be configured with 2 or 4 channels, supports automatic baud rate detection and software-configurable baud rate range, with a maximum baud rate of 10Mbps. This high-speed serial transceiver submodule supports software-switchable interface modes between RS232, RS422, and RS485. Data bits are configurable from 5 to 8 bits, and stop bits are configurable from 1 / 1.5 / 2 bits. Parity checks include no parity, odd parity, and even parity. The buffer depth is 512 bytes for both receive and transmit FIFOs. Mode switching is achieved through internal register mapping within the FPGA chip. The Linux host accesses specific register addresses via the PCIe bus to switch between RS232, RS422, and RS485 modes. Mode switching between RS232 and RS422 is implemented via the sysfs interface, while automatic RS485 transmit / receive switching is implemented through driver encapsulation.

[0028] The CAN FD transceiver submodule supports both Classical CAN and CAN FD modes, configurable with 2 or 4 channels, and integrates a 120Ω terminating resistor and a software-controllable switch. This CAN FD transceiver submodule supports ISO 11898-1 (CAN 2.0A / 2.0B) and ISO 11898-2 (CAN FD) protocols, with a nominal bit rate of 5kbps to 1Mbps and a data stage bit rate of 500kbps to 8Mbps (CAN FD mode). It has a bus load capacity of ≥112 CAN nodes, with each channel featuring an independent 120Ω resistor that is software-controllable. Error detection includes CRC check, frame check, acknowledgment check, and bit monitoring. The terminating resistor switch control signal is connected to the FPGA chip via a custom GPIO. The FPGA chip maps these control signals to internal registers, and the Linux host accesses the FPGA chip's registers via the PCIe bus to achieve independent control of the terminating resistor for each CAN channel, supporting both global and single-channel control.

[0029] The FlexRay transceiver submodule supports the FlexRay 2.1A protocol standard, employs a dual-channel redundant design to meet automotive functional safety requirements, and integrates a star coupler interface. This FlexRay transceiver submodule uses the FlexRay 2.1A protocol standard, can be configured with 2 or 4 channels, has a transmission rate of 10Mbps (fixed), supports bus, star, and hybrid network topologies, has a built-in clock synchronization unit, and provides error detection methods including frame header CRC, frame CRC, and BSS (Bus Guardian).

[0030] The SPI / I2C bus driver circuit submodule provides high-speed SPI and standard I2C interface expansion, supports multi-master mode (I2C), and integrates level conversion functionality. This SPI / I2C bus driver circuit submodule has a maximum SPI rate of 25MHz and supports MODE0-3. 2 The C-band supports standard 100kHz, fast 400kHz, and high-speed 3.4MHz speeds, with 4 SPI channels plus 4 I / O channels. 2 C, voltage level is configurable to 1.8V / 3.3V / 5V, I 2 The C bus load supports up to 16 slave devices.

[0031] 3. Intelligent Recognition and Configuration Module The intelligent identification and configuration module automatically identifies the type and configuration parameters of the pluggable transceiver module when the interface card starts up or when the pluggable transceiver module is plugged in or removed, and automatically configures the corresponding protocol driver and FPGA logic based on the identification results. This intelligent identification and configuration module includes an EEPROM identification submodule and an automatic scanning and configuration submodule.

[0032] The EEPROM identification submodule automatically identifies modules by storing module information in the EEPROM integrated into each pluggable transceiver module. Each pluggable transceiver module's EEPROM is connected to its I²C bus via Pins 11-12 (SDA / SCL) of the standard interface. The EEPROM's data structure includes basic identification information (magic identifier, module type ID, module version, vendor ID, product ID), functional parameters (number of channels, maximum transmission rate, supported feature bitmap), extended information (custom configuration parameters, GPIO function definitions, clock requirements), and data integrity information (checksum, CRC checksum). This EEPROM identification submodule uses a multi-level connection architecture for automatic module identification. The EEPROM connects to the I²C controller inside the FPGA chip via the I²C bus. The FPGA chip connects to the MFD driver on the Linux host via the PCIe bus. The MFD driver registers the I²C adapter and creates the I²C bus. The I²C adapter (core layer) scans the I²C bus and instantiates the EEPROM's device driver. The EEPROM's device driver reads the module identification information.

[0033] The automatic scanning and configuration submodule automatically identifies all pluggable transceiver modules during interface card startup, following a process of initialization, scanning, verification, parsing, configuration, and registration. During initialization, the MFD driver initializes the PCIe devices and configures the I²C controller within the FPGA chip. During scanning, it sequentially scans the four transceiver slots (I²C addresses 0x50-0x53) and attempts to read the EEPROM. During verification, it verifies the magic number and checksum of the read data to confirm the module's validity. During parsing, it parses the module type, number of channels, and functional parameters, and constructs a system configuration table. During configuration, it loads the corresponding FPGA bit file and the Linux host's MFD driver module based on the identification results. During registration, it registers the corresponding devices (CAN devices, serial devices, etc.) with the Linux host. This automated identification and configuration process enables plug-and-play identification and configuration, supports rapid on-site reconfiguration, and reduces manual configuration errors.

[0034] 4. Protocol Adaptation and Control Module The protocol adaptation and control module is used to implement protocol-specific software control functions through the FPGA chip's register mapping and sysfs interface. It provides a unified control interface for different protocols and supports protocol-specific control requirements such as UART mode switching, CAN terminating resistor control, and FlexRay configuration. This module includes a UART mode control submodule, a CAN terminating resistor control submodule, and a protocol configuration management submodule.

[0035] The UART mode control submodule is used to software switch the UART operating mode of the pluggable transceiver module through register mapping within the FPGA chip. This submodule maps UART mode switching control signals to registers within the FPGA chip. The Linux host accesses specific register addresses via the PCIe bus to switch between RS232, RS422, and RS485 modes. RS232 and RS422 switching is implemented through the sysfs interface, while automatic RS485 transmit / receive switching is implemented through driver encapsulation. This UART mode control submodule supports independent configuration of the operating mode for each UART channel, providing a user-friendly configuration method through the sysfs interface. For example, the command `echo rs422> / sys / bus / pci / devices / 0000:01:00.0 / uart_mode / uart1_mode` can set UART1 to RS422 mode.

[0036] The CAN terminating resistor control submodule is used to implement software control of the CAN channel terminating resistors of a pluggable transceiver module through register mapping within the FPGA chip. This submodule connects the terminating resistor switch control signals to the FPGA chip via a custom GPIO. The FPGA chip maps these control signals to internal registers, and the Linux host accesses these registers via the PCIe bus to achieve independent control of the 120Ω terminating resistor for each CAN channel. This submodule supports both global and single-channel control modes, providing a unified control interface through the sysfs interface. For example, the command `echo 0x3ff> / sys / class / can_term / can_term / termination` globally enables the terminating resistors for all CAN channels, while the command `echo 1> / sys / class / can_term / can_term / can0_term` individually controls the terminating resistor for CAN0 channel.

[0037] The protocol configuration management submodule provides a unified configuration management interface for different protocols, enabling the querying and configuration of protocol parameters for pluggable transceiver modules via the sysfs interface. This submodule maintains protocol configuration status, supports real-time querying and dynamic configuration, and provides a unified interface abstraction for applications. It also supports specific configuration requirements for protocols such as FlexRay, shielding the configuration differences between protocols through a unified interface abstraction layer, allowing applications to easily manage and configure parameters for different protocols. This protocol adaptation and control mechanism achieves unified management of different protocols, improving system usability and maintainability.

[0038] (III) Typical Configuration Examples 5.1 Industrial Gateway Configuration • Slot 0: 4-channel high-speed UART module (for connecting special equipment) • Slot 1: 2-channel CAN FD module (connects to controller / sensor / actuator network) • Slot 2: 2-channel FlexRay module (connects to security system) • Slot 3: Empty (Reserved for future expansion) 5.2 Vehicle Testing Platform Configuration • Slot 0: 4-channel CAN FD module (main test bus) • Slot 1: 4-channel CAN FD module (main test bus) • Slot 2: 2-channel FlexRay module (FlexRay network test) • Slot 3: 4-channel high-speed UART module (other interface testing) 5.3 Data Acquisition System Configuration • Slot 0: 4-channel high-speed UART module (serial data acquisition) • Slot 1: 4-channel high-speed UART module (serial data acquisition) • Slot 2: 4-channel SPI module (high-speed sensor interface) • Slot 3: 4-channel I2C module (slow sensor interface) Compared with the prior art, the present invention has the following beneficial effects: 1. High hardware reusability: The universal carrier board can support a variety of transceiver module combinations, which greatly reduces hardware development costs and inventory management complexity.

[0039] 2. High configuration flexibility: Users can quickly adjust the protocol configuration by replacing the transceiver module according to specific application requirements.

[0040] 3. High degree of standardization: The unified transceiver interface standard ensures the interchangeability and compatibility of different module models.

[0041] 4. Rapid market response: Targeted products can be launched quickly by simply combining modules without redesigning the hardware.

[0042] 5. Significant cost optimization: Compared with the traditional solution of multiple dedicated hardware sets, it can save 60-80% of hardware development and inventory costs.

[0043] 6. Strong scalability: The standardized interface reserves ample room for future expansion to support new protocols.

[0044] Example 1: 4-channel UART + 2-channel CAN FD combination This embodiment describes a typical industrial communication gateway application configuration.

[0045] Hardware configuration: • Transceiver slot 0: Insert a 4-channel UART module • Transceiver slot 1: Insert a 2-channel CAN FD module • Transceiver slots 2-3: Unused System identification process: # System startup identification log [2.135] xbus_card: Transceiver Module detected: slot=0, type=0x1002, channels=4[2.142]xbus_card: Transceiver Module detected: slot=1, type=0x1001, channels=2[2.156] xbus_card: Configuration: 4xUART + 2xCANFD[2.163]xbus_card: Hardware validation passed Functional verification and configuration examples: UART mode configuration The system provides a sysfs interface for switching UART operating modes. # Set UART1 to RS422 mode echo rs422> / sys / bus / pci / devices / 0000:01:00.0 / uart_mode / uart1_mode# Check the current UART0 mode cat / sys / bus / pci / devices / 0000:01:00.0 / uart_mode / uart0_mode# Sets UART2 to RS485 transmit mode. echo rs485_tx> / sys / bus / pci / devices / 0000:01:00.0 / uart_mode / uart2_mode CAN Termination Resistor Control Supports global and single-channel terminating resistor control. # Enable all CAN channel terminating resistors globally echo 0x3ff> / sys / class / can_term / can_term / termination# Enable CAN0 and CAN1 terminating resistors only echo 0x3> / sys / class / can_term / can_term / termination# Individual control of CAN0 terminating resistor: echo 1> / sys / class / can_term / can_term / can0_ # Check CAN2 terminating resistor status: cat / sys / class / can_term / can_term / can2_term Example 2: Rapid Product Reconfiguration This example demonstrates the ease of changing product configurations.

[0046] Original configuration: 4-channel UART + 2-channel CAN FD New configuration requirement: 8-channel CAN FD + 2-channel FlexRay Reconfiguration process: 1. Power off and remove the UART module. 2. Insert two 4-channel CAN FD modules and one 2-channel FlexRay module. 3. Power on, the system will automatically recognize the new configuration. 4. It works normally without any software modifications. Configuration time comparison: • Traditional solution: Requires hardware redesign, taking 3-6 months. • Solution of this invention: Only module replacement is required, time <10 minutes This invention provides an efficient and flexible hardware architecture solution for multi-protocol bus interface cards through a modular transceiver interface design, significantly improving the product's market adaptability and cost-effectiveness.

[0047] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A multi-protocol bus interface card with a modular transceiver interface, characterized in that, It includes a general-purpose carrier board module, a pluggable transceiver module, an intelligent identification and configuration module, and a protocol adaptation and control module; The general-purpose carrier board module is used to provide the infrastructure for interface cards, including pluggable transceiver modules, PCIe interfaces, FPGA chips and I²C buses. It provides a unified physical and electrical interface for pluggable transceiver modules and implements hardware functions such as domain clock management, domain power management and signal integrity protection through FPGA chips. Pluggable transceiver modules are used to provide independent physical layer modules designed for different protocols. They are plugged into a general-purpose carrier board module through a standard interface to realize the physical layer functions of specific protocols, as well as level conversion, isolation, and termination resistor functions. The intelligent identification and configuration module is used to read information from the EEPROM in the pluggable transceiver module through the I²C controller inside the FPGA chip provided by the general carrier board module, identify the module type and configuration parameters, and complete device instantiation and resource configuration through the MFD driver of the Linux host. The protocol adaptation and control module is used to implement protocol-specific software control functions for pluggable transceiver modules through the register mapping and sysfs interface of the FPGA chip provided by the general carrier board module. These functions include UART mode switching, CAN terminating resistor control, and FlexRay configuration, providing a unified control interface for different protocols.

2. The method as described in claim 1, characterized in that, This universal carrier board module includes a standardized interface submodule, an FPGA central control submodule, and a signal integrity protection submodule; • The standardized interface submodule defines a unified 20-pin standard interface, ensuring the physical interchangeability of pluggable transceiver modules with different protocols. This standardized interface submodule adopts LVDS differential signal design and provides dual power supplies of 3.3V and 5V to meet the power requirements of different pluggable transceiver modules. It also reserves 8 GPIOs for protocol-specific control functions. This FPGA central control submodule implements the I²C master controller logic within the FPGA chip, responsible for generating I²C clock and data signals. It maps the I²C controller registers to the PCIe configuration space, enabling Linux hosts to access them. BAR0 is used for the control registers, and BAR1 is used for the DMA data channel, supporting MSI interrupt reporting of faults. This FPGA central control submodule also implements domain-specific clock management, generating independent clock signals for each slot through the FPGA chip's internal clock management unit. It supports programmable frequency output from 25MHz to 200MHz via a standard interface pin. Sections 9-10 are provided for the pluggable transceiver modules, enabling different pluggable transceiver modules to operate at different clock frequencies. This FPGA central control submodule also implements domain-specific power management, independently controlling the power enable of each slot through the power management logic inside the FPGA chip. It provides dual power outputs of 3.3V and 5V, with a maximum output of 1A per channel. It supports software-controlled power switching and software reset of the pluggable transceiver modules, and shuts down the power when a pluggable transceiver module needs to be removed. This FPGA central control submodule also implements GPIO to internal register mapping logic, allowing the Linux host to access the register space inside the FPGA chip through the PCIe MFD driver, and supports partial reconfiguration of the FPGA chip to load different protocol logic. The signal integrity protection submodule ensures reliable signal transmission through differential signal design, signal isolation, and EMI suppression. All high-speed signals in this submodule utilize LVDS differential transmission, transmitting data via Pins 7-8 of the standard interface.

3. The method as described in claim 1, characterized in that, The pluggable transceiver module includes a high-speed serial transceiver sub-module, a CAN FD transceiver sub-module, a FlexRay transceiver sub-module, and an SPI / I 2 C bus drive circuit sub-module, etc. The high-speed serial transceiver submodule supports multiple serial communication standards, including RS232, RS422, and RS485. It can be configured with 2 or 4 channels, supports automatic baud rate detection and software-configurable baud rate range, with a maximum baud rate of 10Mbps. This high-speed serial transceiver submodule supports software-switchable interface modes between RS232, RS422, and RS485. Data bits are configurable from 5 to 8 bits, and stop bits are configurable from 1, 1.5, or 2 bits. Parity checks include no parity, odd parity, and even parity. The buffer depth is 512 bytes for both receive and transmit FIFOs. Mode switching is achieved through register mapping within the FPGA chip. The Linux host accesses specific register addresses via the PCIe bus to switch between RS232, RS422, and RS485 modes. The CAN FD transceiver submodule supports both Classical CAN and CAN FD modes, configurable with 2 or 4 channels, and integrates a 120Ω terminating resistor and a software-controllable switch. This CAN FD transceiver submodule supports ISO11898-1 and ISO 11898-2 protocols, with a nominal bit rate of 5kbps to 1Mbps, a data stage bit rate of 500kbps to 8Mbps, and a bus load capacity of ≥112 CAN nodes. Each channel has an independent 120Ω resistor that is software-controllable. Error detection includes CRC check, frame check, acknowledgment check, and bit monitoring. The terminating resistor switch control signal is connected to the FPGA chip via a custom GPIO. The FPGA chip maps these control signals to internal registers. The Linux host accesses the FPGA chip's registers via the PCIe bus to achieve independent control of the terminating resistor for each CAN channel, supporting both global and single-channel control. The FlexRay transceiver submodule supports the FlexRay 2.1A protocol standard, adopts a dual-channel redundant design, and integrates a star coupler interface. This FlexRay transceiver submodule uses the FlexRay 2.1A protocol standard, can be configured with 2 or 4 channels, has a transmission rate of 10Mbps, supports bus, star, and hybrid network topologies, has a built-in clock synchronization unit, and provides error detection methods including frame header CRC, frame CRC, and BSS. SPI / I 2 C bus driving circuit sub-module provides SPI and standard I 2 C interface extension, supports multi-host mode, integrates level conversion function; the SPI rate of the SPI / I2C bus driving circuit sub-module is up to 25MHz, supports MODE 0-3, I 2 C rate supports standard 100kHz, fast 400kHz, high speed 3.4MHz, and the channel number is 4-way SPI plus 4-way I 2 C, I 2 C bus load supports up to 16 slave devices.

4. The method as described in claim 3, characterized in that, Mode switching between RS232 and RS422 is implemented by the sysfs interface, while automatic switching between RS485 transmit and receive is implemented by driver encapsulation.

5. The method as described in claim 1, characterized in that, The intelligent identification and configuration module is used to automatically identify the type and configuration parameters of the pluggable transceiver module when the interface card starts up or when the pluggable transceiver module is plugged in or removed, and automatically configure the corresponding protocol driver and FPGA logic based on the identification results.

6. The method as described in claim 1, characterized in that, The intelligent identification and configuration module includes an EEPROM identification submodule and an automatic scanning and configuration submodule; The EEPROM identification submodule stores module information in the EEPROM integrated into each pluggable transceiver module, enabling automatic identification of the pluggable transceiver modules. The EEPROM of each pluggable transceiver module is connected to the I²C bus of the pluggable transceiver module via Pins 11-12 of the standard interface. This EEPROM identification submodule achieves automatic identification of the pluggable transceiver modules through a multi-level connection architecture. Specifically, the EEPROM is connected to the I²C controller inside the FPGA chip via the I²C bus. The FPGA chip is connected to the MFD driver of the Linux host via the PCIe bus. The MFD driver registers the I²C adapter and creates the I²C bus. The I²C adapter scans the I²C bus and instantiates the device driver for the EEPROM. The device driver for the EEPROM reads the module identification information. The automatic scanning and configuration submodule automatically identifies all pluggable transceiver modules during interface card startup, following the initialization, scanning, verification, parsing, configuration, and registration process. During initialization, the MFD driver initializes the PCIe device and configures the I²C controller inside the FPGA chip. During scanning, it sequentially scans the four transceiver slots (I²C addresses 0x50-0x53) and attempts to read the EEPROM. During verification, it verifies the magic number and checksum of the read data to confirm the module's validity. During parsing, it parses the module type, number of channels, and functional parameters, and constructs the system configuration table. During configuration, it loads the corresponding FPGA bit file and the Linux host's MFD driver based on the identification results. Finally, during registration, it registers the corresponding devices with the Linux host.

7. The method as described in claim 6, characterized in that, The data structure of an EEPROM includes basic identification information, functional parameters, extended information, and data integrity information.

8. The method as described in claim 1, characterized in that, The protocol adaptation and control module includes a UART mode control submodule, a CAN terminating resistor control submodule, and a protocol configuration management submodule. The UART mode control submodule is used to switch the UART operating mode of the pluggable transceiver module in software through register mapping inside the FPGA chip. This UART mode control submodule maps the UART mode switching control signal to the register inside the FPGA chip. The Linux host accesses specific register addresses through the PCIe bus to switch between RS232, RS422 and RS485 modes. The CAN terminating resistor control submodule is used to implement software control of the CAN channel terminating resistors of a pluggable transceiver module through register mapping within the FPGA chip. This submodule connects the terminating resistor switch control signals to the FPGA chip via a custom GPIO. The FPGA chip maps these control signals to internal registers, and the Linux host accesses these registers via the PCIe bus to achieve independent control of the 120Ω terminating resistor for each CAN channel. This CAN terminating resistor control submodule supports both global and single-channel control modes, providing a unified control interface through the sysfs interface. The protocol configuration management submodule provides a unified configuration management interface for different protocols, enabling the querying and configuration of protocol parameters for pluggable transceiver modules through the sysfs interface. This submodule maintains protocol configuration status, supports real-time querying and dynamic configuration, and provides a unified interface abstraction for applications. It also supports specific configuration requirements for protocols such as FlexRay, shielding the configuration differences between different protocols through a unified interface abstraction layer, allowing applications to manage and configure parameters for different protocols.

9. The method as described in claim 8, characterized in that, This UART mode control submodule supports independent configuration of the working mode for each UART channel and provides a user-friendly configuration method through the sysfs interface.

10. A system for implementing the method as described in any one of claims 1 to 9.

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