Semiconductor device, operation method and system thereof, and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, an operation method and system thereof and electronic equipment, and the semiconductor device comprises a first semiconductor structure which comprises a storage sensing circuit; the second semiconductor structure comprises a storage array and a source electrode layer coupled with the source electrode end of the storage array, and the source electrode layer is located between the storage array and the first semiconductor structure; the third semiconductor structure comprises a storage control circuit; the second semiconductor structure is in bonding connection with the first semiconductor structure and the third semiconductor structure, and the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure; the storage sensing circuit is coupled with the source electrode layer through the bonding layer.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor device and its operating methods, systems, and electronic devices. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device and its operating method, system and electronic device.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, comprising: a first semiconductor structure including a memory sensing circuit; a second semiconductor structure including a memory array and a source layer coupled to a source terminal of the memory array, the source layer being located between the memory array and the first semiconductor structure; and a third semiconductor structure including a memory control circuit; the second semiconductor structure being bonded to the first semiconductor structure and the third semiconductor structure respectively, the second semiconductor structure being located between the first semiconductor structure and the third semiconductor structure; and the memory sensing circuit being coupled to the source layer through a bonding layer.

[0005] In some implementations, the storage array is configured to store weight data; the storage array includes multiple storage strings, each storage string including multiple storage cells connected in series between a bit line and a source layer; the source layer includes multiple first sub-source layers spaced along the bit line direction, and the M storage strings containing M storage cells storing the same weight data are respectively coupled to different first sub-source layers; M is an integer greater than 1.

[0006] In some implementations, M storage units storing the same weight data are coupled to the same bit line.

[0007] In some implementations, the memory control circuit is configured to write N weight data into M*N memory cells; N is an integer greater than 0; and to apply a corresponding input voltage to the bit line coupled to the memory cell where the weight data is written.

[0008] In some implementations, the memory sensing circuit includes multiple sensing circuits configured to acquire the output current signals of M first sub-source layers to which M memory cells storing the same weight data are respectively coupled, and to perform analog-to-digital conversion processing on the voltage signals corresponding to the acquired current signals to obtain digital information.

[0009] In some embodiments, the storage sensing circuit further includes a shift circuit and an arithmetic circuit; the shift circuit is configured to receive digital information and perform shift processing on at least a portion of the digital information according to a preset rule; the arithmetic circuit is configured to sum the shifted results corresponding to the multiple digital information to obtain an arithmetic result.

[0010] In some embodiments, the second semiconductor structure further includes a first connection structure that runs through the memory array; one end of the first connection structure is connected to the memory sensing circuit, and the other end is connected to the memory control circuit; the first connection structure is used to realize information transmission between the memory sensing circuit and the memory control circuit.

[0011] In some implementations, the source layer includes multiple second sub-source layers spaced apart along the word line direction, and the M memory strings containing the M memory cells storing the same weight data are all coupled to the same second sub-source layer.

[0012] In some implementations, a second sub-source layer is coupled to several memory strings, the number of bit lines coupled to the memory strings being related to the amount of input data; the input voltage applied to the bit lines is related to the data value of the input data.

[0013] In some embodiments, the second semiconductor structure further includes a first bonding layer and a second bonding layer, the memory array is bonded to the third semiconductor structure through the first bonding layer, and the memory array is bonded to the first semiconductor structure through the second bonding layer.

[0014] In some embodiments, the first bonding layer includes a first bonding contact and a first dielectric layer that isolates the first bonding contact; the third semiconductor structure includes a third bonding layer, which includes a third bonding contact and a third dielectric layer that isolates the third bonding contact; the first bonding contact and the third bonding contact are bonded, and the first dielectric layer and the third dielectric layer are bonded.

[0015] In some embodiments, the second bonding layer includes a second bonding contact and a second dielectric layer that isolates the second bonding contact; the first semiconductor structure includes a fourth bonding layer, which includes a fourth bonding contact and a fourth dielectric layer that isolates the fourth bonding contact; the second bonding contact and the fourth bonding contact are bonded, and the second dielectric layer and the fourth dielectric layer are bonded.

[0016] In some implementations, the memory sensing circuit is coupled to the source layer through the fourth bonding layer and the second bonding layer to acquire the output current signal of the source layer.

[0017] In some embodiments, the first semiconductor structure further includes a data processing circuit configured to shift at least a portion of the digital information according to a preset rule; and to sum the shifted results corresponding to the multiple digital information to obtain a calculation result.

[0018] In some implementations, the semiconductor device includes a three-dimensional NAND-type memory.

[0019] Secondly, embodiments of this disclosure provide an operation method for a semiconductor device, the method comprising: storing weighted data through a memory array in a second semiconductor structure, wherein the second semiconductor structure includes a memory array and a source layer coupled to the source end of the memory array; acquiring an output current signal coupled to the source layer through a memory-sensing circuit in a first semiconductor structure, and performing analog-to-digital conversion processing on the voltage signal corresponding to the acquired current signal to obtain digital information, wherein the second semiconductor structure is bonded to the first semiconductor structure, and the memory-sensing circuit is coupled to the source layer through a bonding layer.

[0020] In some embodiments, the method further includes: shifting at least a portion of the digital information in a plurality of digital information according to a preset rule by a memory control circuit in a third semiconductor structure; and summing the shifted results corresponding to the plurality of digital information to obtain a calculation result.

[0021] Thirdly, embodiments of this disclosure provide a packaging structure, including: a packaging substrate, a semiconductor device according to any one of the first aspects, and a molding compound; the semiconductor device is disposed on the packaging substrate; and the molding compound encapsulates the semiconductor device.

[0022] Fourthly, embodiments of this disclosure provide a system comprising: a semiconductor device as described in any of the first aspects; and a controller connected to the semiconductor device and configured to send input data to the semiconductor device and receive computation results from the semiconductor device.

[0023] In some implementations, it further includes: a calculation module; the second calculation module is configured to perform a second calculation on the numerical calculation result.

[0024] In some implementations, the second operation includes one of the following: compensation, activation, shift, or pooling operations.

[0025] Fifthly, embodiments of this disclosure provide an electronic device, including: a semiconductor device according to any one of the first aspects.

[0026] This disclosure provides a semiconductor device, its operating method, system, and electronic device. The semiconductor device includes: a first semiconductor structure including a memory sensing circuit; a second semiconductor structure including a memory array and a source layer coupled to the source terminals of the memory array, the source layer being located between the memory array and the first semiconductor structure; and a third semiconductor structure including a memory control circuit. The second semiconductor structure is bonded to both the first and third semiconductor structures, and is located between the first and third semiconductor structures. The memory sensing circuit is coupled to the source layer via a bonding layer. In this embodiment, the source layer is located between the memory sensing circuit and the memory array, thereby greatly shortening the path for the output current signal output from the source layer to the memory sensing circuit. Attached Figure Description

[0027] Figure 1 Schematic diagram of a semiconductor device provided in an embodiment of this disclosure Figure 1 ;

[0028] Figure 2 A schematic circuit diagram of a semiconductor device provided for an embodiment of this disclosure;

[0029] Figure 3A This is a schematic cross-sectional view of a storage array including NAND-type memory strings according to an embodiment of the present disclosure;

[0030] Figure 3B This is a perspective view of a storage array including NAND-type memory strings according to an embodiment of the present disclosure;

[0031] Figure 4 This is a schematic diagram of an exemplary semiconductor device including a memory array and peripheral circuitry according to an embodiment of the present disclosure;

[0032] Figure 5 This is a three-dimensional schematic diagram of an embodiment of the present disclosure, including a storage array. Figure 1 ;

[0033] Figure 6 This is a top view schematic of an embodiment of the present disclosure including a storage array. Figure 1 ;

[0034] Figure 7 This is a three-dimensional schematic diagram of an embodiment of the present disclosure, including a storage array. Figure 2 ;

[0035] Figure 8A This is a top view schematic diagram of an embodiment of the present disclosure including a storage array. Figure 2 ;

[0036] Figure 8B This is a top view of an embodiment of the present disclosure, including a storage array;

[0037] Figure 9A This is a schematic diagram of the hardware composition including peripheral circuits in an embodiment of this disclosure. Figure 1 ;

[0038] Figure 9B This is a schematic diagram of the hardware composition including peripheral circuits in an embodiment of this disclosure. Figure 2 ;

[0039] Figure 10 This is a top view schematic diagram of an embodiment of the present disclosure including a storage array. Figure 4 ;

[0040] Figure 11 Schematic diagram of a semiconductor device provided in an embodiment of this disclosure Figure 2 ;

[0041] Figure 12 Schematic diagram three of a semiconductor device provided according to an embodiment of this disclosure;

[0042] Figure 13 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0043] Figure 14A This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0044] Figure 14B This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0045] Figure 15 This is a schematic diagram illustrating the implementation flow of an operation method for a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0046] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0047] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0048] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0050] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0052] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0053] As the parameters of large AIGC (Artificial Intelligence Generated Content) models continue to grow, the traditional von Neumann architecture faces the "memory wall" and "power wall" problems. The bandwidth between the central processing unit (CPU) and memory has become a bottleneck restricting the performance of AI chips. Inspired by the working mode of the human brain, in-memory computing architecture has flourished in recent years. By embedding computing functions in memory, it avoids data transfer back and forth, reducing the impact of the memory wall and power wall, and thus has the potential to build high-performance, high-bandwidth, and high-energy-efficiency computing systems. At the same time, the data era places higher demands on storage density, and more bits, such as 4.5 bits, is an effective way to increase storage density. Based on this, semiconductor devices that can simultaneously realize more bits of storage and in-memory computing will be of great significance.

[0054] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their conductivity, based on their physical properties. Computational capability refers to the ability to perform vector-matrix multiplication calculations within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random-Access Memory (SRAM), NAND flash memory, and Dynamic Random-Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied and important component in IMC chips.

[0055] This disclosure provides a semiconductor device, Figure 1 Schematic diagram of a semiconductor device provided in an embodiment of this disclosure Figure 1 , refer to Figure 1The semiconductor device includes: a first semiconductor structure 100, including a memory sensing circuit 110; a second semiconductor structure 200, including a memory array 301 and a source layer 210 coupled to the source terminal of the memory array 301, the source layer 210 being located between the memory array 301 and the first semiconductor structure 100; and a third semiconductor structure 300, including a memory control circuit; the second semiconductor structure 200 is bonded to the first semiconductor structure 100 and the third semiconductor structure 300 respectively, the second semiconductor structure 200 being located between the first semiconductor structure 100 and the third semiconductor structure 300; and the memory sensing circuit is coupled to the source layer 210 through a bonding layer.

[0056] In some embodiments, the first semiconductor structure 100, the second semiconductor structure 200, and the third semiconductor structure 300 are in different planes and stacked on top of each other. In this way, the planar size of the semiconductor device can be reduced.

[0057] In some embodiments, a first semiconductor structure 100, a second semiconductor structure 200, and a third semiconductor structure 300 may be formed in parallel on different substrates. For example, a memory sensing circuit 110 may be formed on the first substrate, a memory array 301 may be formed on the second substrate, and a memory control circuit may be formed on the third substrate. Then, various bonding techniques such as hybrid bonding and transfer bonding may be used to stack them on top of each other.

[0058] In some embodiments, during the computation phase using a semiconductor device as a memory computing chip, weight data is written into the corresponding memory cell of the memory array according to a certain mapping rule before the operation begins. A single memory cell, such as a TLC, can store weight data with 3 data bits (INT3). Then, based on the input data, input voltages are applied to the corresponding bit lines, and finally, the output current of the source layer is received to obtain the computation result. It is understood that in this embodiment of the disclosure, data is input from the bit lines, and the computation result is obtained based on the output current output from the source layer, thus increasing the input accuracy. That is, the source end is an analog information (output current) output terminal.

[0059] In this embodiment, by vertically integrating the first semiconductor structure 100, the second semiconductor structure 200, and the third semiconductor structure 300, and vertically separating the memory sensing circuit 110, the memory array 301, and the memory control circuit into different planes, the chip size can be reduced and the storage density can be increased. Furthermore, when the source terminal is an analog information (output current) output terminal, since the source layer 210 is located between the memory array 301 and the first semiconductor structure 100, the memory sensing circuit 110 on the first semiconductor structure 100 can be directly coupled to the source layer 210 through a bonding layer. This allows for direct acquisition of the output current signal from the source layer 210 and subsequent analog-to-digital conversion. This significantly shortens the transmission path between the output current signal and the memory sensing circuit.

[0060] In some embodiments, the memory control circuit can also be referred to as the peripheral circuit of the memory array. In other words, the peripheral circuit of the memory array is formed in a third semiconductor structure.

[0061] The following explanation uses a three-dimensional NAND flash memory as an example to illustrate the memory array and memory control circuit. It should be noted that the memory control circuit described below refers to... Figure 4 It can be understood through the peripheral circuits.

[0062] Figure 2 This is a schematic circuit diagram of a semiconductor device provided for one embodiment of the present disclosure. The semiconductor device may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. The semiconductor device is illustrated as a three-dimensional NAND flash memory. Memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0063] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell, TLC), four bits per cell (also referred to as a quad-level cell, QLC), five bits per cell (also referred to as a penta-level cell, PLC), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0064] It should be noted that the storage state referred to here is the same as the storage state of the storage cell as described in this disclosure. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has two storage states (i.e., two memory states), which include one programming state and one erase state. Another example is an MLC type storage cell with four storage states, including one erase state and three programming states. Yet another example is a TLC type storage cell with eight storage states, including one erase state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, including one erase state and fifteen programming states.

[0065] like Figure 2As shown, each memory string 308 may include a lower selection transistor (BSG) 310 (also known as a source-side selection transistor) at its source end and an upper selection transistor (TSG) 312 (also known as a drain-side selection transistor) at its drain end. BSG 310 and TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled through the same source layer (SL) 210 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0066] like Figure 2 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source layer 210 (e.g., coupled to ground). In some implementations, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source layer 210 of the selected memory block 304 and the unselected memory blocks 304 on the same face as the selected memory block 304. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0067] refer to Figure 2 Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0068] Figure 3A A schematic cross-sectional view of an exemplary memory array 301, including a memory string 308, exemplified by NAND, is shown according to some aspects of this disclosure. Figure 3A As shown, the NAND memory array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure perpendicularly penetrating the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and adjacent gate layers 411 are separated by an insulating layer 412.

[0069] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0070] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0071] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0072] Figure 3B This is a perspective view of a storage array including NAND flash memory strings according to an embodiment of this disclosure. Figure 3B As shown, the memory array 301 sequentially includes multiple bit lines BL (e.g., m lines), multiple up-select transistor TSG lines (e.g., p lines), multiple word lines (e.g., n lines), down-select transistor BSG lines, source layer CSL, and multiple memory cells coupled to the word lines.

[0073] Return to reference Figure 1 Peripheral circuitry can be coupled to memory array 301 via bit line 316, word line 318, source layer 210, BSG line 315, and TSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source layer 210, BSG line 315, and TSG line 313. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0074] Figure 4 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 4 Additional peripheral circuitry not shown.

[0075] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0076] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. The row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0077] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0078] Figure 5 This is a three-dimensional schematic diagram of an embodiment of the present disclosure, including a storage array. Figure 1 ; Figure 6 This is a top view schematic diagram of an embodiment of the present disclosure including a storage array. Figure 1 In some embodiments, during the computation phase using semiconductor devices as in-memory computing chips, before the computation begins, weight data is written into the corresponding memory cells of the memory array according to a certain mapping rule. For example... Figure 5 As shown, a single memory cell, such as a TLC, can store a weight data of 3 bits (INT3). Then, based on the input data, input voltages are applied to the corresponding bit lines, and finally, the output current of the source layer SL is received to obtain the computation result. It is understandable that in the above embodiment, the in-memory computing technology based on 3D NAND uses one memory cell to store one weight data. The number of bits in the weight data is limited by the number of bits in the memory cell, resulting in low parallelism and low precision. While inputting data from the bit line BL can increase input precision, it further reduces parallelism.

[0079] In some embodiments, both the gate line isolation structure (GLS) and the top select gate (or TSG line) isolation structure (TSGCUT) extend in a direction perpendicular to the bit line extension direction. GLS and TSGCUT divide the memory block into multiple memory shards (String), such as 6 shards. Figure 6 The example shows two Strings, String1 and String2, each coupled to a different TSG. For example... Figure 6 As shown, bit lines BL are coupled to channel structures CH, where adjacent memory cells in a row of channel structures along the bit line extension direction are coupled to different bit lines BL. Source layer SL ( Figure 6(Not shown in the diagram) Interconnected in units of storage blocks. It is understandable that regardless of the size of the input data, the entire storage block will be occupied due to the interconnection of the source layer SL, and bit lines BL and storage cells not used for data input will be wasted. In other words, due to the interconnection of the source layer SL, the parallelism is extremely low, especially for small-scale weighted data where significant waste occurs.

[0080] In this embodiment of the disclosure, the storage unit is configured to store weight data; the source layer includes a plurality of first sub-source layers spaced along the bit line direction, and the M storage strings containing the M storage units storing the same weight data are respectively coupled to different first sub-source layers; M is an integer greater than 1.

[0081] Here, the storage array can refer to the aforementioned storage array 301 and... Figure 2 , Figure 4 For understanding; the storage string can be referred to as the aforementioned storage string 308 and... Figure 3A , Figure 3B For understanding; the bit line can be referred to as bit line 316 mentioned above and Figure 3A , Figure 3B For understanding; the source layer can be referred to as the aforementioned source layer 314 and... Figure 2 , Figure 3B For understanding; the storage unit can refer to the aforementioned storage unit 306 and... Figure 2 The details are not elaborated here.

[0082] Here and below, the first direction is the same as the direction of bit line extension; the second direction is perpendicular to the direction of bit line extension and parallel to the direction of word line extension; the third direction is perpendicular to both the first and second directions, and the direction of storage string extension can be parallel to the third direction.

[0083] In this embodiment of the disclosure, the source layer is no longer connected as a single block of memory, but rather comprises multiple first sub-source layers spaced apart along the bit line direction. In some embodiments, such as Figure 8A , Figure 8B As shown, the source layer is divided into multiple first sub-source layers by a first source layer isolation structure SLCUT1 extending along the second direction. The first source layer isolation structure SLCUT1 can penetrate the source layer along the third direction. It should be noted that... Figure 8A , Figure 8B Other logos can be referenced. Figure 6 The identifier in the text.

[0084] In this embodiment of the present disclosure, during the computation stage using a semiconductor device as a memory computing chip, before the computation begins, weight data is written into the corresponding storage cells of the storage array according to a certain mapping rule. Furthermore, the M storage strings containing the M storage cells storing the same weight data are respectively coupled to different first sub-source layers, where M is an integer greater than 1. In other words, this embodiment of the present disclosure uses at least two storage cells to store the same weight data together. Figure 7 The illustration shows a case where the same weight data is stored together using two storage units; wherein, at least two different storage units are used to store different data bits of the same weight data, so that the number of bits of weight data is not limited by the number of bits of storage units, thereby providing storage for more bits of weight data in the embodiments of this disclosure, thereby improving parallelism.

[0085] It is understood that in this embodiment of the disclosure, the source layer is divided into multiple first sub-source layers. The separation of these multiple first sub-source layers facilitates the execution of different subsequent operations on the output data of different first sub-source layers, such as performing different shift operations, and then summing the shifted data. The separation of multiple first sub-source layers enables different storage units in the M storage units used to store the same weight data to be used to store different data bits of the same weight data.

[0086] In some embodiments, M can be determined based on the data type of the weight data and the number of bits in the storage unit. For example, if the weight data is a six-bit positive integer, then M can be 2 for TLC; if the weight data is a nine-bit positive integer, then M can be 3 for TLC; if the weight data is a sixteen-bit positive integer, then M can be 4 for QLC.

[0087] In some embodiments, the configuration of the first source layer isolation structure SLCUT1 can be determined based on the coupling between the bit line BL and the memory cells in the channel structure, and the number of M. For example, as... Figure 8A , 8B In a row of channel structures extending along the bit line extension direction, adjacent channel structure storage cells are coupled to different bit lines BL. If M=2, then a first source layer isolation structure SLCUT1 can be set every two rows of channels to complete one source layer isolation. This embodiment does not limit the specific setting of the first source layer isolation structure SLCUT1, but regardless of the setting, it must satisfy the requirement that the M storage strings containing the M storage cells storing the same weight data are respectively divided into different first sub-source layers.

[0088] In some embodiments, M memory cells storing the same weight data are coupled to the same bit line. It is understood that, in the embodiments of this disclosure, during the computation phase using a semiconductor device as a memory computing chip, data is input by applying voltage to the bit line. If the M memory cells storing the same weight data can be coupled to the same bit line, the voltage applied to the same bit line can be mapped to the multiple memory cells coupled to it, effectively saving bit lines.

[0089] In some embodiments, two storage units storing the same weight data are coupled to the same bit line. That is, in this case, M=2, such as... Figure 7 As shown.

[0090] In some embodiments, the M storage strings containing the M storage units storing the same weight data are each coupled to the same selection line, such as... Figure 8A As shown, taking M=2 as an example, the two storage cells within the dashed box coupled to the leftmost bit line BL are used to store the same weight data. Here and below, the selection line may include a TSG line and / or a BSG line. In some embodiments, the selection line may be a TSG line.

[0091] In some embodiments, the M storage strings containing the M storage units storing the same weight data are respectively coupled to different selection lines, such as... Figure 8B As shown, taking M=2 as an example, the two storage cells within the dashed box coupled to the leftmost bit line BL are used to store the same weight data. Furthermore, in... Figure 8B In this embodiment, the two storage units used to store the same weight data are located in two adjacent storage slices (String) along the first direction. In some embodiments not shown, the two storage units used to store the same weight data may also be located in two spaced-apart storage slices (String) along the first direction.

[0092] In some embodiments, the memory control circuit is configured to: write N weight data into M*N memory cells; where N is an integer greater than 0; and apply a corresponding input voltage to the bit line coupled to the memory cell where the weight data is written.

[0093] Here, N can be the number of weight data to be written. N can be one or more. Each weight data is stored using M storage units. Based on this, N weight data are written into M*N storage units.

[0094] As described above, in this embodiment of the present disclosure, during the computation stage using a semiconductor device as a memory computing chip, before the computation begins, weight data is written into the corresponding memory cell of the memory array according to a certain mapping rule; then, according to the input data, a corresponding input voltage is applied to the bit line coupled to the memory cell where the weight data is written. The output current of the first sub-source layer in the source layer SL is received through the memory computing sensing circuit, and based on the received current signal, the computation result obtained is the product or sum of the input data and the data stored in the memory array (corresponding to the weight data).

[0095] In some embodiments, the weight data mapping rule may involve multiple memory cells in a memory array coupled to a selected word line. The weight data in this disclosure embodiment may be vector-type or matrix-type weight data. In some embodiments, the weight data is a matrix, and each data point in the matrix is ​​written into multiple memory cells in the memory array according to a multiple set of position settings, with M memory cells as a group, extending along a first direction and a second direction respectively. This process is similar to the programming operation of a semiconductor device.

[0096] In some embodiments, the memory control circuit is configured to apply corresponding input voltages to the bit lines coupled to the memory cells where weighted data is written, based on the input data. That is, the input voltage applied to the bit lines is related to the data value of the input data. The input data can be vector-type or matrix-type. In some embodiments, the input data is a vector. Different input voltages can represent different data values ​​of the input data; for example, applying a programming enable voltage to the bit line BL, which puts the channel structure in a conducting state, represents the data value "1"; applying a programming disable voltage to the bit line BL, which puts the channel structure in a turning state, represents the data value "0".

[0097] In some embodiments, the memory sensing circuit includes multiple sensing circuits, which are configured to acquire the output current signals of M first sub-source layers to which M memory cells storing the same weight data are respectively coupled, and to perform analog-to-digital conversion processing on the voltage signals corresponding to the acquired current signals to obtain digital information.

[0098] In some embodiments, the sensing circuit is coupled to the first sub-source layer and configured to: acquire the output current signals of the M first sub-source layers to which the M storage cells storing the same weight data are respectively coupled, and perform analog-to-digital conversion processing on the voltage signals corresponding to the acquired current signals to obtain digital information.

[0099] In some embodiments, the storage and sensing circuit further includes a shift circuit and an arithmetic circuit; the shift circuit is configured to receive digital information and perform shift processing on at least a portion of the digital information according to a preset rule; the arithmetic circuit is configured to sum the shifted results corresponding to the multiple digital information to obtain an arithmetic result.

[0100] In some embodiments, the shift circuit is coupled to the sensing circuit and configured to: shift at least a portion of the digital information among a plurality of digital information according to a preset rule; the operation is coupled to the shift circuit and configured to: sum the results of the shifted digital information corresponding to the plurality of digital information to obtain the operation result.

[0101] For example, let's illustrate this by using two storage units to store the same weight data. Figure 9A , Figure 9B As shown, the in-memory sensing circuit includes multiple sensing circuits 801, one or more shift circuits 802, and one or more arithmetic circuits 803. The output terminals of different first sub-source layers ( Figure 9A and Figure 9B Out1 and Out3 can correspond to Figure 7 (Understanding Out1 and Out3 in the original text) can be coupled to the input terminals of different sensing circuits 801, each sensing circuit 801 acquiring and converting the input signal from analog to digital; then the output terminal of the sensing circuit 801 can be selectively coupled to the input terminal of the shift circuit 802. Figure 9A Only one sensing circuit 801 is coupled to the shift circuit 802. Figure 9B Both sensing circuits 801 are coupled to shift circuit 802, which performs shift processing on the input digital signal. Figure 9B The two shift circuits 802 need to satisfy the requirement that the shift difference is the same as the actual high-low bit difference of the weighted data; the output of each shift circuit 802 that has undergone shift processing is coupled to the input of the same arithmetic circuit 803, or the output of the sensing circuit 801 of the branch that has not undergone shift processing and the output of the shift circuit 802 of the branch that has undergone shift processing are coupled to the input of the same arithmetic circuit 803. The arithmetic circuit 803 performs a summation operation on the input data and outputs the operation result.

[0102] In some embodiments, the plurality of sensing circuits 801 may include a plurality of single-channel analog-to-digital converters (ADCs) or one or more multi-channel ADCs. In some embodiments, the shift circuit 802 may include, but is not limited to, a shift register. In some embodiments, the arithmetic circuitry may include an adder.

[0103] The above-described embodiments of the present disclosure improve the parallelism of in-memory computing from the perspective of storing more bit weight data.

[0104] In some embodiments, the memory sensing circuit further includes a differential circuit, which is coupled to the first sub-source layer and configured to: perform differential processing on two current signals of the same direction output from each of the M first sub-source layers to which the 2M memory cells storing weight data are respectively coupled; the sensing circuit is coupled to the differential circuit and configured to: acquire the differentially processed differential data pair signals and perform analog-to-digital conversion processing on the voltage signals corresponding to the differential data pair signals respectively. In some embodiments, the differential circuit includes, but is not limited to, a differential amplifier.

[0105] In some embodiments, before differential processing of the two signals output from the source layer, the two current signals output from the source layer (the two current signals have the same direction) are converted into voltage signals through sampling resistors, etc., and differential processing is performed on the two voltage signals. Then, the differentially processed voltage signals are converted into digital signals.

[0106] The embodiments of this disclosure can also improve the accuracy of in-memory computing by introducing differential circuits. It is understood that interference signals generally act simultaneously on both signals of the differential data pair. The receiver in the differential data pair is concerned with the difference between the two signals, so the interference signals suffered by both signals will be completely canceled out, thereby improving accuracy through differential data pairs.

[0107] In some embodiments, the source layer includes a plurality of second sub-source layers spaced apart along the word line direction, and the M storage strings containing the M storage cells storing the same weight data are all coupled to the same second sub-source layer.

[0108] In this embodiment of the disclosure, the source layer may further include a plurality of second sub-source layers spaced apart along the word line direction. In some embodiments, such as Figure 10 As shown, the source layer is divided into multiple second sub-source layers by a second source layer isolation structure SLCUT2 extending along a first direction. The second source layer isolation structure SLCUT2 can penetrate the source layer along a third direction. It should be noted that... Figure 10 Other logos can be referenced. Figure 6 The identifier in the diagram. The M storage strings containing the M storage units storing the same weight data are all coupled to the same second sub-source layer. It should be noted that each second sub-source layer is also divided into multiple parts by the first source layer isolation structure SLCUT1.

[0109] In some embodiments, a second sub-source layer is coupled to a plurality of memory strings, the number of bit lines coupled to the plurality of memory strings being related to the amount of input data; the input voltage applied to the bit lines is related to the data value of the input data.

[0110] In this embodiment of the disclosure, the segmentation of the source layer SL along the extension direction of the bit line BL is related to the amount of input data, that is, to the amount of computation performed each time. For example, if the size of the input data is 32, then the source layer SL is segmented every 32 bit lines; if the size of the input data is 64, then the source layer SL is segmented every 64 bit lines.

[0111] It is understood that, in the embodiments of this disclosure, the source layer SL can be adaptively divided along the extension direction of the bit line BL according to the specifications of the input data, thereby avoiding the waste of bit lines BL and storage units that are not used for data input, and thus improving the parallelism of the source layer output.

[0112] In some embodiments, the second semiconductor structure further includes a first bonding layer and a second bonding layer, the memory array is bonded to the third semiconductor structure through the first bonding layer, and the memory array is bonded to the first semiconductor structure through the second bonding layer.

[0113] Figure 11 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 2 , refer to Figure 11 The second semiconductor structure 200 also includes a first bonding layer 101 and a second bonding layer 102. The memory array 301 is bonded to the third semiconductor structure 300 through the first bonding layer 101, and the memory array 301 is bonded to the first semiconductor structure 100 through the second bonding layer 102.

[0114] In some embodiments, the first semiconductor structure 100 and the second semiconductor structure 200, and the third semiconductor structure 300, can be vertically connected by bonding. This bonding connection includes hybrid bonding connections (also known as "metal / dielectric hybrid bonding connections"), a direct bonding technique, such as forming bonds between surfaces without the use of intermediate layers such as solder or adhesives, and simultaneously achieving metal-to-metal bonding and dielectric-to-dielectric bonding. It should be noted that the term "bonding" as used in this disclosure can refer to any suitable bonding technique, such as the hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding mentioned above.

[0115] In some embodiments, the first bonding layer includes a first bonding contact and a first dielectric layer that isolates the first bonding contact; the third semiconductor structure includes a third bonding layer, which includes a third bonding contact and a third dielectric layer that isolates the third bonding contact; the first bonding contact and the third bonding contact are bonded, and the first dielectric layer and the third dielectric layer are bonded.

[0116] In some embodiments, the second bonding layer includes a second bonding contact and a second dielectric layer that isolates the second bonding contact; the first semiconductor structure includes a fourth bonding layer, the fourth bonding layer including a fourth bonding contact and a fourth dielectric layer that isolates the fourth bonding contact; the second bonding contact and the fourth bonding contact are bonded, and the second dielectric layer and the fourth dielectric layer are bonded.

[0117] Reference Figure 11 The third semiconductor structure 300 includes a third bonding layer 103, and the first semiconductor structure 100 includes a fourth bonding layer 104. The first bonding layer 101 is bonded to the third bonding layer 103, and the second bonding layer 102 is bonded to the fourth bonding layer 104.

[0118] In some embodiments, the memory sensing circuit 110 and the memory control circuit are located on opposite sides of the memory array 301. That is, the memory array 301 is vertically located between the memory sensing circuit 110 and the memory control circuit.

[0119] In some embodiments, the semiconductor device may further include a first bonding interface between the third bonding layer 103 and the first bonding layer 101, and a second bonding interface between the fourth bonding layer 104 and the second bonding layer 102. Data transfer between the first sub-semiconductor structure and the second sub-semiconductor structure can be achieved through interconnects (e.g., bonding contacts) across the first bonding interface. Data transfer between the first semiconductor structure and the second semiconductor structure can be achieved through interconnects (e.g., bonding contacts) across the second bonding interface.

[0120] Figure 12 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure, in conjunction with reference to... Figure 11 and Figure 12 In some embodiments, a first interconnect layer 230 may be included between the memory array 301 and the first bonding layer 101, and a second interconnect layer 330 may be included between the memory control circuit and the third bonding layer 103. In some embodiments, a third interconnect layer 240 may be included between the memory array 301 and the second bonding layer 102, and a fourth interconnect layer 130 may be included between the memory sensing circuit and the third bonding layer 103. The first interconnect layer 230, the second interconnect layer 330, the third interconnect layer 240, and the fourth interconnect layer 130 may include multiple interconnect structures, such as lateral lines and vias, and the interconnect structures may be formed in one or more interlayer dielectric (ILD) layers. The interconnect structures may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0121] In some embodiments, the bonding contacts may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In a specific example, the bonding contacts of the bonding layer include Cu. The remaining area of ​​the bonding layer may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer and the surrounding dielectric can be used for hybrid bonding, simultaneously achieving metal-to-metal bonding and dielectric-to-dielectric bonding.

[0122] In some embodiments, the memory sensing circuit is coupled to the source layer through the fourth bonding layer and the second bonding layer to acquire the output current signal of the source layer.

[0123] In some embodiments, the memory sensing circuit 110 is coupled to the source layer through the fourth bonding layer 104 and the second bonding layer 102, thereby directly acquiring the output current signal of the source layer and performing analog-to-digital conversion. This greatly shortens the transmission path between the output current signal and the memory sensing circuit. It is understood that placing the memory sensing circuit adjacent to the source layer in the embodiments of this disclosure can reduce the wiring complexity of the output of the first sub-source layer.

[0124] In some embodiments, the second semiconductor structure further includes a first connection structure extending through the memory array; one end of the first connection structure is connected to a memory sensing circuit, and the other end is connected to a memory control circuit; the first connection structure is used to realize information transmission between the memory sensing circuit and the memory control circuit. (Refer to reference...) Figure 1 and Figure 12 One end of the first connection structure 220 is connected to the memory sensing circuit 110 through the second bonding layer 102 and the fourth bonding layer 104, and the other end is connected to the memory control circuit through the first bonding layer 101 and the third bonding layer 103. Thus, the memory control circuit can transmit control signals to the memory sensing circuit 110 through the first connection structure 220 to control the memory sensing circuit 110 to perform computational operations.

[0125] In some embodiments, the first semiconductor structure 100 further includes a data processing circuit 120, which is configured to perform shift processing on at least a portion of the digital information in a plurality of digital information according to a preset rule; and to sum the shift processing results corresponding to the plurality of digital information to obtain a calculation result.

[0126] In some embodiments, return to reference Figure 1 The first semiconductor structure 100 also includes a data processing circuit 120, which can be used to assist in computational processing. That is, when the computational workload is large, the data processing circuit 120 can work together with the shift circuit and the computational circuit in the storage and sensing circuit 110 to perform shift processing and operation processing, so as to speed up the computation.

[0127] In some embodiments, the data processing circuit 120 includes a processor, which may include a dedicated processor, including but not limited to a CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), vision processing unit (VPU), neural processing unit (NPU), coprocessor unit (SPU), physical processing unit (PPU), and image signal processor (ISP). In a specific example, the data processing circuit is a GPU. The GPU can perform operations such as arithmetic / logic operations and shift operations.

[0128] In some embodiments, the first semiconductor structure 100 may further include a first interface circuit. The first interface circuit is configured to receive and transmit data between the semiconductor device and other external devices. Specifically, the first interface circuit is configured to output the computation result from the memory sensing circuit 110 to the external device, and the first interface circuit is also configured to output the computation result from the digital processing circuit 120 to the external device.

[0129] In some embodiments, the first interface circuit may be disposed adjacent to the data processing circuit 120, and the interface protocol may be used as the first interface circuit between the semiconductor device and the external device. Thus, the semiconductor device can communicate with the external device through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, Firewire protocol, etc.

[0130] In some embodiments, the semiconductor device includes a three-dimensional NAND-type memory.

[0131] This disclosure also provides a system comprising: at least one semiconductor device provided in this disclosure; and a controller connected to the semiconductor device and configured to send input data to the semiconductor device and receive computation results from the semiconductor device.

[0132] In some embodiments, the system further includes: a calculation module; the second calculation module is configured to perform a second calculation on the numerical calculation result.

[0133] In some embodiments, the computing module includes a processor, which may include a dedicated processor, including but not limited to a CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), vision processing unit (VPU), neural processing unit (NPU), collaborative processing unit (SPU), physical processing unit (PPU), and image signal processor (ISP). In a specific example, the computing module is an NPU. The NPU can perform operations such as arithmetic / logic operations, rotation and shift operations, compensation operations, activation operations, and pooling operations.

[0134] In some embodiments, the second operation includes one of compensation, activation, shift, or pooling operations. In a specific example, the semiconductor device is configured to store a weight matrix to perform multiplication-accumulation operations and output a numerical calculation result; the operation module is configured to perform an activation operation on the numerical calculation result to generate an output result. In some embodiments, the activation operation can be implemented using an activation function stored in the NPU, which may include, but is not limited to, a step function, a correction function, a sigmoid function, a hyperbolic tangent (tanh) function, and a softplus function (also known as a smoothing correction).

[0135] In some embodiments, the system described above may be as follows: Figure 13 The memory system 102 shown includes a memory controller 106 and a memory device 104 coupled to the memory controller 106. Here, the memory device 104 may be a semiconductor device as described in the above embodiments. The controller in the above embodiments may be, for example, a... Figure 13 , Figure 14A as well as Figure 14B The memory controller 106 shown is an example. In other embodiments, the system described above may be as follows: Figure 13 The system 100 shown includes a host device 108 and a memory system 102 coupled to the host device 108. The controller in the above embodiment may be a control unit independent of the memory controller 106, such as the CPU in the host device. The input data here includes vectors or matrices. According to some implementations, such as... Figure 13As shown, memory controller 106 is coupled to memory device 104 and host device 108 and is configured to control the operation of memory device 104, such as read, erase, program, and compute operations. Memory controller 106 can manage data stored in memory device 104 and communicate with host device 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as secure digital cards, compact flash memory cards, Universal Serial Bus flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0136] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 14A In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a compact flash memory card, a smart media card, a memory stick, a multimedia card, a secure digital card, UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host device (e.g., Figure 13 The host device 108 in the memory card connector 204 is coupled to it. In such a way... Figure 14B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include interfaces for connecting the SSD 206 to host devices (e.g., Figure 13 The SSD connector 208 is coupled to the host device 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0137] Based on a concept similar to the aforementioned semiconductor device, this disclosure also provides a method for operating a semiconductor device. Figure 15 This is a schematic flowchart illustrating the operation method of the semiconductor device provided in the embodiments of this disclosure, such as... Figure 15 As shown, the operation method of a semiconductor device includes the following steps:

[0138] Step S10: Storing weight data through a memory array in a second semiconductor structure, wherein the second semiconductor structure includes a memory array and a source layer coupled to the source end of the memory array.

[0139] Step S20: The in-memory sensing circuit in the first semiconductor structure acquires the output current signal coupled to the source layer, and performs analog-to-digital conversion on the voltage signal corresponding to the acquired current signal to obtain digital information. The second semiconductor structure is bonded to the first semiconductor structure, and the in-memory sensing circuit is coupled to the source layer through a bonding layer.

[0140] In some embodiments, the method further includes: shifting at least a portion of the digital information among a plurality of digital information according to a preset rule by a storage control circuit in a third semiconductor structure; and summing the shifted results corresponding to the plurality of digital information to obtain a calculation result.

[0141] Based on the above-described semiconductor device, this disclosure also provides a packaging structure, including: a packaging substrate, a semiconductor device as described in any of the above embodiments, and a molding compound; the semiconductor device is disposed on the packaging substrate; and the molding compound encapsulates the semiconductor device.

[0142] In some embodiments, the packaging substrate includes a substrate and a redistribution layer formed on the substrate, wherein a connection circuit is formed in the redistribution layer, and a semiconductor device is disposed on the side of the redistribution layer opposite to the substrate.

[0143] Based on the above-described semiconductor device, this disclosure also provides an electronic device, including: a semiconductor device as described in any of the above embodiments.

[0144] Here, the specific structure of the semiconductor device is described in the above embodiments. Since this electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0145] In some embodiments, the electronic device may further include a host, wherein the host may be a processor of the electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), wherein the SoC may be, for example, an application processor (AP).

[0146] In some embodiments, the aforementioned electronic device may be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, or power bank.

[0147] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0148] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: The first semiconductor structure includes a memory sensing circuit; The second semiconductor structure includes a memory array and a source layer coupled to the source end of the memory array, the source layer being located between the memory array and the first semiconductor structure; The third semiconductor structure includes in-memory control circuitry; The second semiconductor structure is bonded to the first semiconductor structure and the third semiconductor structure respectively, and the second semiconductor structure is located between the first semiconductor structure and the third semiconductor structure; The in-memory sensing circuit is coupled to the source layer through a bonding layer.

2. The semiconductor device according to claim 1, characterized in that, The storage array is configured to store weight data; the storage array includes multiple storage strings, each of which includes multiple storage cells connected in series between the bit line and the source layer. The source layer includes multiple first sub-source layers spaced apart along the bit line direction. M storage strings containing M storage units storing the same weight data are respectively coupled to different first sub-source layers; M is an integer greater than 1.

3. The semiconductor device according to claim 2, characterized in that, The M storage units storing the same weight data are coupled to the same bit line.

4. The semiconductor device according to claim 3, characterized in that, The in-memory control circuit is configured to write N weight data into M*N storage units; where N is an integer greater than 0. ； A corresponding input voltage is applied to the bit line coupled to the storage cell where the weighted data is written.

5. The semiconductor device according to claim 4, characterized in that, The storage and computing sensing circuit includes multiple sensing circuits. The sensing circuits are configured to acquire the output current signals of the M first sub-source layers that are respectively coupled to the M storage cells storing the same weight data, and to perform analog-to-digital conversion on the voltage signals corresponding to the acquired current signals to obtain digital information.

6. The semiconductor device according to claim 5, characterized in that, The storage and sensing circuit further includes a shift circuit and an arithmetic circuit; the shift circuit is configured to receive the digital information and perform shift processing on at least a portion of the digital information according to a preset rule; the arithmetic circuit is configured to sum the shifted results corresponding to the multiple digital information to obtain an arithmetic result.

7. The semiconductor device according to claim 1, characterized in that, The second semiconductor structure further includes a first connection structure that extends through the memory array; one end of the first connection structure is connected to the memory-sensing circuit, and the other end is connected to the memory-control circuit; the first connection structure is used to realize information transmission between the memory-sensing circuit and the memory-control circuit.

8. The semiconductor device according to claim 2, characterized in that, The source layer includes multiple second sub-source layers spaced apart along the word line direction, and the M storage strings containing the M storage units storing the same weight data are all coupled to the same second sub-source layer.

9. The semiconductor device according to claim 8, characterized in that, A second sub-source layer is coupled to a plurality of memory strings, the number of bit lines coupled to the plurality of memory strings being related to the amount of input data; the input voltage applied to the bit lines is related to the data value of the input data.

10. The semiconductor device according to claim 1, characterized in that, The second semiconductor structure further includes a first bonding layer and a second bonding layer. The memory array is bonded to the third semiconductor structure through the first bonding layer, and the memory array is bonded to the first semiconductor structure through the second bonding layer.

11. The semiconductor device according to claim 10, characterized in that, The first bonding layer includes a first bonding contact and a first dielectric layer that isolates the first bonding contact. The third semiconductor structure includes a third bonding layer, which includes a third bonding contact and a third dielectric layer that isolates the third bonding contact. The first bonding contact and the third bonding contact are bonded together, and the first dielectric layer and the third dielectric layer are bonded together.

12. The semiconductor device according to claim 11, characterized in that, The second bonding layer includes a second bonding contact and a second dielectric layer that isolates the second bonding contact; the first semiconductor structure includes a fourth bonding layer, which includes a fourth bonding contact and a fourth dielectric layer that isolates the fourth bonding contact; The second bonding contact and the fourth bonding contact are bonded, and the second dielectric layer and the fourth dielectric layer are bonded.

13. The semiconductor device according to claim 12, characterized in that, The in-memory sensing circuit is coupled to the source layer through the fourth bonding layer and the second bonding layer to acquire the output current signal of the source layer.

14. The semiconductor device according to claim 5, characterized in that, The first semiconductor structure further includes a data processing circuit, which is configured to perform shift processing on at least a portion of the digital information among the plurality of digital information according to a preset rule; The results of the shifting processes corresponding to the multiple digital information are summed to obtain the calculation result.

15. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a three-dimensional NAND flash memory.

16. A method of operating a semiconductor device, characterized in that, The method includes: Weight data is stored through a memory array in a second semiconductor structure, wherein the second semiconductor structure includes a memory array and a source layer coupled to the source end of the memory array; The in-memory sensing circuit in the first semiconductor structure acquires the output current signal coupled to the source layer, and performs analog-to-digital conversion on the voltage signal corresponding to the acquired current signal to obtain digital information. The second semiconductor structure is bonded to the first semiconductor structure, and the in-memory sensing circuit is coupled to the source layer through a bonding layer.

17. The operating method according to claim 16, characterized in that, The method further includes: The memory-based control circuit in the third semiconductor structure performs shift processing on at least a portion of the digital information according to a preset rule; the results of the shift processing corresponding to the multiple digital information are summed to obtain the calculation result.

18. A packaging structure, characterized in that, include: The packaging substrate, the semiconductor device according to any one of claims 1-15, and the molding layer; The semiconductor device is disposed on the packaging substrate; The molding compound encapsulates the semiconductor device.

19. A system, characterized in that, include: The semiconductor device as described in any one of claims 1-15; as well as, The controller is connected to the semiconductor device and configured to send input data to the semiconductor device and receive the calculation results from the semiconductor device.

20. The system according to claim 19, characterized in that, Also includes: Computation module; The second calculation module is configured to perform a second calculation on the numerical calculation result.

21. The system according to claim 19, characterized in that, The second operation includes one of the following: compensation, activation, shift, or pooling operations.

22. An electronic device, characterized in that, include: The semiconductor device according to any one of claims 1-15.

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