Power converter and turn-on time control circuit and control method thereof

Abstract

The invention provides a power converter and a turn-on time control circuit and control method thereof, and the turn-on time control circuit comprises a charging current generation circuit which charges a first capacitor through a charging current during the turn-on period of a main power tube; the comparison unit compares voltage on the first capacitor with first reference voltage to generate a turn-off trigger signal, the charging current generation circuit determines charging current at least according to first current, second current and first compensation current, the second current is generated according to a first voltage signal, and the second current is generated according to a second voltage signal; and when the power converter needs to lock the conduction time of the main power tube, the conduction time of the main power tube is locked by performing voltage locking on the first voltage signal. According to the scheme, when the load is small, the conduction time of the main tube can be locked in a voltage locking mode, the response speed to light-load small ripples is higher, the control precision is higher, and the advantages of being small in area, high in accuracy and high in stability are achieved.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, specifically to a power converter and its on-time control circuit and control method. Background Technology

[0002] In recent years, power conversion chips with low standby power consumption, high frequency, high efficiency, strong load capacity, and fast transient response have become the development target for power management chips. Such high-performance chips have excellent application prospects. Portable power supply devices are increasingly demanding higher power, requiring high efficiency under no-load, light-load, and heavy-load conditions. Furthermore, in practical applications, different operating modes are selected based on the system's efficiency and output ripple requirements. Additionally, reducing power consumption and achieving high efficiency under light loads can extend battery life.

[0003] Taking Buck converters as an example, low-ripple under light load refers to the function of reducing output voltage Vout fluctuations by reducing the on-time (ton) of the main conductor, i.e., reducing the rise time of the inductor current, when the load is very small. With the increasing number of light-load applications, the demand for low-ripple under light load functionality has become important, and how to achieve low-ripple under light load with small area and high efficiency has become an important research direction. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a power converter and its on-time control circuit and method, aiming to improve the system's response speed and control accuracy to light loads and small ripples, enabling the system to achieve light loads and small ripples with a smaller area and higher stability and accuracy.

[0005] According to a first aspect of this application, a power converter on-time control circuit is provided, comprising:

[0006] First capacitor;

[0007] A charging current generating circuit charges the first capacitor using the charging current during the conduction of the main power transistor in the power converter.

[0008] The comparison unit compares the voltage on the first capacitor with the first reference voltage to generate a turn-off trigger signal. When the turn-off trigger signal is valid, it triggers the main power transistor to turn off.

[0009] The charging current generating circuit determines the charging current based on at least a first current, a second current, and a first compensation current. The first current is related to the input voltage and / or output voltage of the power converter, and the second current is generated based on the first voltage signal.

[0010] When the power converter needs to lock the on-time of the main power transistor, the charging current generating circuit performs voltage locking on the first voltage signal to lock the on-time of the main power transistor.

[0011] Optionally, the charging current generating circuit includes:

[0012] A first current generating unit is used to generate the first current;

[0013] The second current generating unit is used to perform error amplification processing on the control signal and reference clock signal of the main power transistor, generate the first voltage signal according to the error amplification result, and perform voltage-to-current processing on the first voltage signal to generate the second current.

[0014] A first compensation current generating unit is used to provide the first compensation current;

[0015] A voltage-locking unit is used to lock the first voltage signal with a first limiting voltage when the power converter needs to lock the on-time of the main power transistor.

[0016] Optionally, when the power converter needs to lock the on-time of the main power transistor, the locking unit limits the first voltage signal to no more than a first predetermined voltage.

[0017] Optionally, the locking unit obtains the first defined voltage by performing sample-and-hold processing on the first voltage signal.

[0018] Optionally, the locking unit includes:

[0019] The first switch is activated when the power converter needs to lock the on-time of the main power transistor.

[0020] A voltage regulation unit is configured to compare the first voltage signal and the first limiting voltage when the first switch is turned on, and to reduce the first voltage signal when the first voltage signal is greater than the first limiting voltage, so as to limit the first voltage signal from exceeding the first limiting voltage.

[0021] Optionally, the locking unit includes:

[0022] The sample-and-hold unit is used to determine the voltage range of the first voltage signal based on multiple threshold voltages, and output the upper threshold voltage corresponding to the voltage range as the first defined voltage.

[0023] Optionally, the second current generating unit includes:

[0024] The first frequency-to-voltage module is used to convert the control signal of the main power transistor into a voltage signal;

[0025] The second frequency-to-voltage module is used to convert the reference clock signal into a voltage signal;

[0026] The error amplifier receives a voltage signal corresponding to the control signal of the main power transistor at its first input terminal, receives a voltage signal corresponding to the reference clock signal at its second input terminal, and outputs a second voltage signal at its output terminal.

[0027] The first transistor has a control terminal that receives the second voltage signal, a first transmission electrode that is connected to the first end of a first resistor, a second end of the first resistor that is connected to a reference ground, and a second current generating unit that generates the second current at the second transmission electrode of the first transistor.

[0028] The first voltage signal is the voltage across the first terminal of the first resistor.

[0029] Optionally, the voltage regulation unit regulates the first voltage signal by regulating the second voltage signal.

[0030] Optionally, the voltage regulation unit includes:

[0031] The second transistor has its control terminal connected to the first transmission electrode, and the first transmission electrode receives the second voltage signal through the first switch.

[0032] The third transistor has a control terminal that receives the first limited voltage and a first transmission electrode that is connected to the first current source.

[0033] The fourth transistor has its control terminal connected to the second transmission terminal of the second transistor, and its first transmission terminal connected to the first current source.

[0034] A fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor forming a first current mirror structure, the fifth transistor being connected between the second transmission electrode of the third transistor and the reference ground, and the sixth transistor being connected between the second transmission electrode of the fourth transistor and the reference ground;

[0035] The seventh transistor and the eighth transistor form a second current mirror structure. The seventh transistor is connected between the second transmission electrode of the third transistor and the reference ground, and the eighth transistor is connected between the control terminal of the fourth transistor and the reference ground.

[0036] Optionally, the threshold voltages of the first transistor and the second transistor are matched.

[0037] Optionally, the sample-and-hold unit includes:

[0038] A voltage follower receives the first voltage signal at its input and outputs a third voltage signal at its output.

[0039] A threshold voltage generation unit generates the plurality of threshold voltages based on the power supply voltage;

[0040] A voltage range determination unit is used to perform analog-to-digital conversion processing on the third voltage signal based on the plurality of threshold voltages to generate a voltage range indication signal, wherein the voltage range indication signal is used to indicate the voltage range in which the first voltage signal is located;

[0041] The gating unit receives the plurality of threshold voltages at its input terminal and the voltage range indication signal at its control terminal, and is used to select one threshold voltage from the plurality of threshold voltages as the first limited voltage output according to the voltage range indication signal.

[0042] Optionally, the threshold voltage generating unit includes a first resistor string, which generates the plurality of threshold voltages by dividing the power supply voltage to different degrees through the first resistor string.

[0043] Optionally, the voltage range determination unit includes:

[0044] Multiple comparators are used to compare the third voltage signal with multiple threshold voltages respectively according to a first clock signal, and generate multiple comparison signals;

[0045] A logic circuit receives the plurality of comparison signals and performs logical processing on the plurality of comparison signals to generate the voltage range indication signal.

[0046] Optionally, the charging current generating circuit further includes:

[0047] The compensation unit is used to detect predetermined parameters of the power converter, generate a compensation signal based on the amount of change of the predetermined parameters when a change is detected, and adjust the charging current based on the compensation signal in the intermittent conduction mode.

[0048] Optionally, the predetermined parameters include at least one of the input voltage and system temperature.

[0049] Optionally, the locking unit uses a sixth capacitor to store energy in the first voltage signal to obtain the first defined voltage.

[0050] Optionally, the charging current is equal to the sum of the first current and the second current, minus the first compensation current;

[0051] Alternatively, the charging current is equal to the sum of the first current and the first compensation current, minus the second current.

[0052] According to a second aspect of this application, a power converter is provided, including: a main power transistor and a control circuit for controlling the switching state of the main power transistor, the control circuit including an on-time control circuit as disclosed in any embodiment of this application.

[0053] According to a third aspect of this application, a method for controlling the on-time of a power converter is provided, comprising:

[0054] A charging current is generated based on a first current, a second current, and a first compensation current. The first current is obtained from the input voltage and / or output voltage of the power converter, and the second current is related to the first voltage signal.

[0055] The charging current is used to charge the first capacitor, and the voltage on the first capacitor is compared with the first reference voltage to generate a shutdown trigger signal. When the shutdown trigger signal is valid, the main power transistor is triggered to shut down.

[0056] When the power converter needs to lock the on-time of the main power transistor, the first voltage signal is voltage locked to lock the on-time of the main power transistor.

[0057] The beneficial effects of this application include at least the following:

[0058] The power converter and its conduction time control circuit and control method provided in this application charge the first capacitor at least using a first current, a second current and a first compensation current during the conduction period of the main power transistor, and control the conduction time of the main power transistor according to the comparison result of the voltage on the first capacitor and the first reference voltage. The second current is generated based on the first voltage signal, and when it is determined that the power converter needs to lock the conduction time of the main power transistor, the conduction time of the main power transistor can be locked by locking the first voltage signal. Compared with the existing solution, the method of locking the conduction time of the main power transistor by locking the voltage in this application is easier to implement and the locking result is more accurate. It can improve the response speed and control accuracy for light load and small ripple, and the system area is smaller, the accuracy is higher and the stability is stronger.

[0059] In a further preferred embodiment, the final fixed value for locking the conduction time is obtained by sampling and holding the first voltage signal, making the locking result for the conduction time more stable and accurate.

[0060] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description

[0061] Figure 1 This diagram shows a structural block diagram of a power converter provided according to an embodiment of this application;

[0062] Figure 2 A schematic diagram of a frequency-locking implementation circuit for a power converter in related technologies is shown.

[0063] Figure 3 A schematic diagram of a power converter achieving low ripple under light load is shown in the relevant technology.

[0064] Figure 4a A schematic diagram illustrating an embodiment of the charging current generating circuit provided according to the first embodiment of this application is shown;

[0065] Figure 4b A schematic diagram illustrating an embodiment of the charging current generating circuit according to the second embodiment of this application is shown;

[0066] Figure 5 Show Figure 4a and / or Figure 4b A schematic diagram illustrating the implementation of the second current generating unit and the latching unit;

[0067] Figure 6 Show Figure 5 A schematic diagram illustrating the implementation of the sample-and-hold unit in the diagram;

[0068] Figure 7 Show Figure 6 A schematic diagram illustrating the implementation of the comparator in the diagram;

[0069] Figure 8a A schematic diagram illustrating an embodiment of the charging current generating circuit according to the third embodiment of this application is shown.

[0070] Figure 8b A schematic diagram illustrating an embodiment of the charging current generating circuit according to the fourth embodiment of this application is shown.

[0071] Figure 9 A schematic diagram showing the timing waveforms of the corresponding signals of the power converter provided according to an embodiment of this application during mode switching is shown;

[0072] Figure 10 This diagram illustrates the implementation flow of the power converter on-time control method provided in an embodiment of this application. Detailed Implementation

[0073] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0074] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0075] In the description of this application, words such as "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. The term "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0076] In addition, the same reference numerals in the figures indicate the same or similar structures, so repeated descriptions of them will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive methods. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referred to each other.

[0077] Switching power converters use power switches to capture a portion of the input energy and store it in an inductor, then continuously release the energy to the load through the inductor, achieving power conversion. Their basic topologies are buck, boost, and buck-boost. Buck-type DC / DC converters are the most widely used.

[0078] Taking the buck converter topology as an example, Figure 1 This diagram illustrates a structural block diagram of a power converter provided according to an embodiment of this application. (Refer to...) Figure 1 The power converter includes: a main power transistor Q1, a rectifier transistor Q2, an inductor L, an output capacitor Co, and a control circuit 100.

[0079] The main power transistor Q1 is coupled between the application terminal of the input voltage Vin and the switching node SW. The rectifier transistor Q2 is coupled between the switching node SW and the reference ground. Figure 1 The example shown only illustrates that the main power transistor Q1 and rectifier Q2 are N-type transistors, meaning that the main power transistor Q1 and rectifier Q2 are turned on when the control signal is high and turned off when the control signal is low. Of course, the technical solution of this application can also be applied to scenarios where the main power transistor Q1 and rectifier Q2 are P-type transistors. In this case, the power transistor Q1 and rectifier Q2 will be turned on when the control signal is low and turned off when the control signal is high.

[0080] The first terminal of inductor L is coupled to the switching node SW, and the second terminal of inductor L is coupled to the first terminal of output capacitor Co. The second terminal of output capacitor Co is coupled to reference ground. The switching power supply generates an output voltage Vout at the first terminal of output capacitor Co.

[0081] The control circuit 100 is coupled to the control terminals of the main power transistor Q1 and the rectifier transistor Q2. It is used to provide control signal PWM1 to the main power transistor Q1 and control signal PWM2 to the rectifier transistor Q2, thereby controlling the switching state of the main power transistor Q1 and the rectifier transistor Q2 through control signal PWM1 and control signal PWM2, and realizing the conversion from input voltage Vin to output voltage Vout.

[0082] In this embodiment, the control circuit 100 further includes: a turn-on trigger signal generation circuit 110, a turn-on time control circuit 120, and a drive circuit 130. The turn-on trigger signal generation circuit 110 generates a turn-on trigger signal Von based on the output feedback signal VFB and the second reference voltage Vref2. This turn-on trigger signal Von is used to trigger the main power transistor Q1 to turn on when it is active. The turn-on time control circuit 120 charges the first capacitor C1 with the charging current Ich during the turn-on period of the main power transistor Q1 and compares the voltage on the first capacitor C1 with the first reference voltage Vref1 to generate a turn-off trigger signal Voff. The turn-off trigger signal Voff is used to trigger the main power transistor Q1 to turn off when it is active. The drive circuit 130 generates control signals PWM1 and PWM2 based on the turn-on trigger signal Von and the turn-off trigger signal Voff.

[0083] The drive circuit 130, for example, outputs a valid control signal PWM1 when the turn-on trigger signal Von is valid, outputs an invalid control signal PWM1 when the turn-off trigger signal Voff is valid, and outputs a valid control signal PWM2 when the control signal PWM1 is invalid or after a first dead time following its invalidation, and outputs an invalid control signal PWM2 after a predetermined turn-on time of the rectifier diode Q2 or after the zero-crossing detection signal ZCD is detected. The turn-on time of the power transistor Q1 (denoted as Ton) is the time during which the control signal PWM1 is valid, specifically the time period from the moment the turn-on trigger signal Von is detected to the moment the turn-off trigger signal Voff is detected to become valid; the turn-on time of the rectifier diode Q2 (denoted as Bon) is the time during which the control signal PWM2 is valid.

[0084] Unless otherwise specified, this article mainly uses the high-level state as the valid state of each signal for example. However, it can be understood that in actual applications, the valid state of each signal can be either high-level or low-level.

[0085] In some embodiments, the control circuit 100 further includes a mode switching circuit, which is used to detect at least one signal parameter of the power converter to determine the current load state, and control the power converter to operate in different operating modes according to the detected different load states. (Reference) Figure 9 This includes, but is not limited to: controlling the power converter to operate in Continuous Conduction Mode (CCM) when the load condition is greater than the first threshold (e.g., before time t1), and controlling the power converter to operate in Discontinuous Conduction Mode (DCM) when the load condition is less than the second threshold (e.g., after time t1).

[0086] Assuming the switching cycle of the power converter is T, in CCM mode, the inductor current (denoted as IL) of the power converter will rise from a non-zero value in each switching cycle, then fall back to that non-zero value, and repeat the cycle. At this time, the sum of the rise time and fall time of the inductor current IL is equal to T. In DCM mode, if the inductor current rises from zero in each switching cycle, then falls back to zero and remains there for a period of time, the sum of the rise time and fall time of the inductor current IL is less than T.

[0087] For example, the turn-on trigger signal generation circuit 110 may be a comparator circuit (not shown) that compares the output feedback signal VFB, which characterizes the output voltage Vout, with the second reference voltage Vref2, thereby generating the turn-on trigger signal Von. Of course, the turn-on trigger signal generation circuit 110 may also be implemented in other ways, and this application does not impose strict limitations on it.

[0088] Continue to refer to Figure 1 The conduction time control circuit 120 further includes: a charging current generating circuit 121, switches S1 and S2, a capacitor C1, and a comparison unit 122. The charging current generating circuit 121 provides a charging current Ich. Switch S1 is controlled by a control signal PWM1 and conducts during the active period of PWM1. Switch S2 is controlled by the inverted signal PWM1_n of PWM1 and conducts during the inactive period of PWM1. During the active period of switch S1, the charging current Ich charges capacitor C1. During the active period of switch S2, capacitor C1 discharges to ground based on switch S2. The first terminal of the comparison unit 122 receives the voltage on capacitor C1, and the second terminal receives a first reference voltage Vref1. The comparison unit 122 compares the voltage on capacitor C1 with the second reference voltage Vref2. When the voltage on capacitor C1 is greater than the first reference voltage Vref1, a valid turn-off trigger signal Voff is output; when the voltage on capacitor C1 is less than the first reference voltage Vref1, an invalid turn-off trigger signal Voff is output. The first reference voltage Vref1 is obtained by sampling the output voltage Vout. For example, the first reference voltage Vref1 is equal to k0·Vout, where k0 is the sampling coefficient and 0 <k0<1。

[0089] Figure 2 A schematic diagram of a frequency-locking implementation circuit for a power converter in related technologies is shown, combined with... Figure 1 and Figure 2 In this related technology, the charging current Ich provided by the charging current generation circuit 121 is obtained solely from the voltage-to-current operation of the input voltage Vin. The power converter utilizes comparator 210 to achieve frequency locking. The positive input of comparator 210 receives the voltage V1 generated by current source I1 flowing through capacitor C2 during the validity period of the clock signal clk11, and the negative input of comparator 210 receives the voltage V2 generated by current source I2 flowing through capacitor C3 during the validity period of the reference clock signal ref_clk1. The output of comparator 210 is connected to the reference voltage adjustment circuit 220. The output current of current source I1 is equal to the output current of current source I2, and the capacitance values ​​of capacitors C2 and C3 are equal.

[0090] Figure 2In the example shown, the validity period of the clock signal clk11 is equal to the current operating cycle of the main power transistor Q1 (i.e., fs_actual represents the total duration of the actual frequency of the control signal PWM1, and in CCM mode, the validity period of the clock signal clk11 is equal to Ton + Bon = The validity period of the reference clock signal ref_clk1 is equal to the reference period (i.e., (where fs_ref represents the reference frequency). Furthermore, the clock signal clk11 controls the current source I1 to charge capacitor C2 for a duration equal to the current operating cycle, and the reference clock signal ref_clk1 controls the current source I2 to charge capacitor C3 for a duration equal to the reference cycle fs_ref.

[0091] When voltage V1 is greater than voltage V2, it means Greater than When the actual frequency fs_actual of the control signal PWM1 is less than the reference frequency fs_ref, the comparator 210 controls the reference voltage adjustment circuit 220 to decrease the first reference voltage Vref1 in increments of ΔV each cycle. This results in the on-time Ton of the main power transistor Q1 decreasing after multiple switching cycles, and the actual frequency fs_actual of the control signal PWM1 increasing. When voltage V1 is less than voltage V2, it indicates... Less than When the actual frequency fs_actual of the control signal PWM1 is greater than the reference frequency fs_ref, the comparator 210 controls the reference voltage adjustment circuit 220 to increase the first reference voltage Vref1 in increments of ΔV each cycle. This results in the on-time Ton of the main power transistor Q1 increasing after multiple switching cycles, and the actual frequency fs_actual of the control signal PWM1 decreasing. Thus, by continuously adjusting the first reference voltage Vref1, the switching frequency of the power converter can be dynamically locked to the system-specified reference frequency fs_ref.

[0092] Figure 3 This diagram illustrates a scheme for achieving low ripple under light load in a power converter in related technologies. Figure 1 , Figure 2 and Figure 3In this related technology, the power converter mainly utilizes comparator 310 to lock the conduction time of rectifier diode Q1 under light load, thereby achieving low ripple under light load. Specifically, the positive input terminal of comparator 310 receives the voltage V4 generated by current source I4 flowing through capacitor C4 during the validity period of clock signal clk12, and the negative input terminal of comparator 310 receives the voltage V4 generated by current source I3 flowing through capacitor C5 during the validity period of reference clock signal ref_clk2. The output terminal of comparator 310 outputs a lock signal hold. The output current of current source I3 is equal to the output current of current source I4, and the capacitance values ​​of capacitors C4 and C5 are equal. Figure 3 In this context, the validity period of clock signal clk12 is equal to the sum of the on-time Ton of power transistor Q1 and the on-time Bon of rectifier transistor Q2, and the validity period of reference clock signal ref_clk2 is equal to half the validity period of reference clock signal ref_clk1 (i.e., Furthermore, the clock signal clk12 controls the current source I4 to charge capacitor C4 for each time, with the duration equal to Ton + Bon. The reference clock signal ref_clk2 controls the current source I3 to charge capacitor C5 for each time, with the duration equal to half of the reference cycle.

[0093] If voltage V4 is greater than voltage V3 during the load reduction process, it indicates that... Greater than At this time, comparator 210 controls reference voltage adjustment circuit 220 to decrease the first reference voltage Vref1 in increments of ΔV, until the first reference voltage Vref1 is reduced to half of its original value. Then, voltage V4 is less than voltage V3, indicating that... Less than At this time, comparator 210 outputs a valid lock signal hold, which controls the reference voltage adjustment circuit 220 to stop adjusting the first reference voltage Vref1, thereby locking the first reference voltage Vref1.

[0094] However, Figure 2 and Figure 3 The related technologies shown have the following problems:

[0095] 1. When the power converter achieves frequency locking in CCM mode, it relies on the output state of comparator 210. Comparator 210 only has two output states: high level and low level. This makes the power converter's frequency locking in CCM mode stable between two states: [-ΔV, +ΔV]. This means that the frequency locking control accuracy depends on the size of the step value ΔV. If ΔV is large, the frequency locking control accuracy of the power converter cannot be guaranteed. If ΔV is small, it will result in a slow regulation rate of the first reference voltage Vref1, which may not keep up with the load or the change rate of the input voltage Vin and the output voltage Vout.

[0096] 2. The related technical solution requires multiple switching cycles to adjust the second reference voltage when performing frequency locking and achieving low ripple under light load, resulting in slow response speed and the need to apply a large number of triggers, leading to a large system area.

[0097] 3. The main sources of error in this technical solution are capacitor, charging current Ich, current sources I1~I4 and their matching. Multiple test modes are required for adjustment during the design process, which is complicated and involves many steps.

[0098] Based on this, the implementation scheme of the conduction time control circuit 120 in this application embodiment is optimized, including the charging current Ich, the frequency locking implementation method, and the implementation method of achieving light load and small ripple (i.e., locking the conduction time of the main power transistor Q1). This makes the system respond faster to frequency locking and locking the conduction time of the main power transistor Q1, and has higher control accuracy. It can achieve light load and small ripple with a smaller area and higher stability accuracy.

[0099] Figure 4a A schematic diagram illustrating an embodiment of the charging current generating circuit provided in the first embodiment of this application is shown. Figure 4b A schematic diagram illustrating an embodiment of the charging current generating circuit provided in the second embodiment of this application is shown. Figure 5 It shows Figure 4a and / or Figure 4b A schematic diagram illustrating the implementation of the second current generating unit and the latching unit. Figure 6 It shows Figure 5 A schematic diagram illustrating the implementation of the sample-and-hold unit in the diagram. Figure 7 It shows Figure 6 A schematic diagram illustrating the implementation of the comparator in the diagram.

[0100] refer to Figure 4a and Figure 4bIn this embodiment, the charging current generating circuit 121 provides a charging current Ich to capacitor C1 during the conduction of switch S1, which is determined at least based on the first current Ivin, the second current IR, and the first compensation current Ioffset1. The first current Ivin is related to the input voltage Vin and / or the output voltage Vout of the power converter. For example, when the power converter is a buck converter, the first current Ivin is positively correlated with the input voltage Vin, and the first reference voltage Vref1 is positively correlated with the output voltage Vout. This can be written as: Ivin = k1 * Vin, Vref1 = k11 * Vout, where k1 and k11 are positive numbers and can be set according to actual conditions. When the power converter is a boost converter, the first current Ivin is positively correlated with the output voltage Vout. When the input voltage Vout is positively correlated with the output voltage Vout, the first reference voltage Vref1 is positively correlated with the difference between the input voltage Vout and the output voltage Vin, which can be written as: Ivin = k1 * Vout, Vref1 = k11 * (Vout - Vin). When the power converter is a buck-boost converter, the first current Ivin is positively correlated with the sum of the input voltage Vin and the output voltage Vout. In this case, the first reference voltage Vref1 is positively correlated with the output voltage Vout, which can be written as: Ivin = k1 * (Vout + Vin), Vref1 = k11 * Vout. The second current IR is generated based on the first voltage signal (denoted as VRf), that is, the second current IR is positively correlated with the first voltage signal VRf, and the first voltage signal VRf is determined based on the frequency error between the control signal PWM1 of the main power transistor Q1 and the reference clock signal ref_clk1. The first compensation current Ioffset1 is a constant current.

[0101] Specifically, in Figure 4a In the illustrated embodiment, the charging current Ich is equal to the sum of the first current Ivin and the second current IR, minus the first compensation current Ioffset1, i.e., Ich = Ivin + IR - Ioffset1. Figure 4b In the embodiment shown, the charging current Ich is equal to the sum of the first current Ivin and the first compensation current Ioffset1, minus the second current IR, i.e., Ich = Ivin + Ioffset1 - IR.

[0102] Furthermore, when the power converter needs to lock the on-time of the main power transistor Q1, the charging current generating circuit 121 locks the on-time Ton of the main power transistor Q1 by voltage locking the first voltage signal VRf.

[0103] In specific implementation, such as Figure 4a and Figure 4bAs shown, the common connection node between the output terminal of the charging current generating circuit 121 and the switch S1 is node A, and the common connection node between the switch S1 and the capacitor C1 is node B. The charging current generating circuit 121 further includes: a first current generating unit 410, a second current generating unit 420, a latching unit 430, and a first compensation current generating unit 440.

[0104] The first current generation unit 410 generates a first current Ivin. The second current generation unit 420 amplifies the control signal PWM1 and the reference clock signal ref_clk1 of the main power transistor Q1 to generate an error, generates a first voltage signal VRf based on the error amplification result, and converts the first voltage signal VRf into a voltage-to-current converter to generate a second current IR. The voltage locking unit 430 uses a first limiting voltage (denoted as Fll_vclamp) to lock the first voltage signal VRf when the power converter needs to lock the on-time of the main power transistor Q1. The first compensation current generation unit 440 provides a first compensation current Ioffset1.

[0105] Optionally, the second current IR generated by the second current generating unit 420 can be provided to node A, for example, through a current mirror 450. Figure 4a In the embodiment shown, the charging current Ich = Ivin + k2 * IR - Ioffset1; Figure 4b In the illustrated embodiment, the charging current Ich = Ivin + Ioffset1 - k2 * IR, where k2 is the mirror ratio of the current mirror (450°). Figure 4a In the example shown, the current mirror 450 includes transistors M1 and M2, both of which are P-type transistors, and the width-to-length ratio of transistors M2 and M1 is k2. Figure 4b In the example shown, the current mirror 450 includes transistors M1, M2, M11, and M12. Transistors M1 and M2 are both P-type transistors, and transistors M11 and M12 are both N-type transistors. The product of the width-to-length ratio of transistors M2 and M1 and the width-to-length ratio of transistors M12 and M11 is k2.

[0106] exist Figure 5In the example shown, the second current generating unit 420 further includes: a frequency-to-voltage module 520, a frequency-to-voltage module 540, an error amplifier 550, a transistor M3, and a resistor Rf. The frequency-to-voltage module 520 is used to convert the control signal PWM1 of the main power transistor Q1 into a voltage signal f2v1; the frequency-to-voltage module 540 is used to convert the reference clock signal ref_clk1 into a voltage signal f2v2; the first input terminal of the error amplifier 550 receives the voltage signal f2v1 corresponding to the control signal PWM1 of the main power transistor, the second input terminal of the error amplifier 550 receives the voltage signal f2v2 corresponding to the reference clock signal ref_clk1, and the output terminal of the error amplifier 550 outputs a second voltage signal ngate characterizing the error between the control signal PWM1 and the reference clock signal ref_clk1; the control terminal of the transistor M3 receives the second voltage signal ngate, the first transmission terminal of the transistor M3 is connected to the first end of the first resistor Rf, the second end of the first resistor Rf is connected to the reference ground, and the second current generating unit 420 generates a second current IR at the second transmission terminal of the transistor M3. Wherein, the first voltage signal VRf is the voltage across the first terminal of the first resistor Rf, and the second voltage signal ngate can characterize the first voltage signal VRf. Wherein, the higher the frequency of the clock signal input to the frequency-to-voltage module 520 and the frequency-to-voltage module 540, the lower the output voltage.

[0107] Optionally, transistor M3 is, for example, an N-type transistor.

[0108] During operation, when the hold signal is invalid, if the frequency of the control signal PWM1 is less than the frequency of the reference clock signal ref_clk1, then f2v1 > f2v2. At this point, under the combined action of the error amplifier 550 and transistor M3, the second current IR increases, and the charging current Ich increases, thus reducing the on-time (Ton_CCM) of the main power transistor Q1 in CCM mode. Conversely, if the frequency of the control signal PWM1 is greater than the frequency of the reference clock signal ref_clk1, the charging current Ich decreases, thus increasing the on-time (Ton_CCM) of the main power transistor Q1 in CCM mode. This process continues until the frequency of the control signal PWM1 equals the frequency of the reference clock signal ref_clk1, at which point f2v1 = f2v2. The adjustment process then stops, the loop stabilizes, and the switching frequency of the power converter is fixed, achieving frequency locking.

[0109] It is understood that the conduction time control circuit 120 disclosed in the embodiments of this application can realize the analog frequency locking of the power converter based on the charging current generation circuit 121, which solves the problem that the power converter's switching frequency locking in CCM mode will be stable between the two states of [-ΔV, +ΔV], and the frequency locking result is more stable and accurate.

[0110] Furthermore, when the power converter needs to lock the on-time of the main power transistor Q1, the latching unit 430 is configured to limit the first voltage signal VRf from exceeding the first limit voltage Fll_vclamp.

[0111] Continue to refer to Figure 5 The latching unit 430 includes a switch S8 and a voltage regulation unit 580. The control terminal of switch S8 receives a latching signal hold, which becomes active when the power converter needs to lock the on-time of the main power transistor Q1, thereby controlling switch S8 to turn on. The voltage regulation unit 580 compares a first voltage signal VRf with a first limiting voltage Fll_vclamp when switch S8 is on, and decreases the first voltage signal VRf when VRf is greater than the first limiting voltage Fll_vclamp, thereby limiting VRf from exceeding the first limiting voltage Fll_vclamp.

[0112] The hold signal is provided, for example, by the hold signal generation unit 560, see reference. Figure 9 When the lock signal generation unit 560 detects that the power converter needs to lock the conduction time of the main power transistor Q1 (such as at time t2), it outputs a valid lock signal hold.

[0113] exist Figure 5 In the illustrated embodiment, switch S8 is connected between the control terminal of transistor M3 and voltage regulation unit 580. In this case, voltage regulation unit 580 adjusts the first voltage signal VRf by adjusting the second voltage signal ngate. Of course, in other embodiments, switch S8 can also be directly connected between the first terminal of resistor Rf and voltage regulation unit 580, so that voltage regulation unit 580 can directly adjust the first voltage signal VRf.

[0114] In specific implementation, such as Figure 5As shown, the voltage regulation unit 580 further includes: a current source I5 and transistors M4 to M10. The control terminal of transistor M4 is connected to the first transmission electrode of transistor M4, and the first transmission electrode of transistor M4 receives a second voltage signal ngate through switch S8; the control terminal of transistor M7 receives a first limiting voltage Fll_vclamp, and the first transmission electrode of transistor M7 is connected to the current source I5; the control terminal of transistor M8 is connected to the second transmission electrode of transistor M4, and the first transmission electrode of transistor M8 is connected to the current source I5; transistors M9 and M10 form a first current mirror structure, with transistor M9 connected between the second transmission electrode of transistor M7 and reference ground, and transistor M10 connected between the second transmission electrode of transistor M8 and reference ground; transistors M6 and M5 form a second current mirror structure, with transistor M6 connected between the second transmission electrode of transistor M7 and reference ground, and transistor M5 connected between the control terminal of transistor M8 and reference ground. Figure 5 In the embodiment shown, transistors M7 and M8 are P-type transistors, and transistors M4~M6 and M9~M10 are N-type transistors.

[0115] Preferably, the threshold voltages of transistor M3 and transistor M4 are matched. For example, the threshold voltages of transistor M3 and transistor M4 are equal or approximately equal.

[0116] During operation, if the second voltage signal ngate is greater than the first limiting voltage Fll_vclamp, the control terminal voltage of transistor M8 is higher than the first limiting voltage Fll_vclamp. At this time, the current flowing through transistor M8 is less than the current flowing through transistor M7, that is, the current flowing through transistor M9 is less than the current flowing through transistor M7. As a result, the excess current flows through transistor M6. Due to the current mirror effect between transistors M6 and M5, there will also be a current flowing to the reference ground in transistor M5. This current pulls down the second voltage signal ngate through transistor M4, thereby reducing the first voltage signal VRf. Conversely, if the second voltage signal ngate is less than the first limiting voltage Fll_vclamp, there will be no current flowing to the reference ground in transistor M5, and therefore it will not affect the second voltage signal ngate.

[0117] It is understandable that when the power converter needs to lock the on-time of the main power transistor Q1, the voltage regulation unit 580 will limit the first voltage signal VRf to a level less than or equal to the first limiting voltage Fll_vclamp, thereby locking the voltage of the first voltage signal VRf and ultimately locking the on-time Ton of the main power transistor Q1. This ensures that the on-time Ton of the main power transistor Q1 will not exceed the on-time threshold corresponding to the first limiting voltage Fll_vclamp, thus realizing the light-load, low-ripple function of the power converter.

[0118] In some embodiments, the locking unit 430 obtains the first limiting voltage Fll_vclamp by sampling and holding the first voltage signal VRf. In other embodiments, the locking unit 430 may also obtain the first limiting voltage by storing energy in the first voltage signal VRf using a capacitor. This method is simple to implement, but under extremely light load conditions, the capacitor charge may leak, resulting in the loss of the first limiting voltage, which reduces the accuracy of voltage locking and may even lead to voltage loss of lockout.

[0119] The following section provides a detailed explanation of the scheme by which the locking unit 430 obtains the first limiting voltage Fll_vclamp by sampling and holding the first voltage signal VRf.

[0120] exist Figure 5 In the embodiment shown, the latching unit 430 further includes a sample and hold unit 570, which is used to determine the voltage range of the first voltage signal VRf based on a plurality of threshold voltages, and output the upper limit threshold voltage corresponding to the voltage range as a first limiting voltage Fll_vclamp.

[0121] In this embodiment, the sample-and-hold unit 570 specifically includes: a voltage follower, a threshold voltage generation unit, a voltage range determination unit, and a gating unit.

[0122] The voltage follower receives a first voltage signal VRf at its input and outputs a third voltage signal VA at its output. For example, Figure 6 In the example shown, the voltage follower is implemented by an operational amplifier 610. The positive input terminal of the operational amplifier 610 receives the first voltage signal VRf, the negative input terminal of the operational amplifier 610 is connected to the output terminal of the operational amplifier 610, and the operational amplifier 610 outputs the third voltage signal VA.

[0123] A threshold voltage generation unit is used to generate multiple threshold voltages based on a power supply voltage AVDD. For example, the threshold voltage generation unit includes a first resistor string, which divides the power supply voltage AVDD to different degrees to generate the multiple threshold voltages. Figure 6 In the example shown, the first resistor string includes resistors R61, R62, R63, R64, R65 and R66 connected in series between the current source I6 and the reference ground. The threshold voltage generation unit divides the power supply voltage AVDD based on the first resistor string to obtain threshold voltages VRes1 to VRes5, wherein the threshold voltages VRes1 to VRes5 decrease step by step.

[0124] The voltage range determination unit performs analog-to-digital conversion on the third voltage signal VA based on multiple threshold voltages generated by the threshold voltage generation unit to generate a voltage range indication signal. This voltage range indication signal indicates the voltage range of the first voltage signal VRf. For example, the voltage range determination unit includes multiple comparators and logic circuitry. The multiple comparators compare the third voltage signal VA with the multiple threshold voltages according to a clock signal clk2, generating multiple comparison signals. The logic circuitry receives the multiple comparison signals and performs logical processing on them to generate the voltage range indication signal. Figure 6 In the example shown, multiple comparators are included: comparator 621 for comparing the third voltage signal VA with the threshold voltage VRes1, comparator 622 for comparing the third voltage signal VA with the threshold voltage VRes2, comparator 623 for comparing the third voltage signal VA with the threshold voltage VRes3, comparator 624 for comparing the third voltage signal VA with the threshold voltage VRes4, and comparator 625 for comparing the third voltage signal VA with the threshold voltage VRes5; the logic circuit includes: NAND gate logic circuits 641-644, NOT gate logic circuits 631-634, and D latches 651-655. The first input of the NAND gate logic circuit 641 receives the comparison signal output by comparator 621, the second input of the NAND gate logic circuit 641 receives the inverted signal of the comparison signal output by comparator 622 through NOT gate logic circuit 631, and the first input of the NAND gate logic circuit 642 receives the comparison signal output by comparator 622, and... The second input of NOT gate 642 receives the inverted signal of the comparison signal output by comparator 623 through NOT gate 632. The first input of NAND gate 643 receives the comparison signal output by comparator 623. The second input of NAND gate 643 receives the inverted signal of the comparison signal output by comparator 624 through NOT gate 633. The first input of NAND gate 644 receives the comparison signal output by comparator 624. The second input of NAND gate 644 receives the inverted signal of the comparison signal output by comparator 625 through NOT gate 634. The data inputs of D latches 651-655 are connected to the outputs of NAND gates 641-644, respectively. The clock inputs of D latches 651-655 all receive the clock signal Setclk. The non-inverting outputs of D latches 651-655 output voltage range indication signals Qut1-Out5, which are equivalent to multi-bit digital signals. Among them, the clock signal Setclk is, for example, a frequency division signal of the control signal PWM1.

[0125] The gating unit receives multiple threshold voltages generated by the threshold voltage generation unit at its input terminals, and receives a voltage range indication signal generated by the voltage range determination unit at its control terminal. The gating unit is used to select one threshold voltage from the multiple threshold voltages as the first limiting voltage Fll_vclamp based on the voltage range indication signal and output it. For example, the gating unit includes multiple switches, the first terminals of which receive the multiple threshold voltages respectively, the control terminals of which receive the voltage range indication signal, and the second terminals of which are all connected to the output terminal of the sample-and-hold unit 570. Figure 6 In the example shown, the gating unit includes switches S61~S65. The first terminal of switch S61 receives the threshold voltage VRes1, and the second terminal of switch S61 is connected to the output terminal of sample-and-hold unit 570. The control terminal of switch S61 receives the non-inverting output signal Out1 of D latch 651. The first terminal of switch S62 receives the threshold voltage VRes2, and the second terminal of switch S62 is connected to the output terminal of sample-and-hold unit 570. The control terminal of switch S62 receives the non-inverting output signal Out2 of D latch 652. The first terminal of switch S63 receives the threshold voltage VRes3. The second terminal is connected to the output terminal of the sample-and-hold unit 570. The control terminal of switch S63 receives the non-inverting output signal Out3 of D latch 653. The first terminal of switch S64 receives the threshold voltage VRes4. The second terminal of switch S64 is connected to the output terminal of the sample-and-hold unit 570. The control terminal of switch S64 receives the non-inverting output signal Out4 of D latch 654. The first terminal of switch S65 receives the threshold voltage VRes5. The second terminal of switch S65 is connected to the output terminal of the sample-and-hold unit 570. The control terminal of switch S65 receives the non-inverting output signal Out5 of D latch 655.

[0126] During operation, assuming the threshold voltages VRes1~VRes5 are 2.5V, 2V, 1.5V, 1V, and 0.5V respectively, and the first voltage signal VRf is 1.3V when the hold signal switches from an invalid state to an active state, then after comparison by multiple comparators, the comparison signals output by comparators 621~623 are all high-level, and the comparison signals output by comparators 624~625 are all low-level. At this time, the outputs of NAND gate logic circuits 641, 642, and 644 are low-level, and the output of NAND gate logic circuit 643 is high-level. Simultaneously, the clock signal Setclk stops changing, and the D latches 651~655 latch the output signals of the NAND gate logic circuits 641~644 and the output signal of the comparator 625. They also output a voltage range indicator signal "00100", indicating that the voltage value of the first voltage signal VRf is 1.3V, which is within the voltage range [1.0V, 1.5V]. This controls the switch S62 in the gating unit to turn on, using the upper threshold voltage of 1.5V, i.e., the threshold voltage VRes3, corresponding to this voltage range, as the first limiting voltage Fll_vclamp and outputting it. Essentially, after the latch signal hold becomes active, the first limiting voltage Fll_clamp will be equal to the threshold voltage value corresponding to the first voltage signal VRf before the latch signal hold becomes active. This allows for locking the conduction time Ton of the main power transistor Q1 when the latch signal hold is active.

[0127] In some preferred embodiments, reference Figure 7Each comparator in the voltage range determination unit includes: switches S71~S73, capacitors C71 and C72, transistors M71 and M72, current sources I7 and I8, and inverters 710 and 720. The positive terminal of capacitor C71 is connected to the negative terminal of capacitor C72, and the negative terminal of capacitor C71 is connected to the positive terminal of capacitor C73. The first terminal of switch S71 receives the corresponding threshold voltage VRes, the second terminal of switch S71 is connected to the positive terminal of capacitor C71, and the control terminal of switch S71 receives the inverted signal clk2_n of clock signal clk2. The first terminal of switch S72 receives the third voltage signal VA, the second terminal of switch S72 is connected to the positive terminal of capacitor C71, and the control terminal of switch S72 receives clock signal clk2. Transistor M71... The control terminal is connected to the negative terminal of capacitor C71. The first transmission terminal of transistor M71 is connected to current source I7, and the second transmission terminal of transistor M71 is connected to reference ground. Switch S73 is connected between the control terminal and the first transmission terminal of transistor M71, and the control terminal of switch S73 receives the clock signal clk. The control terminal of transistor M72 is connected to the first transmission terminal of transistor M71, and the first transmission terminal of transistor M72 is connected to current source I8. The second transmission terminal of transistor M72 is connected to reference ground. Inverters 710 and 720 are connected in series between the first transmission terminal of transistor M72 and the output terminal of the corresponding comparator. Specifically, the input terminal of inverter 710 is connected to the first transmission terminal of transistor M72, and the output terminal of inverter 720 outputs the corresponding comparison signal. As an example, Figure 7 In this configuration, both transistors M71 and M72 are N-type transistors.

[0128] In this circuit, capacitors C71 and C72 are both var capacitors. When their plates are reversed, their capacitance drops drastically. Therefore, by reversing the connection of capacitors C71 and C72, the capacitance value is always visible regardless of transient voltage changes. During operation, the comparator transmits the third voltage signal VA to capacitors C71 and C72 during the high level of the clock signal clk2, and transmits the corresponding threshold voltage VRes to them during the low level of the clock signal clk2. When the third voltage signal VA is less than the corresponding threshold voltage VRes, transistor M71 is turned on, transistor M72 is turned off, and the inverter 720 outputs a high-level comparison signal. When the third voltage signal VA is greater than the corresponding threshold voltage VRes, transistor M71 is turned off, transistor M72 is turned on, and the inverter 720 outputs a low-level comparison signal. Figure 7 The comparator structure shown is smaller in area while still being able to compare the magnitudes of the input voltages, which is beneficial for achieving small-size circuit designs.

[0129] In summary, the charging current generation circuit shown in Figure 4 can lock the on-time Ton of the main power transistor Q1 when the hold signal is valid. However, changes in other parameters such as system temperature and input voltage Vin can affect the accuracy of locking the on-time Ton.

[0130] Furthermore, Figure 8a A schematic diagram illustrating an embodiment of the charging current generating circuit provided in the third embodiment of this application is shown. Figure 8b A schematic diagram of an embodiment of the charging current generating circuit provided in the fourth embodiment of this application is shown. (Refer to...) Figure 8a and Figure 8b The charging current generating circuit 120 disclosed in these embodiments is basically the same in structure as the charging current generating circuit 120 disclosed in FIG. 4, except that: Figure 8a and Figure 8b In the illustrated embodiment, the charging current generation circuit 120 further includes a compensation unit 460. This compensation unit 460 detects predetermined parameters of the power converter and, when it detects a change in the predetermined parameters that affects the locking effect on the on-time Ton, generates a compensation signal based on the amount of change in the predetermined parameters. In the intermittent conduction mode, it adjusts the charging current Ich based on the compensation signal. That is, the compensation unit 460 can compensate for the change in the predetermined parameters in the charging current Ich in the DCM mode, thereby improving the locking accuracy of the on-time Ton.

[0131] Among them, Figure 8a In the illustrated embodiment, the compensation signal generated by the compensation unit 460 is manifested as a compensation current Ioffset2. In the intermittent conduction mode, the compensation unit 460 can provide this compensation current Ioffset2 to node A or node B to adjust the charging current Ich. Figure 8a In the illustrated embodiment, the compensation signal generated by the compensation unit 460 is a current adjustment signal. In the intermittent conduction mode, the compensation unit 460 can provide the current adjustment signal ctr1 to the first current generating unit 410, and adjust the charging current Ich by adjusting the voltage-to-current coefficient of the first current generating unit 410; or, the compensation unit 460 can also provide the current adjustment signal ctr2 to the first compensation current generating unit 440, and adjust the charging current Ich by adjusting the voltage-to-current coefficient of the first compensation current generating unit 440.

[0132] Optionally, the predetermined parameters include at least one of the input voltage Vin and the system temperature.

[0133] by Figure 8aTaking the illustrated embodiment as an example, during operation, when the predetermined parameter is temperature, if the temperature decreases, the resistance Rf decreases, causing the second current IR to decrease and the conduction time Ton to increase. At this time, the compensation unit 440 provides a temperature-based compensation current to the charging current Ich, making the charging current Ich equal to the sum of the first current Ivin, the second current IR, and the second compensation current Ioffset2, minus the first compensation current Ioffset1, i.e., Ich = Ivin + IR + Ioffset2 - Ioffset1, maintaining the locking effect on the conduction time Ton. If the temperature increases, the resistance Rf increases, causing the second current IR to increase and the conduction time Ton to decrease. However, the conduction time Ton_DCM in DCM mode is still less than half of the conduction time Ton_CCM in CCM mode, so the compensation unit 440 does not perform temperature compensation. If the temperature exceeds the chip's temperature protection point, the system can be shut down and restarted after the temperature recovers.

[0134] When the predetermined parameter is the input voltage Vin, if the input voltage Vin decreases, the duty cycle of the control signal PWM1 needs to increase. In this case, Ton_DCM is still less than or equal to 1 / 2 * Ton_CCM, meaning it won't affect the locking effect on the conduction time To in DCM mode. Therefore, the compensation unit 440 does not perform input voltage compensation. If the input voltage Vin increases, the duty cycle of the control signal PWM1 needs to decrease. In this case, the compensation unit 440 provides a compensation current based on the input voltage Vin to the charging current Ich, making the charging current Ich equal to the sum of the first current Ivin, the second current IR, and the second compensation current Ioffset2, minus the first compensation current Ioffset1, i.e., Ich = Ivin + IR + Ioffset2 - Ioffset1, to maintain the locking effect on the conduction time To.

[0135] Of course, the predetermined parameters can also be any other parameters that affect the accuracy of the conduction time Ton, and the compensation unit 440 can simultaneously or time-divisionally detect and compensate for multiple parameters.

[0136] This application's solution can directly lock the conduction time of the main conductor by locking the voltage when the load is small. This method of locking the conduction time of the main conductor is easier to implement and the locking result is more accurate. It can improve the response speed and control accuracy for light loads and small ripples, and the system area is smaller, with higher accuracy and stronger stability. In addition, when locking the corresponding voltage, the final fixed value of the voltage, i.e., the first limiting voltage, can be obtained by sampling and holding, making the locking effect on the conduction time more stable and accurate.

[0137] Furthermore, this application embodiment also provides a method for controlling the on-time of a power converter. This method can be applied to the control circuit 100 disclosed in any of the foregoing embodiments of this application. In specific implementation, such as... Figure 10 As shown, the control method includes performing the following steps:

[0138] Step 101: Generate a charging current based on the first current, the second current, and the first compensation current. The first current is related to the input voltage and / or output voltage of the power converter, and the second current is obtained based on the first voltage signal.

[0139] Step 102: Charge the first capacitor using the charging current, and compare the voltage on the first capacitor with the second reference voltage to generate a turn-off trigger signal. When the turn-off trigger signal is valid, the main power transistor is turned off.

[0140] Step 103: When the power converter needs to lock the conduction time of the main power transistor, the first voltage signal is voltage locked to lock the conduction time of the main power transistor.

[0141] In specific implementation, the specific implementation of each step in the power converter conduction time control method described above and the technical effects that can be brought about after implementation can be found in the relevant content of the power converter and its control circuit 100 and conduction time control circuit 120 described in the foregoing embodiments, which will not be repeated here.

[0142] In summary, the power converter and its control scheme disclosed in the various embodiments of this application have at least the following advantages:

[0143] 1. The frequency locking is achieved by analog method, which is more stable and accurate. It can ultimately stabilize the system switching frequency at a unique frequency value. The adjustment step and speed are mainly determined by the loop. The response speed and frequency locking speed are much faster than the existing solutions.

[0144] 2. Fewer triggers or latches are used, resulting in a smaller system area;

[0145] 3. The sample-and-hold scheme used when locking the first voltage signal utilizes an ADC-like structure to store the first limiting voltage when the main power transistor needs to be locked during its conduction time, thus avoiding the problem of capacitor leakage and making the voltage locking effect more stable and accurate.

[0146] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A power converter's on-time control circuit, comprising: First capacitor; A charging current generating circuit charges the first capacitor using the charging current during the conduction of the main power transistor in the power converter. The comparison unit compares the voltage on the first capacitor with the first reference voltage to generate a turn-off trigger signal. When the turn-off trigger signal is valid, it triggers the main power transistor to turn off. The charging current generating circuit determines the charging current based on at least a first current, a second current, and a first compensation current. The first current is related to the input voltage and / or output voltage of the power converter, and the second current is generated based on the first voltage signal. When the power converter needs to lock the on-time of the main power transistor, the charging current generating circuit performs voltage locking on the first voltage signal to lock the on-time of the main power transistor.

2. The conduction time control circuit according to claim 1, wherein, The charging current generating circuit includes: A first current generating unit is used to generate the first current; The second current generating unit is used to perform error amplification processing on the control signal and reference clock signal of the main power transistor, generate the first voltage signal according to the error amplification result, and perform voltage-to-current processing on the first voltage signal to generate the second current. A first compensation current generating unit is used to provide the first compensation current; A voltage-locking unit is used to lock the first voltage signal with a first limiting voltage when the power converter needs to lock the on-time of the main power transistor.

3. The conduction time control circuit according to claim 2, wherein, When the power converter needs to lock the on-time of the main power transistor, the locking unit limits the first voltage signal to no more than a first predetermined voltage.

4. The conduction time control circuit according to claim 2 or 3, wherein, The locking unit obtains the first defined voltage by sampling and holding the first voltage signal.

5. The conduction time control circuit according to claim 3, wherein, The locking unit includes: The first switch is activated when the power converter needs to lock the on-time of the main power transistor. A voltage regulation unit is configured to compare the first voltage signal and the first limiting voltage when the first switch is turned on, and to reduce the first voltage signal when the first voltage signal is greater than the first limiting voltage, so as to limit the first voltage signal from exceeding the first limiting voltage.

6. The conduction time control circuit according to claim 4, wherein, The locking unit includes: The sample-and-hold unit is used to determine the voltage range of the first voltage signal based on multiple threshold voltages, and output the upper threshold voltage corresponding to the voltage range as the first defined voltage.

7. The conduction time control circuit according to claim 5, wherein, The second current generating unit includes: The first frequency-to-voltage module is used to convert the control signal of the main power transistor into a voltage signal; The second frequency-to-voltage module is used to convert the reference clock signal into a voltage signal; The error amplifier receives a voltage signal corresponding to the control signal of the main power transistor at its first input terminal, receives a voltage signal corresponding to the reference clock signal at its second input terminal, and outputs a second voltage signal at its output terminal. The first transistor has a control terminal that receives the second voltage signal, a first transmission electrode that is connected to the first end of a first resistor, a second end of the first resistor that is connected to a reference ground, and a second current generating unit that generates the second current at the second transmission electrode of the first transistor. The first voltage signal is the voltage across the first terminal of the first resistor.

8. The conduction time control circuit according to claim 7, wherein, The voltage regulation unit regulates the first voltage signal by adjusting the second voltage signal.

9. The conduction time control circuit according to claim 8, wherein, The voltage regulation unit includes: The second transistor has its control terminal connected to the first transmission electrode, and the first transmission electrode receives the second voltage signal through the first switch. The third transistor has a control terminal that receives the first limited voltage and a first transmission electrode that is connected to the first current source. The fourth transistor has its control terminal connected to the second transmission terminal of the second transistor, and its first transmission terminal connected to the first current source. A fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor forming a first current mirror structure, the fifth transistor being connected between the second transmission electrode of the third transistor and the reference ground, and the sixth transistor being connected between the second transmission electrode of the fourth transistor and the reference ground; The seventh transistor and the eighth transistor form a second current mirror structure. The seventh transistor is connected between the second transmission electrode of the third transistor and the reference ground, and the eighth transistor is connected between the control terminal of the fourth transistor and the reference ground.

10. The conduction time control circuit according to claim 6, wherein, The sample-and-hold unit includes: A voltage follower receives the first voltage signal at its input and outputs a third voltage signal at its output. A threshold voltage generation unit generates the plurality of threshold voltages based on the power supply voltage; A voltage range determination unit is used to perform analog-to-digital conversion processing on the third voltage signal based on the plurality of threshold voltages to generate a voltage range indication signal, wherein the voltage range indication signal is used to indicate the voltage range in which the first voltage signal is located; The gating unit receives the plurality of threshold voltages at its input terminal and the voltage range indication signal at its control terminal, and is used to select one threshold voltage from the plurality of threshold voltages as the first limited voltage output according to the voltage range indication signal.

11. The conduction time control circuit according to claim 10, wherein, The threshold voltage generating unit includes a first resistor string, which generates the plurality of threshold voltages by dividing the power supply voltage to different degrees through the first resistor string.

12. The conduction time control circuit according to claim 10, wherein, The voltage range determination unit includes: Multiple comparators are used to compare the third voltage signal with multiple threshold voltages respectively according to a first clock signal, and generate multiple comparison signals; A logic circuit receives the plurality of comparison signals and performs logical processing on the plurality of comparison signals to generate the voltage range indication signal.

13. The conduction time control circuit according to claim 2, wherein, The charging current generating circuit further includes: The compensation unit is used to detect predetermined parameters of the power converter, generate a compensation signal based on the amount of change of the predetermined parameters when a change is detected, and adjust the charging current based on the compensation signal in the intermittent conduction mode.

14. The conduction time control circuit according to claim 13, wherein, The predetermined parameters include at least one of the input voltage and system temperature.

15. The conduction time control circuit according to claim 1, wherein, The charging current is equal to the sum of the first current and the second current, minus the first compensation current; or, The charging current is equal to the sum of the first current and the first compensation current, minus the second current.

16. A power converter, comprising: The main power transistor and a control circuit for controlling the switching state of the main power transistor, the control circuit including the conduction time control circuit as described in any one of claims 1-15.

17. A method for controlling the on-time of a power converter, comprising: A charging current is generated based on a first current, a second current, and a first compensation current. The first current is related to the input voltage and / or output voltage of the power converter, and the second current is obtained based on the first voltage signal. The charging current is used to charge the first capacitor, and the voltage on the first capacitor is compared with the first reference voltage to generate a shutdown trigger signal. When the shutdown trigger signal is valid, the main power transistor is triggered to shut down. When the power converter needs to lock the on-time of the main power transistor, the first voltage signal is voltage locked to lock the on-time of the main power transistor.

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