Spread spectrum modulator

Abstract

The invention relates to a spread spectrum modulator. A circuit (400) includes a switching converter (110), an oscillator (130), and a spread spectrum modulator (SSM) (420). The oscillator (130) has a modulated input and a clock output. The clock output is coupled to the switching converter (110). The oscillator (130) is configured to generate a clock signal at the clock output having a frequency based on a modulated signal at the modulation input. The SSM (420) has a modulated output coupled to the modulated input of the oscillator. The SSM (420) is configured to generate the modulated signal at the modulation output while adjusting a rate of change of the modulated signal based on a magnitude of the modulated signal at a boundary of a modulation time period.

Description

Technical Field

[0001] This application relates to a spread spectrum modulator. Background Technology

[0002] Switching power converters (SPDs) include or are coupled to an oscillator that generates a clock signal to control the state of the transistors switching within the SPD. For some SPDs, the clock frequency is fixed. A fixed clock frequency can cause the SPD to generate electromagnetic interference (EMI), which can adversely affect other devices in the same system. Spread spectrum modulation (SSM) is a technique that varies the clock frequency over a specific time period (modulation period). Varying the clock frequency can reduce the amount of EMI generated by the SPD. Summary of the Invention

[0003] In one example, a circuit includes a switching converter, an oscillator, and a spread spectrum modulator (SSM). The oscillator has a modulation input and a clock output. The clock output is coupled to the switching converter. The oscillator is configured to generate a clock signal at the clock output having a frequency based on the modulation signal at the modulation input. The SSM has a modulation output coupled to the modulation input of the oscillator. The SSM is configured to generate a modulation signal at the modulation output while adjusting the rate of change of the modulation signal based on the magnitude of the modulation signal at the boundaries of the modulation time period.

[0004] In another example, a circuit includes a switching converter, an oscillator, and an SSM. The oscillator has a modulation input and a clock output. The clock output is coupled to the switching converter. The oscillator is configured to generate a clock signal at the clock output having a frequency based on the modulation signal at the modulation input. The SSM has a modulation output coupled to the modulation input of the oscillator. The SSM is configured to generate a modulation signal at the modulation output while adjusting the rate of change of the modulation signal based on the magnitude of the modulation signal and the modulation clock signal.

[0005] In yet another example, a circuit includes an oscillator having a modulation input and a clock output. The oscillator is configured to generate a clock signal at the clock output having a frequency based on the modulation signal at the modulation input. The modulator has a modulation output coupled to the modulation input of the oscillator. The modulator is configured to generate a modulation signal at the modulation output while adjusting the rate of change of the modulation signal based on the magnitude of the modulation signal at the boundaries of the modulation time period. Attached Figure Description

[0006] Figure 1 This is a block diagram of a power converter in an example.

[0007] Figure 2 It is the waveform of the instance clock frequency of the power converter.

[0008] Figure 3 This is a graph showing the reduction in average and peak electromagnetic interference relative to the modulation period of the power converter in one example.

[0009] Figure 4 This is a block diagram of a power converter with a self-tuned spread spectrum modulator in another example.

[0010] Figure 5 , 6 And 7 are shown in various instances Figure 4 The waveforms of the self-tuning spread spectrum modulator operating under different duty cycle conditions.

[0011] Figure 8 In an instance Figure 4 A schematic diagram of a self-tuning spread spectrum modulator.

[0012] Figure 9 In another instance Figure 4 A schematic diagram of a self-tuning spread spectrum modulator. Detailed Implementation

[0013] Use the same reference numerals or other reference numerals in the drawings to indicate the same or similar (functional and / or structural) features.

[0014] Figure 1 This is a schematic diagram of a power converter 100 in one example. The power converter 100 converts an input voltage VIN to an output voltage VOUT. In this example, the power converter 100 includes a switching converter 110, a spread spectrum modulator (SSM) 120, an oscillator 130, a digital isolator 140, a comparator 150, a reference voltage circuit 155, an AND gate 160 (or other type of logic gate), and an electromagnetic interference (EMI) filter 170. The switching converter 110 includes input terminals 110a and 110b and output terminals 110c and 110d. Input terminals 110a and 110b are coupled to the input voltage VIN and ground GNDP, respectively, via the EMI filter 170. The EMI filter 170 helps reduce the amount of EMI generated by the power converter 100.

[0015] The switching converter 110 in the example power converter 100 is an isolated switching converter, which includes a transformer driver 111, an isolation circuit 112, a rectifier 113, and a gate driver 114. Accordingly, the power converter 100 can be an isolated power converter. The transformer driver 111 is coupled to input terminals 110a and 110b. The transformer driver 111 may include one or more transistors (e.g., half-bridge, full-bridge) driven by a pulse-width modulation (PWM) signal from the gate driver 114. The isolation circuit 112... Figure 1 In this example, the circuit is a transformer, referred to as transformer 112. In other examples, the isolation circuit can be different types of isolators, such as optical isolators or capacitive isolators. The primary winding 112a of transformer 112 is coupled to transformer driver 111. The secondary winding 112b of transformer 112 is coupled to rectifier 113. The output of rectifier 113 is coupled to output terminals 110c and 110d to provide the output voltage VOUT and isolation ground GNDS, respectively. The input voltage VIN is converted into a time-varying voltage by transformer driver 111, which transfers energy to rectifier 113 via primary winding 112a and secondary winding 112b. Rectifier 113 then rectifies the voltage from secondary winding 112b to the output voltage VOUT.

[0016] SSM 120 has a control input 120a and a modulation output 120b. Oscillator 130 has a modulation input 130a and a clock output 130b. AND gate 160 has inputs 160a and 160b and an output. Comparator 150 has a negative (-) input, a positive (+) input, and an output 150a. Digital isolator 140 has input 140a and output 140b. Output 140b of digital isolator 140 is coupled to input 160b of AND gate 160 and control input 120a of SSM 120. Modulation output 120b of SSM 120 is coupled to modulation input 130a of oscillator 130. Clock output 130b of oscillator 130 is coupled to input 160a of AND gate 160. Output of AND gate 160 is coupled to input 114a of gate driver 114. Output 114b of gate driver 114 is coupled to transformer driver 111.

[0017] Output terminal 110c is coupled to the negative input of comparator 150. The reference voltage VREF generated by reference voltage circuit 155 is provided to the positive input of comparator 150. If the output voltage VOUT is lower than the reference voltage VREF, the output signal from comparator 150 will be logic high, and if the output voltage VOUT is higher than the reference voltage VREF, the output signal will be logic low. The output signal from comparator 150 is provided as signal PSON to control input 120a of AND gate 160 and SSM 120 via digital isolator 140.

[0018] The switch converter 110 is turned on or off based on the logic state of the signal PSON from the output 140b of the digital isolator 140. Figure 1In this example, the switch converter 110 is turned on when the signal PSON is logic high and turned off when the signal PSON is logic low. When the signal PSON is logic high, a clock signal (CLK) from the oscillator 130 is provided to the gate driver 114 via the AND gate 160 to turn the transistor switches within the transformer driver 111 on and off based on the clock signal CLK. When the switch converter 110 is on, energy is transferred across the isolation circuit 112, and the output voltage VOUT increases (e.g., linearly). When the output voltage VOUT rises above the reference voltage VREF, the output signal from the comparator 150 becomes logic low, and the signal PSON is also forced low. When the signal PSON is logic low, the switch converter 110 is turned off, and the output voltage VOUT decreases.

[0019] When signal PSON is logic high, SSM 120 generates a modulation signal MOD 123, which is provided to oscillator 130. In one example, modulation signal MOD 123 is a digital signal that increases and decreases in an approximately triangular shape. In another example, modulation signal MOD 123 is an analog signal (e.g., voltage) with a triangular waveform. Modulation signal MOD 123 causes oscillator 130 to change the frequency of clock signal CLK, thus also having a triangular shape.

[0020] Figure 2 The frequency (f) of the clock signal CLK SW0 Example waveforms of the clock signal CLK and the corresponding PWM signal from gate driver 114. The frequency of the clock signal CLK has a frequency of t during the modulation period. MOD The frequency distribution within the range changes from a lower frequency 201 to a higher frequency 202 and then returns to a lower frequency 201 in an approximate triangular pattern. The difference between the higher frequency 202 and the lower frequency 201 is the differential frequency Δf. SW The gate driver 114 receives signals whose frequency distribution is... Figure 2 The clock signal CLK is displayed, and a corresponding PWM signal is generated. The frequency of the PWM signal is higher at higher frequencies of the clock signal CLK than at lower frequencies.

[0021] Figure 3 Includes the modulation period t MOD The curves 301 and 302 show the average reduction of EMI as a function of the EMI level. EMI can be calculated as an average or peak value. Curve 301 corresponds to the EMI reduction at the average EMI level. Curve 302 corresponds to the EMI reduction at the peak EMI level. With the modulation period t... MODAs the modulation period increases, the reduction in average EMI decreases. However, with increasing modulation period, the reduction in peak EMI initially decreases between approximately 3 and approximately 5 microseconds. Above 5 microseconds, the reduction in peak EMI increases. Above, for example, 20 microseconds, while the reduction in average EMI is advantageously low, the reduction in peak EMI is undesirably high, and the reduction in peak EMI is undesirably low. The modulation period range 310 is... Figure 3 Shown in and below about Figure 4 Let's have a discussion.

[0022] Figure 4 This is a schematic diagram of a power converter 400, where the spread spectrum modulator is a self-tuned spread spectrum modulator (SSM) 420. The self-tuned SSM 420 modulates the modulation period t by dynamically varying the rate of change of the frequency of the clock signal CLK. MOD Maintain within the range of 310 ( Figure 3 This addresses the aforementioned issues within a specific range. In one example, the modulation period 310 ranges from 8 microseconds to 20 microseconds. Below 8 microseconds, the reduction in both average and peak EMI is unacceptably small, and above 20 microseconds, the reduction in peak EMI is unacceptably small. By dynamically adjusting the modulation frequency of the clock signal CLK across the modulation period range 310, the reduction in both average and peak EMI exceeds the target level.

[0023] Figure 4 The power converter 400 is largely related to Figure 1 The power converter 400 is identical to the power converter 100. The difference between the two power converters is that the power converter 400 includes a self-tuning SSM 420, while the SSM 120 of the power converter 100 does not have self-tuning capability. The self-tuning SSM 420 has a control input 420a and a modulation output 420b. The output 140b of the digital isolator 140 is coupled to the control input 420a of the self-tuning SSM 420. The modulation output 420b of the self-tuning SSM 420 is coupled to the modulation input 130a of the oscillator 130. The self-tuning SSM 420 dynamically adjusts the rate of change of the modulation signal MOD 423 so that the modulation period of the clock signal CLK is within a target range, for example, 8 microseconds to 20 microseconds. In one example, the modulation signal MOD 423 is a voltage such as a ramp voltage, which is used by the oscillator 120 to adjust the frequency of the clock signal CLK.

[0024] Figure 5 , 6 7 represents the frequencies (f) of the output voltage VOUT, signal PSON, and clock signal CLK. SW0 The example waveform of ), and waveform S SWThis indicates a higher duty cycle condition ( Figure 5 ), medium duty cycle conditions ( Figure 6 ) and lower duty cycle conditions ( Figure 7 Waveform S SW It refers to f SW0 The slopes of the rising and falling edges of the triangular waveform—S SW A higher value means f SW0 The absolute value of the slope is higher than S. SW The lower value. First refer to Figure 5 A higher duty cycle condition is reflected in the signal PSON in each burst time period (t BUR Most of the time, the signal PSON is high. When the signal PSON is logic high, the switch converter 110 is turned on and delivers power via the isolation circuit 112. Accordingly, the output voltage VOUT increases, as shown at 501. When the signal PSON is logic low, the switch converter 110 is turned off, and the output voltage VOUT decreases, as shown at 502. The difference between the upper level and the lower level of the output voltage VOUT is ΔVOUT.

[0025] When the signal PSON is logic high, the oscillator 130 adjusts the frequency f of the clock signal CLK. SW0 The modulation signal MOD 423 is increased and decreased at a rate (e.g., slope) based on the rate (as shown at 503 and 504) of increase and decrease. The self-tuned SSM 420 implements a modulation period (t) within a target range (e.g., 8 microseconds to 20 microseconds). MOD During the modulation period 0t MOD(0) Initially, the clock signal CLK is at a low frequency of 505. During the modulation period t... MOD(0) During this period, the self-tuning SSM 420 generates a modulation signal MOD 423 that increases and then decreases. In response to the increasing modulation signal MOD 423, the oscillator 130 generates a clock signal CLK with an increasing clock frequency, as shown at 503. Then, the self-tuning SSM 420 changes the direction of the modulation signal MOD 423, and the modulation signal MOD 423 decreases. The frequency of the clock signal CLK reaches a peak at a higher frequency 506, and then decreases based on the decreasing modulation signal MOD 423, as shown at 504.

[0026] The self-tuning SSM 420 is determined at modulation period 0t. MOD(0) The value of the modulation signal MOD 423 at time point 508 at the end. At time point 508, the modulation signal MOD 423 has not yet reached its value during the modulation period 0t. MOD(0) The initial voltage level, and correspondingly, the frequency f of the clock signal CLK. SW0It has not yet returned to the lower frequency 505. This is in response to determining the frequency F of the modulation signal MOD423 (and the clock signal CLK). SW0 The self-tuning SSM420 has not yet returned to its initial level at the start of the modulation period. It responds by increasing the rate of change of the modulation signal MOD 423 during the next modulation period, which is modulation period 1 (t). MOD(1) This process continues until the value of the modulation signal MOD 423 (and the frequency of the clock signal CLK) at the end of each modulation cycle approximately matches the value of the modulation signal MOD 423 (and the clock frequency) at the beginning of the modulation cycle.

[0027] Figure 5 Another benefit of the self-tuned SSM 420 is demonstrated. When the PSON signal transitions to a logic low level at the falling edge 509 to turn off the switch converter 110, the value of the modulation signal MOD 423 is captured, so that at the next rising edge 510 of the PSON signal, the oscillator 130 receives the same value of the modulation signal and continues by generating the same clock frequency as when the switch converter 110 was previously turned off. By freezing the value of the modulation signal MOD 423 at the end of each modulation cycle and changing the modulation signal MOD only while the power converter is switching, the switch converter 110 can fully utilize the entire frequency modulation range across different duty cycles, while also avoiding sudden changes in the switching frequency.

[0028] Figure 6 This indicates a connection to the preceding text regarding... Figure 5 The same concept is described, but the modulation period (t) MOD Longer than the sudden occurrence time period (t) BUR ).exist Figure 6 In this example, the modulation period spans three burst cycles. As described above, the value of the modulation signal MOD 423 at the rising edge 610 of the PSON signal is the same as the value of the modulation signal MOD at the preceding falling edge 609 of the PSON signal. The self-tuning SSM 420 determines the value of the modulation signal MOD at the end of each modulation cycle and adjusts the rate of change of the modulation signal MOD to increase or decrease the rate so that the period of the modulation signal MOD is incrementally matched to a target period (e.g., 8 microseconds to 20 microseconds).

[0029] Figure 7 This indicates a connection to the preceding text regarding... Figure 5 and 6The same concept is described, but for relatively low duty cycle conditions. As mentioned above, the value of the modulation signal MOD 423 at the rising edge 710 of the PSON signal is the value of the modulation signal MOD at the previous falling edge 709 of the PSON signal. As mentioned above, the self-tuning SSM 420 determines the value of the modulation signal MOD at the end of each modulation cycle and adjusts the rate of change of the modulation signal MOD to increase or decrease the rate so that the period of the modulation signal MOD is incrementally matched to a target period (e.g., 8 microseconds to 20 microseconds).

[0030] Figure 8 This is a schematic diagram of a self-tuning SSM 420 based on an example. In this example, the self-tuning SSM 420 includes a counter 802, register A 804, register B 806, comparator 810, NAND gate 812, flip-flops 814 and 818, and a counter clock generator 816. Figure 8 In this example, counter 802 is an increment / decrement counter, and comparator 810 is a digital comparator. Counter 802 has an enable input 802a, a control input 802b, a clock input 802c, a counter output 802d, an overflow output 802e, and a count-to-zero output 802f. Counter output 802d is coupled to modulation output 420b and register input 804a of register A 804 and register input 806a of register B 806. Register A 804 has clock input 804b and register output 804c. Similarly, register B 806 has clock input 806b and register output 806c. Clock input 806b is an inverted clock input relative to clock input 804b. For example, a modulation clock signal CLK_MOD generated within the self-tuning SSM 420 is coupled to clock inputs 804b and 806b. In one example, the rising edge of the modulation clock signal CLK_MOD causes register A804 to store the digital value Q0 from the counter output 802d of counter 802, and the falling edge of the modulation clock signal CLK_MOD causes register B806 to store the digital value Q0 from the counter output 802d. The output 804c of register A804 is coupled to input A of comparator 810, and the output 806c of register B806 is coupled to input B of comparator 810. Comparator 810 compares the digital values ​​from registers A and B and generates an A>B signal at output 810a. In one example, if the digital value from register A804 is greater than the digital value from register B806, comparator 810 asserts that the A>B signal is logic high, and if the digital value from register A804 is less than the digital value from register B806, comparator 810 asserts that the A>B signal is logic low.

[0031] When the digital value at counter output 802d reaches its maximum value, counter 802 asserts the overflow signal OVF as logic high. Comparator output 810a is coupled to input 812a of NAND gate 812, and overflow output 802e is coupled to input 812b of NAND gate 812. The output of NAND gate 812 is coupled to the data (D) input of flip-flop 814. The clock input of flip-flop 814 receives the modulated clock signal CLK_MOD.

[0032] The counter clock generator 816 includes a counter (e.g., an increment / decrement counter) 820, a frequency divider 822, and a delay circuit 824. The counter 820 has a control input 820a, a clock input 820b, and a counter output 820c. The Q output of a flip-flop 814 provides the signal TUNE and is coupled to the control input 820a of the counter 820. The delay circuit 824 has an input 824a and an output 824b. The input 824a of the delay circuit receives a modulated clock signal CLK_MOD, and the output 824b of the delay circuit is coupled to the clock input 820b of the counter 820. The frequency divider 822 has a clock input 822a, a control input 822b, and a clock output 822c. The clock input 822a receives a clock signal CLK_HF, which may have a higher frequency than the modulated clock signal CLK_MOD. The counter output 820c is coupled to the control input 822b. Frequency divider 822 divides its input clock signal CLK_HF by a factor selected based on the output count value at counter output 820c of counter 820. In one example, the frequency divider has a lookup table (LUT) indexed by the output count value from counter 820. The output clock signal from frequency divider 822 is the clock signal CLK_CNT. The clock output 822c of frequency divider 822 is coupled to the clock input 802c of counter 802.

[0033] The D input of flip-flop 818 is connected to a logic high ("1") signal. The reset (RST) input of D flip-flop 818 is coupled to the count-to-zero output 802f of counter 802, and receives the signal CNT0 from counter 802. When the digital value Q from counter 802... n When the value is 0, the counter 802 asserts the signal CNT0 as a logic high level, and when the digital value Q... n When the value is not 0, the counter asserts the signal CNT0 as logic low. The overflow output 802e from the counter 802 is coupled to the clock input of the flip-flop 818. The output is coupled to the control input 802b of the counter 802.

[0034] When the signal PSON is logic high, counter 802 is enabled and increments or decrements its digital value Q on a given edge (e.g., rising edge) of the clock count signal CLK_CNT from frequency divider 822. n In one example, if the signal output from Qbar of flip-flop 818 is logic high, counter 802 increments its output digital value Q. n Furthermore, if the signal from the Qbar output of the flip-flop 818 is logic low, the counter decrements its output digital value Q. n When the output digital value Q n When the maximum value is reached, the counter 802 asserts that the overflow signal OVF is logic high, and when the output digital value Q... n When the value reaches zero, the assertion signal CNT0 of counter 802 is logic high.

[0035] Register A 804 is timed on the rising edge of the modulation clock signal CLK_MOD and accordingly stores the digital output value Q from counter 802 at the beginning of each modulation time period. n Register B 806 is timed on the falling edge of the modulation clock signal CLK_MOD and accordingly stores the output digital value Q from counter 802 at the end of each modulation time cycle. n The digital value Q output from counter 802 n The modulation signal is MOD 423. Comparator 810 compares the output digital value from counter 802 at the beginning and end of each modulation time period. When the overflow signal OVF is logic high, the comparison result A>B signal is inverted via NAND gate 812. Accordingly, if the A>B signal is logic high, the output signal from NAND gate 812 will be logic low, and flip-flop 814 will latch its TUNE output signal to logic low on the rising edge of the modulation clock signal CLK_MOD. The logic low level of the TUNE output signal causes counter 820 to count down. Counter 820 is timed by a delayed version of the modulation clock signal CLK_MOD via delay circuit 824. If the A>B signal is logic low, the output signal from NAND gate 812 will be logic high, and flip-flop 814 will latch its TUNE output signal to logic high on the rising edge of the modulation clock signal CLK_MOD. The logic high level of the TUNE output signal causes counter 820 to count up.

[0036] The incrementing or decrementing output count value from counter 820 causes frequency divider 822 to divide its input clock signal CLK_HF by different factors. The different frequencies of the frequency divider's output clock signal CLK_CNT cause counter 802 to increment or decrement at different rates, thereby adjusting the rate of change of modulation signal MOD 423.

[0037] Figure 8 The example circuit system of the self-tuned SSM 420 is a digital implementation that generates a modulation signal MOD 423 as a multi-bit digital signal. In this example, oscillator 130 is a digital oscillator. An example of a digital oscillator is a ring oscillator. Accordingly, Figure 8 The oscillator 130 in the middle can be implemented as a ring oscillator.

[0038] Figure 9 This is a schematic diagram of a self-tuned SSM 420 in another example. In this example, the self-tuned SSM 420 includes an SSM ramp generator 910 coupled to a sample-and-hold integrator 950. The SSM ramp generator 910 includes current source circuits 911 and 912, switches 913 and 914 (e.g., transistors), AND gates 915 and 916, a capacitor C1, a voltage summer 917, and a comparator 918. Switch 913 has terminals 913a and 913b and a control input 913c. Switch 914 has terminals 914a and 914b and a control input 914c. Terminal 913a is coupled to current source circuit 911. Terminals 913b and 914a are coupled together and coupled to terminals of capacitor C1 and input 917a of voltage summer 917. The other terminal of capacitor C1 is coupled to ground. In one example, current source circuits 911 and 912 are voltage-controlled current sources. Accordingly, current source circuits 911 and 912 have control inputs 911a and 912a, respectively. Current sources 911 and 912 generate currents proportional to the voltages supplied at their respective control inputs 911a and 912a. The control input 420a of the self-tuned SSM 420 is coupled to inputs 915a and 916a of AND gates 915 and 916, respectively. The output of comparator 918 is coupled to inputs 915b and 916b of AND gates 915 and 916, respectively. In this example, input 916b of AND gate 916 is the inverting input. The output of AND gate 915 is coupled to the control input 913c of switch 913. The output of AND gate 916 is coupled to the control input 914c of switch 914. Capacitor C1 is also coupled to the negative input of comparator 918. The voltage across capacitor C1 is voltage V. SSM Threshold voltage V SSM_TH It is provided to the positive input of comparator 918. Voltage V FFSW0 It can be generated, for example, by a bandgap reference circuit. Voltage V FFSW0The switching frequency at the output 130b of oscillator 130 without an SSM can be correlated and is provided to the input 917b of voltage summer 917. The output 917c of voltage summer 917 is coupled to modulation output 420b and provides modulation signal MOD 423. In this example, modulation signal MOD 423 is an analog signal (e.g., voltage), and oscillator 130 is an analog oscillator, such as a voltage-controlled oscillator. Oscillator 130 generates a clock signal CLK having a frequency proportional to the magnitude of modulation signal 423.

[0039] The sample-and-hold integrator 950 includes a reference voltage generator 951, a transconductance amplifier 952, a single-trigger circuit 953, a switch 954 (e.g., a transistor), and a capacitor C2. The positive input of the transconductance amplifier 952 is coupled to the output 917c of the voltage summer 917 and the modulation output 420b of the self-tuned SSM 420. The output of the reference voltage generator 951 provides the reference voltage V. MOD_TH It is also coupled to the negative input of transconductance amplifier 952. The output of transconductance amplifier 952 is coupled to terminal 954a of switch 954. The other terminal 954b of switch 954 is coupled to capacitor C2 and the control inputs 911a and 912a of current source circuits 911 and 912, respectively. The voltage across capacitor C2 is voltage V. COMP These signals are provided to control inputs 911a and 912a of current source circuits 911 and 912, respectively. A single trigger circuit 953 receives the modulated clock signal CLK_MOD. The output of the single trigger circuit 953 is coupled to the control input of switch 954.

[0040] The modulation signal 423 is a voltage that slopes up when switch 913 is closed and the current from current source circuit 911 charges capacitor C1, and slopes down when switch 914 is closed and capacitor C1 discharges via current source circuit 912. The magnitudes of the charging current to capacitor C1 and the discharging current from said capacitor are given by voltage V. COMP Control is provided to the control inputs 911a and 912a of the corresponding voltage-controlled current sources 911 and 912. The difference between the modulation signal 423 and the threshold voltage VMOD_TH is amplified by the transconductance amplifier 952 and converted into a current. During the pulse generated by the single trigger circuit 953 on each rising edge of the modulation clock signal CLK_MOD, the resulting current from the transconductance amplifier 952 charges the capacitor C2. Accordingly, the voltage V COMP Proportional to the difference between the modulation signal 423 and the threshold voltage VMOD_TH. Figure 9 In this example, the large difference between the modulation signal 423 and the threshold voltage VMOD_TH causes the voltage V across capacitor C2 to... COMPThe larger difference causes the current source circuits 911 and 912 to increase the current generated from them. This increases the rate of change of the modulation signal MOD 423. Similarly, the smaller difference between the modulation signal 423 and the threshold voltage VMOD_TH causes the voltage V... COMP The smaller current source circuits 911 and 912 reduce the current generated from them. This consequently reduces the rate of change of the modulation signal MOD 423.

[0041] In some instances, the modulation signal 423 is a triangular wave. The currents generated by current source circuits 911 and 912 can be approximately the same for a given voltage VCOMP, thus making the modulation signal 423 a triangular wave. In other instances, the modulation signal 423 is a sawtooth wave. The currents generated by current source circuits 911 and 912 can be different for a given voltage VCOMP, thus making the modulation signal 423 a sawtooth wave. For example, to make the modulation signal MOD 423 a sawtooth wave, the discharge current generated by current source circuit 912 can be greater than the charging current generated by current source circuit 911.

[0042] In this specification, the term "coupling" may encompass a connection, link, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0043] Furthermore, in this description, the statement "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0044] A device “configured to” perform a task or function can be configured by the manufacturer at manufacturing time (e.g., programming and / or hardwiring) to perform the function and / or can be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration can be performed via firmware and / or software programming of the device, via the construction and / or layout of the device’s hardware components and interconnections, or a combination thereof.

[0045] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0046] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacture by an end user and / or a third party.

[0047] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors respectively coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors respectively coupled in series between the same two nodes as a single resistor or capacitor.

[0048] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as being external to the integrated circuit may be contained within the integrated circuit, and / or some features shown as being internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0049] The use of the phrase "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "generally" preceding a parameter means within + / - 10% of said parameter, or, if the parameter is zero, within a reasonable range of values ​​near zero.

[0050] Within the scope of the claims, modifications to the described instances are possible, and other instances are also possible.

Claims

1. A circuit comprising: Switch converter; An oscillator having a modulation input and a clock output coupled to the switching converter, the oscillator being configured to generate a clock signal at the clock output having a frequency based on the modulation signal at the modulation input; as well as A spread spectrum modulator (SSM) having a modulation output coupled to the modulation input of the oscillator, the SSM being configured to generate the modulation signal at the modulation output while adjusting the rate of change of the modulation signal based on the magnitude of the modulation signal at the boundary of the modulation time period.

2. The circuit of claim 1, wherein the clock output is a first clock output, and wherein the oscillator has a digital control input, and the SSM comprises: A counter clock generator with a control input and a second clock output; as well as A counter having a clock input and a counter output, the clock input being coupled to a second clock output and the counter output being coupled to the digital control input.

3. The circuit according to claim 2, wherein the counter is an increment / decrement counter.

4. The circuit of claim 2, wherein the counter output is a first counter output, and the counter clock generator comprises: An increment / decrement counter having the control input and a second counter output; as well as A frequency divider having a clock input, a control input, and a second clock output, wherein the control input of the frequency divider is coupled to the second counter output.

5. The circuit of claim 2, wherein the clock input is a first clock input, and the SSM further comprises: A first register having a first register input coupled to the output of the counter, a second clock input, and a first register output; The second register has a second register input coupled to the output of the counter, a third clock input, and a second register output; as well as A comparator having a first comparator input coupled to the output of the first register, a second comparator input coupled to the output of the second register, and a comparator output coupled to the control input of the counter clock generator.

6. The circuit according to claim 1, wherein the SSM comprises: The first voltage-controlled current source circuit has a first control input; The second voltage-controlled current source circuit has a second control input; as well as A sample-and-hold integrator having an input and an output, the input being coupled to the modulation output, and the output of the sample-and-hold integrator being coupled to the first and second control inputs.

7. The circuit of claim 6, wherein the SSM further comprises a capacitor coupled to the first and second voltage-controlled current source circuits.

8. The circuit of claim 6, wherein the sample-and-hold integrator comprises a transconductance amplifier having a first amplifier input coupled to the modulation output and a second amplifier input coupled to a reference voltage generator.

9. The circuit of claim 1, wherein the switching converter comprises an isolated power converter.

10. A circuit comprising: Switch converter; An oscillator having a modulation input and a clock output coupled to the switching converter, the oscillator being configured to generate a clock signal at the clock output having a frequency based on the modulation signal at the modulation input; as well as A spread spectrum modulator (SSM) having a modulation output coupled to the modulation input of the oscillator, the SSM being configured to generate the modulation signal at the modulation output while adjusting the rate of change of the modulation signal based on the magnitude of the modulation signal and a modulation clock signal.

11. The circuit of claim 10, wherein the clock output is a first clock output, and wherein the oscillator has a digital control input, and the SSM comprises: A counter clock generator with a control input and a second clock output; as well as A counter having a clock input and a counter output, the clock input being coupled to a second clock output and the counter output being coupled to the digital control input.

12. The circuit of claim 11, wherein the counter is an increment / decrement counter.

13. The circuit of claim 11, wherein the counter output is a first counter output, and the counter clock generator comprises: An increment / decrement counter having the control input and a second counter output; as well as A frequency divider having a clock input, a control input, and a second clock output, wherein the control input of the frequency divider is coupled to the second counter output.

14. The circuit of claim 11, wherein the clock input is a first clock input, and the SSM further comprises: A first register having a first register input coupled to the output of the counter, a second clock input, and a first register output; The second register has a second register input coupled to the output of the counter, a third inverting clock input, and a second register output; as well as A comparator having a first comparator input coupled to the output of the first register, a second comparator input coupled to the output of the second register, and a comparator output coupled to the control input of the counter clock generator.

15. The circuit of claim 10, wherein the SSM comprises: The first voltage-controlled current source circuit has a first control input; The second voltage-controlled current source circuit has a second control input; A sample-and-hold integrator having an input and an output, the input of the sample-and-hold integrator being coupled to the modulation output, and the output of the sample-and-hold integrator being coupled to the first and second control inputs; as well as A capacitor coupled to the first and second voltage-controlled current source circuits.

16. The circuit of claim 15, wherein the sample-and-hold integrator comprises a transconductance amplifier having a first amplifier input coupled to the modulation output and a second amplifier input coupled to a reference voltage generator.

17. A circuit comprising: An oscillator having a modulation input and a clock output, the oscillator being configured to generate a clock signal at the clock output having a frequency based on the modulation signal at the modulation input; as well as A modulator having a modulation output coupled to the modulation input of the oscillator, the modulator being configured to generate the modulation signal at the modulation output while adjusting the rate of change of the modulation signal based on the magnitude of the modulation signal at the boundary of the modulation time period.

18. The circuit of claim 17, wherein the clock output is a first clock output, and wherein the oscillator has a digital control input, and the modulator comprises: A first increment / decrement counter having a first counter output coupled to the modulation output and having a first clock input; The second increment / decrement counter has a second clock input and a second counter output; as well as A frequency divider having a third clock input coupled to the output of the second counter and a second clock output coupled to the first clock input.

19. The circuit of claim 18, wherein the second increment / decrement counter has a control input, and the circuit further comprises: A first register having a first register input coupled to the output of the first counter and having a first register output; A second register having a second register input coupled to the output of the first counter and having a second register output; as well as A comparator having a first comparator input coupled to the output of the first register, a second comparator input coupled to the output of the second register, and a comparator output coupled to the control input of the second increment / decrement counter.

20. The circuit of claim 17, wherein the oscillator has an analog control input, and wherein the modulator comprises: First voltage-controlled current source circuit; Second voltage-controlled current source circuit; as well as A capacitor, which is coupled to the first and second voltage-controlled current source circuits and to the analog control input of the oscillator.

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