Four-phase clock phase calibration circuit based on digital time converter

Abstract

The invention relates to a four-phase clock phase calibration circuit based on a digital time converter, and solves the technical problems that a four-phase clock phase calibration circuit in the prior art is difficult to realize high-precision calibration and relatively large in phase deviation. The phase error detection circuit comprises a four-phase phase adjustment module with a DTC module, a phase error detection link, a comparison judgment module and a digital calibration logic module, and the phase error detection link is used for selecting a pair of voltage domain signals which are processed and output to represent phase difference information from a four-phase clock output by the four-phase phase adjustment module. The comparison judgment module is used for carrying out judgment according to a voltage domain signal output by the phase error detection link and outputting a low level or a high level as a judgment result; and the digital calibration logic module is used for updating a control word corresponding to the DTC in the four-phase phase adjustment module according to the judgment result. The method is suitable for phase calibration of the multi-phase clock in a high-speed clock system.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit clock and calibration technology, and more specifically, to a four-phase clock phase calibration circuit based on a digital time converter. Background Technology

[0002] With the development of high-speed integrated circuit technology towards higher frequencies, wider bandwidths, and multiple channels, multiphase clocks are widely used in applications such as high-speed serial transceivers, data converters, phase-locked loop clock distribution, and multiphase sampling. Four-phase clocks are a common type of multiphase clock. Because they can provide multiple timing references with adjacent phase intervals of approximately 90°, they are often used in key modules such as multi-channel sampling, I / Q demodulation, edge selection, and clock reconstruction. Their phase consistency and long-term stability directly affect the system's sampling accuracy, jitter performance, and timing margin.

[0003] However, in actual chip implementation, the phase of a four-phase clock is affected by variations in process technology, voltage, temperature, layout parasites, and device mismatches, resulting in deviations. Even if the four-phase clocks are generated from the same clock source, inconsistencies in buffers, traces, loads, and device parameters across different phase paths will still introduce fixed phase deviations, which will drift under environmental changes, causing the interval between adjacent phases to deviate from the ideal value. This type of phase error not only reduces the accuracy of multiplexing or phase selection operations but may also be amplified into more significant timing violations and performance degradation in high-frequency scenarios. Therefore, how to reliably detect and implement closed-loop calibration of the four-phase clock phase error within the chip is a key issue in improving the robustness and consistency of high-speed multiphase clock systems.

[0004] Existing four-phase clock phase calibration techniques aim to ensure that the phase interval between adjacent clocks is close to the ideal value (e.g., a 90° phase difference between the four clocks) and to suppress fixed deviations and drift under conditions of PVT fluctuations, layout parasitics, and device mismatch. Existing technologies typically revolve around "error detection, decision-making, delay adjustment, and closed-loop convergence," and mainly include the following technical approaches: (1) Calibration based on multiphase DLL or multi-tap delay chain (analog closed loop): Adjustable delay units are used to construct multiphase DLL or multi-tap delay chains, and closed loop locking is achieved through phase frequency detectors, charge pumps, and loop filters. This type of scheme belongs to analog closed loop system, and its stability is easily affected by process, voltage, temperature changes and power supply noise; at the same time, there is a coupling relationship between multiphase taps, and adjusting the delay of one path will change the phase relationship of other paths, making the calibration more complicated and potentially introducing residual phase errors. Constrained by multiphase coupling and loop stability, and the difficulty in achieving both delay adjustment step and gain consistency under high-frequency conditions. In addition, many DLL circuits use inverter delay chains and other structures as delay adjustment units, and it is difficult to obtain a sufficiently small adjustment step in high-frequency scenarios; if the delay gain lacks good linearity with the control word, the equivalent loop gain will fluctuate significantly with the code word, which can easily lead to unstable convergence speed, convergence point offset and increased steady-state residual phase error, thus requiring an additional linear gain calibration module, increasing its circuit complexity.

[0005] (2) Digital phase measurement calibration based on time-to-digital converter (digital measurement): The phase difference is quantized using a time-to-digital converter or a multiphase sampling structure, and a programmable delay line, phase interpolator, or digitally controllable delay unit is driven to perform closed-loop updates. This type of scheme usually requires high time resolution and good linearity in high-frequency scenarios to ensure the accuracy of phase measurement and control updates. However, it brings high area and power consumption overhead, high implementation cost of high-resolution time-to-digital converter, and is susceptible to quantization noise and metastability. When approaching convergence, the control word may easily switch periodically between adjacent code values ​​due to quantization noise and decision uncertainty, making it difficult to stabilize at a single code value, thus introducing residual phase error and degrading clock jitter in steady state. Additional digital filtering or algorithms are usually required to improve stability.

[0006] Overall, it is difficult to achieve high-precision calibration with existing technical solutions. At the same time, it requires high linearity of the delay adjustment unit or measurement link. Insufficient linearity will significantly affect the closed-loop convergence and steady-state error level, thereby increasing the difficulty of system implementation. Summary of the Invention

[0007] This application aims to solve the technical problems of existing four-phase clock phase calibration circuits, which are difficult to achieve high-precision calibration and have large phase deviations, by providing a four-phase clock phase calibration circuit based on a digital time converter.

[0008] This application provides a four-phase clock phase calibration circuit based on a digital time converter, including a four-phase phase adjustment module, a phase error detection link, a comparison and decision module, and a digital calibration logic module. The four-phase phase adjustment module includes a DTC module. The phase error detection link is used to select a pair of four-phase clocks output from the four-phase phase adjustment module, process them, and output a voltage domain signal representing the phase difference information. The comparison and decision module is used to make a sign decision based on the voltage domain signal output by the phase error detection link and output a low level or a high level as the decision result. The digital calibration logic module is used to update the control word of the corresponding DTC in the four-phase phase adjustment module according to the decision result, so that the corresponding clock phase moves in the direction of reducing error.

[0009] Preferably, in the four-phase phase adjustment module, the digital control code of the DTC module is eight bits.

[0010] Preferably, the digital calibration logic module is configured to increase the control word of the DTC module in the four-phase phase adjustment module when the output of the comparison decision module is low, and decrease the control word of the DTC module in the four-phase phase adjustment module when the output of the comparison decision module is high.

[0011] Preferably, the digital calibration logic module uses a 12-bit accumulator to suppress the influence of noise through integral accumulation and update. The high 8 bits are used as the DTC control word output, and the low 4 bits are used for the accumulation and carry of the decision result.

[0012] Preferably, the phase error detection link includes a phase pair selection module, a phase detection module, and a phase voltage conversion module. The phase pair selection module is used to select a pair from the four-phase clocks output by the four-phase phase adjustment module. The phase detection module is used to process the pair of clocks and output phase difference information. The phase voltage conversion module is used to convert the phase difference information into a voltage domain signal.

[0013] Preferably, the phase-to-voltage conversion module includes a first IDAC, a second IDAC, node VP, node VN, and node... ,node The following components are connected to node Rst, capacitor C1, capacitor C2, MOSFETs Q1, Q2, Q3, Q4, Q5, inverters G1, G2, and G3. Node VP is grounded through capacitor C1. The input of the first IDAC is connected to node VP, the output of the first IDAC is connected to the drain (D) of MOSFET Q1, and the source (S) of MOSFET Q1 is connected to the output of inverter G1. The first inverter G1 is connected to the input terminal; the drain (D) of the third MOSFET Q3 is connected to node VP; the gate (G) of the third MOSFET Q3 is connected to node Rst; node VN is grounded through the second capacitor C2; the input terminal of the second IDAC is connected to node VN; the output terminal of the second IDAC is connected to the drain (D) of the second MOSFET Q2; the source (S) of the second MOSFET Q2 is connected to the output terminal of the second inverter G2; node... The fourth MOSFET Q4 is connected to the input of the second inverter G2. Its drain (D) is connected to node VP, and its gate (G) is connected to node Rst. The gate (G) of the fifth MOSFET Q5 is connected to the gates of the first MOSFET Q1 and the second MOSFET Q2, respectively. The source (S) of the fifth MOSFET Q5 is connected to the output of the third inverter. ,node Nodes VP and VN serve as the input terminals of the phase voltage conversion module, while nodes VP and VN serve as the output terminals.

[0014] Preferably, the phase error detection link further includes a frequency divider module, which is connected between the phase pair selection module and the phase detection module. The frequency divider module is used to down-clock a pair of clocks output by the phase pair selection module.

[0015] The beneficial effects of this application are that it enables high-precision calibration, effectively reduces the phase deviation and drift of four-phase clocks, and improves the phase consistency and overall performance of multi-phase clock systems. It also reduces dependence on linearity and improves convergence robustness. It is suitable for high-frequency applications.

[0016] An integral accumulation control word update mechanism is adopted, which accumulates the comparison decision results obtained by the comparison decision module in the time domain before updating the DTC control word. This can effectively suppress random jitter updates caused by noise and instantaneous misjudgment in each module, and improve the closed-loop convergence stability and steady-state accuracy.

[0017] Further features and aspects of this application will be clearly described in the following detailed description with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a circuit block diagram of a four-phase clock phase calibration circuit based on a digital time converter; Figure 2 This is the circuit diagram of the phase-to-voltage conversion module; Figure 3 This is one of the specific circuit diagrams for the four-phase phase adjustment module; Figure 4 The results are from a calibration simulation of a four-phase clock phase calibration circuit based on a digital time converter.

[0019] Explanation of symbols in the diagram: 1. Four-phase clock generation module; 2. Four-phase phase adjustment module; 3. Phase error detection link; 3-1. Phase pair selection module; 3-2. Frequency division module; 3-3. Phase detection module; 3-4. Phase voltage conversion module; 4. Comparison and decision module; 5. Digital calibration logic module. Detailed Implementation

[0020] The application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The specific embodiments described below are merely preferred embodiments of this application, and the scope of protection of this application is not limited thereto. For those skilled in the art, based on or in accordance with the principles, concepts, and spirit of this application, some modifications or variations can be made, and the technical solutions formed by these modifications or variations should all be covered within the scope of protection of this application.

[0022] like Figure 1 As shown, the four-phase clock generation module 1 provides four clock signals (CLK0, CLK90, CLK180, CLK270) with phases of 0°, 90°, 180°, and 270° respectively. The four clock signals are output to the four-phase phase adjustment module 2.

[0023] The four-phase phase adjustment module 2 employs a controllable delay structure centered on a digital time converter (DTC). It applies programmable, minute time offsets to each of the four clock signals to achieve phase adjustment. Each signal passes through a DTC module to eliminate the delay introduced by the DTC itself. The DTC control word is uniformly adjusted by the digital calibration logic module 5. The specific circuit diagram of the four-phase phase adjustment module 2 is shown below. Figure 3 As shown, Figure 3 It showed one path, CLK REF For input (receiving one of the clock signals output by the four-phase clock generation module 1), CLK DTC For output, the digital control code of the DTC module is an eight-bit DTC[0:7]; the entire four-phase phase adjustment module 2 has four channels. Figure 3 The circuit shown.

[0024] To construct a closed-loop calibration path, a phase error detection link 3 is set up, which is used to select the phase pair to be detected from the four-phase clocks and output information characterizing the direction of the phase error. The phase error detection link 3 includes a phase pair selection module 3-1, a frequency divider module 3-2, a phase detection module 3-3, and a phase voltage conversion module 3-4. The phase pair selection module 3-1 selects a pair of clocks from the four clocks as the detection input. The frequency divider module 3-2 down-clocks the selected pair of clocks (i.e., the two clocks) to reduce the speed pressure on the subsequent detection circuit. The down-clocked two clocks are input to the phase detection module 3-3, which outputs phase difference information, which reflects the phase sequence. Then, the phase difference information is input to the phase voltage conversion module 3-4, which converts the phase difference information into a voltage domain signal output.

[0025] The specific circuit for phase selection module 3-1 can be a conventional circuit from the prior art. The specific circuit for frequency divider module 3-2 can be a conventional cascaded frequency divider circuit to form an octet frequency divider circuit. The specific circuit for phase detection module 3-3 can be a conventional D flip-flop with a reset terminal phase detector from the prior art.

[0026] The specific circuit for phase-voltage conversion module 3-4 can be found in the following reference. Figure 2 Configure two programmable current source arrays (IDACs), nodes ,node As input, node VP is grounded through the first capacitor C1. The input terminal of the first IDAC is connected to node VP, the output terminal of the first IDAC is connected to the drain of the first MOSFET Q1, and the source terminal of the first MOSFET Q1 is connected to the output terminal of the first inverter G1. The input terminal of the first inverter G1 serves as the node... The drain (D) of the third MOSFET Q3 is connected to node VP, and the gate (G) of the third MOSFET Q3 is connected to node Rst. Node VN is grounded through the second capacitor C2. The input of the second IDAC is connected to node VN, the output of the second IDAC is connected to the drain of the second MOSFET Q2, and the source (S) of the second MOSFET Q2 is connected to the output of the second inverter G2. The input of the second inverter G2 serves as the node... The drain (D) of the fourth MOSFET Q4 is connected to node VP, and the gate (G) of the fourth MOSFET Q4 is connected to node Rst. The gate (G) of the fifth MOSFET Q5 is connected to the gates of the first MOSFET Q1 and the second MOSFET Q2, respectively. The source (S) of the fifth MOSFET Q5 is connected to the output of the third inverter G3, and the bias current is connected to the drain (D) of the fifth MOSFET Q5. The digital control input of the first IDAC is a 5-bit digital control signal dacN_ctrl[4:0], and the digital control input of the second IDAC is also a 5-bit digital control signal dacN_ctrl[4:0]. By adding inverters to the sources of the first MOSFET Q1 and the second MOSFET Q2, the phase voltage conversion error caused by leakage current of the current source is eliminated. Two programmable current source arrays (IDACs) are used to compensate for the error caused by the mismatch between the two current sources. ,node As the input terminal of the phase voltage conversion module 3-4, the output terminal of the phase detection module 3-3 is connected to the node. ,node Nodes VP and VN serve as the output terminals of phase voltage conversion module 3-4.

[0027] The voltage domain signals output from nodes VP and VN are input to comparison and decision module 4 for sign determination. Comparison and decision module 4 outputs the decision result of the phase error direction, which is either low level 0 or high level 1. This decision result is input to digital calibration logic module 5. The specific circuit of comparison and decision module 4 can be a dynamic latch comparator from the prior art. The dynamic latch comparator compares the input voltage signals and outputs either low level 0 or high level 1.

[0028] The digital calibration logic module 5 updates the control word of the corresponding DTC in the four-phase phase adjustment module 2 based on the decision result, causing the corresponding clock phase to shift in the direction of error reduction and bringing the interval between adjacent phases to the target quarter cycle, thus forming a closed-loop calibration of "detection-decision-update". Specifically, the digital calibration logic module 5 is a digital circuit, composed of basic digital circuit units such as registers, logic gates, adders or subtractors, accumulators, and update enable logic. When the output result of the comparison decision module 4 is 0, the control word of the DTC is increased; when the output result of the comparison decision module 4 is 1, the control word of the DTC is decreased, thereby adjusting the phase according to the comparison result of the phase error to achieve phase calibration. When the digital calibration logic module 5 uses an integral accumulation update method to suppress the influence of noise, it is preferably implemented with a 12-bit accumulator. The high 8 bits are used as the DTC control word output, and the low 4 bits are used for the accumulation and carry of the decision result. This ensures that the control word is updated only when the accumulated amount reaches the carry condition (when the low 4 bits accumulate to 16, a carry is triggered, and the high 8 bits are incremented by 1). When the decision result of the comparison decision module 4 is 1, the total value of the 12-bit control word is decremented by 1, and the low 4 bits are decremented by 1. After accumulating 16 decrements, the high bits are decremented by 1. Because the initial control word of the DTC is initially set from the middle of the 8 bits (127), it ensures that the control word can be increased or decreased. This reduces random jitter updates caused by noise.

[0029] To reduce the impact of system errors caused by mismatch in key functional modules on closed-loop convergence, a foreground calibration process can be performed during system startup. Specifically, before the aforementioned four-phase clock phase calibration circuit based on a digital time converter officially operates, the output of the four-phase clock generation module 1 is passed through a selector, which continuously outputs an in-phase signal to the phase voltage conversion module 3-4, thereby setting the phase error to zero. The comparison decision module 4 compares the two outputs of the phase voltage conversion module 3-4 to express the polarity of the bias voltage of the phase voltage conversion module 3-4. The comparison result is then sent to the digital calibration logic module 5, which outputs a control word to the two programmable current source arrays (IDACs) in the phase voltage conversion module 3-4, thereby adjusting the magnitude of the two currents in the phase voltage conversion module 3-4 circuit to reduce the offset voltage. The comparison decision module 4 reduces the input offset voltage by using offset suppression methods such as background self-zeroing and charge redistribution to minimize the impact of the equivalent input offset voltage on the decision result. The phase voltage conversion modules 3-4 adjust the gain of both paths via a programmable unit to reduce the equivalent offset voltage. During the foreground calibration, the digital calibration logic module 5 freezes the DTC control word; after the foreground calibration is completed, it unfreezes and enters the background calibration mode, thus continuously tracking and compensating for phase drift during system operation. Background tracking calibration continuously compensates for slowly changing phase errors caused by environmental drift, enhancing the system's long-term stability and robustness. It is suitable for applications such as multiphase sampling, clock reconstruction, and high-speed serial interfaces.

[0030] The four clock signals output by the four-phase phase adjustment module 2 serve as the final clock signals after calibration. The phase deviation of the four clock signals output by the four-phase phase adjustment module 2 is very small, which improves the four-phase orthogonality and consistency.

[0031] The output of the four-phase phase adjustment module 2 can also be sent to the edge-selectable programmable fractional frequency divider module to select the output according to a preset sequence among the four-phase edges, so as to realize a programmable frequency divider clock with different frequency division ratios; the phase selection sequence is preferably updated synchronously with the output clock to avoid glitches introduced by selection switching.

[0032] This invention achieves high-precision calibration, suitable for GHz-level high-frequency applications. It enables high-precision phase fine-tuning under high-frequency operating conditions and reduces dependence on the linearity of the delay adjustment unit, with a minimum adjustment step of 18 fs. Closed-loop calibration employs a differential decision and update mechanism based on adjacent calibration cycles, making control updates primarily dependent on the monotonicity of the adjustment unit rather than high linearity. This reduces the linearization design burden and improves convergence robustness and repeatability under conditions of process, voltage, temperature variations, and device mismatch.

[0033] The feasibility and effectiveness were verified through circuit-level simulation and statistical mismatch simulation. Monte Carlo simulation (N=200) of the aforementioned four-phase clock phase calibration circuit based on a digital time converter was performed using Spectre on the Cadence Virtuoso platform. Phase error (deviation from the ideal phase interval) was used as the evaluation metric, and the results were as follows: Figure 4 The results are shown. Figure 4 The blue area represents "calibrated", and the red area represents "uncalibrated". (For easier comparison, the uncalibrated distribution is shown in the figure shifted by +11.25 ps along the horizontal axis. The shift does not affect its statistics. The unit ps represents picoseconds.) Figure 4 The horizontal axis represents the phase error in fs (fs), and the vertical axis represents the number of samples. Simulation results show that the phase error distribution converges significantly after calibration, with a mean (Mean) of 141 fs (fs represents femtoseconds) and a standard deviation (StdDev) of 638 fs. Without calibration, the mean (Mean) is 114 fs, and the standard deviation (StdDev) is 2045 fs. Therefore, the calibration scheme of this invention can reduce the phase error dispersion (standard deviation) by approximately 3.2 times (approximately 69%) under device mismatch conditions, verifying the effectiveness of this invention in improving the four-phase phase consistency under mismatch perturbation and the effectiveness of the calibration algorithm.

[0034] It should be noted that the phase error detection link 3 may also omit the frequency divider module 3-2.

Claims

1. A four-phase clock phase calibration circuit based on a digital time converter, characterized in that, It includes a four-phase phase adjustment module, a phase error detection link, a comparison and decision module, and a digital calibration logic module; The four-phase phase adjustment module is equipped with a DTC module; The phase error detection link is used to select a pair of four-phase clocks from the four-phase clocks output by the four-phase phase adjustment module, process them, and output a voltage domain signal that represents the phase difference information. The comparison decision module is used to make a sign decision based on the voltage domain signal output by the phase error detection link, and output a low level or a high level as the decision result. The digital calibration logic module is used to update the control word of the corresponding DTC in the four-phase phase adjustment module according to the decision result, so that the corresponding clock phase moves in the direction of reducing error.

2. The four-phase clock phase calibration circuit based on a digital time converter according to claim 1, characterized in that, In the four-phase phase adjustment module, the digital control code of the DTC module is eight bits.

3. The four-phase clock phase calibration circuit based on a digital time converter according to claim 1, characterized in that, The digital calibration logic module is configured to increase the control word of the DTC module in the four-phase phase adjustment module when the output of the comparison decision module is low, and decrease the control word of the DTC module in the four-phase phase adjustment module when the output of the comparison decision module is high.

4. The four-phase clock phase calibration circuit based on a digital time converter according to claim 3, characterized in that, The digital calibration logic module uses a 12-bit accumulator to suppress the influence of noise through integral accumulation and update. The high 8 bits are used as the DTC control word output, and the low 4 bits are used for the accumulation and carry of the decision result.

5. The four-phase clock phase calibration circuit based on a digital time converter according to claim 1, characterized in that, The phase error detection link includes a phase pair selection module, a phase detection module, and a phase voltage conversion module. The phase pair selection module is used to select a pair of clocks from the four-phase clocks output by the four-phase phase adjustment module. The phase detection module is used to process the pair of clocks and then output phase difference information. The phase-to-voltage conversion module is used to convert the phase difference information into a voltage domain signal.

6. The four-phase clock phase calibration circuit based on a digital time converter according to claim 5, characterized in that, The phase-voltage conversion module includes a first IAC, a second IAC, node VP, node VN, and node... ,node The system includes node Rst, first capacitor C1, second capacitor C2, first MOSFET Q1, second MOSFET Q2, third MOSFET Q3, fourth MOSFET Q4, fifth MOSFET Q5, first inverter G1, second inverter G2, and third inverter G3. Node VP is grounded through the first capacitor C1. The input terminal of the first IDAC is connected to node VP, the output terminal of the first IDAC is connected to the drain (D) of the first MOSFET Q1, and the source (S) terminal of the first MOSFET Q1 is connected to the output terminal of the first inverter G1. The third MOSFET Q3 is connected to the input of the first inverter G1. The drain (D) of Q3 is connected to node VP, and the gate (G) of Q3 is connected to node Rst. Node VN is grounded through the second capacitor C2. The input of the second IDAC is connected to node VN, the output of the second IDAC is connected to the drain (D) of the second MOSFET Q2, and the source (S) of the second MOSFET Q2 is connected to the output of the second inverter G2. The fourth MOSFET Q4 is connected to the input terminal of the second inverter G2. Its drain (D) is connected to node VP, and its gate (G) is connected to node Rst. The gate (G) of the fifth MOSFET Q5 is connected to the gates of the first MOSFET Q1 and the second MOSFET Q2, respectively. The source (S) of the fifth MOSFET Q5 is connected to the output terminal of the third inverter. ,node As the input terminals of the phase voltage conversion module, nodes VP and VN serve as the output terminals of the phase voltage conversion module.

7. The four-phase clock phase calibration circuit based on a digital time converter according to claim 5, characterized in that, The phase error detection link also includes a frequency division module, which is connected between the phase pair selection module and the phase detection module. The frequency division module is used to down-clock a pair of clocks output by the phase pair selection module.

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